A method to improve the performance and reliability of RF LDMOS

Abstract

The application provides a method for improving the performance and reliability of RF LDMOS, which comprises the following steps: forming a first oxide layer; defining a drain end region by photoetching, etching the first oxide layer and a silicon substrate in the drain end region to form a groove; depositing polysilicon to fill the groove; defining a gate position, removing the first oxide layer far from the drain end region on one side of the gate position to form a gate oxide layer, covering the gate oxide layer with a layer of polysilicon to form a gate polysilicon layer; etching the gate polysilicon layer to form a gate polysilicon structure; the side of the gate polysilicon structure far from the drain end region is a source end region; forming a P-type body region, a P+ region, an N+ region and an NLDD region; forming a metal silicide on the polysilicon in the source end region, on the top of the gate polysilicon structure and in the groove; forming a second oxide layer which continuously covers the metal silicide of the source end region, the metal silicide on the top of the gate polysilicon, a side wall, the first oxide layer and the metal silicide of the drain end region; forming a gate shielding cover on the side of the gate polysilicon structure close to the drain end region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for improving the performance and reliability of RF LDMOS. Background Technology

[0002] RFLDMOS is widely used in high-power radio frequency fields such as base stations and broadcast television transmission. By using power arrays and multi-chip synthesis, the output power of the products can reach more than 500 watts. The contradiction between the radio frequency performance and reliability of RFLDMOS is the focus of research.

[0003] On-resistance and output capacitance are the main factors affecting the efficiency of RF LDMOS transistors. Reducing on-resistance and output capacitance can decrease the power loss caused by these two factors, thereby improving the device's efficiency and gain.

[0004] Reducing the input / output capacitance and feedback capacitance can effectively improve the characteristic frequency, maximum oscillation frequency, and gain of the device.

[0005] Currently, the drain of RFLDMOS is achieved by using a polysilicon structure combined with N-type ion implantation and contact hole lead-out. On the one hand, the regularity between N-type polysilicon / source-base / contact hole determines that the N-type polysilicon must be wide enough, so the drain output capacitance is large. On the other hand, in order to reduce the gate resistance and improve efficiency, a relatively thick silicide is required for the gate / source / drain, but this will cause the drain to have the risk of leakage.

[0006] Therefore, the design of the drain terminal is an extremely important factor in the RF performance of RFLDMOS. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method to improve the performance and reliability of RF LDMOS, in order to solve the problem of leakage risk in RF LDMOS in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides a method for improving the performance and reliability of RF LDMOS.

[0009] Step 1: Provide a silicon substrate and form a first oxide layer on the silicon substrate;

[0010] Step 2: The drain region is defined by photolithography, and then the first oxide layer and the silicon substrate are etched in the drain region to form a groove; the etching width of the silicon substrate in the groove is smaller than the etching width of the first oxide layer.

[0011] Step 3: Deposit polysilicon to fill the groove and planarize the surface until the first oxide layer is exposed;

[0012] Step 4: Define the gate location and remove the first oxide layer on the side of the gate location away from the drain region;

[0013] Step 5: Form a gate oxide layer, which covers the silicon substrate, the first oxide layer, and the polysilicon within the groove;

[0014] Step 6: Cover the gate oxide layer with a layer of polysilicon to form a gate polysilicon layer; then etch the gate polysilicon layer to form a gate polysilicon structure at the gate location; the side of the gate polysilicon structure away from the drain region is the source region;

[0015] Step 7: Form a P-type body region in the silicon substrate in the source region; form a P+ region in the P-type body region; form an N+ region in the P-type body region between the P+ region and the gate polysilicon structure and in the silicon substrate below the groove filled with polysilicon; form an NLDD region in the silicon substrate on the side of the gate polysilicon structure away from the P-type body region.

[0016] Step 8: Form a sidewall on the sidewall of the gate polysilicon structure;

[0017] Step 9: Form metal silicide on the polysilicon in the grooves of the source region, the top of the gate polysilicon structure, and the drain region;

[0018] Step 10: Form a second oxide layer, which continuously covers the metal silicide in the source region, the metal silicide on top of the gate polysilicon, the sidewalls, the first oxide layer, and the metal silicide in the drain region.

[0019] Step 11: Form a gate shield on the side of the gate polysilicon structure near the drain region. The gate shield starts from the second oxide layer on the top side of the gate polysilicon structure and extends along the second oxide layer on the sidewall of the gate polysilicon structure to the second oxide layer between the drain region and the gate polysilicon structure.

[0020] Preferably, the method for forming the groove in step two is as follows: firstly, anisotropic etching is performed on the first oxide layer and the silicon substrate in the drain region to form a groove with a through opening; then, isotropic etching is performed on the first oxide layer in the groove with the through opening to widen the opening width of the first oxide layer on the sidewall of the groove with the through opening.

[0021] Preferably, the planarization method in step three is chemical mechanical polishing.

[0022] Preferably, the method for removing the first oxide layer in step four is wet etching.

[0023] Preferably, in step seven, the upper surfaces of the P-type body region, P+ region, NLDD region, and N+ region are all flush with the upper surface of the silicon substrate; and the N+ region located within the P-type body region is connected to the P+ region; the depth of the NLDD region within the silicon substrate is less than the depth of the P-type body region within the silicon substrate; and one side of the gate polysilicon structure covers the top of one side of the P-type body region.

[0024] Preferably, the sidewall in step eight is silicon oxide, and the sidewall is formed by depositing a silicon oxide layer first, and then etching the silicon oxide layer to remove the silicon oxide layer outside the sidewall of the gate polysilicon structure.

[0025] Preferably, the metal silicide in step nine is a Ti-containing silicide.

[0026] Preferably, the method further includes step 12: forming a dielectric layer covering the source region, the gate polysilicon structure, and the drain region; then forming a contact hole in the dielectric layer that connects the polysilicon in the drain region groove and the top of the source region; next, filling the contact hole with metal; covering the dielectric layer with a metal layer; and finally etching the metal layer to form a metal line connected to the metal-filled contact hole.

[0027] As described above, the method for improving the performance and reliability of RF LDMOS according to the present invention has the following beneficial effects: The method of the present invention adopts the drain polysilicon combined with N-type ion implantation, which will naturally form a concentration gradient between the drain and the LDD region; it is beneficial to improve the hot carrier effect, and the contact hole falls on the drain polysilicon, which will not affect the drain junction, so there is no risk of leakage, and the reliability of the product can be effectively improved; at the same time, due to the use of drain polysilicon N-type ion bonding process, the drain size is significantly reduced, which can effectively reduce the output capacitance and improve product performance. Attached Figure Description

[0028] Figures 1 to 11 The diagram shows the structure formed at each stage of the RFLDMOS fabrication process in this invention.

[0029] Figure 12 The diagram shows a flowchart of the method for improving the performance and reliability of RF LDMOS according to the present invention. Detailed Implementation

[0030] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] Please see Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0032] This invention provides a method for improving the performance and reliability of RF LDMOS, the method comprising at least the following steps:

[0033] Step 1: Provide a silicon substrate, and form a first oxide layer on the silicon substrate; such as Figure 1 As shown, in step one, a silicon substrate 01 is provided, and a first oxide layer 02 is formed on the silicon substrate 01. Forming the first oxide layer on the silicon substrate includes forming the first oxide layer on the back side of the silicon substrate as well.

[0034] Step 2: The drain region is defined by photolithography, and then the first oxide layer and the silicon substrate are etched in the drain region to form a groove; the etching width of the silicon substrate in the groove is smaller than the etching width of the first oxide layer.

[0035] In a further step of this invention, the method for forming the groove in step two of this embodiment is as follows: firstly, anisotropic etching is performed on the first oxide layer and the silicon substrate in the drain region to form a groove with a through opening; then, isotropic etching is performed on the first oxide layer in the groove with the through opening to widen the opening width of the first oxide layer on the sidewall of the groove with the through opening.

[0036] like Figure 2 As shown, in step two, photolithography defines the drain region. Then, the first oxide layer 02 and the silicon substrate 01 are etched in the drain region to form a groove 04. The etching width of the silicon substrate 01 in the groove is smaller than the etching width of the first oxide layer 02. In this embodiment, the first oxide layer 02 and the silicon substrate 01 in the drain region are first anisotropically etched to form a through-hole groove. Then, the first oxide layer 02 is isotropically etched within the through-hole groove to widen the opening width of the first oxide layer on the sidewall of the through-hole groove, ultimately forming a groove as shown. Figure 2The groove shown has a narrower etching width on the silicon substrate than on the first oxide layer. Step two uses a photoresist layer 03 to photolithographically define the drain region, thus forming the groove 04.

[0037] Step 3: Deposit polysilicon to fill the groove and planarize the surface until the first oxide layer is exposed;

[0038] Furthermore, in this embodiment, the planarization method in step three is chemical mechanical polishing. For example... Figure 3 As shown, in step three, polycrystalline silicon 05 is deposited to fill the groove 04, and the surface is planarized until the first oxide layer 02 is exposed; the planarization method in this embodiment is chemical mechanical polishing.

[0039] Step 4: Define the gate location and remove the first oxide layer on the side of the gate location away from the drain region;

[0040] Furthermore, in this embodiment, the method for removing the first oxide layer in step four is wet etching. For example... Figure 4 As shown, in step four, the gate location (the boundary between the first oxide layer and the retained boundary) is defined, and the first oxide layer on the side of that location away from the drain region is removed. Figure 4 The area on the left side of the middle section is the source region where the first oxide layer has been removed (which will be the source region in subsequent steps). This step uses photoresist 06 to define the gate position and the area where the first oxide layer has been removed (i.e., the source region in subsequent steps). In this embodiment, the method for removing the first oxide layer is wet etching.

[0041] Step 5: Form a gate oxide layer, which covers the silicon substrate, the first oxide layer, and the polysilicon within the trench; as shown below. Figure 5 As shown, in step five, a gate oxide layer 07 is formed, which covers the silicon substrate 01 (referring to the silicon substrate covering the source region) and the first oxide layer ( Figure 5 The remaining first oxide layer in the left region and the polycrystalline silicon 05 in the groove.

[0042] Step Six: Deposit a layer of polysilicon onto the gate oxide layer to form a gate polysilicon layer; then etch the gate polysilicon layer to form a gate polysilicon structure at the gate location; the side of the gate polysilicon structure away from the drain region is the source region; as shown... Figure 6 As shown, in step six, a layer of polysilicon is deposited on the gate oxide layer 07 to form a gate polysilicon layer 08; as Figure 7 As shown, the gate polysilicon layer 08 is then etched to form a gate polysilicon structure 09 at the gate location; the side of the gate polysilicon structure 09 away from the drain region is the source region. Figure 7 The left side of the gate polysilicon structure 09 described in the image is the source region.

[0043] Step 7: Form a P-type body region in the silicon substrate in the source region; form a P+ region in the P-type body region; form an N+ region in the P-type body region between the P+ region and the gate polysilicon structure and in the silicon substrate below the groove filled with polysilicon; form an NLDD region in the silicon substrate on the side of the gate polysilicon structure away from the P-type body region.

[0044] In a further embodiment of the present invention, the upper surface of the P-type body region, the upper surface of the P+ region, the upper surface of the NLDD region, and the upper surface of the N+ region in step seven are all flush with the upper surface of the silicon substrate; and the N+ region located in the P-type body region is connected to the P+ region; the depth of the NLDD region in the silicon substrate is less than the depth of the P-type body region in the silicon substrate; and one side of the gate polysilicon structure covers the upper side of the P-type body region.

[0045] like Figure 8 As shown, in step seven, a P-type body region 10 is formed within the silicon substrate in the source region; a P+ region 12 is formed within the P-type body region 10; an N+ region (13) is formed within the P-type body region 10 between the P+ region 12 and the gate polysilicon structure 09; and an N+ region (11) is formed within the silicon substrate 01 below the groove filled with polysilicon 05; an NLDD region 14 is formed within the silicon substrate 01 on the side of the gate polysilicon structure 09 away from the P-type body region 10. This embodiment step... In step seven, the upper surfaces of the P-type body region 10, P+ region 12, NLDD region 14, and N+ regions (11 and 13) are all flush with the upper surface of the silicon substrate 01; and the N+ region 13 located within the P-type body region 10 is connected to the P+ region 12; the depth of the NLDD region 14 within the silicon substrate is less than the depth of the P-type body region 10 within the silicon substrate 01; one side of the gate polysilicon structure 06 covers the top of one side of the P-type body region 10.

[0046] Step 8: Form a sidewall on the sidewall of the gate polysilicon structure;

[0047] Furthermore, in step eight of this embodiment, the sidewall is silicon oxide, and the method for forming the sidewall is as follows: first, a silicon oxide layer is deposited, and then the silicon oxide layer is etched to remove the silicon oxide layer outside the sidewall of the gate polysilicon structure.

[0048] like Figure 9As shown, step eight forms a sidewall 15 on the sidewall of the gate polysilicon structure 09; in step eight of this embodiment, the sidewall 15 is silicon oxide, and the method for forming the sidewall 15 is as follows: first deposit a silicon oxide layer, and then etch the silicon oxide layer to remove the silicon oxide layer outside the sidewall of the gate polysilicon structure 09.

[0049] Step 9: Form metal silicide on the polysilicon in the grooves of the source region, the top of the gate polysilicon structure, and the drain region;

[0050] Furthermore, in this embodiment, the metal silicide in step nine is a Ti-containing silicide. For example... Figure 10 As shown, step nine is performed in the source region ( Figure 10 Metal silicide 16 is formed on the polysilicon 05 in the groove of the gate polysilicon structure (left side), the top of the gate polysilicon structure 09, and the drain region. Figure 10 (The three metal silicides are uniformly identified by 16); the metal silicide 16 in step nine of this embodiment is a Ti-containing silicide.

[0051] Step 10: Form a second oxide layer, which continuously covers the metal silicide in the source region, the metal silicide on top of the gate polysilicon, the sidewalls, the first oxide layer, and the metal silicide in the drain region; as shown. Figure 11 As shown, step ten forms a second oxide layer 17, which continuously covers the metal silicide in the source region, the metal silicide on top of the gate polysilicon, the sidewall 15, the first oxide layer, and the metal silicide in the drain region.

[0052] Step 11: Form a gate shield on the side of the gate polysilicon structure near the drain region. The gate shield begins at the second oxide layer on the top side of the gate polysilicon structure and extends along the second oxide layer on the sidewall of the gate polysilicon structure to the second oxide layer between the drain region and the gate polysilicon structure. Figure 11 As shown, in step eleven, a gate shield 18 is formed on the side of the gate polysilicon structure 09 near the drain region. The gate shield 18 starts from the second oxide layer 17 on the top side of the gate polysilicon structure 09 and extends along the second oxide layer 17 on the sidewall of the gate polysilicon structure 09 until it reaches the second oxide layer 17 between the drain region and the gate polysilicon structure 09.

[0053] In a further embodiment of the present invention, the method further includes step 12: forming a dielectric layer covering the source region, the gate polysilicon structure, and the drain region; then forming a contact hole in the dielectric layer that connects the polysilicon in the drain region groove and the top of the source region; next, filling the contact hole with metal; covering the dielectric layer with a metal layer; and finally etching the metal layer to form a metal line connected to the metal-filled contact hole.

[0054] In summary, the method of this invention employs a drain-end polysilicon combined with N-type ion implantation, which naturally creates a concentration gradient between the drain and the LDD region. This helps improve the hot carrier effect, and since the contact holes fall on the drain-end polysilicon, they do not affect the drain junction, thus eliminating the risk of leakage and effectively improving product reliability. Furthermore, due to the use of drain-end polysilicon N-type ion bonding, the drain size is significantly reduced, effectively lowering the output capacitor cost and improving product performance. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0055] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for improving the performance and reliability of RF LDMOS, characterized in that, At least including: Step 1: Provide a silicon substrate and form a first oxide layer on the silicon substrate; Step 2: The drain region is defined by photolithography, and then the first oxide layer and the silicon substrate are etched in the drain region to form a groove; the etching width of the silicon substrate in the groove is smaller than the etching width of the first oxide layer. Step 3: Deposit polysilicon to fill the groove and planarize the surface until the first oxide layer is exposed; Step 4: Define the gate location and remove the first oxide layer on the side of the gate location away from the drain region; Step 5: Form a gate oxide layer, which covers the silicon substrate, the first oxide layer, and the polysilicon within the groove; Step 6: Cover the gate oxide layer with a layer of polysilicon to form a gate polysilicon layer; then etch the gate polysilicon layer to form a gate polysilicon structure at the gate location; the side of the gate polysilicon structure away from the drain region is the source region; Step 7: Form a P-type body region in the silicon substrate in the source region; form a P+ region in the P-type body region; form an N+ region in the P-type body region between the P+ region and the gate polysilicon structure and in the silicon substrate below the groove filled with polysilicon; form an NLDD region in the silicon substrate on the side of the gate polysilicon structure away from the P-type body region. Step 8: Form a sidewall on the sidewall of the gate polysilicon structure; Step 9: Form metal silicide on the polysilicon in the grooves of the source region, the top of the gate polysilicon structure, and the drain region; Step 10: Form a second oxide layer, which continuously covers the metal silicide in the source region, the metal silicide on top of the gate polysilicon, the sidewalls, the first oxide layer, and the metal silicide in the drain region. Step 11: Form a gate shield on the side of the gate polysilicon structure near the drain region. The gate shield starts from the second oxide layer on the top side of the gate polysilicon structure and extends along the second oxide layer on the sidewall of the gate polysilicon structure to the second oxide layer between the drain region and the gate polysilicon structure.

2. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: The method for forming the groove in step two is as follows: firstly, anisotropic etching is performed on the first oxide layer and the silicon substrate in the drain region to form a groove with an open through; then, isotropic etching is performed on the first oxide layer in the groove with an open through to widen the opening width of the first oxide layer on the sidewall of the groove with an open through.

3. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: The planarization method in step three is chemical mechanical polishing.

4. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: The method for removing the first oxide layer in step four is wet etching.

5. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: In step seven, the upper surfaces of the P-type body region, P+ region, NLDD region, and N+ region are all flush with the upper surface of the silicon substrate; and the N+ region located within the P-type body region is connected to the P+ region; the depth of the NLDD region within the silicon substrate is less than the depth of the P-type body region within the silicon substrate; one side of the gate polysilicon structure covers the top of one side of the P-type body region.

6. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: The sidewalls mentioned in step eight are silicon oxide, and the sidewalls are formed by first depositing a silicon oxide layer, and then etching the silicon oxide layer to remove the silicon oxide layer outside the sidewalls of the gate polysilicon structure.

7. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: The metal silicide mentioned in step nine is a Ti-containing silicide.

8. The method for improving the performance and reliability of RF LDMOS according to claim 1, characterized in that: The method further includes step 12: forming a dielectric layer covering the source region, the gate polysilicon structure, and the drain region; then forming a contact hole in the dielectric layer that connects the polysilicon in the drain region groove and the top of the source region; next, filling the contact hole with metal; covering the dielectric layer with a metal layer; and finally etching the metal layer to form a metal line connected to the metal-filled contact hole.

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