A power amplifier with segmented modulation

Abstract

This invention discloses a power amplifier with partial modulation, relating to the field of wireless communication technology. It includes a Doherty power amplifier for partial modulation and a balanced power amplifier for global modulation. The Doherty power amplifier for partial modulation includes an RF signal input terminal, a power divider, sub-amplifiers D3 and D4, and a load modulation network. The RF signal input terminal inputs the RF signal to sub-amplifiers D3 and D4 through the power divider, and after amplification by the sub-amplifiers, it is synthesized by the load modulation network. The balanced power amplifier includes an RF signal input terminal, an input coupler, sub-amplifiers D1 and D2, and an output coupler. The output of the Doherty power amplifier is connected to the isolation port of the balanced power amplifier's output coupler. This invention achieves an extended dynamic range, solves the main path oversaturation phenomenon in timing modulation power amplifiers, establishes a systematic and complete technical foundation for the design of broadband large dynamic load modulation power amplifiers, and expands the application scenarios of wireless communication networks.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more specifically, to a power amplifier with distributed modulation. Background Technology

[0002] From simple voice communication to multimedia data transmission, from point-to-point communication to the Internet of Things, contemporary wireless communication technology is profoundly changing people's production and lifestyles. As a core component of the radio frequency (RF) front-end, the RF power amplifier typically accounts for more than half of the total energy consumption of a wireless communication transmitter. Furthermore, with the widespread adoption of array technology, the demand for power amplifiers is increasing dramatically. Therefore, developing high-efficiency integrated power amplifier chips not only effectively reduces the overall power consumption of wireless base stations but also has significant academic value.

[0003] On the other hand, modern wireless communication systems commonly employ complex modulation signals, and bandwidth is constantly increasing. This leads to a continuous rise in the peak-to-average power ratio (PAR), making the average efficiency of power amplifiers more important than their peak efficiency. However, the efficiency of traditional power amplifiers declines rapidly with power back-off, and the energy required to process broadband modulation signals is clearly insufficient for system requirements. Furthermore, the significantly increased number of 5G communication frequency bands, coupled with backward compatibility, means that broadband communication components are indispensable. Therefore, broadband Doherty power amplifiers are gradually dominating the current base station market, and their bandwidth and dynamic range extension technologies have received widespread attention in recent years. Thus, how to extend the bandwidth of high-efficiency power amplifiers while simultaneously expanding their dynamic range warrants in-depth research.

[0004] In summary, the characteristics of RF power amplifiers in the new era of communication are: large quantity and high power consumption; wide bandwidth and high modulation. Therefore, high-efficiency, wide-bandwidth, high-dynamic-range power amplifiers will inevitably become a hot topic and a research challenge for the entire industry. Thus, research on bandwidth and dynamic expansion technologies for high-efficiency power amplifiers is not only of great significance, but also has a very broad market prospect in 5G / 6G and even future mobile communication fields. Summary of the Invention

[0005] The purpose of this invention is to provide a distributed modulation power amplifier that addresses the shortcomings of existing technologies by overcoming the problems of dynamic range and operating bandwidth in current power amplifiers. It also provides a broadband design scheme for balanced modulation power amplifiers. This invention discloses a power amplifier architecture with broadband, large dynamic load modulation characteristics. Through the proposed distributed modulation power amplifier theory, it solves the main path oversaturation phenomenon in time-load-modulated balanced power amplifiers, thereby achieving the goal of further expanding the high-efficiency power range while maintaining wide bandwidth operation.

[0006] The above-mentioned technical objective of the present invention is achieved through the following technical solution: a power amplifier with partial modulation, comprising a Doherty power amplifier for partial modulation and a balanced power amplifier for global modulation;

[0007] The locally modulated Doherty power amplifier includes an RF signal input terminal, a power divider, sub-power amplifiers D3 and D4, and a load modulation network. The RF signal input terminal inputs the RF signal to the two sub-power amplifiers D3 and D4 through the power divider, and after amplification, it is synthesized through the load modulation network.

[0008] The balanced power amplifier includes an RF signal input terminal 2, an input coupler, sub-power amplifiers D1 and D2, and an output coupler.

[0009] The output of the Doherty amplifier is connected to the isolation port (port #3) of the output coupler of the balanced amplifier; a phase compensation line is provided before the local Doherty amplifier or the balanced amplifier to adjust the phase difference between the local Doherty amplifier and the balanced amplifier.

[0010] The present invention is further configured such that: each of the sub-amplifiers D1, D2, D3, and D4 is provided with a broadband input matching network, an active transistor, and a broadband output matching network connected in series; the active transistor is connected with a gate bias circuit and a drain bias circuit; the broadband input matching network matches the optimal source impedance of the active transistor to the system impedance; the broadband output matching network matches the optimal load impedance of the active transistor to the system impedance.

[0011] The present invention is further configured such that the broadband output matching networks of the two sub-amplifiers D1 and D2 of the balanced power amplifier are respectively connected to ports #1 and #2 of the output coupler.

[0012] The present invention is further configured such that: the broadband output matching network of the two sub-amplifiers D3 and D4 of the Doherty amplifier is connected to port #3 of the output coupler through a load modulation network; the two sub-amplifiers of the Doherty amplifier are carrier amplifier D3 and peak amplifier D4, respectively.

[0013] The present invention is further configured such that the gate bias circuit and the drain bias circuit are implemented using microstrip lines, so that the DC power supply provides a stable operating voltage for the active transistor.

[0014] In summary, the present invention has the following beneficial effects: The local load modulation balanced amplifier proposed in this invention, through a local-to-global modulation method, achieves dynamic range expansion without sacrificing operating bandwidth, and solves the main path oversaturation phenomenon in timing modulation power amplifiers. It establishes a systematic and complete technical foundation for the design of broadband large dynamic load modulation power amplifiers and expands the application scenarios of wireless communication networks.

[0015] After the locally modulated Doherty amplifier is turned on, it modulates the balanced amplifier, thereby performing global load modulation. By using the concept of local load modulation, oversaturation of the sub-amplifier is avoided, and the high-efficiency power range can be further extended; at the same time, due to the broadband nature of the Doherty amplifier, the operating bandwidth of this invention can also be guaranteed. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the distributed modulation power amplifier architecture of the present invention;

[0017] Figure 2 Here is a block diagram of an existing broadband large backoff load modulation balanced amplifier.

[0018] Figure 3 This is a basic block diagram of a sub-amplifier in a distributed modulation power amplifier.

[0019] Figure 4 A simplified schematic diagram of a modulated power amplifier;

[0020] Figure 5 A simplified global modulation state architecture diagram based on a 90° coupler;

[0021] Figure 6 This is a schematic diagram comparing the back-off amount of the power amplifier architecture of the present invention with that of the existing power amplifier architecture;

[0022] Figure 7 This is a simulation schematic diagram of a distributed modulation power amplifier example built based on the present invention;

[0023] Figure 8 The simulation results are for a distributed modulation power amplifier embodiment. Detailed Implementation

[0024] The following is in conjunction with the appendix Figure 1-8 The present invention will be described in further detail below.

[0025] Example: A distributed modulation power amplifier, compared to existing wideband large backoff power amplifiers (see...) Figure 2 This power amplifier architecture features wideband operation and achieves dynamic range extension through a distributed load modulation architecture. For example... Figure 1-8 As shown, it includes a Doherty power amplifier for local modulation and a balanced power amplifier for global modulation.

[0026] The locally modulated Doherty power amplifier includes an RF signal input terminal 1, a power divider, sub-power amplifiers D3 and D4, and a load modulation network. The RF signal input terminal 1 inputs the RF signal to the two sub-power amplifiers D3 and D4 through the power divider. After amplification, the signal is combined through the load modulation network.

[0027] The balanced power amplifier includes an RF signal input terminal 2, an input coupler, sub-amplifiers D3 and D4, and an output coupler; the input coupler is a 90° input coupler, and the output coupler is a 90° output coupler.

[0028] The output of the Doherty amplifier is connected to the isolation port (port #3) of the balanced amplifier output coupler; a phase compensation line is provided before the local Doherty amplifier or the balanced amplifier to adjust the phase difference between the local Doherty and the balanced amplifier.

[0029] The input signal of the Doherty power amplifier is sent to carrier amplifier D3 and peak amplifier D4 via a power divider. After power amplification, the power is output to the isolation port of the 90° output coupler of the balanced amplifier through a load modulation network. The input signal of the balanced amplifier is sent to sub-amplifiers D1 and D2 through a 90° input coupler. After power amplification, the signal is sent to ports #1 and #2 of the 90° output coupler, respectively. In the optimal design, the entire distributed modulation amplifier outputs power to the load through port #4 of the 90° output coupler. Sub-amplifier D3 is the carrier amplifier, and sub-amplifier D4 is the peak amplifier.

[0030] To enable the partially loaded modulated balanced amplifier to have a wider dynamic range, this invention biases the D1 and D2 of the balanced power amplifier in Class C, while the Doherty peak path D4 is also biased in Class C. That is, in the low power region, only the main path D3 in the Doherty branch works, reducing additional power consumption.

[0031] The two sub-amplifier current sources in the balanced branch can be described as follows:

[0032] (1)

[0033] in, I max The maximum current of the sub-amplifier transistor is represented by θ = 90°, which is the phase difference between the two paths of the balanced amplifier. α represents the normalized input amplitude of the balanced branch. The overall Doherty power amplifier can utilize current sources. I D The relationship between the port voltage and current of a 90° coupler is represented as follows:

[0034] (2)

[0035] in, V D1 、V D2 、V L and V D These are the voltages at ports #1, #2, #3, and #4 of the output coupler, respectively. I D1 、I D2 、I L and I D These represent the voltages at ports #1, #2, #3, and #4 of the output coupler, respectively. Through derivation, the relationship between the output voltages at the two output ports and the normalized input amplitude and phase difference can be obtained as follows:

[0036] (3)

[0037] (4)

[0038] Equation (4) indicates that the load impedance of the Doherty power amplifier is always... Z 0. It is precisely this characteristic that causes oversaturation in the main circuit of a time-load-modulated balanced power amplifier throughout the high-power region due to the lack of load modulation. This problem can be avoided through the concept of partial load modulation, and this invention employs a Doherty power amplifier to achieve this partial load modulation. Although Z D3 While remaining constant across the entire power range, the Doherty incorporates localized modulation to prevent oversaturation of the sub-amplifiers. Furthermore, it is precisely... Z D3 The invariant characteristic of the Doherty amplifier means that the load of the Doherty amplifier remains constant, so it can be implemented according to the existing broadband design method. On the other hand, the load of the balanced amplifier is modulated by the local Doherty amplifier, as shown in formula (3). However, the balanced amplifier is biased in Class C, so only saturation power matching is required. According to formula (3), the impedance of the balanced amplifier at saturation power can be obtained, and then broadband matching technology can be used to realize the broadband balanced amplifier.

[0039] In summary, the isolation characteristics of the coupler's isolation ports simplify the design of the partially load-modulated balanced amplifier into two relatively independent modules. The Doherty module's local modulation avoids branch oversaturation while significantly expanding the operating bandwidth. Compared to existing power amplifier architectures, the partially modulated power amplifier, comprising one main power amplifier and three peak power amplifiers, has the potential for a larger dynamic range. If sub-amplifiers of the same power level are used, the relationship between the back-off of the load-modulated power amplifier and the number of peak branches can be expressed as:

[0040] (5)

[0041] In the formula, OBO represents the backoff amount, and n represents the number of peak branches. According to formula (5). Figure 4 The diagram illustrates a comparison between the backoff of the partially loaded modulated power amplifier of this invention and existing power amplifier architectures. It can be seen that compared to the 6 dB backoff of the Doherty power amplifier and the 9 dB backoff of the timing-loaded modulated balanced power amplifier, the partially loaded modulated power amplifier can achieve a dynamic range of 12 dB or more, which is in line with the characteristics of modern wireless communication.

[0042] The distributed modulation power amplifier architecture proposed in this embodiment of the invention comprises two modules: a locally modulated Doherty power amplifier and a globally modulated balanced power amplifier. Figure 5 A simulation schematic diagram of a distributed modulation power amplifier embodiment is shown, in which transistors D1-D4 are all CGH40010F.

[0043] Specifically, this partial modulation embodiment operates at 2 GHz.

[0044] Specifically, the carrier voltage of the locally modulated Doherty power amplifier and the gate voltage of the peak sub-power amplifier are -3 V and -4.5 V, respectively, while the gate bias voltage of the globally modulated balanced power amplifier is -5.5 V. This bias voltage setting ensures that the turn-on time of each sub-power amplifier is different, thus making load modulation easier to achieve.

[0045] Specifically, since the transistors in the embodiments have parasitic properties due to package parameters, while the theoretical analysis assumes that the transistors are ideal current sources, the embodiments depackage the transistors to eliminate the influence of parasitic properties and package parameters.

[0046] Specifically, in the embodiment, the sectional modulation power amplifier uses an ideal power divider, coupler, and microstrip line.

[0047] Specifically, the load modulation network of the local Doherty power amplifier consists of three microstrip lines, such as... Figure 5 As shown.

[0048] Specifically, in order to ensure the normal operation of the local Doherty power amplifier, a 90° phase compensation line is inserted before the main power amplifier D3 to ensure in-phase power synthesis between the main and auxiliary channels.

[0049] Specifically, to ensure maximum output power, a 270° phase compensation line is inserted before the locally modulated Doherty power amplifier.

[0050] Specifically, the input matching network of the distributed modulation power amplifier adopts a multi-strip line structure to match the optimal source impedance of the transistor to 50 ohms.

[0051] Specifically, the characteristic impedance Z0 of the output 90° coupler of the balanced power amplifier is 10 ohms. Therefore, in this embodiment, a post-matching network is introduced to match the 50 ohms to 10 ohms.

[0052] Specifically, to achieve a 12 dB backoff, the drain bias voltage of the Doherty power amplifier is set to 14 V, and the drain bias voltage of the globally modulated balanced power amplifier is set to 30 V.

[0053] Figure 8 Simulation data of the drain efficiency and gain of the designed partially loaded modulated balanced amplifier at different frequencies are shown. It can be seen that the partially loaded modulated power amplifier exhibits a very significant improvement in backoff efficiency.

[0054] As can be seen from the above embodiments, the distributed modulation power amplifier architecture proposed in this invention includes one main power amplifier and three peak power amplifiers, and has a larger dynamic range.

[0055] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

Claims

1. A power amplifier with distributed modulation, characterized in that: This includes Doherty power amplifiers for local modulation and balanced power amplifiers for global modulation. The locally modulated Doherty power amplifier includes an RF signal input terminal, a power divider, sub-power amplifiers D3 and D4, and a load modulation network. The RF signal input terminal inputs the RF signal to the two sub-power amplifiers D3 and D4 through the power divider, and after amplification, it is synthesized through the load modulation network. The balanced power amplifier includes an RF signal input terminal 2, an input coupler, sub-power amplifiers D1 and D2, and an output coupler. The output of the Doherty amplifier is connected to the isolation port (port #3) of the output coupler of the balanced amplifier; a phase compensation line is provided before the locally modulated Doherty amplifier or the balanced amplifier to adjust the phase difference between the local Doherty and the balanced amplifier.

2. The power amplifier with distributed modulation according to claim 1, characterized in that: Sub-amplifiers D1, D2, D3, and D4 are each equipped with a broadband input matching network, an active transistor, and a broadband output matching network connected in series. The active transistor is equipped with a gate bias circuit and a drain bias circuit. The broadband input matching network matches the optimal source impedance of the active transistor to the system impedance. The broadband output matching network matches the optimal load impedance of the active transistor to the system impedance.

3. The power amplifier with distributed modulation according to claim 2, characterized in that: The broadband output matching networks of the two sub-amplifiers D1 and D2 of the balanced power amplifier are connected to ports #1 and #2 of the output coupler, respectively.

4. A power amplifier with distributed modulation according to claim 2, characterized in that: The broadband output matching network of the two sub-amplifiers D3 and D4 of the Doherty amplifier is connected to the isolation port of the output coupler through a load modulation network; the two sub-amplifiers of the Doherty amplifier are carrier amplifier D3 and peak amplifier D4.

5. A power amplifier with distributed modulation according to claim 2, characterized in that: The gate bias circuit and the drain bias circuit are implemented using microstrip lines, enabling the DC power supply to provide a stable operating voltage for the active transistor.

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