Testing device and testing method for multi-node management board

Abstract

The embodiments of the present application provide a test device and a test method for a multi-node management board, which relate to the field of chip testing technology and are used to reduce the number of control nodes when testing a multi-node management board, thereby reducing material costs. The test device includes: a control node and a switching unit. The control node is used to generate a test signal; the switching unit has a first signal end and multiple second signal ends; the first signal end is electrically connected to the control node, and the multiple second signal ends are electrically connected to the multiple node connection ends in a one-to-one correspondence; the switching unit is used to: receive the test signal through the first signal end, and transmit the test signal of the first signal end to different second signal ends in a time-sharing manner to test the multiple node connection ends of the multi-node management board. The above-mentioned test device is used to test the multi-node management board.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of chip testing technology, and in particular to a testing device and a testing method for a multi-node management board. Background Art

[0002] As users' computing demands for computers increase, multi-node servers have emerged. A multi-node server refers to a server with multiple server nodes.

[0003] In addition, a multi-node management board is also provided in the multi-node server, and one node of the multi-node management board needs to be electrically connected to the mainboard of one server node. In the prior art, the material cost of testing the multi-node management board is relatively high. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a testing device and a testing method for a multi-node management board, which are used to reduce the number of control nodes when testing the multi-node management board, thereby reducing the testing cost.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0006] On the one hand, a test device board is provided. The test device board is used to test a multi-node management board; wherein the multi-node management board includes multiple node connection terminals. The test device includes: a control node and a switching unit. The control node is used to generate a test signal. The switching unit has a first signal terminal and multiple second signal terminals; the first signal terminal is electrically connected to the control node, and the multiple second signal terminals are electrically connected to the multiple node connection terminals in a one-to-one correspondence; the switching unit is used to: receive the test signal through the first signal terminal, and transmit the test signal of the first signal terminal to different second signal terminals in a time-sharing manner to test the multiple node connection terminals of the multi-node management board.

[0007] In the aforementioned multi-node management board, the switching unit can time-share the test signal of a control node to different second signal terminals. Therefore, only one control node is required to complete the testing of multiple node connection terminals, thereby reducing the number of control nodes and the material cost of the testing device. Furthermore, the control node only needs to be started once to complete the testing of multiple node connection terminals. Therefore, the system startup time is shortened, which reduces the testing time of the multi-node management board. For example, the control node can include the mainboard of the server node.

[0008] In some embodiments, the switching unit includes a switch controller and at least one switch chip. Any of the switch chips is electrically connected between the first signal terminal and the plurality of second signal terminals. The switch controller is electrically connected to the control node and the at least one switch chip. The control node is further configured to generate a selection signal. The switch controller is configured to control the at least one switch chip to connect the first signal terminal to the second signal terminal corresponding to the selection signal based on the selection signal.

[0009] Among them, the switch controller can control the first signal end and the second signal end corresponding to the selection signal to be connected according to the selection signal, so that the corresponding node connection end can receive the test signal, thereby transmitting the test signal to multiple node connection ends in a time-sharing manner.

[0010] In some embodiments, the types of all the switch chips in the switching unit include at least two types; the test signal includes at least two different test sub-signals; one test sub-signal corresponds to one switch chip, and the same test sub-signal can be transmitted to different second signal terminals through the corresponding switch chip in a time-sharing manner.

[0011] By enabling the same test sub-signal to be transmitted to different second signal terminals through the corresponding switch chip in a time-sharing manner, mutual interference between different types of test sub-signals can be avoided.

[0012] In some embodiments, the at least one switch chip includes a first switch chip and a second switch chip; the first switch chip and the second switch chip are of different types; the first signal end includes a first interface group and a second interface group, and the first switch chip is electrically connected to the control node through the first interface group; the second switch chip is electrically connected to the control node through the second interface group; each second signal end includes a third interface group and a fourth interface group; the first switch chip is connected to each node connection end through each third interface group, and the second switch chip is connected to each node connection end through each fourth interface group.

[0013] Among them, by making the first switch chip transmit the signal received by the first interface group to the third interface group, and the second switch chip transmits the signal received by the second interface group to the fourth interface group, the signal received by the first interface group and the signal received by the second interface group can be transmitted on different switch chips, thereby avoiding mutual interference between the signal received by the first interface group and the signal received by the second interface group.

[0014] In some embodiments, the first interface group and the third interface group each include at least one high-speed interface, and the high-speed interface is used to transmit high-speed sub-signals; the second interface group and the fourth interface group each include at least one low-speed interface, and the low-speed interface is used to transmit low-speed sub-signals.

[0015] Among them, the high-speed sub-signal is transmitted through the first switch chip, and the low-speed sub-signal can be transmitted through the second switch chip. Therefore, it is possible to avoid the high-speed sub-signal and the low-speed sub-signal being transmitted on the same switch chip, thereby avoiding large interference between the high-speed sub-signal and the low-speed sub-signal.

[0016] In some embodiments, the first interface group and the third interface group each include at least one of an SGMII (Serial Gigabit Media Independent Interface) interface and a USB (Universal Serial Bus) interface. The second interface group and the fourth interface group each include at least one of an I2C (Inter-Integrated Circuit) interface, an MDIO (Management Data Input / Output) interface, a JTAG (Joint Test Action Group) interface, a GPIO (General-Purpose Input / Output) interface, a UART (Universal Asynchronous Receiver / Transmitter) interface, and a VGA (Video Graphics Array) interface.

[0017] In some embodiments, the control node includes a management control unit and a processing unit electrically connected to the management control unit; the control node includes a first type interface group electrically connected to the management control unit and a second type interface group electrically connected to the processing unit; the test signal includes a first test signal and a second test signal; the management control unit is used to generate the first test signal, and output it by the first type interface group; the management control unit is also used to control the processing unit to generate the second test signal, and output it by the second type interface group.

[0018] Among them, the types of interfaces connected to the management control unit and the processing unit are different. Therefore, by setting the management control unit and the processing unit in the control node, more interfaces can be set in the control node, so that more interfaces in the node connection end can be tested, making the test results of the multi-node pipe riser more reliable.

[0019] In some embodiments, the first interface group includes: at least one of: an I2C interface, a UART interface, an MDIO interface, a VGA interface, an SGMII interface, and a USB interface; the second interface group includes: at least one of: a GPIO interface and a JTAG interface.

[0020] In some embodiments, the management control unit includes a BMC (Baseboard Management Controller) chip; the processing unit includes a CPLD (Complex Programmable Logic Device) chip.

[0021] In another aspect, a method for testing a multi-node management board is provided. The method comprises electrically connecting multiple second signal terminals of the test device provided in some of the above embodiments to multiple node connection terminals of the multi-node management board in a one-to-one correspondence. A control node of the test device generates a test signal. A switching unit of the test device sequentially transmits the test signal to each node connection terminal to test the multiple node connection terminals of the multi-node management board.

[0022] In the above-mentioned testing method of the multi-node management board, the switching unit can transmit the test signal to different second signal ends in a time-sharing manner. Therefore, only one control node is required to complete the testing of multiple node connection ends, thereby reducing the number of control nodes and reducing the material cost of the testing device.

[0023] In some embodiments, the method for testing a multi-node management board further includes: the control node generating a plurality of selection signals. The step of the switching unit of the testing device sequentially transmitting the test signals to each node connection terminal includes: the switch controller controlling each of the switch chips to connect the first signal terminal and the second signal terminal corresponding to the selection signal based on the selection signal, thereby sequentially transmitting the test signals to the plurality of node connection terminals.

[0024] Among them, the switch controller can control the first signal end and the second signal end corresponding to the selection signal to be connected according to the selection signal, so that the corresponding node connection end can receive the test signal, thereby transmitting the test signal to multiple node connection ends in a time-sharing manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings required for use in some embodiments of this application. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of this application.

[0026] Figure 1 This is a structural block diagram of a mainboard electrically connected to a fan management board according to the prior art;

[0027] Figure 2 is a structural block diagram of a test device electrically connected to a multi-node management board according to some embodiments;

[0028] Figure 3 for Figure 2 The control node of the provided test device includes a structural block diagram of a management control unit and a processing unit;

[0029] Figure 4 for Figure 2 The switching unit of the provided test device includes a structural block diagram of a switch controller and a switch chip;

[0030] Figure 5 for Figure 2 The switching unit of the provided test device includes a structural block diagram of four second signal terminals;

[0031] Figure 6 for Figure 2 The switching unit of the provided test device includes a structural block diagram of two switch chips;

[0032] Figure 7 for Figure 4 The provided switch chip includes a structural block diagram of multiple conductive path groups;

[0033] Figure 8 This is the internal circuit diagram of the MAX14979 chip;

[0034] Figure 9 This is the internal circuit diagram of the MAX333 chip;

[0035] Figure 10 for Figure 4 The control node of the provided test device includes a structural block diagram of a management control unit and a processing unit;

[0036] Figure 11 is a flowchart of a method for testing a multi-node management board according to some embodiments;

[0037] Figure 12 Another flowchart of a method for testing a multi-node management board according to some embodiments;

[0038] Figure 13 The figure is a block diagram of the connection structure of a test device, a multi-node management board, and an external device according to some embodiments. DETAILED DESCRIPTION

[0039] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example" or "some examples" are intended to indicate that the specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0040] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0041] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0042] The fan management board is an indispensable board in the server. It is mainly responsible for controlling the fan. It can also serve as an adapter board between the motherboard and external devices. That is, the motherboard can be electrically connected to external devices through the fan management board.

[0043] For a multi-node server, a fan management board needs to be connected to multiple mainboards. The fan management board is provided with multiple node connection terminals, one of which is used to connect to one mainboard.

[0044] Before the fan management board is assembled into the electronic device, it needs to be tested. The fan management board that passes the test can be assembled into the electronic device, thereby improving the phenomenon of malfunction of the fan management board in the electronic device.

[0045] Figure 1 The figure is a structural block diagram of a mainboard electrically connected to a fan management board according to the prior art.

[0046] See also Figure 1 In the prior art, when testing a fan management board, multiple mainboards are used to connect to the fan management board's multiple node connection terminals. For example, if a fan management board has two node connection terminals, two mainboards are required to electrically connect to the two node connection terminals. The multiple mainboards can each generate a test signal and transmit it to the multiple node connection terminals, thereby testing the multiple node connection terminals and completing the fan management board test.

[0047] Therefore, in the prior art, when testing a fan management board, multiple mainboards are required, resulting in a large number of mainboards and high testing costs. In addition, when testing a fan management board, the test systems on multiple mainboards are activated separately, which makes the testing of multiple fan management boards take a long time.

[0048] Based on this, an embodiment of the present application provides a testing device 200 .

[0049] Figure 2 FIG. 2 is a structural block diagram of a test device 200 electrically connected to a multi-node management board 100 according to some embodiments.

[0050] See also Figure 2 The testing device 200 is used to test a multi-node management board 100. The multi-node management board 100 includes a plurality of node connection terminals 110. In some examples, the multi-node management board 100 may be a fan management board.

[0051] The testing device 200 may include a control node 210 and a switching unit 220. The switching unit 220 has a first signal terminal 221 and multiple second signal terminals 222. The first signal terminal 221 is electrically connected to the control node 210, and the multiple second signal terminals 222 are electrically connected to the multiple node connection terminals 110 in a one-to-one correspondence. The switching unit 220 is configured to receive a test signal via the first signal terminal 221 and transmit the test signal from the first signal terminal 221 to different second signal terminals 222 in a time-sharing manner to test the multiple node connection terminals 110 of the multi-node management board 100.

[0052] The control node 210 stores a test program, and the control node 210 can generate a test signal according to the test program. The test signal generated by the control node 210 can be used to test each node connection terminal 110.

[0053] For example, the control node 210 may include a mainboard of a server node.

[0054] For example, the switching unit 220 may be a switching circuit board.

[0055] The plurality of second signal terminals 222 are electrically connected to the plurality of node connection terminals 110 in a one-to-one correspondence. Therefore, the number of the second signal terminals 222 and the number of the node connection terminals 110 can be the same. In the embodiment of the present application, the number of the second signal terminals 222 is not limited. Figure 2 In the figure, the switching unit 220 includes two second signal terminals 222 to illustrate the testing device 200 provided in some embodiments of the present application.

[0056] In some examples, the control node 210 may include an interface, and correspondingly, the first signal terminal 221 may include an interface, each second signal terminal 222 may also include an interface, and each node connection terminal 110 may also include an interface.

[0057] In other examples, the control node 210 may include multiple interfaces. Accordingly, the first signal terminal 221 also includes multiple interfaces, each second signal terminal 222 also includes multiple interfaces, and the node connection terminal 110 also includes multiple interfaces. In this case, the test signal may include multiple test sub-signals, one interface of the control node 210 is used to transmit one test sub-signal, and one interface of each node connection terminal 110 may be used to receive one test sub-signal.

[0058] The interfaces included in the control node 210 , the first signal terminal 221 , each second signal terminal 222 , and each node connection terminal 110 correspond to each other, that is, the types and quantities of the included interfaces may be the same.

[0059] For example, if the control node 210 includes multiple USB interfaces, the first signal terminal 221 and each second signal terminal 222 also include multiple USB interfaces, and the number of USB interfaces in the first signal terminal 221 and each second signal terminal 222 is the same as the number of USB interfaces in the control node 210. In this case, the control node 210 can test the multi-node management board 100 in which each node connection terminal 110 includes multiple USB interfaces.

[0060] In this example, each interface in each node connection terminal 110 can be different. In this case, each interface can receive a different test sub-signal. In addition, some of the multiple interfaces of a node connection terminal 110 can be the same type of interface. In this case, multiple interfaces of the same type can receive the same test sub-signal or different test sub-signals.

[0061] In some examples, multiple node connection terminals 110 are identical. In this case, each node connection terminal 110 includes the same type and number of interfaces. It is understood that since the multiple second signal terminals 222 are connected to the multiple node connection terminals 110 in a one-to-one correspondence, each second signal terminal 222 is identical. In this case, the multiple test sub-signals received by each node connection terminal 110 can be identical.

[0062] The control node 210 is electrically connected to the first signal terminal 221 , so that the first signal terminal 221 can receive a test signal sent by the control node 210 .

[0063] In some examples, the switching unit 220 can electrically connect different second signal terminals 222 to the first signal terminal 221, respectively, so as to transmit the test signal received by the first signal terminal 221 to different second signal terminals 222 in a time-sharing manner, wherein the time-sharing transmission of the test signal to different second signal terminals 222 can be understood as that the test signal can be sent to multiple second signal terminals 222 at different times.

[0064] The plurality of second signal terminals 222 correspond to and are electrically connected to the plurality of node connection terminals 110, respectively. Therefore, the plurality of node connection terminals 110 can receive test signals from the plurality of second signal terminals 222. Therefore, the switching unit 220 can send the test signal sent by a control node 210 to the plurality of node connection terminals 110, thereby testing the plurality of node connection terminals 110 and the multi-node management board 100.

[0065] In the aforementioned testing device 200, the switching unit 220 can time-share the test signal of a control node 210 to different second signal terminals 222. Therefore, only one control node 210 is required to complete the testing of multiple node connection terminals 110, thereby reducing the number of control nodes 110 and lowering testing costs. Furthermore, the control node 210 only needs to be started once to complete the testing of multiple node connection terminals 110. This shortens the system startup time and reduces the testing time of the multi-node management board 100.

[0066] The control node 210 is introduced below.

[0067] Figure 3 for Figure 2The control node 210 of the provided testing device 200 includes a structural block diagram of a management control unit 212 and a processing unit 213 .

[0068] See also Figure 3 In some embodiments, the control node 210 includes a management control unit 212 and a processing unit 213 electrically connected to the management control unit 212 .

[0069] In some examples, the management control unit 212 may include a BMC chip.

[0070] In some examples, the processing unit 213 may include a CPLD chip, which is programmable, highly flexible, low in power consumption, and relatively low in cost.

[0071] In some examples, the management control unit 212 and the processing unit 213 may be integrated on a mainboard.

[0072] The control node 210 includes a first-type interface group 214 electrically connected to a management control unit 212. The test signal includes a first test signal. The management control unit 212 is configured to generate the first test signal, which is outputted via the first-type interface group 214. The first-type interface group 214 can be electrically connected to a first signal terminal 221 so that the first signal terminal 221 receives the first test signal.

[0073] In some examples, the first type interface group 214 may include one or more interfaces, and correspondingly, the first test signal includes one or more test sub-signals.

[0074] In some examples, the multiple interfaces included in the first interface group 214 may all be high-speed interfaces. In this case, the test sub-signals included in the first test signal are all high-speed sub-signals, wherein the high-speed interfaces are used to transmit high-speed sub-signals. For example, the high-speed sub-signals may be high-speed differential signals.

[0075] In other examples, one or more first interfaces included in the first interface group 214 may all be low-speed interfaces. In this case, the multiple test sub-signals included in the first test signal are all low-speed sub-signals, wherein the low-speed interface is used to transmit the low-speed sub-signals. For example, the low-speed sub-signals may be low-speed single-ended signals.

[0076] In some other examples, the first interface group 214 may include two types of interfaces: a high-speed interface and a low-speed interface. In this case, the first test signal includes both a high-speed sub-signal and a low-speed sub-signal.

[0077] In some embodiments, the first interface group 214 includes at least one of an I2C interface, a UART interface, an MDIO interface, a VGA interface, an SGMII interface, and a USB interface. The I2C interface, the UART interface, the MDIO interface, and the VGA interface are high-speed interfaces, while the SGMII interface and the USB interface are low-speed interfaces.

[0078] In some examples, multiple interfaces of the first interface group 214 are integrated on a mainboard.

[0079] In some embodiments, the control node 210 also includes a second type interface group 215 electrically connected to the processing unit 213, the test signal also includes a second test signal, the management control unit 212 can also be used to control the processing unit 213 to generate a second test signal, and output it by the second type interface group 215, the second type interface group 215 can be electrically connected to the first signal end 221 so that the first signal end 221 receives the second test signal.

[0080] In some examples, the second interface group 215 may include one or more first interfaces, and correspondingly, the second test signal includes one or more test sub-signals. For example, the interfaces included in the second interface group 215 may be different from the interfaces included in the first interface group 214.

[0081] In some examples, the multiple first interfaces included in the second type interface group 215 may all be high-speed interfaces. In this case, the test sub-signals included in the second test signal are all high-speed sub-signals.

[0082] In other examples, the multiple first interfaces included in the second type interface group 215 may all be low-speed interfaces. In this case, the multiple test sub-signals included in the second test signal are all low-speed sub-signals.

[0083] In some other examples, the second interface group 215 may include two types of interfaces: high-speed interfaces and low-speed interfaces. In this case, the second test signal includes both high-speed sub-signals and low-speed sub-signals.

[0084] In some embodiments, the second interface group 215 includes at least one of a GPIO interface and a JTAG interface, wherein both the GPIO interface and the JTAG interface are low-speed interfaces.

[0085] In some examples, the interfaces included in the second interface group 215 may be integrated on a mainboard.

[0086] In some of the above embodiments, the types of interfaces connected to the management control unit 212 and the types of interfaces connected to the processing unit 213 are different. Therefore, by setting the management control unit 212 and the processing unit 213 in the control node 210, more interfaces can be set in the control node 210, thereby testing more interfaces in the node connection end 110, making the test results of the multi-node management board 100 more reliable.

[0087] In some of the above embodiments, the control node 210 is introduced, and the switching unit 220 is introduced next.

[0088] Figure 4 for Figure 2 The switching unit 220 of the provided testing device 200 includes a switch controller 223 and a switch chip 224 . Figure 4 A switch chip 224 is used as an example for illustration.

[0089] See also Figure 4 In some embodiments, the switching unit 220 includes: a switch controller 223 and at least one switch chip 224. The switch controller 223 is electrically connected to the at least one switch chip 224, that is, the switch controller 223 can be electrically connected to all switch chips 224, thereby controlling all switch chips 224. Any switch chip 224 is electrically connected between the first signal terminal 221 and the plurality of second signal terminals 222. In the embodiments of the application, there is no limit on the number of switch chips 224. Figure 4 In the figure, some embodiments of the present application are illustrated by taking the switching unit 220 including a switch chip 224 as an example.

[0090] In some examples, the switch controller 223 and the at least one switch chip 224 may be disposed on a circuit board.

[0091] The control node 210 is further configured to generate a selection signal, and the switch controller 223 is electrically connected to the control node 210 to receive the selection signal. Based on the selection signal, the switch controller 223 controls at least one switch chip 224 to connect the first signal terminal 221 to the second signal terminal 222 corresponding to the selection signal, thereby enabling the test signal to be transmitted from the first signal terminal 221 to any second signal terminal 222, thereby enabling the corresponding node connection terminal 110 to receive the test signal.

[0092] The at least one switch chip 224 can connect any second signal terminal 222 to the first signal terminal 221 , wherein multiple second signal terminals 222 are connected to the first signal terminal 221 at different times, so that multiple second signal terminals 222 receive test signals at different times.

[0093] When the first signal terminal 221 and each second signal terminal 222 include multiple interfaces, the switch controller 223 can control at least one switch chip 224 according to the selection signal, so that all interfaces in the second signal terminal 222 corresponding to the selection signal are electrically connected one-to-one with all interfaces in the first signal terminal 221, so that multiple test sub-signals are respectively transmitted to the multiple interfaces in the second signal terminal 222.

[0094] The switch controller 223 may generate a control instruction based on the selection signal and send the control instruction to the switch chip 224 to control the switch chip 224. At this time, the switch controller 223 may send the control instruction to at least some of the switch chips 224 to control at least some of the switch chips 224.

[0095] In some examples, the switch controller 223 may be an IO (Input / Output) expansion chip, wherein the IO expansion chip may have multiple IO pins, and the switch controller 223 may be electrically connected to the control node 210 via at least some of the multiple IO pins. For example, the IO pins of the switch controller 223 may be electrically connected to the control node 210 via an I2C bus. For example, the switch controller 223 may be a PCA9555 chip, which has 16 IO pins.

[0096] For example, the selection signal is a level signal, and the control node 210 sends different level signals to the IO pin of the switch controller 223, thereby changing the level of the IO pin of the switch controller 223. The switch controller 223 can control each switch chip 224 according to the different level signals, so that different second signal terminals 222 are electrically connected to the first signal terminal 221.

[0097] In some examples, the number of selection signals can be the same as the number of second signal terminals 222. Figure 4 In the example given, the number of the second signal terminals 222 is two, and the number of the node connection terminals 110 is two. In this case, the control node 210 can generate two selection signals.

[0098] Some embodiments of the present application are introduced below based on an example in which the number of the second signal terminals 222 is two.

[0099] See also Figure 4 In some examples, the multiple second signal terminals 222 of the switching unit 220 include a first second signal terminal 222A and a second second signal terminal 222B, and the multiple node connection terminals 110 of the multi-node management board 100 include a first node connection terminal 110A and a second node connection terminal 110B.

[0100] The control node 210 may generate a first selection signal and a second selection signal, wherein the first selection signal corresponds to the first second signal terminal 222A and the first node connection terminal 110A, and the second selection signal corresponds to the second second signal terminal 222B and the second node connection terminal 110B.

[0101] When the switch controller 223 receives the first selection signal, it can control the first signal terminal 221 to be electrically connected to the first second signal terminal 222A, so that the test signal can be transmitted to the first second signal terminal 222A and then to the first node connection terminal 110A.

[0102] When the switch controller 223 receives the second selection signal, it can control the first signal terminal 221 to be electrically connected to the second second signal terminal 222B, so that the test signal can be transmitted to the second second signal terminal 222B respectively, and then transmitted to the second node connection terminal 110B.

[0103] When there are two second signal terminals 222, one of the first selection signal and the second selection signal can be a high-level signal, and the other can be a low-level signal. The high-level signal has a higher level than the low-level signal. The control node 210 can be electrically connected to an IO pin of the switch controller 223.

[0104] The number of the second signal terminals 222 may be two, four, eight, or more, which are not listed here one by one. The following takes the example of four second signal terminals 222 to introduce some embodiments of the present application.

[0105] Figure 5 for Figure 2 The switching unit 220 of the provided testing device 200 includes a structural block diagram of four second signal terminals 222 .

[0106] See also Figure 5 The switch unit 220 includes four second signal terminals 222. In this case, the test device 200 can test a multi-node management board 100 having four node connection terminals 110. When testing the multi-node management board 100, the four second signal terminals 222 can correspond to and be electrically connected to the four node connection terminals 110. In this case, the control node 210 can generate four selection signals.

[0107] When there are four second signal terminals 222, the selection signal can include two level signals. In this case, the two IO pins of the switch controller 223 can be electrically connected to the control node 210, so that both IO pins can receive the level signal. In this case, if the IO pin of the switch controller 223 receives a high-level signal, it can be recorded as 1, and if the IO pin of the switch controller 223 receives a low-level signal, it can be recorded as 0. In this example, the signals received by the switch controller 223 can include the following four cases: 00, 01, 10, and 11. These four cases correspond to the four selection signals, respectively.

[0108] When the number of node connection terminals 110 is 8, the three IO pins of the switch controller 223 can be used to receive level signals. At this time, the signals received by the switch controller 223 can include the following eight situations: 000, 010, 001, 011, 100, 101, 110, and 111, and the above eight situations correspond to eight selection signals respectively.

[0109] When the number of the second signal terminals 222 is greater than 2, the switch chip 224 may include a multiplexer.

[0110] In some embodiments, all switch chips 224 in the switching unit 220 include at least two types, and the at least two types of switch chips 224 are respectively used to transmit different types of test sub-signals.

[0111] The test signal includes at least two different test sub-signals. One test sub-signal corresponds to one switch chip 224 , and the same test sub-signal can be transmitted to different second signal terminals 222 in a time-sharing manner through the corresponding switch chip 224 .

[0112] There are multiple switch chips 224 of each type, and each test sub-signal may include multiple different test sub-signals.

[0113] Illustratively, the at least two different test sub-signals include a high-speed sub-signal and a low-speed sub-signal. One of the at least two switch chips 224 is used to transmit the high-speed sub-signal, and the other is used to transmit the low-speed sub-signal. Illustratively, the high-speed sub-signal is a high-speed differential signal, and the low-speed sub-signal is a low-speed single-ended signal. The high-speed sub-signal is transmitted on two wires, and the signals transmitted on the two wires have equal amplitudes and opposite phases. The low-speed sub-signal is transmitted on only one wire, plus a reference wire, i.e., a ground wire.

[0114] The number of high-speed sub-signals in all the test sub-signals may be one or more, and the number of low-speed sub-signals in all the test sub-signals may also be one or more.

[0115] In some of the above examples, by enabling the same test sub-signal to be transmitted to different second signal terminals 222 through the corresponding switch chip 224 in a time-sharing manner, mutual interference between different types of test sub-signals can be avoided.

[0116] Figure 6 for Figure 2 The switching unit 220 of the provided testing device 200 includes a structural block diagram of two switch chips 224 .

[0117] See also Figure 6 The at least one switch chip 224 includes a first switch chip 224A and a second switch chip 224B; the first switch chip 224A and the second switch chip 224B are of different types. The first signal terminal 221 includes a first interface group 2211, through which the first switch chip 224A is electrically connected to the control node 210. Each second signal terminal 222 includes a third interface group 2221, through which the first switch chip 224A is connected to each node connection terminal 110.

[0118] Therefore, the first switch chip 224A is electrically connected between the first signal terminal 221 and each of the third interface groups 2221 , wherein each of the third interface groups 2221 is electrically connected to a different node connection terminal 110 .

[0119] The first signal terminal 221 includes a second interface group 2212, and the second switch chip 224B is electrically connected to the control node 210 via the second interface group 2212. Each second signal terminal 222 includes a fourth interface group 2222. The second switch chip 224B is connected to each node connection terminal 110 via each fourth interface group 2222. Therefore, the second switch chip 224B is electrically connected between the second interface group 2212 and each fourth interface group 2222. Each fourth interface group 2222 is electrically connected to a different node connection terminal 110.

[0120] In which, in the switching unit 220, by making the first switch chip 224A transmit the signal received by the first interface group 2211 to the third interface group 2221, and the second switch chip 224B transmits the signal received by the second interface group 2212 to the fourth interface group 2222, the signal received by the first interface group 2211 and the signal received by the second interface group 2212 can be transmitted on different switch chips 224, thereby avoiding mutual interference between the signal received by the first interface group 2211 and the signal received by the second interface group 2212.

[0121] In some embodiments, the first interface group 2211 and the third interface group 2221 each include at least one high-speed interface for transmitting high-speed sub-signals. The first interface group 2211 and the third interface group 2221 include the same number of high-speed interfaces, and the interfaces correspond to each other.

[0122] The second interface group 2212 and the fourth interface group 2222 each include at least one low-speed interface for transmitting low-speed sub-signals. The number of low-speed interfaces included in the second interface group 2212 and the fourth interface group 2222 is the same and corresponds one to one.

[0123] Among them, the high-speed sub-signal is transmitted through the first switch chip 224A, and the low-speed sub-signal can be transmitted through the second switch chip 224B. Therefore, it can avoid that the high-speed sub-signal and the low-speed sub-signal are transmitted on the same switch chip 224, and further avoid large interference between the high-speed sub-signal and the low-speed sub-signal.

[0124] In some embodiments, the first interface group 2211 and the third interface group 2221 each include at least one of an SGMII interface and a USB interface.

[0125] The second interface group 2212 and the fourth interface group 2222 each include at least one of an I2C interface, an MDIO interface, a JTAG interface, a GPIO interface, a UART interface, and a VGA interface.

[0126] Figure 7 for Figure 4 The switch chip 224 provided includes a structural block diagram of a plurality of conductive path groups 2241 .

[0127] See also Figure 7 The at least one switch chip 224 may include a plurality of conductive path groups 2241, and a conductive path group 2241 includes a plurality of conductive paths, wherein each conductive path has two states of on and off. Figure 7 In the embodiment, a conductive path group 2241 including two conductive paths is taken as an example to illustrate some embodiments of the present application. Figure 7 In the illustrated example, two conductive path groups 2241 are located in the same switch chip 224 .

[0128] In some of the following examples, for the convenience of description, the interface of the control node 210 is defined as the first interface, the interface of the first signal terminal 221 is defined as the second interface, the interface of the second signal terminal 222 is defined as the third interface, and the interface of the node connection terminal 110 is defined as the fourth interface.

[0129] The number of conductive paths in one conductive path group 2241 may be the same as the number of second signal terminals 222 . The number of conductive path groups included in the at least one switch chip is the same as the number of second interfaces in one second signal terminal 222 .

[0130] One end of the multiple conductive pathways in a conductive pathway group 2241 can be electrically connected to a second interface of the first signal terminal 221, while the other ends can be electrically connected to multiple third interfaces, respectively. The second interface and the third interface electrically connected to a conductive pathway group 2241 are the same interface. The multiple third interfaces electrically connected to a conductive pathway group 2241 are located in the multiple second signal terminals 222. The multiple third interfaces electrically connected to a conductive pathway group 2241 can be defined as a group of third interfaces. The multiple fourth interfaces electrically connected to the group of third interfaces are located in the multiple node connection terminals 110.

[0131] When the switch controller 223 receives a selection signal, it can control a conductive path corresponding to the selection signal in each conductive path group 2241 to be turned on, wherein the conductive conductive path in each conductive path group 2241 is electrically connected to the same second signal terminal 222, so that multiple third interfaces in the second signal terminal 222 can receive the test sub-signal, and then the node connection terminal 110 corresponding to the selection signal can receive the test signal.

[0132] For example, in the case where the second signal terminal 222 includes a first second signal terminal 222A and a second second signal terminal 222B, each conductive path group 2241 includes a first conductive path and a second conductive path, wherein the first conductive path is electrically connected to the third interface in the first second signal terminal 222A, and the second conductive path is electrically connected to the interface in the second second signal terminal 222B.

[0133] When the switch controller 223 receives the first selection signal, the switch controller 223 may control the first conductive path electrically connected to the plurality of conductive path groups 2241 to be conductive, thereby electrically connecting the plurality of second interfaces on the first signal terminal 221 to the plurality of third interfaces on the first second signal terminal 222A. When the switch controller 223 receives the second selection signal, the switch controller 223 may control the second conductive path electrically connected to the plurality of conductive path groups 2241 to be conductive, thereby electrically connecting the plurality of second interfaces on the first signal terminal 221 to the plurality of third interfaces on the second second signal terminal 222B.

[0134] The following uses the MDIO interface and VGA interface as examples to illustrate some of the above examples.

[0135] See also Figure 7For example, the control node 210 includes a first MDIO interface, and correspondingly, the first signal terminal 221 includes a second MDIO interface, any second signal terminal 222 includes a third MDIO interface, and any node connection terminal 110 includes a fourth MDIO interface. The second MDIO interface may belong to the second interface group 2212 (e.g., Figure 6 ), and the third MDIO interface can be located in the fourth interface group 2222 (as shown Figure 6 shown).

[0136] A conductive path group 2241 includes a first conductive path and a second conductive path, wherein one end of the first conductive path and one end of the second conductive path are both electrically connected to the second MDIO interface in the first signal terminal 221, and the other end of the first conductive path is electrically connected to the third MDIO interface in the first second signal terminal 222A, and the other end of the second conductive path is electrically connected to the third MDIO interface in the second second signal terminal 222B.

[0137] For example, the control node 210 includes a first VGA interface, and correspondingly, the first signal terminal 221 includes a second VGA interface, any second signal terminal 222 includes a third VGA interface, and any node connection terminal 110 includes a fourth VGA interface. One end of the plurality of conductive paths in another conductive path group 2241 is electrically connected to the second VGA interface in the first signal terminal 221, and the other end is electrically connected to the third VGA interface in the plurality of second signal terminals 222. The second VGA interface can belong to the second interface group 2212 (such as Figure 6 As shown), the third VGA interface can be located in the fourth interface group 2222 (as shown Figure 6 shown).

[0138] In another conductive path group 2241, one end of the first conductive path and one end of the second conductive path are both electrically connected to the second VGA interface in the first signal terminal 221, and the other end of the first conductive path is electrically connected to the third VGA interface in the first second signal terminal 222A, and the other end of the second conductive path is electrically connected to the third VGA interface in the second second signal terminal 222B.

[0139] When the switch controller 223 receives the first selection signal, the switch controller 223 can control the first conductive path electrically connected to the multiple conductive path groups 2241 to be turned on, the second MDIO interface is electrically connected to the third MDIO interface in the first second signal end 222A, and the second VGA interface is electrically connected to the third VGA interface in the first second signal end 222A.

[0140] When the switch controller 223 receives the second selection signal, the switch controller 223 can control the second conductive path electrically connected to the multiple conductive path groups 2241 to be turned on, the second MDIO interface is electrically connected to the third MDIO interface in the second second signal end 222B, and the second VGA interface is electrically connected to the third VGA interface in the second second signal end 222B.

[0141] It should be noted that, in Figure 7 In the examples given, only the MDIO interface and the VGA interface are used to illustrate some embodiments of the present application. In some embodiments of the present application, the control node 210, the first signal terminal 221 and the second signal terminal 222 may also include other interfaces, which are not listed here one by one. Figure 7 In the example given, the switch chip 224 may be a second switch chip 224B.

[0142] The multiple conductive paths of a conductive path group 2241 can be set on the same switch chip 224 or on different switch chips 224 .

[0143] In some examples, in a conductive path group 2241 , each conductive path is provided with a switch, and the switch controller 223 can control the closing or opening of the switch to control the conductive path to be conductive or disconnected.

[0144] In other examples, one or more single-pole multi-throw switches may be included in a conductive path group 2241. For example, the single-pole multi-throw switch may be a single-pole double-throw switch. For example, in the case where a conductive path group 2241 includes two conductive paths, the conductive path group 2241 may include a single-pole double-throw switch, the fixed end of the single-pole double-throw switch is electrically connected to a second interface (for example, a second MDIO interface), and the two movable ends of the single-pole double-throw switch are respectively electrically connected to the third interface corresponding to the above-mentioned second interface in the two second signal terminals 222 (for example, a third MDIO interface), thereby forming two conductive paths between the second interface and the third interface corresponding to the second interface. At this time, the testing device 200 can test the multi-node management board 100 having two node connection terminals 110.

[0145] For example, the SPMT switch can be a SPMT analog switch. For example, the SPDT switch can be a SPDT analog switch.

[0146] Next, a specific example of the switch chip 224 is introduced.

[0147] Figure 8 This is the internal circuit diagram of the MAX14979 chip.

[0148] See also Figure 8 , and also see Figure 6 For example, the first switch chip 224A may be a MAX14979 chip. The first switch chip 224A is not limited to the MAX14979 chip, and may also be other types of analog switch chips, which are not listed here.

[0149] The switch controller 223 may be electrically connected to the SEL pin to control multiple switches in the MAX14979 chip.

[0150] The following takes the SGMII interface as an example, and when there are two second signal terminals 222 , the connection relationship between the first interface group 2211 , the third interface group 2221 , and the MAX14979 chip is described.

[0151] For example, the first interface group 2211 includes one second SGMII interface. There are two second signal terminals 222, so there are two third interface groups 2221. One third interface group 2221 includes one third SGMII interface, so there are two third SGMII interfaces.

[0152] The positive end of the second SGMII interface can be electrically connected to the COM0+ pin, the negative end of the second SGMII interface can be electrically connected to the COM0- pin, the positive end of one of the two third SGMII interfaces is electrically connected to the NC0+ pin, and the negative end is electrically connected to the NC0- pin, and the positive end of the other of the two third SGMII interfaces is electrically connected to the NO0+ pin, and the negative end is electrically connected to the NO0- pin.

[0153] Figure 9 This is the internal circuit diagram of the MAX333 chip.

[0154] See also Figure 9 , and also see Figure 6 The second switch chip 224B may be a MAX333 chip. The second switch chip 224B is not limited to the MAX333 chip, and may also be other types of analog switch chips, which are not listed here.

[0155] The switch controller 223 may be electrically connected to any one of the IN1 pin, the IN2 pin, the IN3 pin, and the IN4 pin, thereby controlling multiple switches in the MAX333 chip.

[0156] The following takes the VGA interface as an example, and when there are two second signal terminals 222 , the connection relationship between the second interface group 2212 and the fourth interface group 2222 and the MAX333 chip is introduced.

[0157] For example, the second interface group 2212 includes a second VGA interface, and the number of the second signal terminals 222 is two, therefore, the number of the fourth interface group 2222 is two, and a fourth interface group 2222 includes a third VGA interface, therefore, the number of the third VGA interfaces is two.

[0158] The second VGA interface can be electrically connected to the COM1 pin, one of the two VGA interfaces can be electrically connected to the NO1 interface, and the other of the two VGA interfaces can be electrically connected to the NC1 interface. Figure 8 In the example given, the COM1 pin may be electrically connected to the NC1 pin.

[0159] Figure 10 for Figure 4 The control node 210 of the provided testing device 200 includes a management control unit 212 and a processing unit 213 .

[0160] See also Figure 10 When the control node 210 includes a management control unit 212 and a processing unit 213, the management control unit 212 may be electrically connected to the switch controller 223. The management control unit 212 is configured to generate a selection signal and send the selection signal to the switch controller 223. For example, the management control unit 212 and the switch controller 223 may be electrically connected via an I2C bus. The I2C bus between the management control unit 212 and the switch controller 223 does not belong to the first-type interface group 214 or the second-type interface 215.

[0161] Based on the testing device 200 provided in some of the above embodiments, an embodiment of the present application further provides a testing method for a multi-node management board.

[0162] Figure 11 The present invention is a flowchart of a method for testing a multi-node management board according to some embodiments.

[0163] See also Figure 11 The method for testing a multi-node management board can be applied to the testing device 200 provided in some of the above embodiments. The method for testing a multi-node management board includes the following steps S10 to S30.

[0164] S10 , electrically connecting the plurality of second signal terminals 222 of the testing device 200 to the plurality of node connection terminals 110 of the multi-node management board 100 in a one-to-one correspondence.

[0165] Please combine Figure 2In the case where a node connection terminal 110 includes multiple fourth interfaces, the second signal terminal 222 includes multiple third interfaces. In step S10, the multiple fourth interfaces of a node connection terminal 110 are electrically connected to the multiple third interfaces of a second signal terminal 222 in a one-to-one correspondence.

[0166] S20 : ​​The control node 210 of the testing device 200 generates a test signal.

[0167] In the case where a node connection terminal 110 includes multiple interfaces, the test signal includes multiple test sub-signals. In this case, the control node 210 can generate the multiple test sub-signals in sequence.

[0168] S30 , the switching unit 220 of the testing device 200 transmits the test signal to each node connection terminal 110 in sequence to test the multiple node connection terminals 110 of the multi-node management board 100 .

[0169] The test signal is transmitted to each node connection terminal 110 in sequence, so that the multiple node connection terminals 110 of the multi-node management board 100 complete the test in sequence.

[0170] In the case where the test signal includes multiple test sub-signals, when testing a node connection terminal 110, multiple test sub-signals are generated in sequence, and then the multiple test sub-signals are transmitted in sequence to the multiple fourth interfaces in the node connection terminal 110, so as to test the multiple fourth interfaces in the node connection terminal 110 in sequence.

[0171] In the testing method of the multi-node management board provided in some embodiments of the present application, the switching unit 220 can transmit the test signal to different second signal terminals 222 in a time-sharing manner. Therefore, only one control node 210 is required to complete the testing of multiple node connection terminals 110, thereby reducing the number of control nodes 110 and lowering the testing cost.

[0172] Figure 12 Another flowchart of a method for testing a multi-node management board according to some embodiments is provided.

[0173] See also Figure 12 , and combined with Figure 4 In the case where the switching unit 220 includes a switch controller 223 and at least one switch chip 224 , the testing method further includes: S21 , controlling the node 210 to generate a plurality of selection signals, wherein the plurality of selection signals correspond to the plurality of second signal terminals 222 in a one-to-one manner.

[0174] S30, the step in which the switching unit 220 of the test device 200 transmits the test signal to each node connection terminal 110 in sequence includes: S3.1, the switch controller 223 controls at least one switch chip 224 to connect the first signal terminal 221 and the second signal terminal 222 corresponding to the selection signal according to the selection signal, so as to transmit the test signal to multiple node connection terminals 110 in sequence.

[0175] In some of the above embodiments, the switch controller 223 controls at least one switch chip 224, so that the test signal can be transmitted to different second signal terminals 222 in a time-sharing manner.

[0176] The control node 210 can alternately generate a selection signal and a test signal. For example, if the selection signal can include a first selection signal and a second selection signal, the control node 210 can first generate the first selection signal so that the first signal terminal 221 is electrically connected to the first second signal terminal 222A. The control node 210 can then sequentially generate a plurality of test sub-signals, so that the plurality of test sub-signals can be transmitted to the first node connection terminal 110A via the first signal terminal 221 and the first second signal terminal 222A, thereby sequentially testing the plurality of fourth interfaces in the first node connection terminal 110A. After testing the plurality of fourth interfaces in the first node connection terminal 110A, the control node 210 can then generate a second selection signal so that the first signal terminal 221 is electrically connected to the second second signal terminal 222B. The control node 210 can then again sequentially generate a plurality of test sub-signals, so that the plurality of test sub-signals can be transmitted to the second node connection terminal 110B via the first signal terminal 221 and the second second signal terminal 222B, thereby testing the plurality of fourth interfaces in the second node connection terminal 110B.

[0177] The following describes a method for testing the multiple fourth interfaces in the node connection terminal 110 in the multi-node management board 100 .

[0178] Figure 13 FIG. 1 is a block diagram of a connection structure among a test device 200 , a multi-node management board 100 , and an external device 300 according to some embodiments.

[0179] See also Figure 13 When testing the multi-node management board 100, the multi-node management board 100 can be electrically connected to the external device 300. At this time, the testing device 200 can control the external device 300 through the multi-node management board 100 to test the multi-node management board 100. Specifically, when testing different fourth interfaces on the multi-node management board 100, different external devices 300 can be used. Of course, when testing some of the fourth interfaces among all the fourth interfaces, the same external device 300 can also be used.

[0180] In some examples, the multi-node management board 100 is provided with a plurality of adapter cables, and the adapter cables can be connected between at least part of the fourth interface and the external device 300 .

[0181] In some examples, in the multi-node management board 100, each node connection terminal 110 includes a first-fourth I2C interface. Correspondingly, in the test device 200, each second signal terminal 222 includes a first-third I2C interface. The first signal terminal 221 includes a first-second I2C interface, and the control node 210 includes a first-first I2C interface. The multi-node management board 100 is also provided with a first I2C adapter cable, one end of which is electrically connected to the first-fourth I2C interface. When testing the first-fourth I2C interface, the external device 300 used can be a PSU (Power Supply Unit) 310. The other end of the first I2C adapter cable can be electrically connected to the PSU 310. In this case, the test sub-signal sent by the test device 200 can be a PSU test sub-signal, which can be sent to the PSU 310 via the first-third I2C interface, the first-fourth I2C interface, and the first I2C adapter cable in sequence. The test signal can control the on / off of the PSU 310. For example, if the PSU 310 can power on or off other devices according to the PSU test sub-signal, it can be considered that the first fourth I2C interface has passed the test. Figure 4 In this case, the management control unit 212 is configured to generate a PSU test sub-signal and transmit it to the first second I2C interface via the first first I2C interface. In some of the above examples, the testing process of the first fourth I2C interface of one node connection terminal 110 is described. The switching unit 220 can switch the PSU test sub-signal for transmission to the first fourth I2C interface of another node connection terminal 110, thereby testing the first fourth I2C interface of the other node connection terminal 110.

[0182] In some examples, in the multi-node management board 100, each node connection terminal 110 includes a second fourth I2C interface, and correspondingly, in the test device 200, each second signal terminal 222 includes a second third I2C interface. The first signal terminal 221 includes a second second I2C interface, and the control node 210 includes a second first I2C interface. The multi-node management board 100 is also provided with a second I2C adapter cable, and one end of the second I2C adapter cable is electrically connected to the second fourth I2C interface. When testing the second fourth I2C interface, the external device 300 used can be a hard disk backplane 320, and the hard disk backplane 320 is provided with a clock signal chip, and the other end of the second I2C adapter cable can be electrically connected to the clock signal chip. At this time, the test sub-signal sent by the test device 200 can be a clock test sub-signal, and the clock test sub-signal can be sent to the clock signal chip in sequence through the second third I2C interface, the second fourth I2C interface and the second I2C adapter. After the clock signal chip receives the clock test sub-signal, it can send the clock waveform to the control node 210 through the second I2C adapter and the second fourth I2C interface and the second third I2C interface and the switching unit 220. If the control node 210 can successfully receive the clock waveform, it can be considered that the second fourth I2C interface has passed the test. For example, the second first I2C interface can be connected to the management control unit 212 (such as Figure 4 In some of the above examples, the test process of the second fourth I2C interface of one node connection terminal 110 is described. The switching unit 220 can switch the clock test sub-signal for transmission to the second fourth I2C interface of another node connection terminal 110, thereby testing the second fourth I2C interface of the other node connection terminal 110.

[0183] In some examples, in the multi-node management board 100, each node connection terminal 110 includes a fourth VGA interface, and correspondingly, in the test device 200, each second signal terminal 222 includes a third VGA interface. The first signal terminal 221 includes a second VGA interface, and the control node 210 includes a first VGA interface. The multi-node management board 100 is also provided with a VGA adapter cable, and one end of the VGA adapter cable is electrically connected to the fourth VGA interface. When testing the fourth VGA interface, the external device 300 used can be a display device 330, and the other end of the VGA adapter cable can be electrically connected to the display device 330. The test sub-signal sent by the test device 200 is a VGA test sub-signal, and the VGA test sub-signal can be sent to the display device 330 in sequence through the third VGA interface, the fourth VGA interface and the VGA adapter cable. If the display device 330 can display the preset screen, it can be considered that the fourth VGA interface has passed the test. For example, the first VGA interface can be connected to the management control unit 212 (such as Figure 4 In some of the above examples, the test process of the fourth VGA interface of one node connection terminal 110 is described. The switching unit 220 can switch the VGA test sub-signal and transmit it to the fourth VGA interface of another node connection terminal 110, thereby testing the fourth VGA interface of the other node connection terminal 110.

[0184] In some examples, in the multi-node management board 100, each node connection terminal 110 includes a fourth USB interface. Correspondingly, in the test device 200, each second signal terminal 222 includes a third USB interface. The first signal terminal 221 includes a second USB interface, and the control node 210 includes a first USB interface. The multi-node management board 100 is also provided with a USB adapter cable, one end of which is electrically connected to the fourth USB interface. When testing the fourth USB interface, the external device 300 used may be a USB flash drive 340, the other end of which is electrically connected to the USB flash drive 340. The test sub-signal sent by the test device 200 is a USB test sub-signal. The USB test sub-signal can be sequentially transmitted to the USB flash drive 340 via the third USB interface, the fourth USB interface, and the USB adapter cable. If the USB flash drive 340 receives the USB test sub-signal, the test device 200 can successfully read and write information to the USB flash drive 340. If the test device 200 can successfully read and write information to the USB flash drive 340, the fourth USB interface is considered to have passed the test. For example, the first USB interface can be connected to the management control unit 212 (such as Figure 4In some of the above examples, the test process of the fourth USB interface of one node connection terminal 110 is described. The switching unit 220 can switch the USB test sub-signal and transmit it to the fourth USB interface of another node connection terminal 110, thereby testing the fourth USB interface of the other node connection terminal 110.

[0185] In some examples, in the multi-node management board 100, each node connection terminal 110 includes a fourth GPIO interface, and correspondingly, in the test device 200, each second signal terminal 222 includes a third GPIO interface. The first signal terminal 221 includes a second GPIO interface, and the control node 210 includes a first GPIO interface. The multi-node management board 100 is also provided with a GPIO adapter cable, one end of the GPIO adapter cable is electrically connected to the fourth GPIO interface. When testing the fourth GPIO interface, the external device 300 used can be a hard disk backplane 320, wherein the hard disk backplane 320 can be used to plug in multiple hard disks, and the other end of the GPIO adapter cable is electrically connected to the hard disk backplane 320. The test sub-signal sent by the test device 200 is a hard disk test sub-signal. The hard disk test sub-signal can be sent to the hard disk backplane 320 in sequence through the third GPIO interface, the fourth GPIO interface and the GPIO adapter cable. If the hard disk backplane 320 can send the hard disk's presence signal to the third GPIO interface through the GPIO adapter cable and the fourth GPIO interface, and the switching unit 220 can feed back the presence signal to the control node 210, then it can be considered that the fourth GPIO interface has passed the test. For example, the first GPIO interface can be electrically connected to the processing unit 213. At this time, the management control unit 212 can control the processing unit 213 to generate a hard disk test sub-signal and send it to the second GPIO interface through the first GPIO interface. In some of the above examples, the test process of the fourth GPIO interface of a node connection terminal 110 is introduced. The switching unit 220 can switch the hard disk test sub-signal for transmission to the fourth GPIO interface of other node connection terminals 110, thereby testing the fourth GPIO interface of other node connection terminals 110.

[0186] In some examples, in the multi-node management board 100, each node connection terminal 110 includes a fourth UART interface, and correspondingly, in the test device 200, each second signal terminal 222 includes a third UART interface. The first signal terminal 221 includes a second UART interface, and the control node 210 includes a first UART interface. The multi-node management board 100 is also provided with a UART adapter cable, and one end of the UART adapter cable is electrically connected to the fourth UART interface. When testing the fourth UART interface, the external device 300 used can be a right operation and maintenance board 350, and the other end of the UART adapter cable is electrically connected to the right operation and maintenance board 350. The test sub-signal sent by the test device 200 is a right operation and maintenance test sub-signal, and the right operation and maintenance test sub-signal can be sent to the right operation and maintenance board through the third UART interface, the fourth UART interface and the UART adapter cable in sequence. If the right operation and maintenance test sub-signal can be successfully sent to the right operation and maintenance board 350, it can be considered that the fourth UART interface has passed the test. For example, the first UAR interface can be connected to the management control unit 212 (such as Figure 4 In some of the above examples, the test process of the fourth UART interface of one node connection terminal 110 is described. The switching unit 220 can switch the right operation and maintenance test sub-signal for transmission to the fourth UART interface of another node connection terminal 110, thereby testing the fourth UART interface of the other node connection terminal 110.

[0187] In some examples, the multi-node management board 100 also includes a CPLD (Complex Programmable Logic Device) chip, and each node connection terminal 110 includes a third or fourth I2C interface connected to the CPLD chip. Furthermore, the multi-node management board 100 also includes a PWM (Pulse Width Modulation) interface connected to the CPLD chip. Correspondingly, in the test device 200, the second signal terminal 222 of the test device 200 includes a third or fourth I2C interface, and the external device 300 can be a fan 360. When testing the third or fourth I2C interface, the third or fourth I2C interface is electrically connected to the third or fourth I2C interface, thereby electrically connecting the test device 200 to the CPLD chip, which is then electrically connected to the fan 360 via the PWM interface. The test sub-signal sent by the test device 200 is a speed test sub-signal, which can be sent to the CPLD chip via the third or fourth I2C interface and the third or fourth I2C interface. If the CPLD chip can send a corresponding pulse width modulation signal according to the speed test sub-signal, and send the pulse width modulation signal to the fan 360 through the PWM interface to control the speed of the fan 360, then it can be considered that the third and fourth I2C interfaces have passed the test. For example, the third and first I2C interfaces can be connected to the management control unit 212 (such as Figure 4 In this case, the management control unit 212 is configured to generate a speed test sub-signal and transmit it to the third second I2C interface via the third first I2C interface. In some of the above examples, the testing process of the third or fourth I2C interface of one node connection terminal 110 was described. The switching unit 220 can switch the speed test sub-signal for transmission to the third or fourth I2C interface of another node connection terminal 110, thereby testing the third or fourth I2C interface of the other node connection terminal 110.

[0188] In some examples, in the multi-node management board 100, each node connection terminal 110 includes a fourth JTAG interface, which is electrically connected to the CPLD chip of the multi-node management board 100. Correspondingly, in the test device 200, each second signal terminal 222 includes a third JTAG interface. The first signal terminal 221 includes a second JTAG interface, and the control node 210 includes a first JTAG interface. When testing the fourth JTAG interface, the fourth JTAG interface is electrically connected to the third JTAG interface. In this case, the test sub-signal emitted by the test device 200 is a JTAG test sub-signal. For example, the JTAG test sub-signal can be a test sub-routine. The test sub-routine emitted by the test device 200 can be written to the CPLD chip via the third and fourth JTAG interfaces. If the test sub-routine is successfully written to the CPLD chip, the CPLD chip can control the rotation of the fan 360 according to the test sub-routine. If the fan 360 rotates according to the test sub-routine, the fourth JTAG interface and the CPLD chip can be considered to have passed the test. The CPLD chip can be electrically connected to the fan 360 via a PWM interface. For example, the first JTAG interface can be connected to the processing unit 213 (eg Figure 4 In the example above, the fourth JTAG interface of one node connection terminal 110 is tested. The switching unit 220 can switch the JTAG test sub-signal to the fourth JTAG interface of another node connection terminal 110, thereby testing the fourth JTAG interface of the other node connection terminal 110.

[0189] In some examples, in the multi-node management board 100, each node connection terminal 110 includes a fourth fourth I2C interface, and the fourth fourth I2C interface is electrically connected to the CPLD chip of the multi-node management board 100. Correspondingly, in the test device 200, the third interface of each second signal terminal 222 includes a fourth third I2C interface, the first signal terminal 221 includes a fourth second I2C interface, and the control node 210 includes a fourth first I2C interface. When testing the fourth fourth I2C interface, the external device 300 can be an operation and maintenance card, and the test sub-signal sent by the test device 200 is an in-position test sub-signal. The in-position test sub-signal can be sent to the CPLD chip of the multi-node management board 100 through the fourth third I2C interface and the fourth fourth I2C interface, and the CPLD chip of the multi-node management board 100 can obtain the in-position signal of the operation and maintenance card according to the in-position test sub-signal. If the CPLD chip of the multi-node management board 100 can obtain the in-position signal of the operation and maintenance card, it can be considered that the fourth fourth I2C interface has passed the test. For example, the fourth first I2C interface can be connected to the management control unit 212 (such as Figure 4 In some of the above examples, the test process of the fourth-fourth I2C interface of one node connection terminal 110 is described. The switching unit 220 can switch the in-place test sub-signal for transmission to the fourth-fourth I2C interface of another node connection terminal 110, thereby testing the fourth-fourth I2C interface of the other node connection terminal 110.

[0190] In some examples, the multi-node management board 100 also includes: a SW (Switch) chip and a PHY (Physical Layer) chip, wherein the SW chip and the PHY chip are electrically connected. Each node connection terminal 110 also includes a fourth MDIO interface, wherein the fourth MDIO interface can be electrically connected to the SW chip and the PHY chip, respectively. Correspondingly, in the test device 200, the second signal terminal 222 includes a third MDIO interface, the first signal terminal 221 includes a second MDIO interface, and the control node 210 includes a first MDIO interface. When testing the fourth MDIO interface, the test sub-signal emitted by the test device 200 is an MDIO test sub-signal, and the MDIO test sub-signal can be sent to the SW chip and the PHY chip through the third MDIO interface and the fourth MDIO interface in sequence. The SW chip includes multiple registers, and the PHY chip includes multiple registers. After the SW chip and the PHY chip receive the MDIO test sub-signal, the register ID can be sent to the test device 200. Therefore, in this example, if the test device 200 can find the register ID of the SW chip and the register ID of the PHY chip, it can be considered that the SW chip, the PHY chip and the fourth MDIO interface have passed the test. For example, the first MDIO interface can be connected to the management control unit 212 (such as Figure 4 In some of the above examples, the test process of the fourth MDIO interface of one node connection terminal 110 is described. The switching unit 220 can switch the MDIO test sub-signal and transmit it to the fourth MDIO interface of another node connection terminal 110, thereby testing the fourth MDIO interface of the other node connection terminal 110.

[0191] In some examples, in the multi-node management board 100, each node connection terminal 110 includes a fourth SGMII interface, which is electrically connected to the SW chip. In this case, the multi-node management board 100 also includes a network interface, which is electrically connected to the SW chip. The network interface can be an RJ45 interface. Correspondingly, in the test device 200, each second signal terminal 222 includes a third SGMII interface. The first signal terminal 221 includes a second SGMII interface, and the control node 210 includes a first SGMII interface. When testing the fourth SGMII interface and the SW chip, the external device 300 used may be a left operation and maintenance card 370, wherein the left operation and maintenance card has a MAC (Media Access Control) address. The test sub-signal sent by the test device 200 may be an addressing test sub-signal. The addressing test sub-signal may be sent to the SW chip via the third and fourth SGMII interfaces. The SW chip forwards the addressing test sub-signal to the left operation and maintenance card 370 via the network interface. After receiving the addressing test sub-signal, the left operation and maintenance card 370 may send the MAC address to the test device 200. If the test device 200 successfully finds the MAC address of the left operation and maintenance card, the fourth SGMII interface and the SW chip may be considered to have passed the test. For example, the first SGMII interface may be electrically connected to the management and control unit 212. In this case, the management and control unit 212 is configured to generate the addressing test sub-signal and send it to the second SGMII interface via the first SGMII interface. In some of the above examples, the test process of the fourth SGMII interface of one node connection end 110 is introduced. The switching unit 220 can switch the addressing test sub-signal and transmit it to the fourth SGMII interface of other node connection ends 110, thereby testing the fourth SGMII interface of other node connection ends 110.

[0192] In some examples, the external device 300 corresponding to each node connection terminal 110 in the multi-node management board 100 can be connected to the multi-node management board 100, so that when different node connection terminals 110 receive test signals, that is, when different node connection terminals 110 are tested, there is no need to change the connection relationship of the external device 300, thereby facilitating the testing of the multi-node management board 100.

[0193] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A testing device, characterized in that: Used to test a multi-node management board; wherein the multi-node management board includes multiple node connection terminals; including: A control node, used for generating a test signal; A switching unit having a first signal end and multiple second signal ends; the first signal end is electrically connected to the control node, and the multiple second signal ends are electrically connected to the multiple node connection ends in a one-to-one correspondence; the switching unit is used to: receive the test signal through the first signal end, and transmit the test signal of the first signal end to different second signal ends in a time-sharing manner to test the multiple node connection ends of the multi-node management board.

2. The testing device according to claim 1, wherein: The switching unit includes: a switch controller and at least one switch chip; Any one of the switch chips is electrically connected between the first signal terminal and the plurality of second signal terminals; The switch controller is electrically connected to the control node, and the switch controller is electrically connected to the at least one switch chip; the control node is also used to generate a selection signal; the switch controller is used to control at least one of the switch chips to connect the first signal end and the second signal end corresponding to the selection signal based on the selection signal.

3. The testing device according to claim 2, characterized in that All the switch chips in the switching unit include at least two types; The test signal includes at least two different test sub-signals; One test sub-signal corresponds to one switch chip, and the same test sub-signal can be transmitted to different second signal terminals in a time-sharing manner through the corresponding switch chip.

4. The testing device according to claim 3, characterized in that: The at least one switch chip includes a first switch chip and a second switch chip; the first switch chip and the second switch chip are of different types; The first signal end includes a first interface group and a second interface group, the first switch chip is electrically connected to the control node through the first interface group; the second switch chip is electrically connected to the control node through the second interface group; Each of the second signal terminals includes a third interface group and a fourth interface group; the first switch chip is connected to each node connection terminal through each third interface group, and the second switch chip is connected to each node connection terminal through each fourth interface group.

5. The testing device according to claim 4, characterized in that: The first interface group and the third interface group each include at least one high-speed interface, and the high-speed interface is used to transmit high-speed sub-signals; The second interface group and the fourth interface group each include at least one low-speed interface, and the low-speed interface is used to transmit a low-speed sub-signal.

6. The testing device according to claim 5, characterized in that: The first interface group and the third interface group both include: at least one of an SGMII interface and a USB interface; The second interface group and the fourth interface group both include at least one of an I2C interface, an MDIO interface, a JTAG interface, a GPIO interface, a UART interface, and a VGA interface.

7. The testing device according to any one of claims 1 to 6, characterized in that: The control node includes a management control unit and a processing unit electrically connected to the management control unit; The control node includes a first type interface group electrically connected to the management control unit and a second type interface group electrically connected to the processing unit; The test signal includes a first test signal and a second test signal; The management control unit is used to generate the first test signal and output it through the first type interface group; the management control unit is also used to control the processing unit to generate the second test signal and output it through the second type interface group.

8. The testing device according to claim 7, characterized in that: The management control unit includes a BMC chip; The processing unit includes a CPLD chip.

9. A method for testing a multi-node management board, characterized in that: include: electrically connecting the plurality of second signal terminals of the test device according to any one of claims 1 to 8 to the plurality of node connection terminals of the multi-node management board in a one-to-one correspondence; The control node of the test device generates a test signal; The switching unit of the testing device transmits the test signal to each node connection end in sequence to test the multiple node connection ends of the multi-node management board.

10. The testing method according to claim 9, characterized in that: In a case where the switching unit includes a switch controller and at least one switch chip, the testing method further includes: The control node generates a plurality of selection signals; The step of the switching unit of the test device transmitting the test signal to each node connection end in sequence includes: The switch controller controls at least one of the switch chips to connect a first signal terminal and a second signal terminal corresponding to the selection signal according to the selection signal, so as to transmit the test signal to the multiple node connection terminals in sequence.

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