Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device, which relate to the field of display technology. The display substrate includes a substrate, a plurality of light-emitting devices, a plurality of pixel circuits, a plurality of data lines and a plurality of control signal lines. The data lines include a first data line and a second data line. The first data line includes a transfer signal line extending along a first direction, a first sub-data line and a second sub-data line extending along a second direction. The transfer signal line is located between the plurality of pixel circuits and is coupled to the first sub-data line and the second sub-data line, respectively. The plurality of control signal lines extend along the first direction, wherein the parasitic capacitance between the first data line and the control signal line has a first capacitance value, the parasitic capacitance between the second data line and the control signal line has a second capacitance value, and the difference between the first capacitance value and the second capacitance value is less than or equal to 0.15fF. The display substrate and the display device provided by the present disclosure can improve the uniformity of the display brightness of the display substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] To improve the visual effect of the display, it is necessary to increase the proportion of the display area as much as possible, that is, to increase the screen-to-body ratio of the display. Displays with a screen-to-body ratio of 100% or close to 100% are usually called "full screens."

[0003] At present, full-screen display devices will adopt under-screen camera technology, that is, the camera is set below the display screen so that the area of ​​the display screen corresponding to the camera is also displayed, avoiding the front camera occupying the display area of ​​the display screen, thereby facilitating the display screen ratio to approach or reach 100%, realizing a full screen. Summary of the Invention

[0004] An object of some embodiments of the present disclosure is to provide a display substrate and a display device to improve the uniformity of display brightness of the display substrate.

[0005] To achieve the above objectives, some embodiments of the present disclosure provide the following technical solutions:

[0006] Firstly,

[0007] A display substrate is provided. The display substrate includes a substrate, multiple light-emitting devices, multiple pixel circuits, multiple data lines, and multiple control signal lines. The substrate includes a display area and a peripheral area located on at least one side of the display area. The display area includes a light-transmitting display area and a main display area located on at least one side of the light-transmitting display area. The multiple light-emitting devices include multiple first light-emitting devices and multiple second light-emitting devices; the multiple first light-emitting devices are located in the light-transmitting display area, and the multiple second light-emitting devices are located in the main display area. Multiple pixel circuits are located in the main display area. The multiple pixel circuits include multiple first pixel circuits and multiple second pixel circuits; the multiple first pixel circuits are coupled to the multiple first light-emitting devices via multiple conductive lines, and the multiple second pixel circuits are coupled to the multiple second light-emitting devices. The multiple second pixel circuits are spaced apart and distributed between the first pixel circuits.

[0008] The plurality of data lines include a plurality of first data lines and a plurality of second data lines. The first data line includes a transfer signal line extending along a first direction, and a first sub-data line and a second sub-data line extending along a second direction. The transfer signal line is located between the plurality of pixel circuits and is coupled to the first sub-data line and the second sub-data line, respectively; the second direction intersects the first direction. The first sub-data line is coupled to the first pixel circuit, and the second data line and the second sub-data line are coupled to the second pixel circuit. A plurality of control signal lines extend along the first direction, and the plurality of control signal lines are coupled to the plurality of first pixel circuits and the plurality of second pixel circuits. The parasitic capacitance between the first data line and the control signal line has a first capacitance value, the parasitic capacitance between the second data line and the control signal line has a second capacitance value, and the difference between the first capacitance value and the second capacitance value is less than or equal to 0.15fF.

[0009] The display substrate provided by the embodiments of the present disclosure increases the parasitic capacitance between the data line segment within the second sub-pixel region and the scan control line, such that the difference between the first capacitance value and the second capacitance value is less than or equal to 0.15 fF. This reduces the difference in data voltage caused by the parasitic capacitance within each sub-pixel region due to interference from surrounding signal transitions, facilitating uniformity in the data voltage stored by the parasitic capacitance within each sub-pixel region, thereby improving the uniformity of the display brightness of the display substrate.

[0010] In some embodiments, the first capacitance value and the second capacitance value are approximately equal.

[0011] In some embodiments, the main display area further includes a plurality of sub-pixel areas. The plurality of pixel circuits are respectively located in the plurality of sub-pixel areas. The plurality of sub-pixel areas include a first sub-pixel area and a second sub-pixel area; the first sub-pixel area includes a switching structure. The second sub-data line is coupled to the switching signal line via the switching structure.

[0012] In some embodiments, the second sub-pixel region further includes a dummy switching structure; the dummy switching structure is coupled to a line segment of the data line in the second sub-pixel region and is separated from the switching signal line.

[0013] In some embodiments, an orthographic projection area of ​​the dummy transfer structure on the substrate is smaller than or substantially equal to an orthographic projection area of ​​the transfer structure on the substrate.

[0014] In some embodiments, the orthographic projection of the switching structure on the substrate at least partially overlaps with the orthographic projection of the second sub-data line on the substrate. The orthographic projection of the dummy switching structure on the substrate at least partially overlaps with the orthographic projection of the second data line on the substrate.

[0015] In some embodiments, the transfer structure includes a first transfer portion coupled to the second sub-data line, and a second transfer portion coupled to both the first transfer portion and the transfer signal line. The dummy transfer structure includes a third transfer portion coupled to the second data line, and a fourth transfer portion coupled to the third transfer portion and separate from the transfer signal line. The transfer signal line, the second transfer portion, and the fourth transfer portion are disposed on the same layer.

[0016] In some embodiments, an average size of the data line segments in the second sub-pixel region in the first direction is greater than an average size of the data line segments in the first sub-pixel region in the first direction.

[0017] In some embodiments, the data line segment within the second sub-pixel region includes a main portion extending along the second direction and an extension portion extending from the main portion along the first direction. An orthographic projection of the extension portion on the substrate at least partially overlaps with an orthographic projection of the control signal line on the substrate.

[0018] In some embodiments, a dimension of the extension portion in the second direction is greater than a dimension of the control signal line in the second direction.

[0019] In some embodiments, in the second direction, a spacing distance between the transfer structure and the control signal line is greater than or equal to 5 μm.

[0020] In some embodiments, the display substrate further comprises a plurality of initial lines, and a distance between at least one of the initial lines and the transfer structure is less than or equal to 2 μm.

[0021] In some embodiments, an orthographic projection of the at least one initial line on the substrate at least partially overlaps with an orthographic projection of the transfer structure on the substrate.

[0022] In some embodiments, in the second direction, the transfer structure is located between the transfer signal line and the control signal line.

[0023] In some embodiments, a plurality of transfer structures are located on one side of the light-transmitting display area in the second direction, and the plurality of transfer structures are arranged in at least one "V" shape.

[0024] In some embodiments, the control signal line includes at least one of a reset signal line and a gate signal line.

[0025] In some embodiments, the display substrate further comprises a plurality of transparent signal lines extending along the first direction, one end of each transparent signal line being coupled to the first pixel circuit, and the other end of each transparent signal line being coupled to the first light-emitting device in the light-transmitting display area.

[0026] In some embodiments, the display substrate further comprises a multiplexer located in the peripheral region, the multiplexer coupled to at least two data lines of the plurality of data lines, and configured to transmit the same data signal to different data lines of the at least two data lines in a time-sharing manner.

[0027] In a second aspect, a display device is provided. The display device includes a display substrate and an optical sensor. The display substrate is any of the display substrates described in the above embodiments. The optical sensor is located on the back side of the display substrate, the back side of the display substrate being the side opposite the display side of the display substrate. The light collection area of ​​the optical sensor at least partially overlaps with the light-transmitting display area of ​​the display substrate.

[0028] The display device provided by the embodiment of the present disclosure includes the display substrate provided by the first aspect, and thus has the beneficial effects of the above-mentioned display substrate, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0030] Figure 1 is a structural diagram of a display device provided according to some embodiments;

[0031] Figure 2 is a structural diagram of a display substrate provided according to some embodiments;

[0032] Figure 3 A partially enlarged view of a display substrate provided according to some embodiments;

[0033] Figure 4 A diagram showing the positions of sub-pixel regions and light-emitting devices in a main display area of ​​a display substrate according to some embodiments;

[0034] Figure 5A is an equivalent circuit diagram of a first pixel circuit in a display substrate provided according to some embodiments;

[0035] Figure 5B is an equivalent circuit diagram of a second pixel circuit in a display substrate provided according to some embodiments;

[0036] Figures 6A to 6C Schematic diagram of a first data line in a display substrate at three viewing angles according to some embodiments;

[0037] Figure 7 A structural diagram of an active layer in a display substrate according to some embodiments;

[0038] Figure 8 is a structural diagram of a first conductive layer in a display substrate according to some embodiments;

[0039] Figure 9 is a structural diagram of a second conductive layer in a display substrate provided according to some embodiments;

[0040] Figure 10A is a structural diagram of a third conductive layer in a display substrate according to some embodiments;

[0041] Figure 10B A structural diagram of a third conductive layer in another display substrate according to some embodiments;

[0042] Figure 11A is a structural diagram of a fourth conductive layer in a display substrate according to some embodiments;

[0043] Figure 11B is a structural diagram of a fourth conductive layer in another display substrate according to some embodiments;

[0044] Figure 12A A structural diagram of a stack of an active layer, a first conductive layer, a second conductive layer, and a third conductive layer in a display substrate according to some embodiments;

[0045] Figure 12B A structural diagram of a stack of an active layer, a first conductive layer, a second conductive layer, and a third conductive layer in another display substrate according to some embodiments;

[0046] Figure 12C A structural diagram of a stack of a first conductive layer and a third conductive layer in a display substrate according to some embodiments;

[0047] Figure 12D A structural diagram showing a stack of an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer in another display substrate according to some embodiments;

[0048] Figure 13 is a structural diagram of a display substrate provided according to some embodiments;

[0049] Figure 14 A timing diagram of a multiplexer and multiple signals in a display substrate according to some embodiments;

[0050] Figure 15 A timing diagram of data voltage transition on a parasitic capacitor in a display substrate according to some embodiments;

[0051] Figure 16 A display diagram of a display substrate provided according to some embodiments;

[0052] Figure 17 A diagram showing the positions of a plurality of transfer structures in a display substrate according to some embodiments;

[0053] Figure 18 A diagram showing the positions of multiple transfer structures in another display substrate according to some embodiments;

[0054] Figure 19 is a flow chart of a display substrate driving method according to some embodiments;

[0055] Figure 20 FIG. 1 is a graph showing grayscale value and brightness reconfiguration in a display substrate driving method according to some embodiments. DETAILED DESCRIPTION

[0056] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0057] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0058] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0059] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0060] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0061] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0062] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0063] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0064] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0065] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0066] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0067] Some embodiments of the present disclosure provide a display device. The display device is a product having an image (including: static image or dynamic image, wherein the dynamic image can be a video) display function. For example, the display device can be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a watch, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as business query equipment for e-government, banks, hospitals, power departments, etc.), a monitor, etc. For another example, the display device can also be any product such as a microdisplay, a VR device or an AR device containing a microdisplay, etc.

[0068] Figure 1 A perspective view of a display device. Figure 2 It is a front view of the display device.

[0069] See also Figure 1 and Figure 2 The display device 1000 may include a display substrate 100 and an optical sensor 200. The display substrate 100 is a flat panel capable of displaying images. For example, the display substrate 100 may be a screen, such as a liquid crystal display substrate 100 or an organic light-emitting display substrate 100. For example, the sensor 200 may be an infrared sensor, an ultrasonic sensor, a LiDAR (Light Detection and Ranging) sensor, a radar sensor, or a camera sensor.

[0070] See also Figure 1 , the display substrate 100 has a display side 100A and a non-display side (i.e., the back side of the display substrate 100) 100B. Among them, the display side 100A is the side of the display substrate 100 that can display images; when the human eye is on the display side 100A, it can see the image displayed by the display substrate 100. The non-display side 100B is opposite to the display side 100A. The optical sensor 200 is arranged on the non-display side 100B of the display substrate 100, so the optical sensor 200 can be called an under-screen sensor. Since the optical sensor 200 needs to receive light signals from the outside world that pass through the display substrate 100, the display substrate 100 needs to have a higher light transmittance in the area corresponding to the optical sensor 200. Based on this, the display substrate 100 can have a display area AA and a peripheral area SA, Figure 1The X direction in the diagram is the direction along which one side of the display area AA extends, such as the short side, or the lateral direction of the display area AA. The Y direction is the direction along which another side of the display area AA extends, such as the long side, or the longitudinal direction of the display area AA. The Z direction is perpendicular to the plane of the display substrate 100. The X, Y, and Z directions are defined identically in the following figures.

[0071] See also Figure 2 and Figure 6C The peripheral area SA is located on at least one side (e.g., one side; or, for example, all four sides, i.e., including the upper and lower sides and the left and right sides) outside the display area AA. The display area AA may include a non-overlapping main display area AA1 and a light-transmitting display area AA2 corresponding to the position of the sensor 200. The light transmittance of the light-transmitting display area AA2 may be higher than the light transmittance of the main display area AA1.

[0072] The orthographic projection of the optical sensor 200's light-collecting area on the display substrate 100 at least partially overlaps with the light-transmitting display area AA2, allowing more light to pass through the display substrate 100 and be received by the optical sensor 200. For example, a portion of the orthographic projection of the optical sensor 200's light-collecting area on the display substrate 100 lies within the light-transmitting display area AA2. For another example, the entire orthographic projection of the optical sensor 200's light-collecting area on the display substrate 100 lies within the light-transmitting display area AA2. The main display area AA1 is the area of ​​the display area AA excluding the light-transmitting display area AA2.

[0073] Some embodiments of the present disclosure provide a display substrate 100. The display substrate 100 may be included in the display device 1000 described above.

[0074] like Figure 3 and Figure 6B As shown, the display area AA includes a plurality of display unit areas arranged in an array. Each display unit area includes a plurality of sub-display areas 130. Each sub-display area 130 includes a light emitting device. It should be noted that, Figure 3 and Figure 6B The light emitting devices in the main display area AA1 are hidden.

[0075] As an example, the multiple sub-display areas 130 include a first sub-display area 130 configured to emit a first color of light, a second sub-display area 130 configured to emit a second color of light, and a third sub-display area 130 configured to emit a third color of light. The first, second, and third colors may be primary colors. For example, the first color is red, the second color is green, and the third color is blue; accordingly, the multiple sub-display areas 130 include a red sub-display area 130, a green sub-display area 130, and a blue sub-display area 130. As another example, the multiple sub-display areas 130 may also include a fourth sub-display area 130 that emits white light. The multiple sub-display areas 130 within a display unit area can work together to emit white light.

[0076] In some examples, the display unit area includes four sub-display areas, which are arranged as follows: a sub-display area 130 of the first color, a sub-display area 130 of the second color, a sub-display area 130 of the third color, and a sub-display area 130 of the second color.

[0077] For example, the first color sub-display area 130 is a red sub-display area, the second color sub-display area 130 is a green sub-display area, and the third color sub-display area 130 is a blue sub-display area. The red sub-display area 130 includes a red light-emitting device E; the green sub-display area 130 includes a green light-emitting device E; and the blue sub-display area 130 includes a blue light-emitting device E. That is, in this example, one display unit area includes one red light-emitting device E, one blue light-emitting device E, and two green light-emitting devices E.

[0078] For example, the light-emitting device E may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including a mini LED or a micro LED), etc. The light-emitting device E (for example, an OLED or a QLED) includes a cathode and an anode. When current flows between the anode and the cathode, the light-emitting device E is illuminated.

[0079] like Figure 3 and Figure 6B As shown, in order to improve the transmittance of the light-transmitting display area AA2, the display substrate does not have a pixel circuit in the light-transmitting display area AA2. The light-emitting devices in the light-transmitting display area AA2 receive electrical signals provided by the pixel circuit in the main display area AA1 to emit light.

[0080] The main display area AA1 includes multiple pixel unit areas arranged in an array. Each pixel unit area includes multiple sub-pixel areas 120. The multiple sub-pixel areas 120 may include a normal sub-pixel area 120A and a dummy sub-pixel area 120B. Each sub-pixel area 120 includes a pixel circuit S. For example, the dummy sub-pixel area 120B includes a first pixel circuit S1, which is coupled to a first light-emitting device via a conductive line; the normal sub-pixel area 120A includes a second pixel circuit S2, which is coupled to a second light-emitting device.

[0081] In some embodiments, a plurality of second pixel circuits S2 are spaced apart and distributed between the first pixel circuits S1 .

[0082] Exemplarily, in the first direction X, at least one dummy sub-pixel region 120B is located between two normal sub-pixel regions 120A. It can be understood that in the first direction X, one first pixel circuit S1 is located between two second pixel circuits S2.

[0083] In some examples, the number of sub-pixel regions 120 in a pixel unit region may be equal to the number of sub-display regions 130 in a display unit region, and multiple pixel circuits S in a pixel unit region may be coupled to multiple light-emitting devices E in a display unit region.

[0084] In some embodiments, in the main display area AA1, the pixel circuit S in the sub-pixel area 120 and the light-emitting device in the sub-display area 130 may partially overlap or completely overlap. Figure 4 As shown, in the main display area AA1, a portion of the light emitting device of a sub-display area 130 may at least partially overlap with a pixel circuit, and another portion may at least partially overlap with another pixel circuit.

[0085] The display substrate 100 may further include a plurality of signal lines. Figure 5A and Figure 5B As shown, for example, the multiple signal lines may include a data line L-Data configured to transmit a data signal, a gate line L-Gate configured to transmit a gate signal, a scan line L-Scan configured to transmit a scan signal, a reset line L-Re configured to transmit a reset signal, an enable line L-EM configured to transmit an enable signal, a first initial line L-Vinit1 configured to transmit a first initial signal, a second initial line L-Vinit2 configured to transmit a second initial signal, a third initial line L-Vinit3 configured to transmit a third initial signal, a first power line L-VDD configured to transmit a first power supply voltage VDD (e.g., a high voltage), and a second power line L-VSS configured to transmit a second power supply voltage VSS (e.g., a low voltage), etc.

[0086] The gate line L-Gate, the scan line L-Scan, the reset line L-Re, the enable line L-EM, the first initial line L-Vinit1, the second initial line L-Vinit2, and the third initial line L-Vinit3 may extend along the row direction (first direction X) of the display substrate. The first power line L-VDD may extend along the column direction (second direction Y) of the display substrate.

[0087] The plurality of data lines L-Data include a plurality of first data lines L-Data1 and a plurality of second data lines L-Data2. The first data lines L-Data1 are coupled to the first pixel circuit S1, and the second data lines L-Data2 are coupled to the second pixel circuit S2.

[0088] like Figures 6A to 6C As shown, the first data line L-Data1 may include a transfer signal line L-Data1-1 extending along the first direction, and a first sub-data line L-Data1-2 and a second sub-data line L-Data1-3 extending along the second direction. The second data line L-Data2 extends along the second direction. Figure 6A and Figure 6B The first data line L-Data1 is represented by a thick black line, and the second data line L-Data2 is represented by a thin black line; Figure 6C The first data line L-Data1 is represented by a black solid line, and the second data line L-Data2 is represented by a black dotted line.

[0089] The pixel circuit S can have various structures, which can be selected based on actual needs. For example, the pixel circuit S can include at least two transistors (denoted by T) and at least one capacitor (denoted by C). For example, the pixel circuit S can have a "2T1C," "6T1C," "7T1C," "6T2C," or "7T2C" structure.

[0090] like Figure 5A As shown, for example, the first pixel circuit S1 has a "7T1C" structure, including: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitor Cst and a light emitting device E.

[0091] A control electrode of the first transistor T1 is coupled to the reset line L-Re, a first electrode of the first transistor T1 is coupled to the first initial line L-Vinit1, and a second electrode of the first transistor T1 is coupled to the first node N1.

[0092] A control electrode of the second transistor T2 is coupled to the gate line L-Gate, a first electrode of the second transistor T2 is coupled to the third node N3, and a second electrode of the second transistor T2 is coupled to the first node N1.

[0093] A control electrode of the third transistor T3 is coupled to the first node N1 , a first electrode of the third transistor T3 is coupled to the second node N2 , and a second electrode of the third transistor T3 is coupled to the third node N3 .

[0094] A control electrode of the fourth transistor T4 is coupled to the scan line L-Scan, a first electrode of the fourth transistor T4 is coupled to the data line L-Data, and a second electrode of the fourth transistor T4 is coupled to the second node N2.

[0095] A control electrode of the fifth transistor T5 is coupled to the enable line L-EM, a first electrode of the fifth transistor T5 is coupled to the first power line L-VDD, and a second electrode of the fifth transistor T5 is coupled to the second node N2.

[0096] A control electrode of the sixth transistor T6 is coupled to the enable line L-EM, a first electrode of the sixth transistor T6 is coupled to the third node N3, and a second electrode of the sixth transistor T6 is coupled to the fourth node N4.

[0097] A control electrode of the seventh transistor T7 is coupled to the scan line L-Scan, a first electrode of the seventh transistor T7 is coupled to the third initial line L-Vinit3, and a second electrode of the seventh transistor T7 is coupled to the fourth node N4.

[0098] A first plate of the capacitor Cst is coupled to the first power line L-VDD, and a second plate of the capacitor Cst is coupled to the first node N1.

[0099] An anode of the first light emitting device E is coupled to the fourth node N4 , and a cathode of the first light emitting device E is coupled to the second power line L-VSS.

[0100] In some embodiments, the fourth transistor T4 is configured to be turned on in response to the scan signal being at an active level (i.e., forming a path between the second node N2 and the data line L-Data), transmit the data signal to the first node N1, and charge the capacitor Cst. The third transistor T3 is configured to control the magnitude of the current flowing through the third transistor T3 in response to the level of the first node N1. Because the light-emitting device E is connected in series with the driving transistor (i.e., the third transistor T3), the brightness of the light-emitting device E changes with the magnitude of the current.

[0101] In some examples, the reset line L-Re of the n-th row of pixel circuits S may be replaced by the scan line L-Scan coupled to the n-1-th row of pixel circuits, which is not limited here.

[0102] In some embodiments, as Figure 5BAs shown, the second pixel circuit S2 has the same structure as the first pixel circuit S1, that is, the second pixel circuit S2 also includes the above-mentioned 7T1C structure. The second pixel circuit S2 differs from the first pixel circuit S1 in that the first electrode of the seventh transistor T7 in the second pixel circuit S2 is coupled to the second initial line L-Vinit2; and the fourth node N4 is coupled to the anode of the second light-emitting device E.

[0103] In some other embodiments, the first electrode of the seventh transistor T7 in the second pixel circuit S2 and the first pixel circuit S1 may also be coupled to the same initial line, which is not limited here.

[0104] like Figures 6A to 6C As shown, the display substrate further includes a plurality of dummy lines L-Dummy. The dummy lines L-Dummy extend along the second direction Y, and the plurality of dummy lines L-Dummy are arranged in parallel and at intervals along the first direction X.

[0105] A fixed number of second data lines L-Data2 may be included between two adjacent virtual lines L-Dummy in the first direction X. For example, seven second data lines L-Data2 or five second data lines L-Data2 may be included between two adjacent virtual lines L-Dummy in the first direction X, which is not limited here.

[0106] The first sub-data line L-Data1-2 may be a partial line segment of a virtual line L-Dummy, wherein the line segment of the virtual line L-Dummy serving as the first sub-data line L-Data1-2 is disconnected from other line segments of the virtual line L-Dummy.

[0107] The first data line L-Data1 utilizes the virtual line L-Dummy and the transfer signal line L-Data1-1 to transmit the data signal around the light-transmitting display area AA2. Figure 6C As shown, a plurality of first data lines L-Data1 continuously arranged in the first direction X respectively utilize virtual lines L-Dummy continuously arranged in the first direction X as first sub-data lines L-Data1 - 2 in their respective first data lines L-Data1 .

[0108] like Figure 6A As shown, the plurality of sub-pixel regions 120 of the display substrate 100 further include a first sub-pixel region 121 and a second sub-pixel region 122. Figures 7 to 11B As shown, in some embodiments, the display substrate includes a semiconductor layer 210 , a first conductive layer 220 , a second conductive layer 230 , a third conductive layer 240 and a fourth conductive layer 250 disposed in a direction away from the substrate.

[0109] like Figure 7As shown, the semiconductor layer 210 may include low-temperature polysilicon (LTPS) material, low-temperature polycrystalline oxide (LTPO) material, or other suitable materials, which are not limited here.

[0110] The first conductive layer 220 , the second conductive layer 230 , the third conductive layer 240 and the fourth conductive layer 250 may include metal materials, alloy materials or other conductive materials, such as aluminum Al, copper Cu, silver Ag, magnesium Mg, ytterbium Yb, lithium Li and the like.

[0111] like Figure 7 As shown, the semiconductor layer 210 may include an active layer of a plurality of transistors in a pixel circuit. Figure 5A Taking the pixel circuit including the first transistor T1 to the seventh transistor T7 as an example, the first semiconductor layer 210 may include active layers (p1-p7) of the first transistor T1 to the seventh transistor T7.

[0112] In some examples, the active layers (p1-p7) of the first transistor T1 to the seventh transistor T7 are interconnected as an integrated structure.

[0113] In some embodiments, a first insulating layer may be included between the semiconductor layer 210 and the first conductive layer 220. The first insulating layer may be made of oxide, nitride, or a combination of one or more oxynitrides, such as silicon oxide, silicon nitride, or silicon oxynitride, which is not limited herein.

[0114] like Figure 8 As shown, in some embodiments, the first conductive layer 220 may include a gate line L-Gate, a scan line L-Scan, an enable line L-EM (also known as a light-emitting control signal line), and control electrodes (g1~g7) of the first transistor T1 to the seventh transistor T7, and a second electrode Cst-2 of the storage capacitor Cst.

[0115] In some examples, the control electrode g2 of the second transistor, the control electrode g4 of the fourth transistor, and the gate line L-Gate are interconnected as an integrated structure.

[0116] In some examples, the control electrode g1 of the first transistor is located on a side of the gate line L-Gate away from the control electrode g3 of the third transistor.

[0117] In some examples, the control electrode g5 of the fifth transistor, the control electrode g6 of the sixth transistor, and the enable line L-EM are interconnected as an integrated structure.

[0118] In some examples, the control electrode g2 of the seventh transistor and the scan line L-Scan are connected to each other as an integral structure.

[0119] In some embodiments, a second insulating layer may be included between the first conductive layer 220 and the second conductive layer 230. The second insulating layer may be made of oxide, nitride, or a combination of one or more oxynitrides, such as silicon oxide, silicon nitride, or silicon oxynitride, which is not limited herein.

[0120] like Figure 9 As shown, in some embodiments, the second conductive layer 230 may include a first initial line L-Vinit1, a second initial line L-Vinit2, a third initial line L-Vinit3, and a first plate Cst-1 of the storage capacitor Cst.

[0121] In some examples, the first initial line L-Vinit1 , the second initial line L-Vinit2 , and the third initial line L-Vinit3 are sequentially arranged from a direction away from the first plate Cst- 1 of the storage capacitor Cst.

[0122] In some examples, the first initial line L-Vinit1 includes a first main portion extending in a first direction, and a first extending portion extending in a direction close to the first plate Cst- 1 of the storage capacitor Cst.

[0123] In some examples, such as Figure 12A 、 Figure 12B and Figure 12D As shown, in the second direction, a scan line L-Scan is located between a first initial line L-Vinit1 and a second initial line L-Vinit2.

[0124] In some embodiments, a third insulating layer may be included between the second conductive layer 230 and the third conductive layer 240. The material of the third insulating layer may be a combination of one or more oxides, nitrides, or oxynitrides, such as silicon oxide, silicon nitride, or silicon oxynitride, which is not limited herein.

[0125] like Figure 10A As shown, in some embodiments, the third conductive layer 240 may include a transition wire L-SW and a plurality of transition pieces.

[0126] The switching line L-SW extends along the first direction and is located between the plurality of pixel circuits.

[0127] In some examples, the plurality of adapters include first to seventh adapters sd1 to sd7 .

[0128] The first adapter sd1 may couple the third initial line L-Vinit3 and the first electrode of the seventh transistor T7 in the second pixel circuit S2 .

[0129] The second adapter sd2 may couple the second initial line L-Vinit2 and the first electrode of the seventh transistor T7 in the first pixel circuit S1 .

[0130] The third switching element sd3 may be coupled to the first electrode of the first transistor T1 and the first initial line L-Vinit1.

[0131] The fourth switching element sd4 can be coupled to the first electrode of the fourth transistor T4 and the data line L-Data.

[0132] The fifth switching element sd5 can couple the second electrode of the fourth transistor T4 and the first electrode of the third transistor T3 .

[0133] The sixth switching element sd6 may be coupled to the first electrode of the fifth transistor T5 and the first plate of the storage capacitor Cst, and the sixth switching element sd6 may be coupled to the first power line L-VDD to obtain a first voltage signal.

[0134] In some embodiments, a fourth insulating layer may be included between the third conductive layer 240 and the fourth conductive layer 250. The fourth insulating layer may be made of a material selected from the group consisting of oxide, nitride, and oxynitride, such as silicon oxide, silicon nitride, and silicon oxynitride, which are not limited herein.

[0135] like Figure 11A As shown, in some embodiments, the fourth conductive layer 250 may include a first power line L-VDD, a data line L-Data, an eighth transfer element sd8 and a ninth transfer element sd9.

[0136] In some examples, such as Figure 11A As shown, in the first pixel circuit S1, the seventh adapter sd7 in the third conductive layer 240 is coupled to the second electrode of the sixth transistor T6 and the eighth adapter sd8 in the fourth conductive layer 250. The eighth adapter sd8 is coupled to the anode of the first light-emitting device E, thereby coupling the second electrode of the sixth transistor T6 and the anode of the first light-emitting device E.

[0137] In other examples, such as Figure 11A As shown, in the second pixel circuit S2, the seventh adapter sd7 in the third conductive layer 240 is coupled to the second electrode of the sixth transistor T6 and the ninth adapter sd9 in the fourth conductive layer 250. The ninth adapter sd9 is coupled to the anode of the second light-emitting device E, thereby coupling the second electrode of the sixth transistor T6 to the anode of the second light-emitting device E.

[0138] In some embodiments, as Figures 6A to 6C As shown, the first data signal line L-Data1 is configured to provide data signals to multiple light-emitting devices located in the same column of the display substrate. For example, the first sub-data line L-Data1-2 within the first data signal line L-Data1 is configured to provide data signals to multiple first light-emitting devices located in the light-transmitting display area within the column; and the second sub-data line L-Data1-3 within the first data signal line L-Data1 is configured to provide data signals to multiple second light-emitting devices located in the main display area within the column.

[0139] Exemplarily, a first data line L-Data1 includes multiple first sub-data lines L-Data1-2 extending along the second direction, and the multiple first sub-data lines L-Data1-2 are arranged parallel to each other and spaced apart along the first direction. The multiple first sub-data lines L-Data1-2 are respectively coupled to the transfer signal line L-Data1-1 extending along the first direction, and the transfer signal line L-Data1-1 is also coupled to the second sub-data line L-Data1-3 extending along the second direction. The multiple first sub-data lines L-Data1-2 are coupled to multiple first light-emitting devices in the same column within the light-transmitting display area. In addition, the end of the first sub-data line L-Data1-2 away from the transfer signal line L-Data1-1 can also be coupled to another segment of the second sub-data line L-Data1-3 extending along the second direction via a conductive wire, thereby forming a complete data signal path.

[0140] It should be noted that the transfer signal line L-Data1-1 can be a local segment of the transfer line L-SW, and this is not limited here. Furthermore, the aforementioned conductor can also be a second sub-data line L-Data1-3 that transfers the data signal back to another segment via the signal transfer line L-SW, or it can be an additional signal line that transfers the data signal back to another segment of the second sub-data line L-Data1-3, and this is not limited here.

[0141] In this way, the data signal is transmitted to the first pixel circuit in sequence through the second sub-data line L-Data1-3, the switching signal line L-Data1-1 and the first sub-data line L-Data1-2, and the first pixel circuit drives the first light-emitting device in the transparent display area to emit light.

[0142] Different second sub-data lines L-Data1-3 can be coupled to different transfer signal lines L-Data1-1. In addition, different transfer signal lines L-Data1-1 can also be coupled to different first sub-data lines L-Data1-2.

[0143] like Figure 6A and Figure 6B As shown, the first pixel circuit is connected to the transparent signal line (in Figure 6AThe transparent signal line L-TG is coupled to the first light emitting device in the light-transmitting display area AA2 (indicated by a dotted line). The transparent signal line L-TG may be, for example, an indium tin oxide (ITO) line.

[0144] In some embodiments, the display substrate 100 further includes multiple transparent conductive layers. For example, the display substrate 100 includes a first transparent conductive layer, a second transparent conductive layer, and a third transparent conductive layer stacked sequentially from the substrate. The multiple transparent conductive layers can be located on a side of the multiple conductive layers away from the substrate.

[0145] The first transparent conductive layer includes a first light-transmitting signal line L-TG extending along the first direction, one end of the first light-transmitting signal line L-TG is coupled to the first pixel circuit, and the other end of the first light-transmitting signal line L-TG is coupled to the first color light-emitting device in the light-transmitting display area AA2.

[0146] The second transparent conductive layer includes a second light-transmitting signal line L-TG extending along the first direction, one end of the second light-transmitting signal line L-TG is coupled to the first pixel circuit, and the other end of the second light-transmitting signal line L-TG is coupled to the second color light-emitting device in the light-transmitting display area AA2.

[0147] The third transparent conductive layer includes a third light-transmitting signal line L-TG extending along the first direction, one end of the third light-transmitting signal line L-TG is coupled to the first pixel circuit, and the other end of the third light-transmitting signal line L-TG is coupled to the third color light-emitting device in the light-transmitting display area AA2.

[0148] Since the first light-transmitting signal line L-TG, the second light-transmitting signal line L-TG and the third light-transmitting signal line L-TG have relatively high light transmittance, the light transmittance of the light-transmitting display area AA2 is not affected.

[0149] In some examples, the light-transmitting signal line L-TG may not be directly coupled to the first pixel circuit S1. The display substrate 100 may further include a bonding wire extending along the first direction. One end of the bonding wire is coupled to the first pixel circuit, and the other end of the bonding wire extends to the edge of the main display area AA1 and couples to the light-transmitting signal line. The bonding wire may be a metal signal line. The electrical conductivity of the bonding wire is greater than that of the light-transmitting signal line. Thus, the electrical resistance can be reduced.

[0150] like Figure 6AAs shown, the first sub-pixel region 121 includes the intersection of the second sub-data line L-Data1-3 and the transfer signal line L-Data1-1; the second sub-pixel region 122 is the sub-pixel region 122 of the plurality of sub-pixel regions 120 excluding the first sub-pixel region 121. A transfer hole is formed in the first sub-pixel region 121, penetrating the fourth insulating layer, and a transfer structure TC is formed in the transfer hole to couple the second sub-data line L-Data1-3 and the transfer signal line L-Data1-1, respectively. This transfer structure TC increases the first capacitance value of the parasitic capacitance (since this parasitic capacitance is formed with the data line, it will be referred to as the parasitic capacitance of the data line hereafter) between the data line in the first sub-pixel region 121 and the surrounding control signal lines (such as reset lines, scan lines, or gate lines). This increases the first capacitance value of the parasitic capacitance of the data line in the first sub-pixel region 121, thereby increasing the second capacitance value of the parasitic capacitance of the data line in the second sub-pixel region 122.

[0151] For example, the second capacitance value of the parasitic capacitance of the data line in the second sub-pixel region 122 and the capacitance value of the parasitic capacitance of the data line in the pixel region 120 with the switching line L-SW are within a range of 0.19fF to 0.31fF; the first capacitance value of the parasitic capacitance of the data line in the first sub-pixel region 121 is within a range of 0.4fF to 0.52fF. For example, the second capacitance value of the parasitic capacitance of the data line in the second sub-pixel region 122 is approximately 0.25fF, and the first capacitance value of the parasitic capacitance of the data line in the first sub-pixel region 121 is approximately 0.46fF.

[0152] In some examples, such as Figure 12A and Figure 12B As shown, in the second direction, the transfer structure TC may be located between the transfer line L-SW and the control signal line.

[0153] In some other examples, in the third direction, the transfer structure TC may be located between the data line and the control signal line. Figure 8 As shown, the control signal line is located in the first conductive layer 220. Figure 11A The data line is located in the fourth conductive layer 250. Figure 10A and Figure 10B The transfer structure TC is located in the third conductive layer 240 between the first conductive layer 220 and the fourth conductive layer 250 .

[0154] like Figure 13As shown, the display substrate 100 may further include a multiplexer (MUX). The multiplexer is located in the peripheral area of ​​the display substrate. The multiplexer is coupled to at least two of the multiple data lines and is configured to transmit the same data signal to different data lines of the at least two data lines in a time-sharing manner. The multiplexer can be connected in series between the data lines and the data driver circuit (Source IC), which can reduce the number of data lines on the display substrate and facilitate the realization of a full-screen display device.

[0155] Among them, Figure 14 As shown, the driving method of MUX is usually: turn on MUX, and write the data signal to the parasitic capacitance of the data line in the main display area AA1 through MUX, and then turn off MUX; thereafter, output the gate signal through the gate line, so that the light-emitting device writes the data signal.

[0156] When the MUX is turned off, the data signal is stored in the parasitic capacitance of the data line, which is in a passive control state and is easily interfered with by external signal fluctuations. When the gate signal on the gate line and / or the scan signal on the scan line L-Scan jumps, the data signal stored in the parasitic capacitance of the data line will be interfered with by the signal jump.

[0157] like Figure 15 As shown, because the larger the parasitic capacitance is, the greater the degree of data signal jump on the parasitic capacitance caused by interference from external signal jumps, the deviation of the data voltage on the parasitic capacitance of the data line stored in the first sub-pixel area 121 caused by interference from gate signal and / or scan signal jumps is greater than the deviation of the data voltage on the parasitic capacitance of the data line stored in the second sub-pixel area 122 caused by interference from gate signal and / or scan signal jumps. Finally, the brightness of the light-emitting device coupled to the pixel circuit in the first sub-pixel area 121 is greater than the brightness of the light-emitting device coupled to the pixel circuit in the second sub-pixel area 122, resulting in the problem of uneven display brightness of the display substrate.

[0158] like Figure 16 As shown, the brightness of the light-emitting devices coupled to the pixel circuits in the first sub-pixel region 121 is greater than the brightness of the light-emitting devices coupled to the pixel circuits in the second sub-pixel region 122. Taking the "V"-shaped arrangement of the first sub-pixel regions 121 as an example, the light-emitting devices coupled to the pixel circuits in the first sub-pixel region 121 form a "V"-shaped bright band below the light-transmitting display area.

[0159] Based on this, the display substrate 100 provided in some embodiments of the present disclosure can overcome the problem of uneven display brightness.

[0160] For ease of understanding, the following description uses the control signal line as the scan line L-Scan and the parasitic capacitance of the data line as the parasitic capacitance between the data line and the scan line L-Scan as an example. However, this should not be used as a limitation on the control signal line and the parasitic capacitance.

[0161] The transfer structure TC is coupled to the first data line L-Data1 and is located between the first data line L-Data1 and the scan line L-Scan in the third direction Z. This increases the parasitic capacitance between the line segment of the data line within the first sub-pixel region 121 and the scan line L-Scan, thereby increasing the first capacitance value of the parasitic capacitance between the first data line L-Data1 and the scan line L-Scan. Furthermore, the orthographic projection of the transfer structure TC on the substrate is not completely covered by the orthographic projection of the data line on the substrate, thereby increasing the parasitic capacitance between the line segment of the data line within the first sub-pixel region 121 and the scan line L-Scan, thereby increasing the first capacitance value of the parasitic capacitance between the first data line L-Data1 and the scan line L-Scan.

[0162] In some embodiments of the present disclosure, the display substrate 100 provides a display substrate 100 that increases the parasitic capacitance between the data line segment within the second sub-pixel region 122 and the scan line L-Scan, such that the difference between the first capacitance value of the parasitic capacitance of the first data line L-Data1 and the second capacitance value of the parasitic capacitance of the second data line L-Data2 is less than or equal to 0.15 fF. This reduces the difference in data voltage caused by interference from peripheral signal transitions in the parasitic capacitances within each sub-pixel region 120, facilitating uniformity in the data voltage stored in the parasitic capacitances within each sub-pixel region 120, and thereby improving the uniformity of display brightness across the display substrate 100.

[0163] Two methods for increasing the second capacitance value of the parasitic capacitance between the data line segment in the second sub-pixel region 122 and the scan line L-Scan are provided below for illustration. It should be understood that the two methods are merely for illustration purposes and do not represent the only two methods.

[0164] The first way: Figure 10A As shown, the second sub-pixel region 122 further includes a dummy switching structure NTC. It can be understood that the dummy switching structure NTC is coupled to the line segment of the data line in the second sub-pixel region 122 and is separated from the switching line.

[0165] It should be noted that the data line segment within the second sub-pixel region 122 can be a segment of the first data line L-Data1 or a segment of the second data line L-Data2. Specifically, if the data line within the second sub-pixel region 122 is a segment of the first data line L-Data1, it can be a segment of the first sub-data line L-Data1-2 or a segment of the second sub-data line L-Data1-3 that is not directly coupled to the adapter line (which can also be understood as a segment of the second sub-data line L-Data1-3 located outside the first sub-pixel region 121).

[0166] In some embodiments, as Figure 10A As shown, the transfer structure TC includes a first transfer portion Z1 coupled to a line segment of the data line in the first sub-pixel region 121, and a second transfer portion Z2 coupled to the first transfer portion Z1 and the transfer line L-SW. Figure 10A As shown, the second transfer portion Z2 may belong to the third conductive layer 240. The first transfer portion Z1 may penetrate the fourth insulating layer, so that the transfer line L-SW of the third conductive layer 240 is coupled to the second sub-data line L-Data1-3 of the fourth conductive layer 250 through the second transfer portion Z2.

[0167] like Figure 10A As shown, the virtual transfer structure NTC includes a third transfer portion Z3 coupled to the line segment of the data line in the second sub-pixel area 122, and a fourth transfer portion Z4 coupled to the third transfer portion Z3 and separated from the transfer line L-SW. Figure 10A As shown, the fourth transfer portion Z4 may belong to the third conductive layer 240. The third transfer portion Z3 may penetrate the fourth insulating layer, so that the fourth transfer portion Z4 of the third conductive layer 240 is coupled to the data line of the fourth conductive layer 250.

[0168] Understandably, if Figure 10A As shown, the transfer line L-SW, the second transfer portion Z2, and the fourth transfer portion Z4 can be simultaneously located in the third conductive layer 240. Therefore, the transfer line L-SW, the second transfer portion Z2, and the fourth transfer portion Z4 can be simultaneously manufactured through a single patterning process, thereby improving the manufacturing efficiency of the display substrate.

[0169] In some embodiments, the dummy transfer structure NTC and the transfer structure TC may be located between the first conductive layer 220 and the fourth conductive layer 250 .

[0170] In this way, the virtual switching structure NTC can shorten the average spacing distance between the scanning signal of the scanning line L-Scan of the first conductive layer 220 and the data signal of the data line of the fourth conductive layer 250 in the third direction, that is, it increases the parasitic capacitance between the line segment of the data line in the second sub-pixel area 122 and the scanning line L-Scan, so that the second capacitance value of the parasitic capacitance on the second data line L-Data2 increases.

[0171] In some embodiments, the orthographic projection area of ​​the dummy transfer structure NTC on the substrate is smaller than or substantially equal to the orthographic projection area of ​​the transfer structure TC on the substrate.

[0172] The orthographic projection of the virtual switching structure NTC on the substrate is not completely covered by the orthographic projection of the data line on the substrate, that is, the parasitic capacitance between the line segment of the data line in the second sub-pixel area 122 and the scan line L-Scan is increased, so that the second capacitance value of the parasitic capacitance on the second data line L-Data2 is increased.

[0173] For example, the orthographic projection area of ​​the dummy transfer structure NTC on the substrate is smaller than the orthographic projection area of ​​the transfer structure TC on the substrate. In this case, compared to the absence of the dummy transfer structure NTC, the dummy transfer structure NTC can increase the capacitance of the parasitic capacitance between the data line segment in the second sub-pixel region 122 and the scan line L-Scan, thereby reducing the difference between the parasitic capacitance in the second sub-pixel region 122 and the parasitic capacitance in the first sub-pixel region 121. This can reduce the difference between the first capacitance value of the parasitic capacitance on the first data line L-Data1 and the second capacitance value of the parasitic capacitance on the second data line L-Data2.

[0174] For example, the orthographic projection area of ​​the virtual transfer structure NTC on the substrate is approximately equal to the orthographic projection area of ​​the transfer structure TC on the substrate, so that the parasitic capacitance between the data line segment in the second sub-pixel region 122 and the scan line L-Scan is approximately equal to the parasitic capacitance between the data line segment in the first sub-pixel region 121 and the scan line L-Scan. In this way, the capacitance of the data line segments within each sub-pixel region 120 is approximately equal, which can ensure that the first capacitance value of the parasitic capacitance on the first data line L-Data1 and the second capacitance value of the parasitic capacitance on the second data line L-Data2 are approximately equal.

[0175] In this way, the difference of each parasitic capacitor due to the interference of peripheral signal jumps can be reduced, which facilitates the unification of the deviation of the data signal stored in each parasitic capacitor, thereby facilitating the improvement of the uniformity of the display brightness of the display substrate.

[0176] In some embodiments, the orthographic projection of the transfer structure TC on the substrate may at least partially overlap with the orthographic projection of the line segment of the second sub-data line L-Data1-3 in the first sub-pixel area 121 on the substrate; the orthographic projection of the virtual transfer structure NTC on the substrate may at least partially overlap with the orthographic projection of the line segment of the data line in the second sub-pixel area 122 on the substrate.

[0177] In this way, the layout space occupied by the transfer structure TC and the dummy transfer structure NTC in the first direction of the display substrate can be reduced, thereby avoiding affecting the layout space of the pixel circuit on the display substrate, thereby being adaptable to display substrates using various pixel circuits.

[0178] It can be understood that the difference between the dummy transfer structure NTC and the transfer structure TC is that the transfer structure TC is coupled to the transfer signal line, while the dummy transfer structure NTC is separated from the transfer signal line.

[0179] Therefore, in the first approach, the virtual transfer structure NTC can increase the parasitic capacitance between the data line segment within the second sub-pixel region 122 and the scan line L-Scan. Consequently, the second capacitance value of the parasitic capacitor on the second data line L-Data2 can be close to, or even roughly equal to, the first capacitance value of the parasitic capacitor on the first data line L-Data1. This can reduce the data voltage differences caused by the parasitic capacitance within each sub-pixel region due to interference from surrounding signal transitions, facilitating the standardization of data voltage deviations stored in the parasitic capacitance within each sub-pixel region, thereby improving the uniformity of display brightness across the display substrate.

[0180] The second way: Figure 11B As shown, the average size of the data line segments in the second sub-pixel region 122 in the first direction is greater than the average size of the data line segments in the first sub-pixel region 121 in the first direction.

[0181] In some embodiments, as Figure 11B As shown, the data line segments within the second sub-pixel region 122 include a second main portion B1 extending along the second direction, and a second extension portion B2 extending from the second main portion B1 along the first direction. The size of the second main portion B1 in the first direction is substantially equal to the size of the data line segments within the first sub-pixel region 121 in the first direction. Therefore, due to the addition of the extension portion B2, the average size of the data line segments within the second sub-pixel region 122 in the first direction is greater than the average size of the data line segments within the first sub-pixel region 121 in the first direction.

[0182] The orthographic projection of the extension portion B2 in the second sub-pixel region 122 on the substrate at least partially overlaps with the orthographic projection of the scan line L-Scan on the substrate. This increases the relative area between the two plates of the parasitic capacitance between the data line segment in the second sub-pixel region 122 and the scan line L-Scan, thereby increasing the parasitic capacitance of the data line in the second sub-pixel region 122.

[0183] For example, Figure 12C As shown, the relative area M1 between the data line segment in the second sub-pixel region 122 and the scan line L-Scan is larger than the relative area M2 between the data line segment in the first sub-pixel region 121 and the scan line L-Scan. Thus, the parasitic capacitance of the data line in the second sub-pixel region 122 is increased.

[0184] Thus, by increasing the capacitance of the parasitic capacitor of the data line in the second sub-pixel area 122 , the first capacitance of the parasitic capacitor on the first data line L-Data1 and the second capacitance of the parasitic capacitor on the second data line L-Data2 can be made substantially equal.

[0185] In some examples, such as Figure 12C As shown, the dimension of the second extension portion B2 in the second direction is greater than the dimension of the scan line L-Scan in the second direction.

[0186] In this way, the range of alignment between the second extension portion B2 of the extension portion and the scan line L-Scan can be increased, the tolerance of alignment errors during the display substrate manufacturing process can be improved, and it can be ensured that the second extension portion B2 of the extension portion can be aligned with the scan line L-Scan, thereby increasing the second capacitance value of the parasitic capacitance of the data line in the second sub-pixel area 122.

[0187] Therefore, in the second approach, by increasing the size of the data line in the first direction within the second sub-pixel region 122, the parasitic capacitance between the data line and the scan line L-Scan within the second sub-pixel region 122 is increased. Thus, by increasing the parasitic capacitance of the data line within the second sub-pixel region 122, the first capacitance of the parasitic capacitance on the first data line L-Data1 and the second capacitance of the parasitic capacitance on the second data line L-Data2 can be made substantially equal. This helps to uniformly adjust the deviation of the data voltage stored in the parasitic capacitance within each sub-pixel region 120, thereby improving the uniformity of the display brightness across the display substrate.

[0188] Secondly, in addition to the two methods mentioned above of increasing the second capacitance value of the parasitic capacitance between the second data line L-Data2 and the scan line L-Scan, the difference between the first capacitance value and the second capacitance value can also be reduced by reducing the first capacitance value of the parasitic capacitance of the data line in the first sub-pixel area 121.

[0189] The following provides an explanation of a method for reducing the first capacitance value of the parasitic capacitance of the data line in the first sub-pixel region 121. It should be understood that this method is only for the sake of illustration and does not represent the only method.

[0190] The third way: Figure 10B 、 Figure 12B and Figure 12D As shown, in the second direction, the spacing distance d between the transfer structure TC and the scan line L-Scan is greater than or equal to 5 μm.

[0191] When the spacing distance d between the transfer structure TC and the scan line L-Scan is 1.45 μm, the first capacitance value of the parasitic capacitance between the data line segment in the first sub-pixel region 121 and the scan line L-Scan is 0.46 femtofarad (fF).

[0192] In this embodiment, the transfer structure TC is arranged away from the scan line L-Scan. For example, the transfer hole is arranged close to the transfer signal line, thereby increasing the spacing between the transfer structure TC and the scan line L-Scan and reducing the orthographic projection area of ​​the fourth transfer portion on the substrate.

[0193] In this way, the spacing distance d between the transfer structure TC and the scan line L-Scan is greater than or equal to 5 μm, thereby reducing the first capacitance value of the parasitic capacitance in the first sub-pixel region 121 .

[0194] Exemplarily, when the spacing distance d between the transfer structure TC and the scan line L-Scan is 6.7 μm, the first capacitance value of the parasitic capacitance between the line segment of the data line in the first sub-pixel area 121 and the scan line L-Scan is reduced to 0.32 femtofarads (fF).

[0195] Therefore, in the third approach, by increasing the spacing between the transfer structure TC and the scan line L-Scan, the first capacitance value of the parasitic capacitor in the first sub-pixel region 121 can be reduced. This can reduce the difference in data voltage caused by the parasitic capacitor in the first sub-pixel region 121 due to interference from scan signal transitions, making it easier to unify the deviation in data voltage stored in the parasitic capacitor in each sub-pixel region, thereby improving the uniformity of display brightness across the display substrate.

[0196] In addition, in addition to reducing the difference between the first capacitance value and the second capacitance value in the above three methods, thereby reducing the difference between the data voltage jump caused by the scan signal jump interference on the parasitic capacitor in the first sub-pixel region 121 and the data voltage jump caused by the scan signal jump interference on the parasitic capacitor in the second sub-pixel region 122, the above initial line can also be used to stabilize the jump of the data voltage on the parasitic capacitor in the first sub-pixel region 121.

[0197] The following provides a method for using the initial line to stabilize the jump of the data voltage on the parasitic capacitor in the first sub-pixel area 121. It should be understood that this method is only for the convenience of illustration and does not mean that this is the only method.

[0198] A fourth method: the spacing distance between at least one initial line and the transfer structure TC is less than or equal to 2 μm.

[0199] The initialization line is configured to transmit an initialization signal with a constant voltage value, thus having stable characteristics. By ensuring that the distance between the transfer structure TC and at least one initialization line is less than or equal to 2μm, the initialization line can mitigate the impact of data voltage jumps on the parasitic capacitance within the first sub-pixel region 121 caused by scan signal jump interference. This reduces or even eliminates the difference in data voltage between the parasitic capacitance within the first sub-pixel region 121 and the parasitic capacitance within the second sub-pixel region 122 caused by scan signal jump interference. This helps to unify the deviation of the data voltage stored in the parasitic capacitance within each sub-pixel region, thereby improving the uniformity of the display brightness of the display substrate.

[0200] In some embodiments, as Figure 12A As shown, the orthographic projection of at least one initial line on the substrate at least partially overlaps with the orthographic projection of the transfer structure TC on the substrate.

[0201] For example, Figure 12A As shown, the orthographic projection of the transfer structure TC on the substrate at least partially overlaps with the orthographic projections of the third initial signal line L-Vinit3 and the second initial signal line L-Vinit2 on the substrate.

[0202] For example, Figure 12B As shown, the orthographic projection of the transfer structure TC on the substrate at least partially overlaps with the orthographic projection of the third initial line L-Vinit3 on the substrate.

[0203] In this way, the distance between the transfer structure TC and the initial line can be shortened, and the initial line can be improved to reduce the data voltage jump on the parasitic capacitor in the first sub-pixel area 121 caused by the interference of the scan signal jump.

[0204] Therefore, in the fourth approach, by reducing the distance between the transfer structure TC and the initial line, the parasitic capacitance within the first sub-pixel region 121 is enhanced in its ability to resist interference, thereby reducing the impact of data voltage jumps on the parasitic capacitance within the first sub-pixel region 121 caused by interference from scanning signal jumps. This facilitates standardizing the deviation of the data voltage stored in the parasitic capacitance within each sub-pixel region, thereby facilitating improved brightness uniformity across the display substrate.

[0205] It should be noted that the above four methods can be implemented individually, in combination with multiple methods, or in combination with other methods, which is not limited here.

[0206] In summary, the display substrate provided by the embodiments of the present disclosure is designed so that the difference between the second capacitance value of the parasitic capacitance between the data line segment in the second sub-pixel region 122 and the scan line L-Scan and the first capacitance value of the parasitic capacitance between the data line segment in the first sub-pixel region 121 and the scan line L-Scan is less than or equal to 0.15 fF. This reduces the difference in data voltage caused by the parasitic capacitance in each sub-pixel region due to interference from surrounding signal transitions, facilitating uniformity in the data voltage stored in the parasitic capacitance in each sub-pixel region, thereby improving the uniformity of the display brightness of the display substrate.

[0207] The embodiment of the present disclosure further provides a method for driving a display substrate, wherein the display substrate is the display substrate of any of the above embodiments.

[0208] In some embodiments, taking the example of a display unit area including a red light-emitting device, a green light-emitting device, and a blue light-emitting device, when the number of columns of first light-emitting devices in the light-transmitting display area is 6a (a is a positive integer) columns and the number of columns of first light-emitting devices in the light-transmitting display area occupies columns m+1 to m+6a, the transfer structure is laid out starting from the n+1th row.

[0209] In some examples, such as Figure 17 As shown, the transition structure arranged from row n+1 to row n+a is used to couple with the green light-emitting device in the light-transmitting display area; the transition structure arranged from row n+a+1 to row n+2a is used to couple with the red light-emitting device in the light-transmitting display area; and the transition structure arranged from row n+2a+1 to row n+3a is used to couple with the blue light-emitting device in the light-transmitting display area.

[0210] The positions of the switching structures can be referred to Table 1, where G(x, y) indicates that the green pixel region is located at the xth row and yth column. The same is true for the red pixel region and the green pixel region, which will not be described here.

[0211] G Pixel G(n+1,m+2) G(n+1,m+5) ...... G(n+a,m+3a-1) G(n+a,m+3a+2) ...... G(n+2,m+6a-4) 3a-1) R Pixel R(n+a+1,m+1) R(n+a+2,m+4) ...... R(n+2a,m+3a-2) R(n+2a,m+3a+1) ...... R(n+a+2,m+6a-5) R(n+a+1,m+6a-1) B pixel R(n+2a+1,m+3) R(n+2a+1,m+6) ...... B(n+3a,m+3a) B(n+3a+1,m+3a+3) ....... B(n+2a+2,m+6a-3) B(n+2a+1,m+6a)

[0212] Table 1

[0213] Among them, the multiple transfer structures arranged in rows n+1 to n+a are arranged in a "V" shape; similarly, the multiple transfer structures arranged in rows n+a+1 to n+2a are arranged in a "V" shape; similarly, the multiple transfer structures arranged in rows n+2a+1 to n+3a are arranged in a "V" shape.

[0214] In other examples, such as Figure 18As shown, rows n+1 to n+3a are arranged in sequence: a transfer structure for coupling with a red light-emitting device in the light-transmitting display area, a transfer structure for coupling with a green light-emitting device in the light-transmitting display area, and a transfer structure for coupling with a blue light-emitting device in the light-transmitting display area.

[0215] The positions of the switching structures can be referred to Table 2, where G(x, y) indicates that the green pixel region is located at the xth row and yth column. The same is true for the red pixel region and the green pixel region, which will not be described in detail here.

[0216] G Pixel G(n+2,m+2) G(n+5,m+5) ...... G(n+3a-1,m+3a-1) G(n+3a-1,m+3a+2) ...... G(n+5m+6a-4) G(n+2,m+6a-1) R Pixel R(n+1,m+1) R(n+4,m+4) ...... R(n+3a-2,m+3a-2) R(n+3a-2,m+3a+1) ...... R(n+6,m+6a-5) R(n+3,m+6a-2) B pixel B(n+3,m+3) B(n+6,m+6) ...... B(n+3a,m+3a) B(n+3a,m+3a+3) ...... B(n+4a,m+6a-3) B(n+1,m+6a)

[0217] Table 2

[0218] Among them, the multiple transfer structures arranged in rows n+1 to n+6a are arranged in a "V" shape.

[0219] It should be noted that when the display substrate adopts the above-mentioned different layout methods for multiple adapter structures, the data driving circuit needs to match different data voltages for each light-emitting device. Regardless of which adapter structure layout method the display substrate adopts in Table 1 or Table 2, the display substrate driving method provided in the embodiments of the present disclosure is applicable.

[0220] The driving method of the display substrate, such as Figure 19 As shown, it includes: steps S510 to S530.

[0221] Step S510: obtaining a first sub-pixel region where a transfer structure is located among a plurality of pixel regions.

[0222] As mentioned above, the first capacitance value of the parasitic capacitance in the first pixel area is greater than the second capacitance value of the parasitic capacitance in the second pixel area, resulting in the phenomenon that the brightness of the light-emitting device coupled to the pixel circuit in the first sub-pixel area is greater than the brightness of the light-emitting device coupled to the pixel circuit in the second sub-pixel area.

[0223] Therefore, in some examples, the data driving circuit can detect the brightness of each light-emitting device to determine the light-emitting device with higher brightness, and then determine the first sub-pixel region where the pixel circuit coupled to the light-emitting device with higher brightness is located. In other examples, the data driving circuit can also detect the capacitance value of the parasitic capacitance of the data line in each sub-pixel region to determine the first sub-pixel region where the parasitic capacitance with higher capacitance is located.

[0224] In addition, in some other examples, the data driving circuit may also receive data information including a preset first sub-pixel region input by a staff member, thereby determining the first sub-pixel region where the switching structure is located.

[0225] Step S520 : reducing the grayscale value corresponding to the first sub-pixel region, and increasing the voltage value of the data signal based on the reduced grayscale value.

[0226] like Figure 20 As shown, Figure 20 The solid line in the middle is the grayscale value corresponding to the original first sub-pixel area. Figure 20 The middle dashed line represents the grayscale value corresponding to the first sub-pixel region after the grayscale value is reduced. It can be understood that the grayscale value of the first sub-pixel region is remapped to a lower grayscale value.

[0227] When the first sub-pixel regions are coupled to light-emitting devices of different colors, each first sub-pixel region may have the same mapping lines or different mapping lines, which is not limited here. Furthermore, when the display substrate is in different brightness bar scenarios, the mapping lines corresponding to a first sub-pixel region may be the same or different to meet the display requirements of different environments, which is not limited here.

[0228] in, Figure 20 The configuration lines in can only determine the grayscale values ​​corresponding to some brightness values, and the grayscale values ​​corresponding to the remaining brightness values ​​can be calculated based on the linear relationship.

[0229] In order for the first sub-pixel region to display based on the reduced grayscale value, the data driving circuit increases the voltage value of the data signal provided to the pixel circuit in the first sub-pixel region.

[0230] Step S530: providing a data signal with a boosted voltage value to each first sub-pixel region, so that the light-emitting device corresponding to the first pixel region emits light.

[0231] The data driving circuit transmits the data signal with a boosted voltage value to the pixel circuit in the first sub-pixel area, which is then provided to the corresponding light-emitting device by the pixel circuit in the first sub-pixel area, thereby reducing the brightness of the light-emitting device coupled to the pixel circuit in the first sub-pixel area, thereby making the brightness of the light-emitting device coupled to the pixel circuit in the first sub-pixel area close to or even equal to the brightness of the light-emitting device coupled to the pixel circuit in the second sub-pixel area.

[0232] In summary, the display substrate driving method provided by the embodiments of the present application can reduce the brightness of the light-emitting devices coupled to the pixel circuits in the first sub-pixel region, thereby making the brightness of the light-emitting devices coupled to the pixel circuits in the first sub-pixel region close to or even equal to the brightness of the light-emitting devices coupled to the pixel circuits in the second sub-pixel region. This can improve the uniformity of the brightness of the light-emitting devices on the display substrate, thereby enhancing the display quality of the display device.

[0233] like Figure 1As shown, an embodiment of the present disclosure provides a display device 1000. The display device 1000 includes a display substrate 100 and an optical sensor 200. The display substrate 100 is the display substrate 100 provided in any of the above embodiments.

[0234] The display substrate 100 includes a display side 100A for emitting light and a back side 100B opposite to the display side 100A. The optical sensor 200 is located on the back side 100B of the display substrate 100 , with its light-collecting side facing the back side 100B.

[0235] The light collection area of ​​the optical sensor 200 at least partially overlaps with the light-transmitting display area AA2 of the display substrate 100, so that the optical sensor 200 can capture images (such as facial images, scenes, etc.) on the display side 100A of the display substrate 100 through the light-transmitting display area AA2 of the display substrate 100.

[0236] In some examples, the orthographic projection of the edge of the light-collecting area of ​​the optical sensor 200 on the display substrate 100 substantially coincides with the edge of the light-transmitting display area AA2 .

[0237] In some examples, optical sensor 200 may be a camera.

[0238] Since the display device 1000 includes the display substrate 100 provided by any of the above embodiments, the display device 1000 has the beneficial effects of the display substrate 100 provided by any of the above embodiments, which are not described in detail here.

[0239] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, characterized in that: include: A substrate comprising a display area and a peripheral area located on at least one side of the display area, wherein the display area comprises a light-transmitting display area and a main display area located on at least one side of the light-transmitting display area; A plurality of light-emitting devices, including a plurality of first light-emitting devices and a plurality of second light-emitting devices, wherein the plurality of first light-emitting devices are located in the light-transmitting display area, and the plurality of second light-emitting devices are located in the main display area; a plurality of pixel circuits located in the main display area; the plurality of pixel circuits including a plurality of first pixel circuits and a plurality of second pixel circuits, the plurality of first pixel circuits being coupled to the plurality of first light-emitting devices via a plurality of conductive lines, the plurality of second pixel circuits being coupled to the plurality of second light-emitting devices, and the plurality of second pixel circuits being spaced apart and distributed between the first pixel circuits; a plurality of data lines, including a plurality of first data lines and a plurality of second data lines; the first data lines include a transfer signal line extending along a first direction, a first sub-data line and a second sub-data line extending along a second direction, the transfer signal line being located between the plurality of pixel circuits and coupled to the first sub-data line and the second sub-data line, respectively, the second direction intersecting the first direction; the first sub-data line being coupled to the first pixel circuit, and the second data line and the second sub-data line being coupled to the second pixel circuit; a plurality of control signal lines extending along the first direction, wherein the plurality of control signal lines are coupled to the plurality of first pixel circuits and the plurality of second pixel circuits; The parasitic capacitance between the first data line and the control signal line has a first capacitance value, the parasitic capacitance between the second data line and the control signal line has a second capacitance value, and the difference between the first capacitance value and the second capacitance value is less than or equal to 0.15fF.

2. The display substrate according to claim 1, wherein: The first capacitance value is equal to the second capacitance value.

3. The display substrate according to claim 1 or 2, wherein: The main display area also includes: A plurality of sub-pixel regions, wherein the plurality of pixel circuits are respectively located in the plurality of sub-pixel regions; the plurality of sub-pixel regions include a first sub-pixel region and a second sub-pixel region; the first sub-pixel region includes a transfer structure; The second sub-data line is coupled to the transfer signal line through the transfer structure.

4. The display substrate according to claim 3, wherein: The second sub-pixel region further includes a dummy switching structure; the dummy switching structure is coupled to a line segment of the data line in the second sub-pixel region and is separated from the switching signal line.

5. The display substrate according to claim 4, wherein: The orthographic projection area of ​​the virtual transfer structure on the substrate is smaller than or equal to the orthographic projection area of ​​the transfer structure on the substrate.

6. The display substrate according to claim 4, wherein: The orthographic projection of the switching structure on the substrate at least partially overlaps with the orthographic projection of the second sub-data line on the substrate; The orthographic projection of the dummy switching structure on the substrate at least partially overlaps with the orthographic projection of the second data line on the substrate.

7. The display substrate according to claim 4, wherein: The transfer structure includes a first transfer portion coupled to the second sub-data line, and a second transfer portion coupled to the first transfer portion and the transfer signal line; The virtual transfer structure includes a third transfer portion coupled to the second data line, and a fourth transfer portion coupled to the third transfer portion and separated from the transfer signal line; The transfer signal line, the second transfer portion and the fourth transfer portion are arranged on the same layer.

8. The display substrate according to claim 3, wherein: An average size of the data line segments in the second sub-pixel region in the first direction is greater than an average size of the data line segments in the first sub-pixel region in the first direction.

9. The display substrate according to claim 8, wherein: The line segment of the data line in the second sub-pixel area includes a main portion extending along the second direction, and an extension portion extending from the main portion along the first direction; An orthographic projection of the extension portion on the substrate at least partially overlaps with an orthographic projection of the control signal line on the substrate.

10. The display substrate according to claim 9, wherein: A dimension of the extending portion in the second direction is greater than a dimension of the control signal line in the second direction.

11. The display substrate according to claim 3, wherein In the second direction, a spacing distance between the transfer structure and the control signal line is greater than or equal to 5 μm.

12. The display substrate according to claim 3, wherein Also includes: The distance between at least one of the multiple initial lines and the transfer structure is less than or equal to 2 μm.

13. The display substrate according to claim 12, wherein: An orthographic projection of the at least one initial line on the substrate at least partially overlaps with an orthographic projection of the transfer structure on the substrate.

14. The display substrate according to claim 3, wherein: In the second direction, the switching structure is located between the switching signal line and the control signal line.

15. The display substrate according to claim 3, wherein A plurality of transfer structures are located on one side of the light-transmitting display area in the second direction, and the plurality of transfer structures are arranged in at least one "V" shape.

16. The display substrate according to claim 1, wherein The control signal line includes at least one of a reset signal line and a gate signal line.

17. The display substrate according to claim 1, wherein Also includes: a plurality of transparent signal lines extending along the first direction; One end of each transparent signal line is coupled to the first pixel circuit, and the other end of each transparent signal line is coupled to the first light-emitting device in the light-transmitting display area.

18. The display substrate according to claim 1, wherein The display substrate further includes a multiplexer located in the peripheral area, the multiplexer is coupled to at least two data lines of the plurality of data lines, and the multiplexer is configured to transmit the same data signal to different data lines of the at least two data lines in a time-sharing manner.

19. A display device, characterized in that: include: The display substrate according to any one of claims 1 to 18; an optical sensor, located on the back side of the display substrate, the back side of the display substrate being a side opposite to the display side of the display substrate; The light collection area of ​​the optical sensor at least partially overlaps with the light-transmitting display area of ​​the display substrate.

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