Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The method of fabricating the semiconductor device includes forming a magnetic tunneling junction (MTJ) stack structure on a substrate, forming a first spin orbit torque (SOT) layer on the MTJ stack structure, forming a first hard mask on the first SOT layer, and patterning the first hard mask, the first SOT layer, and the MTJ stack structure using a second hard mask to form an MTJ.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor devices, and more particularly to a method for manufacturing magnetoresistive random access memory (MRAM) devices. Background Technology

[0002] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be fabricated, which has the advantage of retaining stored data even when no power is applied.

[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a semiconductor device. First, a magnetic tunneling junction (MTJ) stack structure is formed on a substrate. Then, a first spin orbit torque (SOT) layer is formed on the MTJ stack structure. A first hard mask is formed on the first SOT layer. Finally, a second hard mask is used to pattern the first hard mask, the first SOT layer, and the MTJ stack structure to form an MTJ.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a magnetic tunneling junction (MTJ) disposed on a substrate, a first spin orbit torque (SOT) layer disposed on the MTJ, a second SOT layer disposed on the first SOT layer, and a hard mask disposed between the first SOT layer and the second SOT layer. Attached Figure Description

[0006] Figures 1 to 7 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention.

[0007] Explanation of main component symbols

[0008] 12: Base

[0009] 14: MRAM region

[0010] 16: Logical Area

[0011] 18: Interlayer dielectric layer

[0012] 20: Metal interconnect structure

[0013] 22: Metal interconnect structure

[0014] 24: Intermetallic dielectric layer

[0015] 26: Metal interconnects

[0016] 28: Stop Layer

[0017] 30: Intermetallic dielectric layer

[0018] 32: Metal interconnects

[0019] 34: Barrier Layer

[0020] 36: Metal layer

[0021] 38: Lower electrode

[0022] 40: MTJ stacked structure

[0023] 42: Upper electrode

[0024] 44: First SOT layer

[0025] 46: Hard Mask

[0026] 48:MTJ

[0027] 50: Covering layer

[0028] 52: Intermetallic dielectric layer

[0029] 54: Second SOT layer

[0030] 56: Intermetallic dielectric layer

[0031] 58: Metal interconnects

[0032] 60: Stop Layer

[0033] 62: Intermetallic dielectric layer

[0034] 64: Metal interconnects

[0035] 66: Interstitial wall

[0036] 68: Hard Mask Detailed Implementation

[0037] Please refer to Figures 1 to 7 , Figures 1 to 7 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of a semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 16 are preferably defined on the substrate 12.

[0038] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 18 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 18 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 18 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0039] Then, metal interconnect structures 20 and 22 are sequentially formed on the interlayer dielectric layer 18 to electrically connect the aforementioned contact plug. The metal interconnect structure 20 includes an intermetal dielectric layer 24 and a metal interconnect 26 embedded in the intermetal dielectric layer 24. The metal interconnect structure 22 includes a stop layer 28, an intermetal dielectric layer 30 and a metal interconnect 32 embedded in the stop layer 28 and the intermetal dielectric layer 30.

[0040] In this embodiment, each metal interconnect 26 in the metal interconnect structure 20 preferably includes a trench conductor, and the metal interconnect 32 in the MRAM region 14 of the metal interconnect structure 22 includes a via conductor. Furthermore, each metal interconnect 26 and 32 in the metal interconnect structures 20 and 22 can be embedded in the inter-metal dielectric layers 24 and 30 and / or the stop layer 28 and electrically connected to each other using a single damascene fabrication process or a double damascene fabrication process. For example, each metal interconnect 26 and 32 may further include a barrier layer 34 and a metal layer 36, wherein the barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), and the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. Furthermore, in this example, the metal layer 36 in the metal interconnect 26 preferably contains copper, the metal layer 36 in the metal interconnect 32 preferably contains tungsten, the intermetallic dielectric layers 24 and 30 preferably contain silicon oxide such as tetraethylorthosilicate (TEOS), and the stop layer 28 contains a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited thereto.

[0041] Next, a lower electrode 38, an MTJ stack structure 40, an upper electrode 42, a first spinorbit torque (SOT) layer 44, a hard mask 68, and another hard mask 46 are formed on the metal interconnect structure 22. In this embodiment, the MTJ stack structure 40 can be formed by first sequentially forming a pinned layer, a barrier layer, and a free layer on the lower electrode 38. In this embodiment, the lower electrode 38 and the upper electrode 42 preferably contain conductive materials, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The pinned layer may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). In addition, the fixing layer can also be made of antiferromagnetic (AFM) materials, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), and nickel oxide (NiO), to fix or restrict the magnetic moment direction of adjacent layers. The barrier layer can be made of insulating materials containing oxides, such as aluminum oxide (AlO). x The free layer can be made of ferromagnetic materials, such as iron, cobalt, nickel, or their alloys, such as cobalt-iron-boron (CoFeB), but is not limited to these. The magnetization direction of the free layer can be "freely" changed by an external magnetic field. In this embodiment, the first SOT layer 44 is preferably a channel for a spin orbit torque (SOT) MRAM, therefore its material can include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), bismuth selenide (Bi). x Se 1-x Alternatively, hard mask 68 may contain conductive or metallic materials such as ruthenium (Ru), while hard mask 46 may contain conductive or dielectric materials such as, but not limited to, titanium nitride.

[0042] Then as Figure 2As shown, an etching process, or more specifically a photolithography and etching process, is performed to pattern the hard mask 46 and expose the surface of the underlying hard mask 68. In detail, the photolithography and etching process performed in this stage preferably first forms a patterned mask (not shown), such as a patterned photoresist, on the hard mask 46. Then, using the patterned mask as a mask, an etching process is performed to remove a portion of the hard mask 46, forming a patterned hard mask 46 and exposing a portion of the surface of the underlying hard mask 68. The etching process performed in this stage preferably includes a reactive ion etching (RIE) process. It should be noted that the hard mask 68 in this embodiment preferably serves as an etch stop layer. Therefore, when removing a portion of the hard mask 46 using the reactive ion etching process in this stage, the etch formulation used can stop on the surface of the hard mask 68 without affecting the magnetic material in the underlying MTJ stack structure 40.

[0043] Subsequently, as Figure 3 As shown, a patterned hard mask 46 is used as a mask to perform one or more etching processes to remove a portion of the hard mask 68, a portion of the first SOT layer 44, a portion of the upper electrode 42, a portion of the MTJ stack structure 40, a portion of the lower electrode 38, and a portion of the intermetallic dielectric layer 30 to form at least one MTJ 48 in the MRAM region 14, and then the patterned mask 46 is removed. It is worth noting that in this embodiment, the etching process performed on the patterned upper electrode 42, MTJ stack structure 40, lower electrode 38, and intermetallic dielectric layer 30 preferably does not include reactive ion etching and only uses, for example, ion beam etching (IBE). Due to the characteristics of ion beam etching, the remaining upper surface of the intermetallic dielectric layer 30 is preferably slightly lower than the upper surface of the metal interconnect 32, and the upper surface of the intermetallic dielectric layer 30 preferably presents an arc or curved surface. Additionally, it should be noted that when removing part of the intermetallic dielectric layer 30 using the ion beam etching process in this embodiment, part of the metal interconnects 32 can be removed simultaneously, causing the metal interconnects 32 to form sloping sidewalls near the junction of the MTJ 48. Secondly, during this stage of the etching process, in addition to removing the aforementioned material layers, it is preferable to remove all the hard masks 46 simultaneously, so that only the hard mask 68 is provided above the first SOT layer 44.

[0044] A masking layer 50 is then formed on the MTJ 48, covering the surface of the intermetallic dielectric layer 30 of the MRAM region 14 and the logic region 16. In this embodiment, the masking layer 50 preferably comprises silicon nitride, but other dielectric materials such as, but not limited to, silicon oxide, silicon oxynitride, or silicon carbide may be selected according to the fabrication process requirements.

[0045] Then as Figure 4As shown, without using any patterned mask, such as a patterned photoresist, an etching process is directly performed to remove part of the masking layer 50 to form a spacer wall 66 surrounding or disposed on the MTJ 48, the first SOT layer 44, and the hard mask sidewalls. The spacer wall 66 formed preferably presents an approximately L-shape at the cross-sectional angle. Then, a deposition process, such as atomic layer deposition (ALD), is performed to form an intermetallic dielectric layer 52 on the hard mask 68, the spacer wall 66, and the intermetallic dielectric layer 30. Then, a planarization process, such as chemical mechanical polishing (CMP) or an etch-back process, is performed to remove part of the intermetallic dielectric layer 52, so that the top surface of the remaining intermetallic dielectric layer 52 is approximately flush with the top surface of the spacer wall 66 and the hard mask 68.

[0046] Subsequently, as Figure 5 As shown, a second SOT layer 54 is first formed on the first SOT layer 44 and the intermetallic dielectric layer 52. Then, a pattern transfer fabrication process is performed, for example, using a patterned mask (not shown) as a mask to remove a portion of the second SOT layer 54 located on the intermetallic dielectric layer 52, so that the remaining second SOT layer 54, besides being disposed on the hard mask 68 and the spacer wall 66, is still disposed on the intermetallic dielectric layer 52 on both sides of the spacer wall 66. In this embodiment, the second SOT layer 54 and the first SOT layer 44 preferably contain the same material. The second SOT layer 54 also serves as a channel for a spin orbit torque (SOT) MRAM, therefore its material can include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), and bismuth selenide (Bi). x Se 1-x (or a combination thereof).

[0047] like Figure 6 As shown, another intermetallic dielectric layer 56 is then formed on the second SOT layer 54 and the intermetallic dielectric layers 52 on both sides. The intermetallic dielectric layer 56 is preferably conformally disposed on the second SOT layer 54, and the intermetallic dielectric layers 52 and 56 may contain an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, for example, but not limited to silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH). Next, a planarization process is performed, for example, using a chemical mechanical polishing (CMP) process or an etch-back process to remove part of the intermetallic dielectric layer 56, but leaving the top surface of the remaining intermetallic dielectric layer 56 higher than the top surface of the second SOT layer 54.

[0048] A pattern transfer fabrication process is then performed, for example, by using a patterned mask (not shown) to remove a portion of the intermetallic dielectric layer 56, a portion of the intermetallic dielectric layer 52, a portion of the intermetallic dielectric layer 30, and a portion of the stop layer 28 between MRAM region 14 and logic region 16 to form contact holes (not shown) and expose the underlying metal interconnects 26. The contact holes are then filled with the desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization fabrication process is performed, for example, by chemical mechanical polishing to remove a portion of the metal material to form contact plugs or metal interconnects 58 electrically connecting the metal interconnects 26 within the contact holes.

[0049] Then as Figure 7 As shown, a stop layer 60 is first formed in the MRAM region 14 and the logic region 16, covering the intermetallic dielectric layer 56 and the metal interconnects 58. An intermetallic dielectric layer 62 is then formed on the stop layer 60. One or more photolithography and etching processes are performed to remove part of the intermetallic dielectric layer 62 and part of the stop layer 60 in the MRAM region 14 and the logic region 16, forming contact holes (not shown). Next, conductive material is filled into each contact hole, and a planarization process such as CMP is used to form metal interconnects 64 in the MRAM region 14 and the logic region 16, respectively, electrically connecting the underlying MTJ 48 and the metal interconnects 58. Preferably, the metal interconnects 64 in the MRAM region 14 directly contact the underlying second SOT layer 54, while the metal interconnects 64 in the logic region 16 contact the underlying metal interconnects 58.

[0050] In this embodiment, stop layer 60 and stop layer 28 may contain the same or different materials, both of which can be selected from the group consisting of nitrogen-doped carbide (NDC), silicon nitride, and silicon carbon nitride (SiCN). As with the aforementioned metal interconnects, the metal interconnects 64 disposed within the intermetallic dielectric layer 62 can be embedded within the intermetallic dielectric layer 62 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnects 64 may further include a barrier layer and a metal layer, wherein the barrier layer can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or dual-damascene fabrication processes are well-known in the art, they will not be described in detail here. This completes the fabrication of a semiconductor element according to an embodiment of the present invention.

[0051] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Include: A magnetic tunneling junction (MTJ) stack structure is formed on the substrate; A first spin orbit torque (SOT) layer is formed on the magnetic tunneling junction stack structure; A first hard mask is formed on the first spin-orbit torque layer, wherein the first hard mask comprises a conductive material; as well as The first hard mask, the first spin-orbit torque layer, and the magnetic tunneling junction stack are patterned using a second hard mask to form a magnetic tunneling junction.

2. The method of claim 1, wherein the substrate comprises an MRAM region and a logic region, the method comprising: A first intermetallic dielectric layer is formed on the substrate; A first metal interconnect is formed within the first intermetallic dielectric layer of the MRAM region; The magnetic tunneling junction stack structure is formed on the first intermetallic dielectric layer and the first metal interconnect. The first spin-orbit torque layer is formed on the magnetic tunneling junction stack structure; The first hard mask is formed on the first spin-orbit torque layer; A second hard mask is formed on the first hard mask; The second hard mask is patterned using a first etching process, and the first hard mask is exposed. as well as A second etching process is used to pattern the first hard mask, the first spin-orbit torque layer, and the magnetic tunneling junction stack to form the magnetic tunneling junction on the first metal interconnect.

3. The method of claim 2, wherein the first etching process comprises a reactive ion etching process.

4. The method of claim 2, wherein the second etching process comprises an ion beam etching process.

5. The method of claim 2, further comprising performing the second etching process to completely remove the second hard mask.

6. The method of claim 2, further comprising: A masking layer is formed on the first hard mask and the first intermetallic dielectric layer; Remove the covering layer to form a spacer wall surrounding the magnetic tunnel junction; A second intermetallic dielectric layer is formed around the gap wall; A second spin-orbit torque layer is formed on the first hard mask and the second intermetallic dielectric layer; Pattern the second spin-orbit torque layer; A third intermetallic dielectric layer is formed on the second spin-orbit torque layer; as well as A second metal interconnect is formed in this logic region.

7. The method of claim 6, wherein the top surface of the second intermetallic dielectric layer is flush with the top surface of the first hard mask.

8. The method of claim 6, wherein the top surface of the second intermetallic dielectric layer is flush with the top surface of the gap wall.

9. The method of claim 6, further comprising: A stop layer is formed on the third intermetallic dielectric layer; A fourth intermetallic dielectric layer is formed on the stop layer; A third metal interconnect is formed in the MRAM region and connects to the second spin-orbit torque layer; and A fourth metal interconnect is formed in the logic region and connected to the second metal interconnect.

10. The method of claim 1, wherein the first hard mask comprises ruthenium.

11. A semiconductor element, characterized in that, Include: A magnetic tunneling junction (MTJ) is located on a substrate. The first spin orbit torque (SOT) layer is disposed on the magnetic tunneling junction; A second spin-orbit torque layer is disposed on the first spin-orbit torque layer; and A hard mask is disposed between the first spin-orbit torque layer and the second spin-orbit torque layer. A gap wall is provided next to the magnetic tunnel junction, the first spin-orbit torque layer, and the hard mask, wherein the top surface of the gap wall is flush with the top surface of the hard mask.

12. The semiconductor device of claim 11, wherein the substrate includes an MRAM region and a logic region, and the semiconductor device comprises: A first intermetallic dielectric layer is disposed on the substrate; The first metal interconnect is disposed within the first metal inter-dielectric layer of the MRAM region; The magnetic tunnel junction is located on the inner interconnect of the first metal; A second intermetallic dielectric layer surrounds the magnetic tunneling junction; and The second metal interconnect is located within the second metal inter-dielectric layer of the logic region.

13. The semiconductor device of claim 12, further comprising: A stop layer is disposed on the second intermetallic dielectric layer; A third intermetallic dielectric layer is disposed on the stop layer; A third metal interconnect is located in the MRAM region and connects to the second spin-orbit torque layer; and The fourth metal interconnect is located in the logic area and connected to the second metal interconnect.

14. The semiconductor device of claim 11, wherein the width of the hard mask is equal to the width of the first spin-orbit torque layer.

15. The semiconductor device of claim 11, wherein the hard mask comprises ruthenium.

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