Error control method and apparatus for memory devices

Abstract

This application is directed to error control for memory devices. A memory device can be configured to perform a memory management operation that includes an error control operation. For example, a memory device can be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device can be configured to write the data to a second memory cell coupled with a target row of the memory array based on performing the error control operation on the data, and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device can also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.

Description

[0001] Cross-references

[0002] This patent application is the national phase of International Patent Application No. PCT / US2021 / 033457 filed by Yamamoto et al. on May 20, 2021, entitled "Error Control for Memory Device," which claims priority to U.S. Patent Application No. 16 / 895,960 filed by Yamamoto et al. on June 8, 2020, entitled "Error Control for Memory Device," both of which are assigned to the assignee and are expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to error control for memory devices. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write to or program the states in the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, and phase-change memory (PCM). Memory devices can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logic state for a long time, even without external power. For example, volatile memory devices like DRAM may lose their stored state when disconnected from external power. FeRAM can achieve densities similar to volatile memory but can have non-volatile characteristics because it uses ferroelectric capacitors as storage devices. Summary of the Invention

[0006] Describe a method. The method may include: initiating a management operation to transfer information from a source row of a memory device to a target row; performing an error control operation on data stored in a first memory cell coupled to the source row of the memory device, the first memory cell being located at a first column address and a first row address of the source row, at least in part based on initiating the management operation; writing the data to a second memory cell coupled to the target row of the memory device, at least in part based on performing the error control operation on the data; determining whether the management operation has been completed, at least in part based on the first column address of the first memory cell; and generating an output signal to perform the error control operation on a third memory cell coupled to the source row, at least in part based on determining whether the management operation has been completed.

[0007] A method is described. The method may include: as part of a management operation transferring information from a first segment of a memory device to a second segment, reading data from a first memory cell into a first sensing component; transferring the data from the first sensing component to an error control component; performing an error control operation on the data by the error control component, at least in part, based on the transfer of the data to the error control component; transferring the data from the error control component to a second sensing component associated with the second segment of the memory device; and transferring the data from the second sensing component to a second memory cell associated with the second segment of the memory device.

[0008] Describe an apparatus. The apparatus may include: a memory array including a first segment and a second segment; and a control component associated with the memory array and configured to cause the apparatus to: initiate a management operation to transfer information from a source row of the memory array to a target row; perform an error control operation on data stored in a first memory cell coupled to the source row of the memory array, the first memory cell being located at a first column address and a first row address of the source row, at least in part based on initiating the management operation; write the data to a second memory cell coupled to the target row of the memory array, at least in part based on performing the error control operation on the data; determine whether the management operation has been completed, at least in part based on the first column address of the first memory cell; and generate an output signal to perform the error control operation on a third memory cell coupled to the source row, at least in part based on determining whether the management operation has been completed.

[0009] Describe an apparatus. The apparatus may include: a memory array including a first segment and a second segment; and a control component associated with the memory array and configured to cause the apparatus to: read data from a first memory cell into a first sensing component as part of a management operation of transferring information from the first segment of the memory device to the second segment; transfer the data from the first sensing component to an error control component; perform an error control operation on the data by the error control component, at least in part based on the transfer of the data to the error control component; transfer the data from the error control component to a second sensing component associated with the second segment of the memory device; and transfer the data from the second sensing component to a second memory cell associated with the second segment of the memory device. Attached Figure Description

[0010] Figure 1 This document describes examples of systems that support error control for memory devices, based on the examples disclosed herein.

[0011] Figure 2 This document describes examples of memory dies that support error control for memory devices, based on the examples disclosed herein.

[0012] Figure 3 This document describes examples of memory device circuitry systems that support error control for memory devices, based on the examples disclosed herein.

[0013] Figure 4 This document describes examples of memory device circuitry systems that support error control for memory devices, based on the examples disclosed herein.

[0014] Figure 5 This document describes an example of a timing diagram supporting error control for memory devices, based on the examples disclosed herein.

[0015] Figure 6 This document describes an example of a timing diagram supporting error control for memory devices, based on the examples disclosed herein.

[0016] Figure 7 A block diagram of a memory device supporting error control for a memory device, based on examples disclosed herein, is shown.

[0017] Figure 8 and 9 A flowchart illustrating one or more methods for supporting error control of memory devices, based on examples disclosed herein, is shown. Detailed Implementation

[0018] Some memory devices can use one or more memory management operations to manage the data stored in the memory device. For example, a memory device can use wear leveling, row copying operations, or other types of operations to distribute wear and / or extend the functional lifetime of the memory device. Some of these operations may not include error control aspects, which could cause error propagation and / or introduce new errors into the data during memory management operations. Some of these operations can be configured to transfer data within the same segment of the memory device, which can limit the possibilities of data wear leveling and other distributions.

[0019] This describes systems, apparatuses, and techniques for using error control operations in memory management operations. In some cases, memory management operations (e.g., row copy operations) can be configured to include error control operations. Column address counters can be used to track whether each memory cell in a source row has been error-controlled and has been stored in a target row. In some cases, memory management operations (e.g., sense copy operations) can be configured to transfer data between different segments of a memory device. Error correction components can be configured to bi-state switch between source and target segments to facilitate the transfer of information and error control.

[0020] Initially, in reference Figure 1-2 The features of this disclosure are described in the context of the memory system and the die. (See references...) Figures 3 to 6 Features of this disclosure are described in the context of the described memory device circuitry and timing diagrams. References to, and such references to, are also provided. Figures 7 to 9 The device diagrams and flowcharts described herein, relating to error control for memory devices, further illustrate and describe these and other features of this disclosure.

[0021] Figure 1 This document describes an example of a system 100 supporting error control for a memory device, based on the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 to the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0022] System 100 may include portions of electronic devices such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptops, tablets, smartphones, cellular phones, wearable devices, networked devices, vehicle controllers, etc. Memory device 110 may be a component of the system operable to store data for use by one or more other components of system 100.

[0023] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to execute processes, such as in a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or other fixed or portable electronic device, and other instances. In some instances, host device 105 may refer to the hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some instances, external memory controller 120 may be referred to as a host or host device 105.

[0024] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various physical package dimensions for host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0025] Memory device 110 may be operable to store data for components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0026] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using bus 135.

[0027] Processor 125 may be operable to provide control or other functionality for at least a portion of system 100 or host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), as well as other instances. In some instances, external memory controller 120 may be implemented by processor 125 or be part of said processor.

[0028] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more read-only memory (ROM), flash memory, or other non-volatile memory.

[0029] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more groups, one or more tiles, one or more segments), wherein each memory cell is operable to store at least one bit of data. Memory device 110 comprising two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0030] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions enabling the memory device 110 to perform various operations, and may be operable to receive, transmit, or execute commands, data, or control information associated with components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, the one or more memory dies 160, or the processor 125. In some instances, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with a local memory controller 165 of the memory die 160.

[0031] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105.

[0032] A local memory controller 165 (e.g., local to memory die 160) may be operable to control the operation of memory die 160. In some instances, the local memory controller 165 may be operable to communicate with device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120 or processor 125, or combinations thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165, or both, may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support the described operation of device memory controller 155 or local memory controller 165.

[0033] External memory controller 120 may be operable to enable the transfer of information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 may translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120 or other components of system 100 or host device 105, or the functionality described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or a combination thereof, implemented by processor 125 or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120 or the functionality described herein may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0034] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be operable to act as part of a channel.

[0035] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be transmitted on channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0036] The memory device 110 can be configured to perform error control operations in memory management operations. For example, the memory device 110 can be configured to perform memory management operations including a row copy operation in which each memory cell of a source row of memory is copied and stored in a target row of memory. The row copy operation (e.g., a memory management operation) may include error control operations to correct bit errors to prevent them from propagating from the source row to the target row. The row copy operation may additionally include a column address counter that tracks whether each memory cell of the source row has been copied, error-controlled by the error control operation, and stored in the target row.

[0037] Alternatively, memory device 110 may be configured to perform error control operations, such as sense copy operations, during memory management operations. For example, memory device 110 may be configured to perform memory management operations including sense copy operations in which data is transferred between different segments of memory device 110 (e.g., between segments of memory array 170, between memory arrays 170, etc.). During a sense copy operation (e.g., a memory management operation), data may be read from a first memory cell within a first segment of memory device 110 into a first sensing component. An error component may be configured to bi-state switch between a first sensing component and a second sensing component to perform error control operations and transfer data from the first sensing component to the second sensing component. The data may then be transferred from the second sensing component to a second memory cell within a second segment of the memory device.

[0038] Figure 2 This document describes an example of a memory die 200 supporting error control for a memory device, based on the examples disclosed herein. The memory die 200 may be a reference. Figure 1 Examples of memory die 160 described herein. In some instances, memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. Memory die 200 may include one or more memory cells 205, each of which may be programmable to store different logical states (e.g., programmed to one of a set of two or more possible states). For example, memory cell 205 may be operable to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cell 205 (e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, as described in the reference. Figure 1 The memory array 170 is described.

[0039] Memory cell 205 may store states (e.g., polarization states or dielectric charges) representing programmable states in a capacitor. In a FeRAM architecture, memory cell 205 may include capacitor 240, which contains ferroelectric material to store charges and / or polarizations representing programmable states. Memory cell 205 may include logic storage components, such as capacitor 240 and switching component 245. Capacitor 240 may be an example of a ferroelectric capacitor. A first node of capacitor 240 may be coupled to switching component 245, and a second node of capacitor 240 may be coupled to plate line 220. Switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components.

[0040] The memory die 200 may include access lines (e.g., word lines 210, digital lines 215, and board lines 220) arranged in a pattern such as a grid. Access lines may be wires coupled to memory cells 205 and may be used to perform access operations on memory cells 205. In some instances, word lines 210 may be referred to as row lines. In some instances, digital lines 215 may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, bit lines, or board lines, or the like, are interchangeable without loss of understanding or operation. Memory cells 205 may be located at the intersections of word lines 210, digital lines 215, and / or board lines 220.

[0041] Operations such as reading and writing can be performed on memory cells 205 by activating or selecting access lines such as word line 210, digital line 215, and / or board line 220. A single memory cell 205 can be accessed at its intersection by biasing the word line 210, digital line 215, and board line 220 (e.g., applying a voltage to the word line 210, digital line 215, or board line 220). Activating or selecting a word line 210, digital line 215, or board line 220 may involve applying a voltage to the corresponding line.

[0042] Access to memory cell 205 can be controlled via row decoder 225, column decoder 230, and board driver 235. For example, row decoder 225 receives a row address from local memory controller 265 and activates word line 210 based on the received row address. Column decoder 230 receives a column address from local memory controller 265 and activates digital line 215 based on the received column address. Board driver 235 receives a board address from local memory controller 265 and activates board line 220 based on the received board address.

[0043] Selecting or deselecting memory cell 205 can be achieved by activating or deactivating switch assembly 245. Capacitor 240 can be electrically connected to digital line 215 using switch assembly 245. For example, when switch assembly 245 is deactivated, capacitor 240 can be isolated from digital line 215, and when switch assembly 245 is activated, capacitor 240 can be coupled to digital line 215.

[0044] Sensing component 250 can determine the state (e.g., polarization state or charge) stored on capacitor 240 of memory cell 205 and determine the logic state of memory cell 205 based on the detected state. Sensing component 250 may include one or more sensing amplifiers to amplify the signal output of memory cell 205. Sensing component 250 can compare the signal received from memory cell 205 across digital line 215 with reference 255 (e.g., reference voltage). The detected logic state of memory cell 205 may be provided as the output of sensing component 250 (e.g., provided to input / output 260) and may indicate the detected logic state to another component of memory device 110 including memory die 200.

[0045] The local memory controller 265 can control the operation of the memory cell 205 through various components (e.g., row decoder 225, column decoder 230, board driver 235, and sensing component 250). The local memory controller 265 can be a reference. Figure 1 Examples of the described local memory controller 165. In some instances, one or more of the row decoder 225, column decoder 230, and sensing components 235 and 250 may be located in the same location as the local memory controller 265. The local memory controller 265 may be operable to receive one or more commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the performance of one or more operations. The local memory controller 265 may generate row signals and column address signals to activate target word line 210, target digital line 215, and target board line 220. The local memory controller 265 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the magnitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed when operating the memory die 200.

[0046] The local memory controller 265 may be operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, the local memory controller 265 may perform or otherwise coordinate access operations in response to various access commands (e.g., from the host device 105). The local memory controller 265 may be operable to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0047] The local memory controller 265 is operable to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logical state. The local memory controller 265 can identify the target memory cell 205 on which the write operation will be performed. The local memory controller 265 can identify target word lines 210, target digital lines 215, and target board lines 220 coupled to the target memory cell 205. The local memory controller 265 can activate the target word lines 210, target digital lines 215, and target board lines 220 (e.g., apply a voltage to word lines 210, digital lines 215, or board lines 220) to access the target memory cell 205. The local memory controller 265 can apply a specific signal (e.g., a write pulse) to the digital line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 240 of the memory cell 205. The pulse used for the write operation may contain one or more voltage levels over a duration.

[0048] Local memory controller 265 is operable to perform read operations (e.g., sensing operations) on one or more memory cells 205 of memory die 200. During a read operation, a logical state stored on the memory cells 205 of memory die 200 can be determined. Local memory controller 265 can identify the target memory cell 205 on which the read operation will be performed. Local memory controller 265 can identify target word lines 210, target digital lines 215, and target board lines 220 coupled to the target memory cell 205. Local memory controller 265 can activate the target word lines 210, target digital lines 215, and target board lines 220 (e.g., by applying a voltage to word lines 210, digital lines 215, or board lines 220) to access the target memory cell 205. The target memory cell 205 can transmit a signal to sensing component 250 in response to applying a bias voltage to the access lines. Sensing component 250 can amplify the signal. The local memory controller 265 can activate the sensing component 250 (e.g., a latching sensing component) and then compare the signal received from the memory cell 205 with a reference 255. Based on the comparison, the sensing component 250 can determine the logic state stored in the memory cell 205.

[0049] Memory die 200 (e.g., local memory controller 265) may be configured to perform error control operations during memory management operations. For example, local memory controller 265 may be configured to perform a memory management operation including a row copy operation in which each memory cell 205 of a source row is copied and stored in a memory cell 205 of a target row. The row copy operation (e.g., memory management operation) may include error control operations to correct bit errors to prevent propagation from the source row to the target row. In this regard, local memory controller 265 may include or be communicatively coupled to an error control component that performs error control operations on each memory cell 205 during the row copy operation. The row copy operation may include a column address counter to track whether each memory cell 205 of the source row has been copied, error-controlled by the error control operation, and stored in the memory cell 205 of the target row.

[0050] The memory die 200 (e.g., local memory controller 265) may additionally or alternatively be configured to perform error control operations, such as sense copy operations, during memory management operations. For example, the local memory controller 265 may be configured to perform memory management operations including sense copy operations, wherein data is transferred between different segments of the memory die 200 or between a first memory die 200 and a second memory die 200. During a memory management operation (e.g., a sense copy operation), the local memory controller 265 may read data from a first memory cell 205 within the first segment into a sensing component 250. The error component may be configured to bi-state switch between the sensing component 250 and an additional sensing component 250 (e.g., an additional sensing component of the memory die, or a sensing component 250 of an additional memory die) to perform error control operations and transfer data from the sensing component 250 to the additional sensing component 250. The data may then be transferred from the additional sensing component 250 to a second memory cell 205 within a second segment of the memory device. In this respect, the data in the first memory cell 205 within the first segment of the memory die 200 can be copied, error-controlled by an error control operation, and stored in the memory cell 205 within the second segment of the memory die 200. Alternatively, the data in the first memory cell 205 within the first memory die 200 can be copied, error-controlled by an error control operation, and stored in the memory cell 205 within the second memory die 200.

[0051] Figure 3 This document describes an example of a memory device circuitry 300 supporting error control for a memory device, based on the examples disclosed herein. In some examples, the memory device circuitry 300 may include a circuitry of the memory die 200, or a portion thereof (e.g., a portion of the local memory controller 265, or a portion of the memory array 170).

[0052] Some memory devices may use one or more memory management operations to manage the data stored in the memory device. Examples of memory management operations may include row copying operations, sense copying operations, garbage collection operations, wear leveling operations, or other operations used to distribute wear and / or extend the functional lifetime of the memory device. During a row copying operation, data stored in one row of the memory array (e.g., the source row) may be copied and written to a second row of the memory array (e.g., the target row). However, some row copying operations may not include error control aspects, which may cause error propagation and / or introduce new errors into the data during the row copying operation. For example, in the context of a DRAM refresh or row copying operation, the data in the memory cells of the source row may already contain one or more errors when the refresh or row copying operation is performed. In such instances, some row copying operations may fail to detect or correct one or more errors in the data, and thus may propagate the incorrect memory state to the target row. Similarly, row copying operations without error control operations may also introduce new errors into the data during information transfer. Propagating errors and / or introducing new errors can make memory management operations less efficient.

[0053] Therefore, the techniques described herein for using error control operations (e.g., row copying operations, copy-to-copy operations, garbage collection operations, wear leveling operations, other operations, or combinations thereof) in memory management operations are described. In some cases, a row copying operation may include an error control operation configured to identify one or more errors in the information stored in the source row and correct the identified errors before writing the data to the memory cell of the target row. The row copying operation may additionally include techniques for tracking whether each memory cell of the source row has been copied, error control operations have been applied, and written to the target row. For example, memory device circuitry 300 may illustrate an example circuit system that determines when the row copying operation is complete by tracking a column address counter to determine whether each memory cell of the source row has been copied, error control has been applied by the error control operation, and stored in the memory cell of the target row. Such techniques improve row copying operations by preventing the propagation of bit errors throughout the memory device 110 (e.g., memory die 200), thereby improving wear leveling and memory management operations. To implement error control operations during memory management operations, column counters and other control logic can be used to identify when each column of the source row has been read.

[0054] The memory device circuitry 300 may receive a set of input signals for performing row copy operations. For example, the memory device circuitry 300 may receive write status signals, column select signals, refresh signals, and global command address signals. Input signals for the memory device circuitry 300 may be received from the host device 105 (e.g., on a CA channel) or may include or otherwise incorporate commands issued by the memory device 110 (e.g., from the device memory controller 155 or the local memory controller 265). The memory device circuitry 300 may additionally include a set of logic components (e.g., AND gates, inverting gates, etc.) configured to perform combinational logic commands on the input signals of the memory device circuitry system 300.

[0055] The memory device circuitry 300 may include a counter 305 configured to determine whether a memory management operation has been completed. Specifically, the counter 305 may be configured to track (e.g., increment) the column address of the source row of a memory management operation (e.g., a row copy operation) to track whether each column of the source row (and therefore each memory cell 205) has been copied, error-controlled by an error control operation, and written to the target row. In this regard, the counter 305 may receive signals, commands, or other indications or triggers related to the memory management operation (e.g., the row copy operation). For example, the counter 305 may include an input clock (CLK) signal, an input set signal, and an input reset signal. The set signal and reset signal can load the counter 305 with an initial column address associated with the row copy operation, and the CLK signal can periodically pulse to increment the column address counter 305, thereby providing a new column latch value until the row copy operation is complete.

[0056] The memory device circuitry 300 may additionally include a latch 310. The latch 310 may be an example of a three-input latch configured to receive a last-add signal, an activation signal, and a reset signal. The activation signal may be based on a write status signal and a column select signal, and may indicate the beginning of the next time period when the next erase may begin. The activation signal may be configured to cause the latch output to be the value input to the latch via the last-add signal. The last-add input signal may be received from a counter 305 and may indicate whether the last column of the source row of the row copy operation has been addressed. The latch 310 may be configured to generate an output signal for the row copy operation. For example, the output of the latch 310 may be used to generate a next erase signal to trigger the row copy operation on the next column of the source row, and may be used to generate a row copy termination signal when the row copy operation is complete (e.g., after the last column of the row copy operation has been addressed). Specifically, the Last Add signal can have a first value when the column address is not the last column address in the source row and a second value when the column address is the last column address in the source row, indicating when the row operation is complete. In this regard, latch 310 can generate a row copy termination signal indicating that the row copy operation ends when the Last Add input signal indicates the last column of the source row.

[0057] To initiate a row copy operation, host device 105 (e.g., on a CA channel) and / or memory device 110 (e.g., slave device memory controller 155 or local memory controller 265) may determine the source row and target row for the row copy operation. Host device 105, slave device memory controller 155, and / or local memory controller 265 may initiate a row copy operation (e.g., a management operation) to transfer information from the source row to the target row of memory die 200. Host device 105, slave device memory controller 155, and / or local memory controller 265 may initiate the row copy operation by generating one or more command signals. The one or more command signals for initiating the row copy operation may include indications of a first row address associated with the source row and a second row address associated with the target row. The one or more command signals may additionally include an indication of a first column address, indicating the first column of the source address where the row copy operation will begin.

[0058] One or more command signals used to initiate a row copy operation (e.g., a management operation) may include a column select signal, a write status signal, a tRCDdoneRfsh signal, and a global command address (CA) signal. The global CA signal may include multiple address bits indicating the column address (e.g., the first column address) of the source row currently being accessed. A row copy operation may be initiated based on the generation of a tRCDdoneRfsh signal that is high when the write status signal is low and the column select signal is high. The tRCDdoneRfsh signal may indicate that source row data sensing is complete and the copied data is latched in the source row. When the tRCDdoneRfsh signal transitions from low to high, the reset state of latch 310 may be released, while the output of latch 310 remains low. The tRCDdoneRfsh signal may be supplied as input to trigger component 355.

[0059] Trigger H component 355 may include a single trigger pulse generator that is typically low and pulse-high. Trigger H component 355 may detect a rising edge input and generate a high pulse on the output supplied to components 325 and 330 (e.g., AND components 325 and 330). Components 325 and 330 may represent multiple devices (e.g., each of a plurality of global address bits has one device available, which may be indicated via a global CA signal). Each high global CA bit, combined with a high pulse from trigger H component 355 at component 325, causes the corresponding reset to set the associated output bit from counter 305 high to indicate the state of the global CA bit. Each low global CA bit, combined with a high pulse from trigger H component 355 at component 330, causes the corresponding reset to reset the associated output bit from counter 305 low to indicate the state of the global CA bit. Therefore, a low-to-high transition of the tRCDdoneRfsh signal causes the start column address information from the global CA signal to be indicated via a reference command address signal output from counter 305. The reference command address signal can be supplied to component 335 and column latches (e.g., latch 310). The first column of the source row can be read to the error control logic, and the write status input goes high to write the first column data from the error control logic to the target row.

[0060] The write status signal and column select signal can be combined via AND gate 350 or other logic components and can be further input to trigger L component 320, wherein trigger L component 320 outputs a latch signal to be provided to latch 310 at the active input. Trigger L component 320 may include a pulse generator that is generally high and pulse-low, as will be described in more detail herein. A pulse-low at the active input to latch 310 allows the last append output decoded from the reference command address signal via component 335 to be accepted by latch 310 and presented at latch output. The output of component 350 can be additionally combined with the true output of latch 310 to fire a row copy termination signal when the last append input to latch 310 via the reference command address signal is high. The output of component 350 can be further combined with the complement output of latch 310 to fire a next erase signal when the last append input to latch 310 via the reference command address signal is low. If the next erase signal high indicates the start of another erase cycle, the write status signal will transition to a low state. The inverted write status signal can be combined with a sustained high state of the column select signal at component 315 to form a high edge on the CLK input of counter 305. This high CLK edge causes counter 305 to output and count to the next column address via the reference command address signal.

[0061] The reference command address signal can be output as a column latch signal, which triggers a row copy operation for the currently accessed selected memory cell 205. The column latch signal may contain an indication of the column address of the memory cell 205 currently being accessed for the row copy operation. In this regard, the sensing component 250 of the memory device can read the data of the first memory cell 205 of the source row identified via the first column address indicated in the column latch signal. An error control component can be configured to perform an error control operation on the data stored in the first memory cell 205 based on the column latch signal. During the error control operation, the error control component can identify errors in the data of the first memory cell 205 associated with the first row address and the first column address, and correct the errors if they exist. Subsequently, the data of the first memory cell 205 of the source row can be written to the memory cell 205 coupled to the target row of the memory die 200. The data of the first memory cell 205 of the source row can be written to the memory cell 205 of the target row based on the execution of the error control operation.

[0062] A last-added signal can be generated by processing the output of counter 305. Counter 305 can output a column address for the current copy operation or the next copy operation. Component 335 (e.g., an AND gate) can be configured to identify when the last column of the source row is being accessed. In some instances, the AND gate can be configured to combine at least a portion of the column address bits. The AND gate can output a first value when the column address bit is a first value (e.g., logic '1'), otherwise the AND gate can output a second value (e.g., logic '0'). Component 335 used to determine whether the last column address is being accessed or has been accessed can be any type of component used to compare information with a reference or threshold. The AND gate is only a single instance of this type of component. A reference command address signal can be additionally input to component 335 or other logic components configured to determine whether a row copy operation is complete based on the column address being accessed (e.g., the first column address). Specifically, component 335 can be configured to determine whether the column address satisfies a threshold associated with the source row. The threshold associated with the source row can be based on the last column address of the source row. For example, when accessing a first memory cell 205 indicated by a first column address, component 335 may be configured to combine one or more bits of the first column address into a value and compare the value with a threshold associated with the source row.

[0063] In this regard, component 335 can be configured to receive a reference command address signal and output a last-added signal. The last-added signal may contain an indication of whether the row copying operation is complete. For example, when the value generated by combining one or more bits of the first column address meets a threshold associated with the source row, the last-added signal may contain a logic '1' indicating that the row copying operation is complete. Conversely, when the value generated by combining one or more bits of the first column address does not meet the threshold associated with the source row, the last-added signal may contain a logic '0' indicating that the row copying operation is not complete.

[0064] Latch 310 may receive a last-added signal, which includes an indication of whether the row copying operation is complete. Latch 310 may also receive an input latch signal. The input latch signal may be generated based on a column selection signal generated by the device memory controller 155 or the local memory controller 265. Specifically, a column selection signal containing an indication of the column address of the source row currently being accessed may be input to trigger L component 320, which generates an activation signal.

[0065] Latch 310 may output signals to AND gates 340 and 345. AND gate 340 may be configured to receive an output signal from latch 310 and another signal based on a write status signal and a column selection signal. When the output signal of latch 310 indicates that the row copy operation is complete (e.g., the last column of the source row has been copied and written to the target row), AND gate 340 may generate a row copy termination signal to terminate the row copy operation. This will be discussed in more detail herein. AND gate 345 may be configured to receive an output signal from latch 310 and a signal based on a write status signal and a column selection signal. When the output signal of latch 310 indicates that the row copy operation is not complete (e.g., the last column of the source row has not yet been copied and written to the target row), AND gate 345 may generate a next erase signal.

[0066] The next erase signal can be configured to trigger a write status signal to re-execute at a different column address associated with the source row. Alternatively, the next erase signal can be configured to cause a column address counter (e.g., counter 305) associated with the source row to increment. Specifically, the next erase signal can be configured to increment the column address counter indicated by a column select signal. In this respect, the next erase signal can be configured to trigger a row copy operation to continue to the next column of the source address when it is determined that the row copy operation is not complete. For example, when the first column address does not meet the threshold associated with the source row, the last add signal generated by component 335 can indicate "0", indicating that the row copy operation is not complete, which can cause latch 310 to generate an output signal, triggering AND gate 345 to output the next erase signal. In this example, the next erase signal can be configured to activate a write status signal and cause the column address counter indicated by a column select signal to increment to the next column address of the source row. For example, the next erase signal can cause the column address counter to increment to the second column address of the source row.

[0067] Reasserting the write status signal and incrementing the column address counter to the second column address (indicated by the column select signal) causes a row copy operation to be initiated for the next memory cell associated with the source row address and the second column address. The column select signal can be combined with the write status signal via AND gate 315 and input as the CLK signal to counter 305. The write status signal and the column select signal can also be combined via AND gate 350, where AND gate 350 generates a signal provided to trigger L component 320 and AND gate 340.

[0068] Counter 305 can output a reference command address signal (which may contain the column address for the current or next column, part of the row copy operation) based on the CLK signal and a set signal. The reference command address signal may contain an indication of the column address of the memory cell 205 of the source row currently being accessed. For example, when performing a row copy operation on the second memory cell 205 of the source row, indicated by the second column address count, the reference command address signal may contain an indication of the second column address.

[0069] The sensing component 250 of the memory die 200 can read data stored in the second memory cell 205 at the source row address and the second column address. An error control component can be configured to perform an error control operation on the data stored in the second memory cell 205. During the error control operation, the error control component can determine whether an error exists in the data of the second memory cell 205 associated with the first row address and the second column address, and correct the error if present. Subsequently, the data in the source row's second memory cell 205 can be written to the second memory cell 205 coupled to the target row of the memory die 200. The data in the source row's second memory cell 205 can be written to the target row's memory cell 205 based on the execution of the error control operation.

[0070] The reference command address signal can be additionally input to component 335 or other logic components configured to determine whether a row copy operation is complete based on the column address being accessed (e.g., the second column address). Component 335 can be configured to determine whether the column address indicated by the reference command address signal satisfies a threshold associated with the source row. The threshold associated with the source row can be based on the last column address of the source row. For example, when accessing the second memory cell 205 indicated via the second column address, component 335 can be configured to combine one or more bits of the second column address into a value and compare it with the value associated with the source row. In this regard, component 335 can be configured to receive the reference command address signal and output a last append signal. The last append signal can be used to indicate whether a row copy operation is complete. For example, when the value generated by combining one or more bits of the second column address satisfies the threshold associated with the source row, the last append signal can contain an indication of "1", indicating that the row copy operation is complete. Conversely, when the value generated by combining one or more bits of the second column address does not meet the threshold associated with the source row, the last-add signal may contain an indication of "0", which indicates that the row copying operation is not complete.

[0071] Latch 310 may receive a last-added signal, which includes an indication of whether the row copying operation is complete. Latch 310 may also receive an activation signal, which may be based on a column selection signal. Specifically, the column selection signal, which includes an indication of the column address of the source row currently being accessed, may be input to trigger L component 320, which generates the activation signal. Latch 310 may generate an output signal to be provided to AND gates 340 and 345.

[0072] AND gate 345 can be configured to receive an output signal from latch 310 and signals based on a write status signal and a column select signal. If the output of latch 310 indicates that the row copy operation is not complete (e.g., the last column of the source row has not yet been copied and written to the target row), AND gate 345 can generate a next erase signal. For example, if the second column address is not the last column address of the source row, latch 310 can generate an output signal causing AND gate 345 to generate a next erase signal. The next erase signal can be configured to re-assert the write status signal and increment the column address counter associated with the source row. Specifically, the next erase signal can be configured to cause the column address counter to increment via the column select signal. In this respect, the next erase signal can be configured to trigger the row copy operation to continue to the next column of the source row when it is determined that the row copy operation is not complete. For example, when the second column address does not meet the threshold associated with the source row, the last append signal generated by AND gate 335 can indicate "0," indicating that the row copy operation is not complete. This can cause latch 310 to generate an output signal to trigger AND gate 345 to output the next erase signal. In this example, the next erase signal can be configured to activate a write status signal and cause a column address counter, indicated by a column select signal, to increment to the next column address of the source row. For example, the next erase signal can cause the column address counter to increment to the third column address of the source row.

[0073] AND gate 340 can be configured to receive an output signal from latch 310 and another signal based on a write status signal and a column selection signal. When the output signal of latch 310 indicates that the row copy operation is complete (e.g., the last column of the source row has been copied and written to the target row), AND gate 340 can generate a row copy termination signal to terminate the row copy operation. For example, when the second column address meets a threshold associated with the source row, the last append signal can indicate "1," indicating that the row copy operation is complete. This can cause latch 310 to generate an output signal to trigger AND gate 340 to output the row copy termination signal.

[0074] A row copy termination signal indicates that each column of the source row has been addressed through a row copy operation. In this respect, the row copy termination signal indicates the end of the row copy operation for the source row. The row copy termination signal can trigger a refresh signal (e.g., the tRCD completion signal). The refresh signal can be sent to the local memory controller 165 to terminate the row copy operation.

[0075] The target row can be precharged after the row copy operation is completed. In some cases, the device memory controller 155 and / or the local memory controller 265 may generate a signal configured to precharge the target row based on a determination that a memory management operation (e.g., a row copy operation) has been completed.

[0076] The techniques described herein with respect to memory device circuitry 300 enable improvements in memory management operations. More specifically, memory device circuitry 300 can enable row copying operations, including error control operations configured to prevent errors from propagating from the source row to the target row during row copying. Alternatively, memory device circuitry 300 can enable tracking of column address counters for the source row to ensure that row copying operations (and error control operations) are performed for each memory cell 205 (e.g., each column address) of the source row.

[0077] Figure 4 This document describes an example of a memory device circuitry 400 supporting error control for a memory device, based on the examples disclosed herein. In some examples, the memory device circuitry 300 may include the circuitry of the memory die 200, or a portion thereof (e.g., a portion of the local memory controller 265, a portion of the memory array 170).

[0078] Some memory devices can perform memory management operations, such as sense copy operations, to implement wear leveling and manage data stored in the memory device. During a sense copy operation, data from a first memory cell can be read into a sensing component and transferred to a second memory cell different from the first memory cell. However, some sense copy operations may not include error control aspects, which could cause error propagation and / or introduce new errors into the data during the sense copy operation. Furthermore, some sense copy operations are performed by a single sensing component and can transfer data between memory cells within the same segment. For example, some sense copy operations may not be able to transfer data from a first memory cell in a first segment of the memory device to a second memory cell in a second segment of the memory device. As used herein, the term "segment" can be used to refer to any subset of memory devices known in the art. For example, in some cases, a first segment can refer to a first set of sense amplifiers that can be addressed independently of a second set of sense amplifiers. The second set of sense amplifiers may be located in a second segment. Using another example, the first segment may refer to a first region within the memory die, and the second segment may refer to a second region within the memory die.

[0079] This document describes techniques for performing sense copy operations between segments of a memory device using error control operations and a set of sensing components. For example, a sense copy operation can be performed to transfer data between different segments of memory die 200 or between a first memory die 200 and a second memory die 200. In some cases, the sense copy operation may include error control operations configured to identify and correct errors within the first memory cell before copying data from the first memory cell to the second memory cell. During a sense copy operation (e.g., a memory management operation), a local memory controller 265 may read data from a first memory cell 205 within the first segment into a sensing component 250. The error component may be configured to bi-state switch between the sensing component 250 and an additional sensing component 250 associated with a destination address of the data (e.g., an additional sensing component of memory die 200, or a sensing component 250 of an additional memory die 200). The error control component may be configured to perform error control operations to identify and correct bit errors in the data of the first memory cell 205 before transferring the data to the additional sensing component 250. Data can then be transferred from the additional sensing component 250 to a second memory cell 205 within a second segment of the memory device. This technique improves the sensing copy operation, preventing bit errors from propagating throughout the memory device 110 (e.g., memory die 200), thereby improving wear leveling and memory management operations. Furthermore, the techniques disclosed herein enable sensing copy operations to be performed between two different segments of the memory device, thereby increasing flexibility in wear leveling and data management.

[0080] Memory device circuitry 400 may include a first memory cell set 405 and a second memory cell set 435. The first memory cell set 405 may include memory cells 405-a, 405-b, 405-c, and 405-d, and the second memory cell set 435 may include memory cells 435-a, 435-b, 435-c, and 435-d. The first memory cell set 405 may be associated (e.g., coupled) to a first word line 440 (e.g., a source word line 440), and the second memory cell set 435 may be associated with a second word line 445 (e.g., a destination word line 445). In some cases, a first segment of memory device 110 may include the first memory cell set 405, and a second segment of memory device 110 may include the second memory cell set 435. For example, a first segment may include the first memory cell set 405, and a second segment may include the second memory cell set 435. In some respects, the first segment may be associated with a first segment address, and the second segment may be associated with a second segment address.

[0081] The sense copy operation can be configured to transfer data from a first memory cell set 405 to a second memory cell set 435. Where the first memory cell set 405 and the second memory cell set 435 are located in different segments of the memory device 110 (e.g., different segments of the memory array 170), the sense copy operation can be configured to transfer data from one segment of the memory device 110 to another segment of the memory device 110. The memory device circuitry 400 can receive one or more input signals for initiating the sense copy operation. The one or more input signals configured to initiate the sense copy operation can be received from the host device 105 (e.g., on a CA channel), or can include or otherwise be based on commands issued by the memory device 110 (e.g., from the device memory controller 155 or the local memory controller 265).

[0082] During the sensing copy operation, data from the first memory cell 405-a can be read into the first sensing component 415-a. In some cases, the first memory cell 405-a and / or the first sensing component 415-a may be contained within a first segment of the memory device. For example, the first memory cell 405-a and the first sensing component 415-a may be contained within a first segment and / or a memory array of the memory device and / or memory array. Data can be transmitted from the first memory cell 405-a to the first sensing component 415-a via a first digital line 410-a associated with the first segment. Alternatively, data can be read from the first memory cell 405-a to the first sensing component 415-a by activating the first sensing component 415-a of the first segment. In some cases, the host device 105, the device memory controller 155, and / or the local memory controller 265 may activate the first sensing component 415-a.

[0083] Data can then be transmitted from the first sensing component 415-a to the error control component 420-a. The error control component 420-a can be configured to perform error control operations on the data. The error control component 420-a can perform error control operations on the data based on the data transmitted to the error control component 420-a. During the error control operation, the error control component 420-a can determine that the data of the first memory cell set contains one or more errors, and correct the errors if they exist. The error control component 420-a can be disposed within a first segment or a second segment of the memory device or memory array. For example, in some cases, the error control component 420-a can be included in the first segment together with the first memory cell 405-a and the first sensing component 415-a. By another example, in other cases, the error control component 420-a can be included in the second segment. In other cases, the error control component 420 can be located in any part of the memory device and may not be specifically associated with the first segment or the second segment.

[0084] In some cases, data can be transmitted from the first sensing component 415-a in the first segment to the error control component 420-a via a data line. The data line can be routed throughout the memory device and / or memory array and can be traversed from the first segment to the second segment. In this respect, data can be transmitted from the first sensing component 415-a in the first segment to the error control component 420-a in the second segment via a data line routed from the first segment to the second segment.

[0085] In some cases, data can be transferred from the first sensing component 415-a to the error control component 420-a based on the segment address of the first sensing component 415-a being latched in the first latch. For example, the first segment address associated with the first segment (e.g., the first segment address associated with the first sensing component 415-a within the first segment) can be stored in the first latch. In this example, data can be transferred from the first sensing component 415-a to the error control component 420-a based on the first segment address associated with the first sensing component 415-a being stored in the first latch.

[0086] Data can be transmitted from the error control component 420-a to the second sensing component 425-a, such as... Figure 4 As shown in the diagram. The second sensing component 425-b may be associated with a second segment of the memory device or memory array. In some cases, data may be transmitted from the error control component 420-a to the second sensing component 425-a in the second segment via a data line. The data line may be routed throughout the memory device 110 and / or memory array 170 and may be traversed from the first segment to the second segment.

[0087] In some aspects, the error control component 420-a can be configured to bi-state switch between a first sensing component 415-a and a second sensing component 425-a to transfer data between the first sensing component 415-a and the second sensing component 425-a. For example, data can be read from a first memory unit 405-a to the first sensing component 415-a by activating the first sensing component 415-a associated with the first segment. In this example, the activation of the first sensing component can be maintained to transfer data from the first sensing component 415-a to the error control component 420-a, and from the error control component 420-a to the second sensing component 425-a associated with the second segment. In this respect, the error control component 420-a can be configured to bi-state switch between the first sensing component 415-a and the second sensing component 415-b to transfer data between the first sensing component 415-a and the second sensing component 415-b based on maintaining the activation of the first sensing component 415-a.

[0088] The second sensing component 425-a can be activated to transmit data from the error control component 420-a to the second sensing component 425-b. In this regard, data can be transmitted from the error control component 420-a to the second sensing component 425-a based on the activation of the second sensing component 425-a. In some cases, the second sensing component 425-a can be activated based on error control operations performed by the error control component 420-a. In some cases, the second sensing component 425-a can be activated via the host device 105, the device memory controller 155, and / or the local memory controller 265.

[0089] In some cases, data can be transferred from error control component 420-a to second sensing component 425-a based on latching the segment address of second sensing component 425-a in a second latch. For example, the second segment address associated with a second segment (e.g., the second segment address associated with second sensing component 425-a within the second segment) can be stored in the second latch. In this example, data can be transferred from error control component 420-a to second sensing component 425-a based on storing the second segment address associated with second sensing component 425-a in the second latch.

[0090] Data can be transferred from the second sensing component 425-a to the memory unit 435-a. The memory unit 435-a may be associated with (e.g., disposed within) a second segment of the memory device 110 or the memory array 170. In some cases, data can be transferred from the second sensing component 425-a to the memory unit 435-a via a second digital line 430-a associated with the second segment.

[0091] Data stored in memory cells 405-b, 405-c, and 405-d can be similarly transferred to memory cells 435-b, 435-c, and 435-d throughout the sensing replication operation. In this regard, any description associated with transferring data from memory cell 405-a to memory cell 435-a can also be understood to apply to data transfers between memory cells 405-b, 405-c, and 405-d and memory cells 435-b, 435-c, and 435-d. For example, data in memory cell 405-b can be transferred to memory cell 435-b via digital line 410-b, sensing component 415-b, error control component 420-b, sensing component 425-b, and digital line 430-b.

[0092] While sensing components 415-a, 415-b, 415-c and 415-b, sensing components 425-a, 425-b, 425-c and 425-d, and error control components 420-a, 420-b, 420-c and 420-d are shown and described as comprising individual components, this should not be construed as a limitation of the disclosure unless otherwise indicated herein. In this respect, two or more components may be combined into a single component. For example, in some cases, error control components 420-a, 420-b, 420-c and 420-d may comprise a single error control component configured to perform error control operations for transferring data between each respective memory cell of the first memory cell set 405 and the second memory cell set 435. Similarly, in some cases, sensing components 415-a, 415-b, 415-c and 415-b may include a single sensing component associated with the first segment, and sensing components 425-a, 425-b, 425-c and 425-d may include a single sensing component associated with the second segment.

[0093] Figure 5 This document describes an example of a timing diagram 500 supporting error control for a memory device, based on the examples disclosed herein. Timing diagram 500 illustrates an example of sequentially disabling and enabling voltage sources that can be associated with sensing copy operations. Additionally, timing diagram 500 illustrates an example of sequentially disabling and enabling voltage sources that can be associated with components or operations of the memory die 200. In one example, the voltage of timing diagram 500 can be related to a reference... Figure 4 The described memory device circuitry 400 is associated with this. However, the described techniques are applicable to other components, configurations, and quantities of the voltage source for the memory die 200.

[0094] When performing a sense-copy operation to copy memory cells 205 (e.g., memory cell 405) of a source row within a first segment to memory cells 205 (e.g., memory cell 435) of a target row in a target segment, the memory die 200 can activate the source row address associated with the source row by generating a source row address signal. After the source row address becomes valid (e.g., activated), the source word line associated with the source row can be activated by generating a WordLineEnable signal. The source row address signal and the WordLineEnable signal can be configured to allow the memory die 200 to access the memory cells of the source row that will be copied during the sense-copy operation.

[0095] After both the source row address and the word line of memory cell 205 are activated (e.g., both the source row address signal and the WordLineEnable signal are activated), the memory die 200 can activate the sensing component associated with the source row (e.g., sensing component 415) by generating SenseAmpEnable. The sensing component associated with the source row (e.g., sensing component 415) can be activated at some point after the source row is activated to read (e.g., sense) the data currently being accessed in the memory cell 205 of the source row. Subsequently, the memory die 200 can latch the source row by generating the SourceSenseAmpLat signal.

[0096] The activation of the sensing component can be maintained (e.g., the SenseAmpEnable signal remains active) so that erasure can be performed back and forth from the data held in the sensing component (e.g., sensing component 415). Conversely, once the source line has been latched and the data in the memory cell 205 within the source line has been read into the sensing component, the WordLineEnable signal can be turned low, thereby releasing the activation of the source word line. In this regard, the WordLineEnable signal can be pulsed low to allow the memory die 200 to deactivate the source line address and activate the target line address. After the target line address has been activated, the WordLineEnable signal can be reactivated. Additionally, after both the target line address and the word line are activated, the memory die 200 can generate a TargetSenseAmpLat signal to activate and latch the sensing component (e.g., sensing component 425) associated with the target line.

[0097] The memory die 200 can maintain the activation of the source sensing component (e.g., sensing component 415) and the target sensing component (e.g., sensing component 425), as described by the SenseAmpEnable and TargetSenseAmpLat signals, so as to erase back and forth between the source sensing component 415 and the target sensing component 425 for error control component 420 (e.g., bi-state switching). In this respect, the error control component can bi-state switch between the source sensing component and the target sensing component to transfer data from the source sensing component to the target sensing component.

[0098] Figure 6 This document describes an example of a timing diagram 600 supporting error control for a memory device, based on the examples disclosed herein. Timing diagram 600 illustrates an example where voltage sources associated with a sensing copy operation can be sequentially disabled and enabled. Additionally, timing diagram 600 illustrates an example where voltage sources associated with components or operations of a memory die (e.g., memory die 200) can be sequentially disabled and enabled. In one example, the voltage of timing diagram 600 can be related to a reference... Figure 4 The described memory device circuit system 400 and reference Figure 5 The timing diagram 500 described is relevant. However, the described techniques are applicable to other components, configurations, and quantities of voltage sources for memory dies.

[0099] When a sense copy operation is performed, the memory die may activate a word line of the source row (e.g., source word line 440). At some point after the source row word line is activated, the memory die 200 may activate a sensing component (e.g., sensing component 415) associated with the first row. A first read from one or more memory cells 205 (e.g., memory cell 405) within the source row to an error control component (e.g., error control component 420) may be performed when both the source word line and the source sensing component are activated.

[0100] Subsequently, the activation of the source word line can be released, and the memory die can activate the target word line (e.g., target word line 445). The memory die can also activate a target sensing component (e.g., sensing component 425). The memory die can maintain the activation of the source sensing component (e.g., sensing component 415) and the target sensing component (e.g., target sensing component 425) to erase back and forth between the source sensing component and the target sensing component for an error control component (e.g., error control component 420). In this regard, the error control component can bi-state switch between the source sensing component and the target sensing component to transfer data from the source sensing component to the target sensing component. During the erase period, the memory die can maintain the activation of the target word line (e.g., target word line 445) so that data can be transferred from the error control component to the target sensing component throughout the erase period. Therefore, the bold portion within the erase period can additionally or alternatively describe the write pulses that transfer data to the target sensing component and write data from the target sensing component to the target memory cell.

[0101] Figure 7 A block diagram 700 illustrates a memory device 705 supporting error control for a memory device according to an example disclosed herein. The memory device 705 may be as described in the reference... Figure 1-6 Examples of aspects of the described memory device. Memory device 705 may include an error control component 710, an operation manager 715, a command address manager 720, and a precharge component 725. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0102] Error control component 710 can perform error control operations on data stored in a first memory cell coupled to a source row of the memory device, the first memory cell being located at a first column address and a first row address of the source row, based on initiating a management operation. In some instances, error control component 710 can perform error control operations on data by transferring data to the error control component. In some instances, error control component 710 can read data from the first memory cell. In some instances, error control component 710 can determine errors in the data of the first memory cell. In some instances, error control component 710 can correct errors based on the determined errors.

[0103] In some instances, the error control component 710 may transfer data between the first and second sensing components by bi-state switching between a first sensing component in the first segment and a second sensing component in the second segment, based on transferring data to the second memory unit. In some instances, the error control component 710 may maintain the activation of the first sensing component after transferring the data from the first sensing component to the error control component, wherein the bi-state switching between the first sensing component in the first segment and the second sensing component in the second segment is based on maintaining the activation of the first sensing component. In some instances, the error control component 710 may transfer the data from the error control component to the second sensing component associated with the second segment of the memory device. In some cases, the first segment includes a first memory unit. In some cases, the second segment includes a second memory unit.

[0104] Operation manager 715 can initiate management operations to transfer information from a source row of the memory device to a target row. In some instances, operation manager 715 can write the data to a second memory cell coupled to the target row of the memory device based on performing error control operations on the data.

[0105] In some instances, the operation manager 715 may determine whether a management operation is complete based on the first column address of the first memory cell. In some instances, the operation manager 715 may generate an output signal to perform an error control operation on a third memory cell coupled to the source row based on the determination that the management operation is complete. In some instances, as part of a management operation that transfers information from a first segment to a second segment of the memory device, the operation manager 715 may read data from the first memory cell into a first sensing component. In some instances, the operation manager 715 may generate a write status signal and a global command address signal, including an indication for a command address counter.

[0106] In some instances, the operation manager 715 may activate a first sensing component in the first segment, wherein reading data is based on activating the first sensing component. In some instances, the operation manager 715 may activate a second sensing component in the second segment based on performing an error control operation, wherein transferring data from the error control component to the second sensing component is based on activating the second sensing component. In some instances, the operation manager 715 may transfer data from a first memory cell to the first sensing component via a first digital line associated with a first segment of the memory device.

[0107] Command address manager 720 can determine whether a first column address meets a threshold associated with a source row. In some instances, command address manager 720 can combine one or more bits of the first column address into a value. In some instances, command address manager 720 can compare the value with a threshold associated with the source row, wherein determining whether the first column address meets the threshold is based on comparing the value with the threshold. In some instances, command address manager 720 can increment a column address counter associated with the source row based on generating the output signal. In some instances, command address manager 720 can identify a second column address of the third memory cell based on incrementing the column address counter. In some instances, command address manager 720 can determine that the management operation is complete based on a third column address associated with the third memory cell. In some instances, command address manager 720 can determine that the third column address meets a threshold associated with the source row.

[0108] The pre-charge component 725 can pre-charge the target row based on the completion of a defined management operation.

[0109] Figure 8 A flowchart illustrating one or more methods 800 supporting error control for a memory device according to examples disclosed herein is shown. The operation of method 800 can be implemented by a memory device or its components as described herein. For example, it can be implemented by, as referenced... Figure 7 The described memory device performs the operation of method 800. In some instances, the memory device may execute an instruction set to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0110] At 805, the memory device can initiate a management operation to transfer information from a source line of the memory device to a target line. The operation at 805 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 7 The described operation manager performs the 805 operation.

[0111] At 810, the memory device can, based on initiating the management operation, perform an error control operation on data stored in a first memory cell coupled to the source row of the memory device, the first memory cell being located at the first column address and the first row address of the source row. The operation at 810 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 7 The described error control component performs the operation of 810.

[0112] At point 815, the memory device may write the data to a second memory cell coupled to the target row of the memory device based on performing the error control operation on the data. The operation at point 815 may be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 7 The described operation manager performs the operations of 815.

[0113] At 820, the memory device can determine whether the management operation is complete based on the first column address of the first memory cell. The operation at 820 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 7 The described operation manager performs the operations of 820.

[0114] At 825, the memory device may generate an output signal to perform the error control operation on a third memory cell coupled to the source row based on determining whether the management operation has been completed. The operation at 825 may be performed according to the method described herein. In some instances, it may be performed by, as referenced... Figure 7 The described operation manager performs the operations of 825.

[0115] In some instances, the device described herein may perform one or more methods, such as method 800. The device may include features, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: initiating a management operation to transfer information from a source row of a memory device to a target row; performing an error control operation on data stored in a first memory cell coupled to the source row of the memory device, the first memory cell located at a first column address and a first row address of the source row, based on initiating the management operation; writing the data to a second memory cell coupled to the target row of the memory device based on performing the error control operation on the data; determining whether the management operation is complete based on the first column address of the first memory cell; and generating an output signal to perform the error control operation on a third memory cell coupled to the source row based on determining whether the management operation is complete.

[0116] In some instances of the method 800 and device described herein, determining whether the management operation is completed may include operations, features, means, or instructions for determining whether the first column address satisfies a threshold associated with the source row.

[0117] Some examples of the methods 800 and devices described herein may additionally include operations, features, means, or instructions for: combining one or more bits of the first column address into a value; and comparing the value with a threshold associated with the source row, wherein determining whether the first column address satisfies the threshold may be based on comparing the value with the threshold.

[0118] In some instances of the method 800 and apparatus described herein, performing the error control operation on the data stored in the first memory cell may include operations, features, means, or instructions for: reading the data in the first memory cell; determining an error in the data in the first memory cell; and correcting the error based on the determination of the error.

[0119] Some examples of the method 800 and apparatus described herein may additionally include operations, features, means, or instructions for: incrementing a column address counter associated with the source row based on generating the output signal; and identifying a second column address of the third memory cell based on incrementing the column address counter.

[0120] Some examples of the method 800 and device described herein may additionally include operations, features, means, or instructions for determining that the management operation can be performed based on a third column address associated with the third memory cell.

[0121] In some instances of the method 800 and device described herein, determining that the management operation has been completed may include operations, features, means, or instructions for determining that the third column address satisfies a threshold associated with the source row.

[0122] Some examples of the methods 800 and devices described herein may additionally include operations, features, means, or instructions for precharging the target row based on determining that the management operation can be performed.

[0123] In some instances of the method 800 and device described herein, initiating the management operation to transfer the information from the source line to the target line may include operations, features, means, or instructions for generating write status signals and global command address signals, including indications for command address counters.

[0124] Figure 9A flowchart illustrating one or more methods 900 for supporting error control of a memory device according to examples disclosed herein is shown. The operation of method 900 can be implemented by a memory device or its components as described herein. For example, it can be implemented by, as referenced... Figure 7 The described memory device performs the operation of method 900. In some instances, the memory device may execute an instruction set to control the functional elements of the memory device to perform the described function. Alternatively, the memory device may use dedicated hardware to perform aspects of the described function.

[0125] At 905, as part of a management operation to transfer information from a first segment to a second segment of the memory device, the memory device may read data from the first memory cell into the first sensing component. The operation at 905 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 7 The described operation manager performs the 905 operation.

[0126] At point 910, the memory device can transfer the data from the first sensing component to the error control component. Operation 910 can be performed according to the method described herein. In some instances, it can be achieved by, as referenced... Figure 7 The described aspect of the sensor component manager performing the operation of 910.

[0127] At 915, the memory device can perform error control operations on the data by transferring the data to the error control component. The operation at 915 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 7 The described error control component performs the 915 operation.

[0128] At 920, the memory device can transfer the data from the error control component to a second sensing component associated with the second segment of the memory device. The operation at 920 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 7 The described error control component performs the 920 operation.

[0129] At 925, the memory device can transfer the data from the second sensing component to a second memory cell associated with the second segment of the memory device. The operation at 925 can be performed according to the method described herein. In some instances, it can be performed by, as referenced... Figure 7 The described aspect of the sensor component manager performing the 925 operation.

[0130] In some instances, the device as described herein may perform one or more methods, such as method 900. The device may include features, means, or instructions (e.g., processor-executable instructions stored in a non-transitory computer-readable medium) for: reading data from a first memory cell into a first sensing component as part of a management operation to transfer information from a first segment of a memory device to a second segment; transferring the data from the first sensing component to an error control component; performing an error control operation on the data via the error control component based on the transfer of the data to the error control component; transferring the data from the error control component to a second sensing component associated with the second segment of the memory device; and transferring the data from the second sensing component to a second memory cell associated with the second segment of the memory device.

[0131] Some examples of the method 900 and apparatus described herein may additionally include operations, features, means, or instructions for transmitting data to the second memory unit, and switching between the first sensing component in the first segment and the second sensing component in the second segment via the error control component to transmit multiple data between the first sensing component and the second sensing component.

[0132] Some examples of the method 900 and apparatus described herein may additionally include operations, features, means, or instructions for maintaining the activation of the first sensing component after the data is transmitted from the first sensing component to the error control component, wherein a bi-state switching between the first sensing component in the first segment and the second sensing component in the second segment may be based on maintaining the activation of the first sensing component.

[0133] Some examples of the method 900 and apparatus described herein may additionally include operations, features, means, or instructions for: activating the first sensing component of the first segment, wherein reading the data may be based on activating the first sensing component; and activating the second sensing component of the second segment based on performing the error control operation, wherein transmitting the data from the error control component to the second sensing component may be based on activating the second sensing component.

[0134] In some instances of the method 900 and device described herein, the first segment includes the first memory unit, and the second segment includes the second memory unit. In some instances of the method 900 and device described herein, the first segment includes the first sensing component, and the second segment includes the second sensing component.

[0135] Some examples of the method 900 and apparatus described herein may additionally include operations, features, means, or instructions for: transferring the data from the first sensing component to the error control component associated with the first segment of the memory device; and transferring the data from the error control component to the second sensing component associated with the second segment of the memory device.

[0136] Some examples of the method 900 and apparatus described herein may additionally include operations, features, means, or instructions for: transmitting data from the first memory cell to the first sensing component via a first digital line associated with the first segment of the memory device; and transmitting data from the second sensing component to the second memory cell via a second digital line associated with the second segment of the memory device.

[0137] Some examples of the method 900 and apparatus described herein may additionally include operations, features, means, or instructions for: storing a first segment address associated with the first sensing component in a first latch, wherein transferring the data from the first sensing component to the error control component may be based on storing the first segment address in the first latch; and storing a second segment address associated with the second sensing component in a second latch, wherein transferring the data from the error control component to the second sensing component may be based on storing the second segment address in the second latch.

[0138] It should be noted that the methods described herein are possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods can be combined.

[0139] Describe a device. The device may include a memory array comprising a first segment and a second segment; and a control component associated with the memory array and configured to cause the device to: perform an error control operation on data stored in a first memory cell coupled to a source row of the memory array, the first memory cell being located at a first column address and a first row address of the source row, based on initiating a management operation; write the data to a second memory cell coupled to a target row of the memory array based on performing the error control operation on the data; determine whether the management operation is complete based on the first column address of the first memory cell; and generate an output signal to perform the error control operation on a third memory cell coupled to the source row based on determining whether the management operation is complete.

[0140] Some instances may additionally include determining whether the first column address meets a threshold associated with the source row, wherein determining whether the management operation can be completed may be based on determining whether the first column address meets the threshold associated with the source row.

[0141] Some instances may additionally include combining one or more bits of the first column address into a value; and comparing the value with the threshold associated with the source row, wherein determining whether the first column address satisfies the threshold may be based on comparing the value with the threshold.

[0142] Some instances may additionally include reading the data in the first memory cell; determining an error in the data in the first memory cell; and correcting the error based on the determination of the error, wherein performing the error control operation on the data stored in the first memory cell may be based on reading the data in the first memory cell, determining the error in the data in the first memory cell, and correcting the error.

[0143] Describe a device. The device may include a memory array comprising a first segment and a second segment; and a control component associated with the memory array and configured to cause the device to: transmit data from a first sensing component to an error control component; perform an error control operation on the data via the error control component based on the transmission of the data to the error control component; transmit the data from the error control component to a second sensing component associated with the second segment of the memory device; and transmit the data from the second sensing component to a second memory cell associated with the second segment of the memory device.

[0144] Some instances may additionally include transmitting the data to the second memory unit by means of a bi-state switching between the first sensing component in the first segment and the second sensing component in the second segment via the error control component to transmit the data between the first sensing component and the second sensing component.

[0145] Some instances may further include maintaining the activation of the first sensing component after the data is transmitted from the first sensing component to the error control component, wherein bi-state switching between the first sensing component in the first segment and the second sensing component in the second segment may be based on maintaining the activation of the first sensing component.

[0146] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate signaling as a single signal; however, those skilled in the art will understand that a signal can represent a bus of signals, where the bus can have various bit widths.

[0147] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of electrons between them. Components are considered to be in electronic communication with each other (or in conductive contact, connected, or coupled) if any conductive path exists between them that can support the flow of signals at any given time. At any given time, the conductive path between components that are electronically connected (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0148] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship. In an open-circuit relationship, signals cannot currently travel between components via a conductive path; in a closed-circuit relationship, signals can travel between components via a conductive path. When a component, such as a controller, couples other components together, it initiates a change that allows signals to flow between other components via conductive paths that were previously not permitted.

[0149] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components from each other, it prevents signals from flowing between the components using previously permitted conductive paths.

[0150] As used in this article, the term “generally” means that the modified feature (e.g., a verb or adjective modified by the term “generally”) does not have to be absolute but must be close enough to obtain the advantage of the feature.

[0151] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can serve as an electrical contact to a memory cell or other component of a memory array. An electrode may comprise traces, wires, conductive lines, conductive layers, etc., providing conductive paths between elements or components of the memory array.

[0152] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In others, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0153] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or a channel. If the channel is n-type (i.e., the majority of charge carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0154] The description herein, illustrated with reference to the accompanying drawings, describes exemplary configurations and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0155] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0156] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof.

[0157] The various illustrative blocks and components described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0158] The functionality described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented as software executed by a processor, the functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality may also be physically located in various locations, including distributed implementations such that portions of the functionality are implemented in different physical locations. And, as used herein, the word “or” used in the list of items included in the claims (e.g., a list of items beginning with phrases such as “at least one of…” or “one or more of…”) indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase “based on” should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as “based on condition A” may be based on both condition A and condition B. In other words, as used herein, the phrase “based on” should also be interpreted as the phrase “at least partially based on”.

[0159] Computer-readable media includes both non-transitory computer storage media and communication media that include any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then said coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital video discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0160] The description provided herein enables those skilled in the art to make or use this disclosure. Those skilled in the art will appreciate the various modifications that can be made to this disclosure, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for error control for a memory device, comprising: initiating a management operation to transfer information from a source rank of the memory device to a target rank; performing an error control operation on data stored in a first memory cell coupled with the source rank of the memory device based at least in part on initiating the management operation, the first memory cell being at a first column address and a first row address of the source rank; writing the data to a second memory cell coupled with the target rank of the memory device based at least in part on performing the error control operation on the data; determining whether the management operation is complete based at least in part on the first column address of the first memory cell; generating an output signal to perform the error control operation on a third memory cell coupled with the source rank based at least in part on determining whether the management operation is complete; incrementing a column address counter associated with the source rank based at least in part on generating the output signal; and identifying a second column address of the third memory cell based at least in part on incrementing the column address counter.

2. The method of claim 1, wherein determining whether the management operation is complete comprises: determining whether the first column address satisfies a threshold value associated with the source rank.

3. The method of claim 2, further comprising: combining one or more bits of the first column address into a value; and comparing the value to the threshold value associated with the source rank, wherein determining whether the first column address satisfies the threshold value is based at least in part on comparing the value to the threshold value.

4. The method of claim 1, wherein performing the error control operation on the data stored in the first memory cell comprises: reading the data of the first memory cell; determining an error in the data of the first memory cell; and correcting the error based at least in part on determining the error.

5. The method of claim 1, further comprising: determining that the management operation is complete based at least in part on a third column address associated with the third memory cell.

6. The method of claim 5, wherein determining that the management operation is complete comprises: determining that the third column address satisfies a threshold value associated with the source rank.

7. The method of claim 1, wherein initiating the management operation to transfer the information from the source rank to the target rank comprises: generating a write state signal and a global command address signal including an indication for a command address counter.

8. A method for error control for a memory device, comprising: initiating a management operation to transfer information from a source rank of the memory device to a target rank; performing an error control operation on data stored in a first memory cell coupled with the source rank of the memory device based at least in part on initiating the management operation, the first memory cell being at a first column address and a first row address of the source rank; ​ ​ writing the data to a second memory cell coupled to the target row of the memory device based at least in part on performing the error control operation on the data; combining one or more bits of the first column address into a value; comparing the value to a threshold associated with the source row; determining whether the management operation is complete based at least in part on the first column address of the first memory cell, wherein the determining comprises determining whether the first column address satisfies the threshold associated with the source row based at least in part on comparing the value to the threshold; generating an output signal to perform the error control operation on a third memory cell coupled to the source row based at least in part on determining whether the management operation is complete.

9. The method of claim 8, wherein performing the error control operation on the data stored in the first memory cell comprises: reading the data of the first memory cell; determining an error in the data of the first memory cell; and correcting the error based at least in part on determining the error.

10. The method of claim 8, further comprising: incrementing a column address counter associated with the source row based at least in part on generating the output signal; and identifying a second column address of the third memory cell based at least in part on incrementing the column address counter.

11. The method of claim 8, further comprising: determining that the management operation is complete based at least in part on a third column address associated with the third memory cell.

12. The method of claim 11, wherein determining that the management operation is complete comprises: determining that the third column address satisfies a threshold associated with the source row.

13. The method of claim 11, further comprising: precharging the target row based at least in part on determining that the management operation is complete.

14. The method of claim 8, wherein initiating the management operation to transfer the information from the source row to the target row comprises: generating a write state signal and a global command address signal including an indication for a command address counter.

15. A method for error control of a memory device, comprising: initiating a management operation to transfer information from a source row to a target row of the memory device; performing an error control operation on data stored in a first memory cell coupled to the source row of the memory device at a first column address and a first row address of the source row based at least in part on initiating the management operation; writing the data to a second memory cell coupled to the target row of the memory device based at least in part on performing the error control operation on the data; determining whether the management operation is complete based at least in part on the first column address of the first memory cell; determining that the management operation is complete based at least in part on a third column address associated with a third memory cell; precharging the target row based at least in part on determining that the management operation is complete; and ​ ​ based at least in part on determining whether the management operation is complete, generating an output signal to perform the error control operation on a third memory cell coupled with the source row.

16. A method for error control of a memory device, comprising: initiating a management operation to transfer information from a source row of the memory device to a target row, wherein the initiating comprises generating a write state signal and a global command address signal, including an indication for a command address counter; based at least in part on initiating the management operation, performing an error control operation on data stored in a first memory cell coupled with the source row of the memory device, the first memory cell being at a first column address and a first row address of the source row; based at least in part on performing the error control operation on the data, writing the data to a second memory cell coupled with the target row of the memory device; based at least in part on the first column address of the first memory cell, determining whether the management operation is complete; and based at least in part on determining whether the management operation is complete, generating an output signal to perform the error control operation on a third memory cell coupled with the source row.

17. The method of claim 16, further comprising: combining one or more bits of the first column address into a value; and comparing the value to a threshold associated with the source row, wherein determining whether the first column address satisfies the threshold is based at least in part on comparing the value to the threshold.

18. The method of claim 16, wherein performing the error control operation on the data stored in the first memory cell comprises: reading the data of the first memory cell; determining an error in the data of the first memory cell; and correcting the error based at least in part on determining the error.

19. The method of claim 16, further comprising: based at least in part on generating the output signal, incrementing a column address counter associated with the source row; and based at least in part on incrementing the column address counter, identifying a second column address of the third memory cell.

20. The method of claim 16, further comprising: based at least in part on a third column address associated with the third memory cell, determining that the management operation is complete.

21. The method of claim 20, wherein determining that the management operation is complete comprises: determining that the third column address satisfies a threshold associated with the source row.

22. The method of claim 20, further comprising: based at least in part on determining that the management operation is complete, precharging the target row.

23. A memory device, comprising: a memory array comprising a first section and a second section; and a control component associated with the memory array and configured to cause the memory device to: initiate a management operation to transfer information from a source row of the memory array to a target row; performing an error control operation on data stored in a first memory cell coupled with the source row of the memory array, the first memory cell being at a first column address and a first row address of the source row, based at least in part on initiating the management operation; writing the data to a second memory cell coupled with the target row of the memory array based at least in part on performing the error control operation on the data; determining whether the management operation is complete based at least in part on the first column address of the first memory cell; generating an output signal to perform the error control operation on a third memory cell coupled with the source row based at least in part on determining whether the management operation is complete; incrementing a column address counter associated with the source row based at least in part on generating the output signal; and identifying a second column address of the third memory cell based at least in part on incrementing the column address counter.

24. The memory device of claim 23, wherein the control component is further configured to cause the memory device to: determine whether the first column address satisfies a threshold value associated with the source row, wherein determining whether the management operation is complete is based at least in part on determining whether the first column address satisfies the threshold value associated with the source row.

25. The memory device of claim 23, wherein the control component is further configured to cause the memory device to: read the data of the first memory cell; determine an error in the data of the first memory cell; and correct the error based at least in part on determining the error, wherein performing the error control operation on the data stored in the first memory cell is based at least in part on reading the data of the first memory cell, determining the error in the data of the first memory cell, and correcting the error.

26. A memory device, comprising: a memory array comprising a first section and a second section; and a control component associated with the memory array and configured to cause the memory device to: initiate a management operation to transfer information from a source row to a target row of the memory array; perform an error control operation on data stored in a first memory cell coupled with the source row of the memory array, the first memory cell being at a first column address and a first row address of the source row, based at least in part on initiating the management operation; write the data to a second memory cell coupled with the target row of the memory array based at least in part on performing the error control operation on the data; combine one or more bits of the first column address into a value; compare the value to a threshold value associated with the source row; determine whether the management operation is complete based at least in part on the first column address of the first memory cell; generate an output signal to perform the error control operation on a third memory cell coupled with the source row based at least in part on determining whether the management operation is complete; increment a column address counter associated with the source row based at least in part on generating the output signal; and identify a second column address of the third memory cell based at least in part on incrementing the column address counter. determining whether the management operation is complete based at least in part on the first column address of the first memory cell and based at least in part on a determination of whether the first column address satisfies the threshold value associated with the source row, wherein determining whether the first column address satisfies the threshold value is based at least in part on comparing the value to the threshold value; generating an output signal to perform the error control operation on a third memory cell coupled with the source row based at least in part on determining whether the management operation is complete.

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