A circuit for compensating current accuracy and temperature characteristics of a bias current

Abstract

The application discloses a circuit for compensating current precision and temperature characteristics of bias current, comprising: a current generating circuit for generating bias current; the current generating circuit comprises a first branch and a second branch, wherein the first branch comprises a first PMOS tube and a third PMOS tube connected in series, and the second branch comprises a second PMOS tube, a first resistor R1, a second resistor R2 and a fourth PMOS tube connected in series; a temperature compensation circuit for generating a positive temperature coefficient current, comprising a third branch and a fourth branch, wherein the third branch comprises a third resistor R3 and a PTAT current source connected in series, and the fourth branch comprises an ADC controller, one end of the fourth branch is connected between the third resistor R3 and the PTAT current source, and the other end is connected between the first resistor R1 and the second resistor R2, and one part of the resistor structure of the first resistor R1 and the second resistor R2 is a variable resistor, and the resistance value can be adjusted by the PTAT current source current passing through the ADC controller.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a circuit for compensating bias current with current accuracy and temperature characteristics. Background Technology

[0002] With the advancement of CMOS (Complementary Metal Oxide Semiconductor) technology, the development trend of integrated circuits is towards higher integration density, lower power supply voltage, and lower power consumption; low-voltage and low-power design is the mainstream direction of integrated circuit development.

[0003] The bias circuit provides the quiescent operating point and bias current for other components in the circuit, enabling them to perform specific functions. To a certain extent, the magnitude of the bias current determines the magnitude of the overall circuit's quiescent current and even the total current. Effectively reducing the variation of the bias current with the power supply voltage is an effective way to improve the power supply stability of the overall circuit's quiescent current and even the total current. Traditional bias circuits that are independent of the power supply still have a certain degree of power supply dependence. Due to increasingly stringent requirements for current accuracy and temperature characteristics, temperature compensation is generally performed on this module to obtain better current accuracy and temperature characteristics.

[0004] A PTAT (proportional to absolute temperature) current source is a current source whose output current is directly proportional to its absolute temperature (thermodynamic temperature). Due to its unique temperature characteristics, PTAT current sources are frequently used as sub-circuits in integrated circuit design. For example, in integrated circuits, certain performance characteristics of operational amplifiers, comparators, and other modules (such as open-loop gain and slew rate) decrease with increasing temperature. Therefore, at higher temperatures, a larger bias current is needed to compensate for the decrease in circuit performance with increasing temperature, and PTAT current sources precisely meet this requirement.

[0005] In existing technologies, such as Figure 1 The diagram shows a traditional bias circuit independent of the power supply. To uniquely determine the current value, a constraint RS is added to the circuit. Since PMOS transistors M3 and M4 have the same dimensions, although the currents in the two branches are required to be equal, the presence of resistor RS reduces the current in M2. If M1~M4 all operate in the saturation region and λ=0, and M2 is K times the width-to-length ratio of M1, we can write:

[0006] or

[0007] Ignoring volume effects, we can obtain

[0008] This allows us to obtain a current that is independent of the power supply voltage, but is still related to the process and temperature.

[0009] If the channel length modulation effect is negligible, then the circuit in the figure exhibits good power dependence. For this reason, all transistors in this circuit use relatively long channels.

[0010] exist Figure 1 In the circuit, since the source terminals of M1 and M2 are located at different potentials, some errors are assumed to occur in the previous calculations. We can consider using an improved new circuit structure to eliminate such substrate bias effects.

[0011] The bias current generated by the above circuit structure is relatively independent of the power supply voltage, but temperature has a significant impact on its characteristics. Since the requirements for the current accuracy and temperature characteristics of the bias current are currently very high, temperature compensation is required for this module to obtain a better zero temperature coefficient current.

[0012] Based on this, the present invention designs a circuit structure that can compensate for the current accuracy and temperature characteristics of the bias current. Summary of the Invention

[0013] The present invention aims to at least solve one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a circuit for compensating for the current accuracy and temperature characteristics of bias current. Using this circuit, a bias power generation circuit with a good temperature coefficient can be provided. By eliminating the influence of substrate bias effect, a current generation circuit with a good temperature coefficient can be designed through compensation using a PTAT current source.

[0014] The purpose of this invention is to provide a circuit for compensating bias current with improved current accuracy and temperature characteristics, comprising:

[0015] A current generating circuit is used to generate a bias current, which is independent of the power supply voltage;

[0016] The current generating circuit includes a first branch and a second branch, wherein the first branch includes a first PMOS transistor and a third PMOS transistor connected in series, and the second branch includes a second PMOS transistor, a first resistor R1, a second resistor R2, and a fourth PMOS transistor connected in series.

[0017] A temperature compensation circuit for generating a positive temperature coefficient current includes a third branch and a fourth branch. The third branch includes a third resistor R3 connected in series with a PTAT current source. The fourth branch includes an ADC controller. One end of the fourth branch is connected between the third resistor R3 and the PTAT current source, and the other end is connected between the first resistor R1 and the second resistor R2. A portion of the resistance structure of the first resistor R1 and the second resistor R2 is a variable resistor, and its resistance value can be adjusted by the PTAT current through the ADC controller.

[0018] In some embodiments, the source terminals of the first PMOS transistor and the second PMOS transistor are the same.

[0019] In some embodiments, the gate terminal of the first PMOS transistor is connected to the drain terminal of the second PMOS transistor, and the gate terminal of the third PMOS transistor is connected to the gate terminal of the fourth PMOS transistor on the second branch.

[0020] In some embodiments, the gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor in the first branch. The drain of the fourth PMOS transistor is connected to the first resistor R1 and to the gate of the second PMOS transistor. The drain of the second PMOS transistor is connected to the gate via the second resistor R2 and the first resistor R1, and is also connected to the gate of the first PMOS transistor. The source of the second PMOS transistor is connected to the VSS ground terminal.

[0021] In some embodiments, the third PMOS transistor and the fourth PMOS transistor have the same width-to-length ratio.

[0022] In some embodiments, the resistance value of the first resistor R1 is fixed, and the resistance value of the second resistor R2 can be adjusted by the PTAT current source current through the ADC controller.

[0023] In some embodiments, a fifth PMOS transistor is further included, wherein the source terminal of the fifth PMOS transistor is collinear with the source terminals of the third and fourth PMOS transistors, and the drain terminal of the fifth PMOS transistor is connected to the VSS ground terminal.

[0024] In some embodiments, the gate and drain of the third PMOS transistor are connected, and the drain of the third PMOS transistor is connected to the drain of the first PMOS transistor, while the source of the first PMOS transistor is connected to the VSS ground.

[0025] In some embodiments, one end of the third resistor R3 is connected to the VSS ground terminal, and the other end is connected to the ADC control gas.

[0026] This invention improves upon traditional bias current generation circuits that are independent of power supply by eliminating the influence of substrate bias effects and using PTAT current source current for compensation, thereby designing a novel bias current generation circuit with good temperature characteristics. This circuit structure is suitable for modern integrated circuit design due to its good current accuracy and temperature characteristics.

[0027] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0028] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0029] Figure 1 It is a traditional bias circuit diagram that is independent of the power supply in the existing technology;

[0030] Figure 2 This is a power supply-independent bias circuit diagram for eliminating substrate bias effects in the prior art;

[0031] Figure 3 This is a circuit diagram illustrating the current accuracy and temperature characteristics of the compensated bias current according to an embodiment of the present invention.

[0032] Figure label:

[0033] First PMOS transistor 11;

[0034] Second PMOS transistor 12;

[0035] Third PMOS transistor 13;

[0036] Fourth PMOS transistor 14;

[0037] Fifth PMOS transistor 15

[0038] The first resistor R1 is 21;

[0039] The second resistor R2 is 22;

[0040] The third resistor is R3 23;

[0041] PTAT current source 30;

[0042] ADC controller 4040. Detailed Implementation

[0043] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0044] like Figure 2 The diagram shows a power supply-independent bias circuit diagram for eliminating substrate bias effects in the prior art. This circuit structure can eliminate the influence of substrate bias effects. Here, the source potentials of M1 and M2 are the same, and the gate of M1 is connected to the drain of M2. We assume that all MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) operate in the saturation region, and that the PMOS transistors (positive-channel Metal Oxide Semiconductors) M3 and M4 have the same width-to-length ratio and λ=0. The following results can still be obtained:

[0045]

[0046] That is

[0047] This produces a current that is independent of the power supply voltage, but is still related to the process and temperature.

[0048] Traditional bias circuit structures that are independent of power supply generate currents that are less dependent on the power supply voltage, but temperature has a significant impact on their characteristics. Since the requirements for the current accuracy and temperature characteristics of the bias current are currently very high, temperature compensation is required for this module to obtain a better zero-temperature coefficient current.

[0049] like Figure 3 The diagram shown is a circuit diagram of the current accuracy and temperature characteristics of the compensated bias current according to an embodiment of the present invention. The circuit includes: a current generating circuit for generating a bias current, wherein the bias current is independent of the power supply voltage.

[0050] The current generating circuit includes a first branch and a second branch. The first branch includes a first PMOS transistor 11 and a third PMOS transistor 13 connected in series. The second branch includes a second PMOS transistor 12, a first resistor R1 21, a second resistor R2 22 and a fourth PMOS transistor 14 connected in series.

[0051] A temperature compensation circuit for generating a positive temperature coefficient current includes a third branch and a fourth branch. The third branch includes a third resistor R3 connected in series with a PTAT current source 30. The fourth branch includes an ADC controller 40. One end of the fourth branch is connected between the third resistor R3 and the PTAT current source 30, and the other end is connected between the first resistor R1 21 and the second resistor R2 22. A portion of the resistance structure of the first resistor R1 21 and the second resistor R2 22 is a variable resistor, and its resistance value can be adjusted by the PTAT current 30 through the ADC controller 40. The second resistor R2 22 is a variable resistor.

[0052] Specifically, the source terminals of the first PMOS transistor 11 and the second PMOS transistor 12 are the same.

[0053] In some embodiments, the gate terminal of the first PMOS transistor 11 is connected to the drain terminal of the second PMOS transistor 12, and the gate terminal of the third PMOS transistor 13 is connected to the gate terminal of the fourth PMOS transistor 14 on the second branch.

[0054] In some embodiments, the gate of the fourth PMOS transistor 14 is connected to the source of the third PMOS transistor 13 of the first branch. The drain of the third PMOS transistor 13 is connected to the first resistor R1 21 and to the drain of the second PMOS transistor 12. The gate of the second PMOS transistor 12 is connected to the drain via the second resistor R2 22 and the first resistor R1 21, and is connected to the gate of the first PMOS transistor 11. The source of the third PMOS transistor 13 is connected to the VSS (Visual Source Safe) ground.

[0055] The gate of the fourth PMOS transistor 14 is connected to the drain of the third PMOS transistor 13 in the first branch. The drain of the fourth PMOS transistor 14 is connected to the first resistor R1 21 and to the gate of the second PMOS transistor 12. The drain of the second PMOS transistor 12 is connected to the gate via the second resistor R2 22 and the first resistor R1 21, and is also connected to the gate of the first PMOS transistor 11. The source of the second PMOS transistor 13 is connected to the VSS (Visual Source Safe) ground.

[0056] In some embodiments, the width-to-length ratio of the third PMOS transistor 13 and the fourth PMOS transistor 14 is the same.

[0057] In some embodiments, the resistance value of the first resistor R1 21 is fixed, and the resistance value of the second resistor R2 22 can be adjusted by the current from the PTAT current source 30 through the ADC controller 40.

[0058] In some embodiments, a fifth PMOS transistor 15 is further included, wherein the source terminal of the fifth PMOS transistor 15 is collinear with the source terminals of the third PMOS transistor 13 and the fourth PMOS transistor 14, and the drain terminal of the fifth PMOS transistor 15 is connected to the VSS ground terminal.

[0059] In some embodiments, the gate and drain of the third PMOS transistor 13 are connected, and the drain of the third PMOS transistor 13 is connected to the drain of the first PMOS transistor 11, and the source of the first PMOS transistor 11 is connected to the VSS ground.

[0060] In some embodiments, one end of the third resistor R3 23 is connected to the VSS ground terminal, and the other end is connected to the ADC controller 40.

[0061] like Figure 3 The circuit structure shown is in Figure 2 The circuit structure shown eliminates the substrate bias effect, and an external PTAT current source of 30 ohms is added to compensate for the temperature coefficient. Figure 3 In this circuit, the resistance of the first resistor R1 21 is fixed, while the resistance of the second resistor R2 22 can be adjusted via the PTAT current source 30 and the ADC controller 40. Since the PTAT current source 30 has a positive temperature coefficient, a good zero temperature coefficient can be obtained after compensation. Furthermore, by adjusting the resistance of the second resistor R2 22 according to the output current temperature coefficient requirements, a negative temperature coefficient current with a temperature coefficient greater than VBE can also be output. Because this structure can output current with a zero temperature coefficient and a negative temperature coefficient greater than VBE, this current generation circuit is generally applicable to various modern integrated circuit module designs.

[0062] This invention improves upon traditional bias current generation circuits that are independent of power supply by eliminating the influence of substrate bias effects and using PTAT current source 30 for compensation, thereby designing a novel bias current generation circuit with good temperature characteristics. This circuit structure is suitable for modern integrated circuit design due to its good current accuracy and temperature characteristics.

[0063] In the description of this specification, any process or method described in the flowcharts or otherwise herein may be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order according to the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain.

[0064] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0065] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any of the following techniques known in the art, or a combination thereof: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0066] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0067] Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0068] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

[0069] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0070] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A circuit for compensating bias current with current accuracy and temperature characteristics, characterized in that, include: A current generating circuit is used to generate a bias current, which is independent of the power supply voltage; The current generating circuit includes a first branch and a second branch, wherein the first branch includes a first PMOS transistor and a third PMOS transistor connected in series, and the second branch includes a second PMOS transistor, a first resistor R1, a second resistor R2, and a fourth PMOS transistor connected in series. A temperature compensation circuit for generating a positive temperature coefficient current includes a third branch and a fourth branch. The third branch includes a third resistor R3 connected in series with a PTAT current source. The fourth branch includes an ADC controller. One end of the fourth branch is connected between the third resistor R3 and the PTAT current source, and the other end is connected between the first resistor R1 and the second resistor R2. A portion of the resistance structure of the first resistor R1 and the second resistor R2 is a variable resistor, and its resistance value can be adjusted by the PTAT current through the ADC controller. The source terminals of the first PMOS transistor and the second PMOS transistor are the same; The gate of the first PMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor on the second branch. The gate of the fourth PMOS transistor is connected to the drain of the third PMOS transistor in the first branch. The drain of the fourth PMOS transistor is connected to the first resistor R1 and to the gate of the second PMOS transistor. The drain of the second PMOS transistor is connected to the gate via the second resistor R2 and the first resistor R1, and is also connected to the gate of the first PMOS transistor. The source of the second PMOS transistor is connected to the VSS ground terminal.

2. The circuit for compensating bias current accuracy and temperature characteristics according to claim 1, characterized in that, The third PMOS transistor and the fourth PMOS transistor have the same width-to-length ratio.

3. The circuit for compensating bias current accuracy and temperature characteristics according to claim 1, characterized in that, The resistance value of the first resistor R1 is fixed, while the resistance value of the second resistor R2 can be adjusted by the PTAT current source current through the ADC controller.

4. The circuit for compensating bias current accuracy and temperature characteristics according to claim 3, characterized in that, It also includes a fifth PMOS transistor, the source of which is collinear with the sources of the third and fourth PMOS transistors, and the drain of which is connected to the VSS ground terminal.

5. The circuit for compensating bias current accuracy and temperature characteristics according to claim 1, characterized in that, The gate and drain of the third PMOS transistor are connected, and the drain of the third PMOS transistor is connected to the drain of the first PMOS transistor. The source of the first PMOS transistor is connected to the VSS ground terminal.

6. The circuit for compensating bias current accuracy and temperature characteristics according to claim 1, characterized in that, One end of the third resistor R3 is connected to the VSS ground terminal, and the other end is connected to the ADC controller.

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