A data processing apparatus and a method of processing memory access requests
By parsing the address and data information in the memory access request, access control of the visible and invisible fields of the OTP memory is achieved, solving the problem of high cost of hardware range protection and realizing flexible chip design and low-cost security mode switching.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING ESWIN COMPUTING TECH CO LTD
- Filing Date
- 2023-01-20
- Publication Date
- 2026-06-16
AI Technical Summary
In existing technologies, the invisible field protection method of OTP memory in RISC-V architecture chip design relies on hardware range protection, which results in high design costs and difficulty in flexible adjustment.
By employing software operation steps, the access address and data description information in the memory access request are parsed and compared with the association information of the OTP memory, thereby enabling access control of the visible and invisible fields of the OTP memory without the need to set security registers.
It reduces the difficulty and cost of chip design, effectively protects the invisible fields of OTP memory, and supports flexible switching between secure and non-secure modes.
Smart Images
Figure CN115934592B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip design, and more particularly to a data processing apparatus and a method for processing memory access requests. Background Technology
[0002] Reduced Instruction Set Computer (RISC) is a type of CPU architecture. RISC-V is the fifth generation of RISC architecture, officially released by the University of California, Berkeley in 2014.
[0003] To ensure the security of the main control processor in the RISC-V architecture, a secure CPU (SCPU) is set up to manage the chip's security. This secure CPU can have a built-in one-time programmable (OTP) memory, which stores data such as encryption and decryption keys, user private keys, and chip IDs. The secure CPU manages the address area of the OTP memory.
[0004] During system startup, the security processor can be configured to boot in either secure or insecure mode. In secure mode, the SCPU can access the entire address range of the OTP, and the main control processor can access the visible field range within the OTP. In insecure mode, the main control processor can access the visible field range within the OTP, but no data is placed in the invisible field range within the OTP.
[0005] In safe mode, invisible fields in the OTP address region are protected by hardware-based zone protection. This is achieved by setting security registers to prevent software from directly accessing these invisible fields.
[0006] Using hardware-based interval protection to protect invisible fields has the problem of high design costs. Summary of the Invention
[0007] To address any of the aforementioned technical problems, embodiments of this application provide a data processing apparatus and a method for processing memory access requests.
[0008] To achieve the objectives of this application's embodiments, this application provides a data processing apparatus based on a RISC-V architecture, including a main control processor and a security processor. The security processor includes an OTP memory, which is configured with a visible field area and a non-visible field area.
[0009] The main control processor is configured to establish a communication connection with the security processor and send a memory access request, wherein the memory access request is used to perform object data read or write operations on the target address of the visible field area or the invisible field area pointed to by the memory access address involved in the memory access request.
[0010] The security processor is configured to respond to the memory access request by parsing the memory access address and data description information involved in the request, and to compare the information in the parsing result with the associated information of the OTP memory in sequence; and to respond to the comparison result indicating that the information in the parsing result and the associated information are both matched, to store the object data in the target address of the OTP memory or to read it from the target address and return it to the main control processor, otherwise to trigger a security exception operation.
[0011] At least one embodiment of this application provides a method for processing memory access requests, which is applied to the data processing apparatus described above, and the processing method includes:
[0012] The main control processor establishes a communication connection with the security processor and sends a memory access request, wherein the memory access request is used to perform object data read or write operations on the target address of the visible field area or the non-visible field area pointed to by the memory access address involved in the memory access request.
[0013] The security processor responds to the memory access request by parsing the memory access address and data description information involved in the request, and compares the information in the parsing result with the associated information of the OTP memory in sequence; and in response to the comparison result indicating that the information in the parsing result and the associated information match, it stores the object data in the target address of the OTP memory or reads it from the target address and returns it to the main control processor, otherwise it triggers a security exception operation.
[0014] One of the above technical solutions has the following advantages or beneficial effects:
[0015] By parsing the memory access address and data description information in the memory access request, and comparing the information in the parsing result with the associated information of the OTP memory in sequence, the memory access request can be processed according to the comparison result. There is no need to set a security register. Instead, the processing of the memory access request is completed based on the software operation steps. The design is simple, easy to implement, and has low design cost.
[0016] Other features and advantages of the embodiments of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the embodiments of this application. The objects and other advantages of the embodiments of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description
[0017] The accompanying drawings are used to provide a further understanding of the technical solutions of the embodiments of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions of the embodiments of this application.
[0018] Figure 1 This is a schematic diagram of the structure of the data processing apparatus 100 provided in the embodiments of this application;
[0019] Figure 2 for Figure 1 The diagram shows the structure of the OTP memory 30.
[0020] Figure 3 for Figure 1 A schematic diagram of the OTP storage area 31 of the OTP memory 30 shown;
[0021] Figure 4 This is an application diagram of the data processing apparatus 100 provided in the embodiments of this application;
[0022] Figure 5 A flowchart illustrating a memory access request processing method provided in an embodiment of this application;
[0023] Figure 6 A first schematic diagram of a security processor 20 responding to a memory access request, provided for at least one embodiment of this application;
[0024] Figure 7 A second schematic diagram of a security processor 20 responding to a memory access request, provided for at least one embodiment of this application;
[0025] Figure 8 A third schematic diagram showing a security processor 20 responding to a memory access request, provided for at least one embodiment of this application. Detailed Implementation
[0026] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other.
[0027] In the process of developing this application, a technical analysis of the relevant technologies was conducted, and it was found that the relevant technologies have at least the following problems, including:
[0028] During the chip design phase, the address region of the OTP (Out-of-Place) invisible fields needs to be planned in advance to determine the corresponding security registers. If subsequent requirements change, the planned OTP region and security registers need to be adjusted accordingly, increasing the difficulty of chip development and design.
[0029] If, after chip tape-out, it is determined that the chip is a non-secure chip, then the security register function of the OTP is not needed, resulting in design redundancy and increasing design costs and tape-out difficulty.
[0030] In view of the above-mentioned technical problems, the embodiments of this application provide the following solutions:
[0031] Figure 1 This is a schematic diagram of the structure of the data processing apparatus 100 provided in an embodiment of this application. Figure 1 As shown, the device is based on the RISC-V architecture and includes a main control processor 10 and a security processor 20, wherein:
[0032] The security processor 20 includes an OTP memory 30, which is configured with a visible field area and an invisible field area OTP address area.
[0033] Specifically, the address area of the OTP memory 30 is divided into two parts: a visible field area, which can be used to store data such as chip ID, and an invisible field area, which can be used to store data such as encryption / decryption keys and user private keys. In both address areas, some free areas are reserved. According to design requirements, after the chip is fabricated, the reserved free areas can still be used for data storage.
[0034] The main control processor 10 can access the security processor 20 and initiate a memory access request to the security processor 20. The memory access request is used to perform read or write operations on the data stored in the security processor 20.
[0035] The memory access request can be either a read request, used to read data from the security processor 20, or a write request, used to write data into the security processor 20.
[0036] Specifically, the main control processor 10 is configured to establish a communication connection with the security processor 20 and send a memory access request, wherein the memory access request is used to perform object data read or write operations on the target address of the visible field area or the invisible field area pointed to by the memory access address involved in the memory access request.
[0037] Correspondingly, the security processor 20 is configured to respond to the memory access request by parsing the memory access address and data description information involved in the request, and to compare the information in the parsing result with the associated information of the OTP memory 30 in sequence; and in response to the comparison result indicating that the information in the parsing result and the associated information are both matched, to store the object data in the target address of the OTP memory 30 or to read it from the target address and return it to the main control processor 10, otherwise trigger a security exception operation.
[0038] The security processor 20 can be started in either a secure mode or a non-secure mode. In secure mode, the security processor 20 can access the entire address region of the OTP memory 30, but only responds to accesses from the main controller 10 to the visible field regions. In non-secure mode, no data is placed in the invisible field regions of the OTP memory, and accesses from the main controller 10 to the visible field regions are only responded to. Regardless of whether the security processor 20 is in secure or non-secure mode, when it cannot respond to a memory access request, a security exception operation is triggered; for example, it may return empty data.
[0039] The apparatus provided in this application provides a method to process memory access requests by parsing the memory access address and data description information in the memory access request and comparing the information in the parsing result with the associated information of the OTP memory 30 in sequence. This allows the memory access request to be processed based on the comparison result without setting a security register. Instead, the processing of the memory access request is completed based on software operation steps. The design is simple, easy to implement, and has low design cost.
[0040] Figure 2 for Figure 1 The diagram shows the structure of the OTP memory 30. (As shown...) Figure 2 As shown, the OTP memory 30 includes an OTP controller 32 and an OTP storage area 31, wherein:
[0041] The OTP storage area 31 includes at least two address areas, one of which is an invisible field area; the other is a visible field area.
[0042] The OTP controller 32 is used to process memory access requests using data in the OTP memory 30.
[0043] Specifically, a software address range partitioning method can be adopted, so that the data processing device 100 can be used as both a security chip and a non-security chip, thereby achieving uniform chip production.
[0044] The following sections describe the application scenarios after the chip is fabricated:
[0045] (1) If the chip has not yet been programmed with data, it can be used as either a security chip or a non-security chip;
[0046] (2) If too many security chips are produced and some security chips need to be converted to non-security chips, the address range is divided by software. When the main control processor 10 accesses the invisible data field, the security processor 20 returns an error code or invalid data to the main control processor 10. Specifically, it is determined whether the accessed address is within the upper and lower boundaries of the invisible data field. If it is, an error code or invalid data is returned; otherwise, if it is not, access is allowed and data is returned.
[0047] (3) If too many non-secure chips are produced and some of them need to be converted into secure chips, then you only need to write invisible data into the storage area of the invisible data field.
[0048] Figure 3 for Figure 1 A schematic diagram of the OTP storage area 31 of the OTP memory 30 shown. Figure 3 As shown, since the OTP address region expands from low address to high address in the address range, in order to facilitate the development and management of data, a part of the space corresponding to consecutive addresses can be used as the address region for unusable data, and another part of the space corresponding to consecutive addresses can be used as the address region for usable data.
[0049] Alternatively, depending on actual needs, the space corresponding to multiple consecutive addresses can be designated as the address region for unusable data, while the remaining space can be designated as the address region for usable data.
[0050] Furthermore, during the chip design phase, data can be stored in corresponding locations based on its content. For example, the chip ID can be stored in the address area of the visible fields, while the encryption / decryption keys and user private keys can be stored in the address area of the invisible fields. Additionally, some free space is reserved in both of these address areas to allow for data storage after tape-out, depending on design requirements.
[0051] In one exemplary embodiment, at least one of the visible field area and the non-visible field area is configured with a backup storage area.
[0052] The main control processor 10 is also configured to perform data writing operations to the backup storage area configured in the visible field area in non-secure mode to adjust the range of the visible field area;
[0053] The security processor 20 is also configured to perform data write operations to the backup storage area configured in the invisible area in a secure mode to adjust the range of the invisible field area.
[0054] After the chip is fabricated, data needs to be written to the OTP memory 30 in the security processor 20. Specifically:
[0055] Scenario 1: All fields in OTP memory 30 are empty.
[0056] Data can be flexibly written to either visible or invisible empty fields.
[0057] The second scenario: Some fields in the OTP memory 30 are already in use.
[0058] The main control processor 10 performs data writing operations on the idle field according to the operating mode of the security processor 20, including:
[0059] In non-secure mode, the OTP memory 30 has no invisible data and does not need to be managed by the security processor 20. Therefore, the main control processor 10 can directly access the visible data or perform write operations.
[0060] In safe mode, the OTP memory 30 contains both visible and invisible data. If the main controller processor 10 writes data to an invisible field in the OTP memory 30, since the main controller processor 10 cannot access invisible data fields or write via Mailbox, it can use hardware writing to write visible data to a visible field in the OTP memory 30. Alternatively, the control security processor 20 can use the driver of the OTP memory 30 to perform a write operation, thereby achieving the purpose of writing visible data to a visible field in the OTP memory 30. If the main controller processor 10 writes data to a visible field in the OTP memory 30, it can do so via Mailbox or hardware writing.
[0061] In one exemplary embodiment, the data description information includes data size and a flag bit, the flag bit indicating a read or write operation on the object data;
[0062] The data size represents the number of bits of data accessed; the flag bits are used to indicate whether the memory access request is a read or write operation.
[0063] Furthermore, the data description information may also include a mask, which can be used to transmit mask information during write operations. For example, a bit that has been set to 1 cannot be set to 1 again, nor can it be reset to 0, but a bit that is 0 can be written.
[0064] The security processor 20 is configured to, in security mode, determine whether the memory access address is in the visible field region or the invisible field region of the OTP memory 30. In response to the memory access address being in the visible field region, it further compares the data size of the data description information with the data size stored at the target address in the visible field region, and performs corresponding operations based on the flag bit if they are consistent.
[0065] In an exemplary embodiment, the main control processor 10 is configured to output mode control instructions, wherein the mode control instructions are used to control the security processor 20 to start in a secure mode or a non-secure mode;
[0066] The security processor 20 is configured to respond to the mode control command and operate in the mode corresponding to the mode control command.
[0067] Specifically, the main control processor 10 may have built-in software-implemented functional modules, such as Rootrom, to set the boot mode of the security processor.
[0068] Figure 4 This is a schematic diagram illustrating the application of the data processing apparatus 100 provided in an embodiment of this application. For example... Figure 4 As shown, the data processing device 100 is applied in a data processing system, which includes an application layer, software, and hardware. The application layer may include one or more application programs (App). The software layer may include a kernel and a root rom, wherein the root rom is used to output mode control instructions, which are used to control the security processor 20 to start in secure or insecure mode. The kernel provides a platform for the application programs to run. The hardware layer includes a main control processor 10 and a security processor 20, wherein the main control processor 10 provides hardware support for the implementation of the software layer. The security processor 20 is a component in the RISC-V architecture that ensures the security settings of the main control processor 10.
[0069] exist Figure 4 In the system shown, the main control processor 10 will access the security processor 20 in the form of Mailbox in the Inter-Process Communication (IPC) protocol to obtain the required data from the security processor 20.
[0070] Figure 5 for Figure 4 The flowchart shown illustrates the system's method for handling memory access requests. Figure 5 As shown, the method includes:
[0071] Step 501: Bootrom sets the security processor 20 to start in safe mode;
[0072] Step 502: The application requests access to the data stored in the OTP memory 30;
[0073] Step 503: The main control processor 10 and the security processor 20 establish communication through the IPC communication protocol;
[0074] Step 504: The main control processor 10 sends a memory access request to the security processor 20 using Mailbox. The memory access request is used to perform object data read or write operations on the target address of the visible field area or invisible field area pointed to by the memory access address involved in the memory access request.
[0075] Step 505: Security processor 20 receives a memory access request;
[0076] Step 506: The OTP controller parses the information carried in the memory access request; the information carried may be the memory access address and data description information; further, the data description information may be the data size and flag bits;
[0077] Step 507: The OTP controller determines whether the memory access address in the memory access request is within the address region of the invisible field;
[0078] If the storage address in the memory access request is within the address range of the invisible field, proceed to step 511; otherwise, proceed to step 508.
[0079] Step 508: The OTP controller determines whether the size of the data in the memory access request is consistent with the size of the data in the address area of the visible field;
[0080] If the size of the data in the memory access request is consistent with the size of the data in the address area of the visible field, then proceed to step 509; otherwise, proceed to step 511.
[0081] Step 509: The OTP controller determines whether the memory access request is correct based on the value of the flag bit of the memory access request.
[0082] If the flag of the memory access request indicates a data read operation, and data is stored at the corresponding storage address in the OTP, then the memory access request is considered correct; if no data is stored at the corresponding storage address in the OTP, then the memory access request is considered incorrect.
[0083] If the flag of the memory access request indicates a data write operation, and if the corresponding storage address in the OTP has not been written to, or if data has been stored and modification is allowed, then the memory access request is considered correct; otherwise, the memory access request is considered incorrect.
[0084] If the memory access request is valid, proceed to step 510; otherwise, proceed to step 511.
[0085] Step 510: The security processor 20 responds to the memory access request, and the process ends;
[0086] According to the information, if the flag of the memory access request indicates a data read operation, the security processor 20 returns the corresponding visible field; if the flag indicates that data is written to a free area, the security processor 20 writes the transmitted data in the corresponding address range and returns the requested data after completion.
[0087] Step 511: Security processor 20 returns an empty response message, and the process ends.
[0088] The method provided in this application compares the address in the memory access request with the address region of the invisible field in the OTP to achieve effective protection of the invisible field; and uses the data description information in the memory access request to provide protection for secure access to the visible field.
[0089] Figures 6 to 8 These are all schematic diagrams illustrating the response of the security processor 20 to memory access requests. Figures 6 to 8 In the process, the security processor 20 has an built-in OTP. The OTP address area is mainly divided into two parts: one part is a visible field area, such as the chip ID, and the other part is a non-visible field area, such as the encryption / decryption key and the user's private key. In both parts, some free areas are reserved so that data can still be stored after tape-out, according to design requirements, to achieve the function.
[0090] exist Figure 6 In the application scenario shown, the security processor 20 starts in secure mode, and the main control processor 10 accesses the visible field area. The OTP controller 32 allows the access to be responded to, and the security processor 20 responds to the access in the main control processor 10.
[0091] exist Figure 7 In the application scenario shown, the security processor 20 starts in secure mode. When the main control processor 10 accesses the invisible field area, the OTP controller 32 refuses to respond to the access. The security processor 20 does not respond to the access in the main control processor 10 and only returns an empty response message.
[0092] exist Figure 8 In the application scenario shown, the security processor 20 starts in secure mode, and the main control processor 10 initiates at least two memory access requests. One memory access request is to access an invisible field area, specifically writing data to the free area 2 in the invisible field area. The OTP controller 32 refuses to respond to this access, and the security processor 20 does not respond to the access in the main control processor 10, only returning an empty response message. The other memory access request is for the main control processor 10 to access a visible field area, specifically writing data to the free area 1 in the visible field area. In this case, the OTP controller 32 allows the access, and the security processor 20 responds to the access in the main control processor 10.
[0093] This application embodiment also provides a method for processing memory access requests, which is applied to the data processing apparatus 100 described above. The processing method includes:
[0094] The main control processor 10 establishes a communication connection with the security processor 20 and sends a memory access request. The memory access request is used to perform object data read or write operations on the target address of the visible field area or the non-visible field area pointed to by the memory access address involved in the memory access request.
[0095] The security processor 20 responds to the memory access request by parsing the memory access address and data description information involved in the request, and compares the information in the parsing result with the associated information of the OTP memory 30 in sequence; and in response to the comparison result indicating that the information in the parsing result and the associated information are both matched, it stores the object data in the target address of the OTP memory 30 or reads it from the target address and returns it to the main control processor 10, otherwise it triggers a security exception operation.
[0096] In one exemplary embodiment, at least one of the visible field area and the non-visible field area is configured with a backup storage area.
[0097] The method further includes:
[0098] In non-secure mode, the main control processor 10 performs data writing operations to the backup storage area configured in the visible field area to adjust the range of the visible field area;
[0099] In secure mode, the security processor 20 performs data write operations to the backup storage area configured in the invisible region to adjust the range of the invisible field region.
[0100] In one exemplary embodiment, the data description information includes data size and a flag bit, the flag bit indicating a read or write operation on the object data;
[0101] In secure mode, the security processor 20 determines whether the memory access address is in the visible field region or the invisible field region of the OTP memory 30. If the memory access address is in the visible field region, it further compares the data size of the data description information with the data size stored at the target address in the visible field region, and performs corresponding operations based on the flag bit if they are consistent.
[0102] In one exemplary embodiment, the main control processor 10 establishes a communication connection with the security processor 20, including:
[0103] The main control processor 10 establishes a communication connection with the security processor 20 through the Mailbox format in the IPC communication protocol.
[0104] In one exemplary embodiment, the method further includes:
[0105] The main control processor 10 outputs a mode control instruction, wherein the mode control instruction is used to control the security processor 20 to start in a security mode or a non-security mode.
[0106] The security processor 20 responds to the mode control command and operates in the mode corresponding to the mode control command.
[0107] The method provided in this application provides a method that parses the memory access address and data description information in the memory access request, and compares the information in the parsing result with the associated information of the OTP memory 30 in sequence. This allows the memory access request to be processed based on the comparison result. It does not require setting a security register, but is based on software operation steps to complete the processing of the memory access request. The method is easy to design, implements easily, and has low design cost.
[0108] The technical solutions provided in this application have the following technical effects, including:
[0109] In the RISC-V architecture, the address in the memory access request is compared with the address region of the invisible field in the OTP to achieve effective protection of the invisible field.
[0110] During the chip design phase, different data address regions of the OTP can be flexibly adjusted according to design requirements to reduce hardware design complexity, thereby reducing design costs and tape-out difficulty.
[0111] By utilizing the data description information in the memory access request, secure access to visible fields can be protected.
[0112] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.
Claims
1. A data processing apparatus based on a RISC-V architecture, comprising a main control processor and a security processor, wherein the security processor includes an OTP memory configured with a visible field region and a hidden field region, wherein, The main control processor is configured to establish a communication connection with the security processor and send a memory access request, wherein the memory access request is used to perform object data read or write operations on the target address of the visible field area or the invisible field area pointed to by the memory access address involved in the memory access request. The security processor is configured to respond to the memory access request by parsing the memory access address and data description information involved in the request, and to compare the information in the parsing result with the associated information of the OTP memory in sequence; and to respond to the comparison result indicating that the information in the parsing result and the associated information are both matched, to store the object data in the target address of the OTP memory or to read it from the target address and return it to the main control processor, otherwise to trigger a security exception operation.
2. The data processing apparatus according to claim 1, wherein, At least one of the visible field area and the non-visible field area is configured with a backup storage area. The main control processor is also configured to perform data writing operations to the backup storage area configured in the visible field area in non-secure mode to adjust the range of the visible field area; The security processor is further configured to perform data write operations to the backup storage area configured in the invisible area in a secure mode to adjust the range of the invisible field area.
3. The data processing apparatus according to claim 1, wherein, The data description information includes data size and flag bits, wherein the flag bits indicate read or write operations on the object data; The security processor is configured to, in security mode, determine whether the memory access address is in the visible field region or the invisible field region of the OTP memory. In response to the memory access address being in the visible field region, it further compares the data size of the data description information with the data size stored at the target address in the visible field region, and performs corresponding operations based on the flag bit if they are consistent.
4. The data processing apparatus according to claim 1, wherein: The main control processor is configured to establish a communication connection with the security processor via Mailbox in the IPC communication protocol.
5. The data processing apparatus according to claim 1, wherein: The main control processor is configured to output mode control instructions, wherein the mode control instructions are used to control the security processor to start in a security mode or a non-security mode. The security processor is configured to respond to the mode control command and operate in the mode corresponding to the mode control command.
6. A method for processing memory access requests, the method being applied in the data processing apparatus as described in any one of claims 1 to 5, the method comprising: The main control processor establishes a communication connection with the security processor and sends a memory access request, wherein the memory access request is used to perform object data read or write operations on the target address of the visible field area or the non-visible field area pointed to by the memory access address involved in the memory access request. The security processor responds to the memory access request by parsing the memory access address and data description information involved in the request, and compares the information in the parsing result with the associated information of the OTP memory in sequence; and in response to the comparison result indicating that the information in the parsing result and the associated information match, it stores the object data in the target address of the OTP memory or reads it from the target address and returns it to the main control processor, otherwise it triggers a security exception operation.
7. The processing method according to claim 6, wherein, At least one of the visible field area and the non-visible field area is configured with a backup storage area. The method further includes: In non-secure mode, the main control processor performs data writing operations to the backup storage area configured in the visible field area to adjust the range of the visible field area; In secure mode, the security processor performs data write operations to the backup storage area configured in the invisible region to adjust the range of the invisible field region.
8. The processing method according to claim 6, wherein, The data description information includes data size and flag bits, wherein the flag bits indicate read or write operations on the object data; In secure mode, the security processor determines whether the memory access address is in the visible field region or the invisible field region of the OTP memory. If the memory access address is in the visible field region, it further compares the data size of the data description information with the data size stored at the target address in the visible field region, and performs corresponding operations based on the flag bit if they match.
9. The processing method according to claim 6, wherein, The main control processor establishes a communication connection with the security processor, including: The main control processor establishes a communication connection with the security processor via Mailbox in the IPC communication protocol.
10. The processing method according to claim 6, wherein, The method further includes: The main control processor outputs a mode control instruction, wherein the mode control instruction is used to control the security processor to start in a security mode or a non-security mode. The security processor responds to the mode control command and operates in the mode corresponding to the mode control command.