Error-correcting storage systems, chips, and vehicles

Abstract

The present invention provides an error correction storage system, a chip, and a vehicle. The storage device includes: a first memory and a second memory, one of the first memory and the second memory storing error-correctable data, and the other of the first memory and the second memory storing verification data corresponding to the error-correctable data; when the first memory and the second memory also include storable space, the storable space can be used to store non-error-correctable data, wherein the storable space is the storage space in the first memory and the second memory excluding the storage space occupied by the error-correctable data and the verification data.

Description

Technical Field

[0001] This invention relates to the field of data processing technology, and more specifically, to an error correction storage system, a chip, and a vehicle. Background Technology

[0002] In an error-correctable system, the verification data area and the ECC data area coexist.

[0003] Specifically, taking the 32,7 Hamming code as an example, one row is 39 bits, consisting of 32 bits of data and 7 bits of check data.

[0004] When the data in the application does not require ECC verification, ordinary data can only be stored up to 32 bits, and data between 33 and 39 bits cannot be utilized, thus resulting in a waste of storage space. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art or related art.

[0006] Therefore, a first aspect of the present invention is to provide a storage device.

[0007] A second aspect of the present invention is that an error-correcting storage system is provided.

[0008] A third aspect of the present invention is that a chip is provided.

[0009] A fourth aspect of the invention is that a vehicle is provided.

[0010] In view of the above, a first aspect of the present invention provides a storage device, comprising: a first memory and a second memory, wherein one of the first memory and the second memory is used to store error-correctable data, and the other of the first memory and the second memory is used to store verification data corresponding to the error-correctable data; wherein the first memory and the second memory further include storable space, the storable space can be used to store non-error-correctable data, wherein the storable space is the storage space in the first memory and the second memory excluding the storage space occupied by the error-correctable data and the verification data.

[0011] The technical solution of this application proposes a storage device, which consists of a first memory and a second memory, wherein error-correctable data and corresponding verification data are stored in the first memory and the second memory respectively, thereby reducing the storage requirements for error-correctable data and verification data storage. At the same time, it is also convenient to use the above-mentioned memory to store ordinary data, thereby realizing the full utilization of the storage space in the memory.

[0012] Specifically, in the relevant technical solutions, taking 32.7 Hamming code as an example, one line is 39 bits, but ordinary data can only be stored up to 32 bits. Data cannot be stored between the 33rd and 39th bits, thus resulting in a waste of storage space.

[0013] In the technical solution of this application, when error-correctable data and verification data are stored separately, only 32 bits need to be stored in one row, that is, only error-correctable data is stored, while verification data can be stored in another row.

[0014] Taking Hamming code as an example, the check data is 7 bits. By adding a 0 as a placeholder, it can be formed into 8 bits of data. In a 32-bit storage mode, the check data corresponding to the 4 error-correctable data are combined to form 32-bit combined check data. In this case, both the error-correctable data and the combined check data are 32 bits. Therefore, each row in the storage space can be fully utilized. At the same time, the above storage space can also be used to store non-error-correctable data, thereby realizing the reuse of memory space and improving the utilization efficiency of memory.

[0015] In one of the technical solutions, the difference between correctable data and non-correctable data is that correctable data has corresponding verification data, while non-correctable data does not.

[0016] In one of the technical solutions, the error-correctable data can be stored in the first memory or the second memory. Similarly, the verification data can be stored in the first memory or the second memory. It is understood that the error-correctable data and the verification data can be replaced between the first memory and the second memory according to actual use needs, but they cannot be stored in the same memory at the same time.

[0017] In one technical solution, the memory can be Static Random Access Memory (SRAM), which is a type of random access memory. The term "static" means that as long as the memory is powered on, the data stored within it can be permanently retained.

[0018] The storage device, namely the Error Correcting Code (ECC) memory, is a technology that enables "error checking and correction".

[0019] In addition, the storage device proposed in this application has the following additional technical features.

[0020] In the above technical solution, the first memory has a first storage partition, which is used to store error-correctable data. The capacity of the first storage partition is a first value, which is less than or equal to the capacity of the first memory. The second memory has a second storage partition, which is used to store verification data. The capacity of the second storage partition is a second value. The second value is greater than or equal to the first value / the third value. The third value is one of the following: 2, 4, or 8.

[0021] In this technical solution, ECC is developed based on parity checking. In digital circuits, the smallest unit of data is called a "bit," also known as a data "bit." A "bit" is also the smallest unit in memory, and it uses "1" and "0" to represent high and low level signals of data.

[0022] In digital circuits, eight consecutive bits constitute a byte. In memory without parity checking, each byte has only eight bits. If an error occurs in any of these bits, the corresponding data stored in the memory will change, causing errors in the application. Memory with parity checking adds an extra bit to each byte (8 bits) for error detection. For example, if a byte stores a value (1, 0, 1, 0, 1, 0, 1, 1), and these bits are added together (1+0+1+0+1+0+1+1=5), 5 is an odd number. If odd parity is used (i.e., the sum of the 9 corresponding bits in a byte (8 bits) plus the error-checking bit is odd), then the error-checking bit should be 0 (5+0=5 is odd). If even parity is used (i.e., the sum of the 9 corresponding bits in a byte (8 bits) plus the error-checking bit is even), then the error-checking bit should be 1 (5+1=6 is even). When the CPU returns to read the stored data, it will add the data stored in the first 8 bits again and check if the result matches the parity bit. When the CPU finds a difference, it will try to correct these errors. However, Parity's shortcoming is that when memory detects an error in a data bit, it cannot accurately locate the erroneous data bit, and therefore may not be able to correct the error.

[0023] Parity memory checks the correctness of 8 bits of data by adding a parity bit to the original data bits. However, as the number of data bits increases, the number of parity bits also increases exponentially; eight data bits require one parity bit, and sixteen data bits require two parity bits. ECC also adds a parity bit to the original data bits. Unlike Parity, if the data bits are 8 bits, 5 bits are added for ECC error checking and correction. For every doubling of the data bits, ECC only adds one parity bit. That is, when the data bits are 16 bits, the ECC bits are 6; with 32 bits, the ECC bits are 7; with 64 bits, the ECC bits are 8, and so on. ECC has more parity bits, resulting in stronger fault tolerance.

[0024] In the technical solution of this application, by limiting the second value to be greater than or equal to the first value / the third value, wherein the third value can be selected according to different algorithms, the above-mentioned memory can be adapted to existing error correction algorithms.

[0025] Specifically, when the ECC error correction algorithm can use Hamming Code or Hsiao Code, the width of the first memory is 32 bits, and the capacity of the second memory is at least 1 / 4 of the first memory, that is, the width is 8 bits.

[0026] For example, for each 32-bit error-correctable data, there is an 8-bit byte corresponding to the check data. Since 32-bit error-correctable data only requires 7 bits, the 8th bit of each byte can be stored as 0 for padding.

[0027] In any of the above technical solutions, the first memory has a third memory partition and the second memory has a fourth memory partition; wherein the access addresses of the third memory partition and the fourth memory partition are consecutive.

[0028] In this technical solution, the access addresses of the third and fourth storage partitions are made consecutive to improve the convenience of accessing uncorrectable data.

[0029] In one of the technical solutions, the access addresses of the first and second storage partitions are consecutive, while the access addresses of the third and fourth storage partitions are not consecutive.

[0030] In this technical solution, the access addresses of the first and second storage partitions can be selected according to actual design needs to meet actual usage requirements.

[0031] In any of the above technical solutions, the access address of the first storage partition and the access address of the third storage partition have different address ranges; and / or the access address of the second storage partition and the access address of the fourth storage partition have different address ranges.

[0032] In this technical solution, by setting different address ranges for the first and third storage partitions, the address ranges of the access addresses can be used to distinguish between error-correctable and non-error-correctable data when reading data, so as to achieve targeted reading of different data.

[0033] Similarly, by setting different address ranges for the second and fourth storage partitions, when reading data, the address ranges of the access addresses can be used to distinguish between error-correctable and non-error-correctable data, so as to achieve targeted reading of different data.

[0034] For example, when the access address bit HADDR

[20] is high, it is error-correctable data access, and when HADDR

[20] is low, it is non-error-correctable data access.

[0035] In any of the above technical solutions, in the absence of error-correctable data and verification data, the first memory and the second memory can also be used to store non-error-correctable data.

[0036] In this technical solution, when the memory does not need to store error-correctable data and verification data, the storage space used to store error-correctable data and verification data can also be used to store non-error-correctable data, thereby improving the utilization rate of the memory.

[0037] In one of the technical solutions, the size of the first and second storage partitions can be set according to actual usage needs in order to meet the usage requirements of different scenarios.

[0038] In one of the technical solutions, the storage device is a storage device used for error checking and correction.

[0039] A second aspect of the present invention provides an error-correcting storage system, comprising: a storage device as described in any of the first aspects.

[0040] In this technical solution, an error correction storage system is proposed, which includes the storage device as described above. Therefore, the error-correctable data and the corresponding verification data are stored in the first memory and the second memory, respectively, thereby reducing the memory requirements when storing the error-correctable data and the verification data. At the same time, it is also convenient to use the above-mentioned memory to store ordinary data, thereby realizing the full utilization of the storage space in the memory.

[0041] In addition, the error correction storage system proposed in this application has the following additional technical features.

[0042] The above technical solution further includes: a control circuit; a first multiplexer, the first input terminal of which is connected to the control circuit, and the output terminal of which is connected to a first memory in the storage device, the first input terminal of a second multiplexer, and the input terminal of an encoding circuit; an encoding circuit, the output terminal of which is connected to a second input terminal of the second multiplexer; a second multiplexer, the output terminal of which is connected to a second memory in the storage device; and a decoding circuit, the input terminal of which is connected to the first memory and the second memory, and the output terminal of which is connected to the control circuit and the second input terminal of the first multiplexer.

[0043] In this technical solution, by setting up an encoding circuit, a first multiplexer, a second multiplexer, and a decoding circuit, the generation of verification data can be realized. At the same time, the reading and writing of error-correctable data and non-error-correctable data can also be realized, thus making it compatible with data reading and writing in related technical solutions.

[0044] Specifically, the encoding circuit can encode error-correctable data based on error correction algorithms, such as Hamming codes or Sho codes, thereby generating verification data corresponding to the error-correctable data.

[0045] Correspondingly, decoding can combine the read error-correctable data with the corresponding verification data to form new data, thereby achieving error correction and detection.

[0046] The first and second multiplexers are used for mixing data and reading and writing data to a specific access address.

[0047] In any of the above technical solutions, when the error correction storage system is operating in the first mode, the control circuit sends error-correctable data to the first multiplexer, the first multiplexer sends the error-correctable data to the first memory and the encoding circuit, the encoding circuit encodes the error-correctable data to obtain verification data, wherein the verification data is sent to the second memory through the second multiplexer.

[0048] In this technical solution, the first mode is the writing of whole words of error-correctable data, i.e., Word writing. In this mode, the control circuit obtains the error-correctable data from the bus and sends the error-correctable data to the first multiplexer, so that the first multiplexer sends the error-correctable data to the encoding circuit and the first memory, so that the error-correctable data is stored in the first memory. The encoding circuit encodes the error-correctable data to obtain the verification data, and sends the verification data to the second multiplexer, so that the second multiplexer stores the verification data in the second memory.

[0049] Specifically, the first multiplexer stores error-correcting data in a first storage partition of the first memory, and the second multiplexer stores verification data in a second storage partition of the second memory.

[0050] In the context of the first and second multiplexers, "first" and "second" are used only to distinguish different multiplexers when there are multiple multiplexers.

[0051] Among them, multiplexer is another name for data selector. In the process of multi-channel data transmission, the circuit that can select any one of the channels as needed is called a data selector, also known as a multiplexer or multiplexer switch.

[0052] In any of the above technical solutions, when the error correction storage system is operating in the second mode, the control circuit initiates a read operation to the first memory and the second memory. The decoding circuit outputs the read result based on the error-correctable data and the verification data. The first multiplexer updates the error-correctable data based on the error-correctable data to be written and the read result, and sends the updated error-correctable data to the first memory and the encoding circuit. The encoding circuit encodes the updated error-correctable data to obtain the updated verification data. The updated verification data is then sent to the second memory through the second multiplexer.

[0053] In this technical solution, the second mode is byte writing or half-word writing of error-correctable data, also known as Byte or Half-Word writing. In this mode, the control circuit first sends a read operation to the first memory and the second memory to send the error-correctable data in the first memory and the verification data in the second memory to the decoding circuit. At this time, the decoding circuit sends the data as a read result to the first multiplexer, so that the first multiplexer can mix the error-correctable data to be written with the read result, thereby updating the error-correctable data.

[0054] After the error-correctable data is updated, the first multiplexer can send it to the first memory and the encoding circuit to update the error-correctable data in the first memory. At the same time, after receiving the updated error-correctable data, the encoding circuit will also re-encode the updated error-correctable data to update the verification data. Using the connection between the encoding circuit and the second memory, the updated verification data will be sent to the second memory to update the verification data in the second memory.

[0055] In any of the above technical solutions, when the error correction storage system is operating in the third mode, the control circuit initiates a read operation to the first memory and the second memory, wherein the decoding circuit outputs the read result based on the error-correctable data and the verification data; and the control circuit outputs the read result.

[0056] In this technical solution, the third mode can be a read operation of error-correctable data. In this mode, the control circuit sends a read operation to the first memory and the second memory so that the error-correctable data in the first memory and the verification data in the second memory are sent to the decoding circuit. At this time, the decoding circuit sends the data as a read result to the control circuit so that the control circuit sends it to the bus, thereby realizing the reading of data in the memory.

[0057] In any of the above technical solutions, the decoding circuit is further configured to: output status identification information based on the error-correctable data and the verification data; wherein the status identification information includes single bit error correction or at least two bit error detection.

[0058] In this technical solution, the decoding circuit uses verification data to verify the error-correctable data and outputs status identification information based on the verification result for the user to view.

[0059] Specifically, the status information can be no error, single bit error correction, or at least two bit error detection.

[0060] Specifically, in the absence of errors, no state identification information is output; in the presence of a single bit error correction, a 1-bit error is output and the single bit error is corrected; and in the presence of at least two bit errors, a 2-bit error is output.

[0061] In one of the technical solutions, there is a single-bit error correction bit, or SEC.

[0062] In one of the technical solutions, there is at least two bit error detection, known as Double Error Detection (DED).

[0063] Based on this, in the absence of errors, both SEC and DED are 0;

[0064] In the case of a single bit error correction, SEC is 1 and DED is 0;

[0065] In the presence of at least two bit error detections, SEC is 0 and DED is 1.

[0066] In one technical solution, if at least two bit errors are detected, no error correction is performed, and the current write operation is aborted for processing by the central processing unit (CPU) communicating with the control circuit. The CPU and the control circuit communicate via a bus.

[0067] In any of the above technical solutions, when the error correction storage system is operating in the fourth mode, the control circuit sends uncorrectable data to the first multiplexer, and the first multiplexer sends the uncorrectable data to the first memory or the second multiplexer; wherein, when the second multiplexer receives the uncorrectable data, it sends the uncorrectable data to the second memory.

[0068] In this technical solution, the fourth mode is writing non-error-correcting data, that is, writing non-error-correcting data into the memory. At this time, the control circuit can use the first multiplexer to send the non-error-correcting data to the first memory for storage in the first memory; the control circuit can use the first multiplexer to send the non-error-correcting data to the second multiplexer, so that the second multiplexer can send it to the second memory for storage in the second memory.

[0069] In one technical solution, the control circuit can use a first multiplexer to send a portion of the uncorrectable data to a first memory for storage, while simultaneously sending the remaining uncorrectable data to a second multiplexer for transmission to a second memory for storage.

[0070] In the above technical solution, non-error-correctable data can be stored in the memory according to actual writing needs, so as to meet the writing needs in different scenarios.

[0071] In any of the above technical solutions, when the error correction storage system is operating in the fifth mode, the control circuit obtains the uncorrectable data in the first memory and / or the second memory according to the access address.

[0072] In this technical solution, the fifth mode can be reading non-error-correcting data. The control circuit can determine the memory to be accessed based on the access address, and then read non-error-correcting data from the first memory or the second memory.

[0073] A third aspect of the present invention provides a chip comprising: an error-correcting storage system as described in any of the above technical solutions.

[0074] This technical solution proposes a chip that has the aforementioned error correction storage system, and therefore possesses all the beneficial technical effects of the aforementioned error correction storage system, which will not be elaborated further here.

[0075] In the above technical solution, the chip can be a chip on a memory module.

[0076] A fourth aspect of the present invention provides a vehicle comprising: the chip described above.

[0077] This technical solution proposes a vehicle that has the aforementioned chip. Therefore, all the beneficial technical effects of having the aforementioned chip will not be elaborated here.

[0078] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0079] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0080] Figure 1 A schematic block diagram of a storage device according to an embodiment of the present invention is shown;

[0081] Figure 2 A schematic block diagram of the error correction storage system in an embodiment of the present invention is shown.

[0082] in, Figure 1 and Figure 2 The correspondence between the reference numerals and component names in the attached drawings is as follows:

[0083] 102 First memory, 1022 First storage partition, 1024 Third storage partition, 104 Second memory, 1042 Second storage partition, 1044 Fourth storage partition, 202 Control circuit, 204 First multiplexer, 206 Encoding circuit, 208 Second multiplexer, 210 Decoding circuit. Detailed Implementation

[0084] To better understand the above aspects, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other.

[0085] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0086] In one embodiment, such as Figure 1As shown, a storage device is proposed, including: a first memory 102 and a second memory 104, one of the first memory 102 and the second memory 104 is used to store error-correctable data, and the other of the first memory 102 and the second memory 104 is used to store verification data corresponding to the error-correctable data; when the first memory 102 and the second memory 104 also include storable space, the storable space can be used to store non-error-correctable data, wherein the storable space is the storage space in the first memory 102 and the second memory 104 excluding the storage space occupied by the error-correctable data and the verification data.

[0087] The embodiments of this application propose a storage device, which consists of a first memory 102 and a second memory 104, wherein error-correctable data and corresponding verification data are stored in the first memory 102 and the second memory 104, respectively, thereby reducing the storage requirements for error-correctable data and verification data storage. At the same time, it is also convenient to use the above-mentioned memory to store ordinary data, thereby realizing the full utilization of the storage space in the memory.

[0088] Specifically, in the relevant embodiments, taking 32.7 Hamming code as an example, one line is 39 bits, but ordinary data can only be stored up to 32 bits. Data cannot be stored between the 33rd and 39th bits, thus resulting in a waste of storage space.

[0089] In the embodiments of this application, when error-correctable data and verification data are stored separately, only 32 bits need to be stored per row, that is, only error-correctable data is stored, while verification data can be stored in another row.

[0090] Taking Hamming code as an example, the check data is 7 bits. By adding a 0 as a placeholder, it can be formed into 8 bits of data. In a 32-bit storage mode, the check data corresponding to the 4 error-correctable data are combined to form 32-bit combined check data. In this case, both the error-correctable data and the combined check data are 32 bits. Therefore, each row in the storage space can be fully utilized. At the same time, the above storage space can also be used to store non-error-correctable data, thereby realizing the reuse of memory space and improving the utilization efficiency of memory.

[0091] In one embodiment, the difference between correctable data and non-correctable data is that correctable data has corresponding verification data, while non-correctable data does not have corresponding verification data.

[0092] In one embodiment, the error-correctable data can be stored in the first memory 102 and the second memory 104. Similarly, the verification data can be stored in the first memory 102 and the second memory 104. It is understood that the error-correctable data and the verification data can be replaced between the first memory 102 and the second memory 104 according to actual use needs, but they cannot be stored in the same memory at the same time.

[0093] In one embodiment, the memory may be Static Random Access Memory (SRAM), which is a type of random access memory. The term "static" means that the data stored in this type of memory can be permanently retained as long as it is powered on.

[0094] The storage device, namely the Error Correcting Code (ECC) memory, is a technology that enables "error checking and correction".

[0095] In the above embodiments, the first memory 102 has a first storage partition 1022, which is used to store error-correctable data. The capacity of the first storage partition 1022 is a first value, and the capacity of the first storage partition 1022 is less than or equal to the capacity of the first memory 102. The second memory has a second storage partition 1042, which is used to store verification data. The capacity of the second storage partition 1042 is a second value, and the second value is ≥ the first value / 4.

[0096] In this embodiment, ECC is developed based on parity checking. In digital circuits, the smallest unit of data is called a "bit," also known as a data "bit." A "bit" is also the smallest unit in memory, and it uses "1" and "0" to represent high and low level data signals.

[0097] In digital circuits, eight consecutive bits constitute a byte. In memory without parity checking, each byte has only eight bits. If an error occurs in any of these bits, the corresponding data stored in the memory will change, causing errors in the application. Memory with parity checking adds an extra bit to each byte (8 bits) for error detection. For example, if a byte stores a value (1, 0, 1, 0, 1, 0, 1, 1), and these bits are added together (1+0+1+0+1+0+1+1=5), 5 is an odd number. If odd parity is used (i.e., the sum of the 9 corresponding bits in a byte (8 bits) plus the error-checking bit is odd), then the error-checking bit should be 0 (5+0=5 is odd). If even parity is used (i.e., the sum of the 9 corresponding bits in a byte (8 bits) plus the error-checking bit is even), then the error-checking bit should be 1 (5+1=6 is even). When the CPU returns to read the stored data, it will add the data stored in the first 8 bits again and check if the result matches the parity bit. When the CPU finds a difference, it will try to correct these errors. However, Parity's shortcoming is that when memory detects an error in a data bit, it cannot accurately locate the erroneous data bit, and therefore may not be able to correct the error.

[0098] Parity memory checks the correctness of 8 bits of data by adding a parity bit to the original data bits. However, as the number of data bits increases, the number of parity bits also increases exponentially; eight data bits require one parity bit, and sixteen data bits require two parity bits. ECC also adds a parity bit to the original data bits. Unlike Parity, if the data bits are 8 bits, 5 bits are added for ECC error checking and correction. For every doubling of the data bits, ECC only adds one parity bit. That is, when the data bits are 16 bits, the ECC bits are 6; with 32 bits, the ECC bits are 7; with 64 bits, the ECC bits are 8, and so on. ECC has more parity bits, resulting in stronger fault tolerance.

[0099] In the embodiments of this application, the second value is limited to be greater than or equal to the first value / 4 so that the memory can be adapted to existing error correction algorithms.

[0100] Specifically, when the ECC error correction algorithm can be either Hamming Code or Hsiao Code, the width of the first memory 102 is 32 bits, and the capacity of the second memory 104 is at least 1 / 4 of that of the first memory 102, that is, the width is 8 bits.

[0101] For example, for each 32-bit error-correctable data, there is an 8-bit byte corresponding to the check data. Since 32-bit error-correctable data only requires 7 bits, the 8th bit of each byte can be stored as 0 for padding.

[0102] In any of the above embodiments, the first memory 102 has a third storage partition 1024, and the second memory 104 has a fourth storage partition 1044; wherein the access addresses of the third storage partition 1024 and the fourth storage partition 1044 are consecutive.

[0103] In this embodiment, by limiting the access addresses of the third storage partition 1024 and the fourth storage partition 1044 to be consecutive, the convenience of accessing uncorrectable data is improved.

[0104] In one embodiment, the access addresses of the first storage partition 1022 and the second storage partition 1042 are consecutive, while the access addresses of the third storage partition 1024 and the fourth storage partition 1044 are not consecutive.

[0105] In this embodiment, the access addresses of the first storage partition 1022 and the second storage partition 1042 can be selected according to actual design needs in order to meet actual usage requirements.

[0106] In any of the above embodiments, the access address of the first storage partition 1022 and the access address of the third storage partition 1024 have different address ranges; and / or the access address of the second storage partition 1042 and the access address of the fourth storage partition 1044 have different address ranges.

[0107] In this embodiment, by setting different address segments for the first storage partition 1022 and the third storage partition 1024, when reading data, the address segments of the access address can be used to distinguish between error-correctable data and non-error-correctable data, so as to achieve targeted reading of different data.

[0108] Similarly, by setting different address segments for the second storage partition 1042 and the fourth storage partition 1044, when reading data, the address segments of the access address can be used to distinguish between error-correctable data and non-error-correctable data, so as to achieve targeted reading of different data.

[0109] For example, when the access address bit HADDR

[20] is high, it is error-correctable data access, and when HADDR

[20] is low, it is non-error-correctable data access.

[0110] In any of the above embodiments, in the absence of error-correctable data and verification data, the first memory 102 and the second memory 104 can also be used to store non-error-correctable data.

[0111] In this embodiment, when the memory does not need to store error-correctable data and verification data, the storage space used to store error-correctable data and verification data can also be used to store non-error-correctable data, thereby improving the utilization rate of the memory.

[0112] In one embodiment, the size of the first storage partition 1022 and the second storage partition 1042 can be set according to actual usage needs in order to meet the usage needs under different usage scenarios.

[0113] In one embodiment, the storage device is a storage device for error checking and correction.

[0114] In one embodiment, the memory mentioned above may be a memory chip.

[0115] In one embodiment, an error correction storage system is provided, including a storage device as described in any of the above embodiments.

[0116] In this embodiment, an error correction storage system is proposed, which includes the storage device as described above. Therefore, the error-correctable data and the corresponding verification data are stored in the first memory 102 and the second memory 104, respectively, thereby reducing the storage requirements for error-correctable data and verification data. At the same time, it is also convenient to use the above-mentioned memory to store ordinary data, thereby realizing the full utilization of the storage space in the memory.

[0117] In the above embodiments, such as Figure 2 As shown, it also includes: a control circuit 202; a first multiplexer 204, the first input terminal of the first multiplexer 204 being connected to the control circuit 202, and the output terminal of the first multiplexer 204 being connected to the first memory 102 in the storage device, the first input terminal of the second multiplexer 208, and the input terminal of the encoding circuit 206; an encoding circuit 206, the output terminal of the encoding circuit 206 being connected to the second input terminal of the second multiplexer 208; a second multiplexer 208, the output terminal of the second multiplexer 208 being connected to the second memory 104 in the storage device; and a decoding circuit 210, the input terminal of the decoding circuit 210 being connected to the first memory 102 and the second memory 104, and the output terminal of the decoding circuit 210 being connected to the control circuit 202 and the second input terminal of the first multiplexer 204.

[0118] In this embodiment, by setting up an encoding circuit 206, a first multiplexer 204, a second multiplexer 208, and a decoding circuit 210, verification data can be generated. At the same time, error-correctable data and non-error-correctable data can also be read and written, thus ensuring compatibility with data reading and writing in related embodiments.

[0119] Specifically, the encoding circuit 206 can encode the error-correctable data based on error correction algorithms, such as Hamming codes or Sho codes, thereby generating verification data corresponding to the error-correctable data.

[0120] Correspondingly, decoding can combine the read error-correctable data with the corresponding verification data to form new data, thereby achieving error correction and detection.

[0121] The first multiplexer 204 and the second multiplexer 208 are used to mix data and to read and write data to a specific access address.

[0122] In any of the above embodiments, when the error correction storage system is operating in the first mode, the control circuit 202 sends error-correctable data to the first multiplexer 204, the first multiplexer 204 sends the error-correctable data to the first memory 102 and the encoding circuit 206, the encoding circuit 206 encodes the error-correctable data to obtain verification data, wherein the verification data is sent to the second memory 104 through the second multiplexer 208.

[0123] In this embodiment, the first mode is the writing of whole words of correctable data, i.e., Word writing. In this mode, the control circuit 202 obtains the correctable data from the bus and sends the correctable data to the first multiplexer 204, so that the first multiplexer 204 sends the correctable data to the encoding circuit 206 and the first memory 102, so that the correctable data is stored in the first memory 102. The encoding circuit 206 encodes the correctable data to obtain the verification data, and sends the verification data to the second multiplexer 208, so that the second multiplexer 208 stores the verification data in the second memory 104.

[0124] Specifically, the first multiplexer 204 stores the error-correcting data in the first storage partition 1022 of the first memory 102, and the second multiplexer 208 stores the verification data in the second storage partition 1042 of the second memory 104.

[0125] In the case of multiplexer 204 and multiplexer 208, the terms "first" and "second" are used only to distinguish different multiplexers when there are multiple multiplexers.

[0126] Among them, multiplexer is another name for data selector. In the process of multi-channel data transmission, the circuit that can select any one channel as needed is called data selector, also known as multiplexer or multiplexer switch. Data selector can select data from any channel, and can also select 1 byte from one channel and 3 bytes from another channel (byte write), or select 2 bytes from one channel and 2 bytes from another channel (half-word write).

[0127] In any of the above embodiments, when the error correction storage system is operating in the second mode, the control circuit 202 initiates a read operation to the first memory 102 and the second memory 104. The decoding circuit 210 outputs the read result based on the error-correctable data and the verification data. The first multiplexer 204 updates the error-correctable data based on the error-correctable data to be written and the read result, and sends the updated error-correctable data to the first memory 102 and the encoding circuit 206. The encoding circuit 206 encodes the updated error-correctable data to obtain the updated verification data. The updated verification data is sent to the second memory 104 through the second multiplexer 208.

[0128] In this embodiment, the second mode is byte writing or half-word writing of error-correctable data, also known as Byte or Half Word writing. In this mode, the control circuit 202 first sends a read operation to the first memory 102 and the second memory 104 to send the error-correctable data on the first memory 102 and the verification data on the second memory 104 to the decoding circuit 210. At this time, the decoding circuit 210 sends it as a read result to the first multiplexer 204, so that the first multiplexer 204 can mix the error-correctable data to be written with the read result, thereby updating the error-correctable data.

[0129] After the error-correctable data is updated, the first multiplexer 204 can send it to the first memory 102 and the encoding circuit 206 to update the error-correctable data on the first memory 102. At the same time, after receiving the updated error-correctable data, the encoding circuit 206 will also re-encode the updated error-correctable data to update the verification data. Using the connection between the encoding circuit 206 and the second memory 104, the updated verification data will be sent to the second memory 104 to update the verification data in the second memory 104.

[0130] In any of the above embodiments, when the error correction storage system is operating in the third mode, the control circuit 202 initiates a read operation to the first memory 102 and the second memory 104, wherein the decoding circuit 210 outputs the read result based on the error-correctable data and the verification data; and the control circuit 202 outputs the read result.

[0131] In this embodiment, the third mode can be a read operation of error-correctable data, wherein the control circuit 202 sends a read operation to the first memory 102 and the second memory 104 so as to send the error-correctable data on the first memory 102 and the verification data on the second memory 104 to the decoding circuit 210. At this time, the decoding circuit 210 sends it as a read result to the control circuit 202 so that the control circuit 202 sends it to the bus, thereby realizing the reading of data in the memory.

[0132] In any of the above embodiments, the decoding circuit 210 is further configured to: output status identification information based on the error-correctable data and the verification data; wherein the status identification information includes single bit error correction or at least two bit error detection.

[0133] In this embodiment, the decoding circuit 210 uses the verification data to verify the error-correctable data and outputs status identification information based on the verification result for the user to view.

[0134] Specifically, the status information can be no error, single bit error correction, or at least two bit error detection.

[0135] Specifically, in the absence of errors, no state identification information is output; in the presence of a single bit error correction, a 1-bit error is output and the single bit error is corrected; and in the presence of at least two bit errors, a 2-bit error is output.

[0136] In one embodiment, a single-bit error correction bit, SEC.

[0137] In one embodiment, at least two bit error detections, Double Error Detection (DED), are performed.

[0138] Based on this, in the absence of errors, both SEC and DED are 0;

[0139] In the case of a single bit error correction, SEC is 1 and DED is 0;

[0140] In the presence of at least two bit error detections, SEC is 0 and DED is 1.

[0141] In one embodiment, if at least two bit errors are detected, no error correction is performed, and the current write operation is aborted for processing by the central processing unit communicating with the control circuit 202, wherein the central processing unit and the control circuit 202 communicate via a bus.

[0142] In any of the above embodiments, when the error correction storage system is operating in the fourth mode, the control circuit 202 sends uncorrectable data to the first multiplexer 204, and the first multiplexer 204 sends the uncorrectable data to the first memory 102 or the second multiplexer 208; wherein, when the second multiplexer 208 receives the uncorrectable data, it sends the uncorrectable data to the second memory 104.

[0143] In this embodiment, the fourth mode is writing uncorrectable data, that is, writing uncorrectable data into the memory. At this time, the control circuit 202 can use the first multiplexer 204 to send the uncorrectable data to the first memory 102 for storage in the first memory 102; the control circuit 202 can use the first multiplexer 204 to send the uncorrectable data to the second multiplexer 208, so that the second multiplexer 208 can send it to the second memory 104 for storage in the second memory 104.

[0144] In one embodiment, the control circuit 202 can use the first multiplexer 204 to send a portion of the uncorrectable data to the first memory 102 for storage, while simultaneously sending the remaining uncorrectable data to the second multiplexer 208 for transmission to the second memory 104 for storage.

[0145] In the above embodiments, non-error-correcting data can be stored in the memory according to actual writing needs, so as to meet the writing needs in different scenarios.

[0146] In any of the above embodiments, when the error correction storage system is operating in the fifth mode, the control circuit 202 obtains the uncorrectable data on the first memory 102 and / or the second memory 104 according to the access address.

[0147] In this embodiment, the fifth mode can be reading non-error-correcting data. The control circuit 202 can determine the memory to be accessed based on the access address, and then read non-error-correcting data from the first memory 102 or the second memory 104.

[0148] In one embodiment, a chip is provided, including an error-correcting storage system as described in any of the above embodiments.

[0149] In this embodiment, a chip is proposed, wherein the chip has the above-mentioned error correction storage system, and therefore has all the beneficial technical effects of the above-mentioned error correction storage system, which will not be repeated here.

[0150] In the above embodiments, the chip may be a chip on a memory module.

[0151] In one embodiment, a vehicle is provided, including: the chip as described above.

[0152] In this embodiment, a vehicle is proposed that has the aforementioned chip. Therefore, all the beneficial technical effects of having the aforementioned chip will not be repeated here.

[0153] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the textual description of this invention, unless otherwise stated, "a plurality of" means two or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0154] In the textual description of this invention, it is understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing and simplifying the embodiments of this invention, and do not indicate or imply that the structures, devices, or elements referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, these descriptions should not be construed as limiting the invention.

[0155] In the textual description of this invention, it is understood that, unless explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0156] In the claims, description, and accompanying drawings of this invention, the term "plural" refers to two or more. Unless otherwise explicitly defined, the terms "upper," "lower," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the invention and simplifying the description process, not to indicate or imply that the device or element referred to must have the described specific orientation, or be constructed and operated in a specific orientation. Therefore, these descriptions should not be construed as limiting the invention. The terms "connect," "install," "fix," etc., should be interpreted broadly. For example, "connect" can be a fixed connection between multiple objects, a detachable connection between multiple objects, or an integral connection; it can be a direct connection between multiple objects or an indirect connection between multiple objects through an intermediate medium. For those skilled in the art, the specific meaning of the above terms in this invention can be understood based on the specific circumstances described above.

[0157] In the claims, description, and accompanying drawings of this invention, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the invention. In the claims, description, and accompanying drawings of this invention, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0158] The above are merely preferred embodiments of the present invention and are not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An error-correcting storage system, characterized in that, include: A storage device, the storage device including a first memory and a second memory, one of the first memory and the second memory being used to store error-correctable data, and the other of the first memory and the second memory being used to store verification data corresponding to the error-correctable data; In the case where the first memory and the second memory also include storable space, the storable space can be used to store uncorrectable data, wherein the storable space is the storage space in the first memory and the second memory excluding the storage space occupied by the correctable data and the verification data; The error correction storage system also includes: Control circuit; A first multiplexer, the first input of which is connected to the control circuit, and the output of which is connected to the first memory in the storage device, the first input of the second multiplexer, and the input of the encoding circuit. The output terminal of the encoding circuit is connected to the second input terminal of the second multiplexer; The output of the second multiplexer is connected to the second memory in the storage device; A decoding circuit, wherein the input terminal of the decoding circuit is connected to the first memory and the second memory, and the output terminal of the decoding circuit is connected to the control circuit and the second input terminal of the first multiplexer.

2. The error correction storage system according to claim 1, characterized in that, When the error correction storage system is operating in the first mode, the control circuit sends error-correctable data to the first multiplexer, the first multiplexer sends the error-correctable data to the first memory and the encoding circuit, the encoding circuit encodes the error-correctable data to obtain verification data, wherein the verification data is sent to the second memory through the second multiplexer.

3. The error correction storage system according to claim 1, characterized in that, When the error correction storage system is operating in the second mode, the control circuit initiates a read operation to the first memory and the second memory, wherein the decoding circuit outputs the read result based on the error-correctable data and the verification data; The first multiplexer updates the error-correctable data according to the error-correctable data to be written and the read result, and sends the updated error-correctable data to the first memory and the encoding circuit. The encoding circuit encodes the updated error-correctable data to obtain updated verification data. The updated verification data is then sent to the second memory through the second multiplexer.

4. The error correction storage system according to claim 1, characterized in that, When the error correction storage system is operating in the third mode, the control circuit initiates a read operation to the first memory and the second memory, wherein the decoding circuit outputs the read result based on the error-correctable data and the verification data; The control circuit outputs the reading result.

5. The error-correcting storage system according to claim 3 or 4, characterized in that, The decoding circuit is also used for: Output status identification information based on the correctable data and the verification data; The status identification information includes single bit error correction or at least two bit error detection.

6. The error-correcting storage system according to any one of claims 1 to 4, characterized in that, When the error correction storage system is operating in the fourth mode, The control circuit sends uncorrectable data to the first multiplexer, and the first multiplexer sends the uncorrectable data to the first memory or the second multiplexer. Specifically, when the second multiplexer receives the uncorrectable data, it sends the uncorrectable data to the second memory.

7. The error correction storage system according to any one of claims 1 to 4, characterized in that, When the error-correcting storage system is operating in the fifth mode, the control circuit obtains the uncorrectable data in the first memory and / or the second memory according to the access address.

8. The error correction storage system according to claim 1, characterized in that, The first memory has a first storage partition, which is used to store the error-correctable data. The capacity of the first storage partition is a first value, and the capacity of the first storage partition is less than or equal to the capacity of the first memory. The second memory has a second storage partition, which is used to store the verification data, and the capacity of the second storage partition is a second value; The second value is greater than or equal to the first value / the third value; The third value can be one of the following: 2, 4, or 8.

9. The error-correcting storage system according to claim 8, characterized in that, The first memory has a third storage partition, and the second memory has a fourth storage partition; The access addresses of the third storage partition and the fourth storage partition are consecutive.

10. The error-correcting storage system according to claim 9, characterized in that, The access addresses of the first storage partition and the access addresses of the third storage partition have different address ranges; and / or The access address of the second storage partition has a different address range than the access address of the fourth storage partition.

11. The error-correcting storage system according to claim 1, characterized in that, In the absence of the correctable data and the verification data, the first memory and the second memory can also be used to store the uncorrectable data.

12. The error-correcting storage system according to claim 11, characterized in that, The storage device is a storage device used for error checking and correction.

13. A chip, characterized in that, include: The error correction storage system as described in any one of claims 1 to 12.

14. A vehicle, characterized in that, include: The chip as described in claim 13.

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