Semiconductor device and method for manufacturing the same

Abstract

An embodiment of the present application discloses a semiconductor device and a manufacturing method thereof. The manufacturing method of the semiconductor device includes: forming a plurality of first trenches extending along a first direction on a substrate; forming a plurality of second trenches extending along a second direction on the substrate having the first trenches formed thereon; the first direction is perpendicular to the second direction; a first depth of the first trenches is greater than a second depth of the second trenches; forming a first isolation layer in the first trenches and the second trenches; in a cross-section in the second direction, a first gap is respectively formed between the first isolation layer and sidewalls on both sides of the first trenches; a depth of the first gap is less than the first depth; depositing a conductive layer of a first conductive material at bottoms of the first gaps on both sides of the first trenches to form two bit lines parallel to each other and extending along the first direction; forming a word line extending along the second direction in the first trenches, the second trenches and on the conductive layer.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor manufacturing technologies, including but not limited to a semiconductor device and a manufacturing method thereof. Background Art

[0002] With the development of chip and memory technologies, the requirements for integration in semiconductor manufacturing processes are getting higher and higher. To improve the utilization rate of semiconductor substrates and enhance integration, semiconductor devices with vertical channel structures have gradually started to be applied. The transistor channels of the vertical channel structure are perpendicular to the surface of the substrate, so they can be conveniently arranged in an array. However, for semiconductor devices with vertical channel structures, the layout of their wiring and the process still need to be further optimized and improved. Summary of the Invention

[0003] In view of this, embodiments of the present application provide a semiconductor device and a manufacturing method thereof to solve at least one problem existing in the prior art.

[0004] In a first aspect, embodiments of the present application provide a manufacturing method of a semiconductor device, the semiconductor device including a substrate; the method includes:

[0005] Forming a plurality of first trenches extending in a first direction on the substrate;

[0006] Forming a plurality of second trenches extending in a second direction on the substrate on which the first trenches are formed; the first direction is perpendicular to the second direction; a first depth of the first trenches is greater than a second depth of the second trenches;

[0007] Forming a first isolation layer in the first trenches and the second trenches; in a cross-section in the second direction, there are first gaps respectively between the first isolation layer and the side walls on both sides of the first trenches; a depth of the first gaps is less than the first depth;

[0008] Depositing a conductive layer of a first conductive material at the bottoms of the first gaps on both sides of the first trenches to form two mutually parallel bit lines extending in the first direction;

[0009] Forming word lines extending in the second direction in the first trenches, the second trenches, and on the conductive layer.

[0010] In some embodiments, the forming a plurality of second trenches extending in a second direction on the substrate on which the first trenches are formed includes:

[0011] Covering a first insulating material on the surface of the substrate to form a first insulating layer; wherein, the first insulating layer covers the inner walls of the first trenches;

[0012] Fill a second insulating material in the first trench to form a second insulating layer;

[0013] Form the plurality of second trenches extending in a second direction on the substrate.

[0014] In some embodiments, forming a first isolation layer in the first trench and the second trench includes:

[0015] Fill the first insulating material in the second trench;

[0016] Synchronously remove the first insulating material covering positions in the first trench and the second trench with a depth less than a third depth to form the first gap; wherein, the third depth is less than the first depth and greater than the second depth; the remaining first insulating layer and the second insulating layer in the first trench and the second trench are the first isolation layer.

[0017] In some embodiments, after filling the first insulating material in the second trench, the method further includes:

[0018] Remove the first insulating material at a fourth depth to form a recessed area; the fourth depth is less than the second depth;

[0019] Cover the sidewall of the recessed area with the second insulating material to form a protective layer; wherein, the first gap formed after removing the first insulating material is located between the protective layer and the remaining first insulating layer in a direction perpendicular to the surface of the substrate.

[0020] In some embodiments, the synchronously removing the first insulating material covering positions in the first trench and the second trench with a depth less than a third depth to form the first gap includes:

[0021] Use wet etching to remove the first insulating material to form the first gap.

[0022] In some embodiments, the first insulating material includes a silicon nitride material; the etching solution used for the wet etching includes a phosphoric acid solution.

[0023] In some embodiments, covering the surface of the substrate with a first insulating material to form a first insulating layer includes:

[0024] Deposit the first insulating material on the surface of the substrate by atomic layer deposition to form the first insulating layer.

[0025] In some embodiments, after filling a second insulating material in the first trench to form a second insulating layer, the method further includes:

[0026] The second insulating layer and the first insulating layer on the substrate surface are planarized to expose the substrate surface in areas other than the first trench and the second trench.

[0027] In some embodiments, depositing a conductive layer of a first conductive material at the bottom of the first gaps on both sides of the first trench to form two mutually parallel bit lines extending along the first direction includes:

[0028] Filling the first conductive material in the first gaps;

[0029] Removing a part of the first conductive material in the first gaps and retaining the first conductive material at the bottom of the first gaps to form the bit lines; wherein, the first conductive material at the bottom is the conductive layer.

[0030] In some embodiments, forming word lines along the second direction in the first trench and the second trench and on the conductive layer includes:

[0031] Removing a part of the first isolation layer above the conductive layer in the first trench and the second trench to form a third trench;

[0032] Forming a second isolation layer at the bottom of the third trench; wherein, the bottom of the second isolation layer is connected to the remaining first isolation layer between the two bit lines in the first trench, and the top of the second

[0033] isolation layer is lower than the substrate surface in areas other than the first trench and the second trench;

[0034] Forming the word lines in the third trench above the second isolation layer.

[0035] In some embodiments, forming the word lines in the third trench above the second isolation layer includes:

[0036] Forming a gate oxide layer on the sidewalls of the first trench and the second trench on the second isolation layer;

[0037] Filling a second conductive material between adjacent gate oxide layers to form a gate conductive layer;

[0038] Forming a fourth trench along the second direction on the second conductive material; wherein, the fourth trench separates the gate conductive layer in a cross-section along the first direction;

[0039] Filling a first insulating material in the fourth trench to form a third isolation layer; the gate conductive layers where the second conductive materials on both sides of the third isolation layer are connected constitute the word lines.

[0040] Second aspect, embodiments of the present application provide a semiconductor device, including:

[0041] A substrate;

[0042] A plurality of first trenches extending in a first direction and a plurality of second trenches extending in a second direction on the substrate; wherein, the first direction is perpendicular to the second direction; a first depth of the first trenches is greater than a second depth of the second trenches;

[0043] A first isolation layer located in the first trenches and the second trenches; in a cross-section in the second direction, a first gap is respectively formed between the first isolation layer and side walls on two sides of the first trenches; a depth of the first gap is less than the first depth;

[0044] A conductive layer of a first conductive material is deposited at bottoms of the first gaps on two sides of the first trenches, and the conductive layer constitutes two mutually parallel bit lines extending in the first direction;

[0045] Word lines extending in the second direction are disposed in the first trenches and the second trenches and on the conductive layer;

[0046] In some embodiments, the first isolation layer includes:

[0047] A first insulating layer located at bottoms of the first trenches and the second trenches;

[0048] A second insulating layer located on the first insulating layer; the first gap is formed between the second insulating layer and side walls on two sides of the first trenches;

[0049] In some embodiments, a second isolation layer is covered on the first isolation layer and the conductive layer in the first gap;

[0050] The word lines extending in the second direction are disposed on the second isolation layer;

[0051] In some embodiments, the semiconductor device further includes:

[0052] A gate oxide layer, located on the second isolation layer and covering side walls of the first trenches and the second trenches;

[0053] The word lines include: a gate conductive layer located between adjacent gate oxide layers; the gate conductive layer is connected in the second direction;

[0054] A third isolation layer is formed between two adjacent word lines;

[0055] The technical solution provided by the embodiments of the present application forms a trench on a substrate during the manufacturing process of a semiconductor device, forms a first isolation layer in the trench that has a first gap between the sidewalls on both sides of the first trench, and then forms a buried bit line structure in the substrate by lining the first gap on both sides of the first trench with a conductive material of the substrate. In this way, on the one hand, compared with the bit lines formed by doping the semiconductor substrate, the bit lines formed by depositing a conductive material in the embodiments of the present application have higher conductivity, so the overall performance of the semiconductor device can be improved. On the other hand, by forming a parallel double-bit line structure in the first gaps on both sidewalls of the first trench, the integration degree of the semiconductor device can be improved, and the parasitic capacitance between the bit lines can be reduced. Description of the Drawings

[0056] Figure 1 It is a flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present application;

[0057] Figures 2A to 2E It is a top view and cross-sectional views of forming a first trench in the manufacturing method provided by an embodiment of the present application;

[0058] Figures 3A to 3C It is cross-sectional views of covering a first insulating layer in the first trench in the manufacturing method provided by an embodiment of the present application;

[0059] Figures 4A to 4C It is cross-sectional views of covering a second insulating layer in the first trench in the manufacturing method provided by an embodiment of the present application;

[0060] Figures 5A to 5D It is cross-sectional views of forming a second trench in the manufacturing method provided by an embodiment of the present application;

[0061] Figures 6A to 6D It is cross-sectional views of filling a first insulating layer in the second trench in the manufacturing method provided by an embodiment of the present application;

[0062] Figures 7A to 7D It is cross-sectional views of forming a recessed area in the manufacturing method provided by an embodiment of the present application;

[0063] Figures 8A to 8C It is cross-sectional views of forming a protective layer in the recessed area in the manufacturing method provided by an embodiment of the present application;

[0064] Figures 9A to 9D It is cross-sectional views of forming a first gap in the manufacturing method provided by an embodiment of the present application;

[0065] Figures 10A to 10C It is a top view and cross-sectional views after forming a bit line in the first gap in the manufacturing method provided by an embodiment of the present application;

[0066] Figures 11A to 11DCross-sectional views of forming a second isolation layer in the manufacturing method provided by the embodiments of the present application;

[0067] Figures 12A to 12D Cross-sectional views of forming a gate conductive layer in the manufacturing method provided by the embodiments of the present application;

[0068] Figures 13A to 13D Cross-sectional views of forming a word line in the manufacturing method provided by the embodiments of the present application;

[0069] Figure 14 Schematic structural diagram of a semiconductor device provided by the embodiments of the present application. Detailed implementation manners

[0070] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0071] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0072] As Figure 1 shown, the embodiments of the present application provide a manufacturing method of a semiconductor device, the semiconductor device includes a substrate; the method includes:

[0073] Step S101, forming a plurality of first trenches extending in a first direction on the substrate;

[0074] Step S102, forming a plurality of second trenches extending in a second direction on the substrate formed with the first trenches; the first direction is perpendicular to the second direction; a first depth of the first trenches is greater than a second depth of the second trenches;

[0075] Step S103, forming a first isolation layer in the first trenches and the second trenches; in a cross-section in the second direction, there are first gaps between the first isolation layer and the side walls on both sides of the first trenches respectively; a depth of the first gaps is less than the first depth;

[0076] Step S104, depositing a conductive layer of a first conductive material at bottoms of the first gaps on both sides of the first trenches to form two mutually parallel bit lines extending in the first direction;

[0077] Step S105: Form word lines extending in the second direction on the conductive layer within the first trench and the second trench.

[0078] In the embodiment of the present application, trenches with patterns can be formed on the substrate surface by etching. Here, the first direction is the direction extending parallel to the substrate surface. Multiple first trenches can be formed in this direction, and these first trenches are parallel to each other. Exemplarily, the multiple first trenches are parallel to each other and can have equal spacing, depth, and width. Therefore, these first trenches can be formed synchronously by etching. Of course, the above etching can be single etching or multiple etching.

[0079] As Figure 2A shown, it is a top view after the first trenches are formed. Figure 2B 、 Figure 2C 、 Figure 2D and Figure 2E are respectively Figure 2A the cross-sectional views on the aa' section, bb' section, cc' section, and dd' section in , and multiple parallel first trenches 110 are formed on the substrate 100.

[0080] After the first trenches are formed, the method of etching can be used again to form second trenches perpendicular to the distribution of the first trenches. The extending direction of the second trenches is also parallel to the substrate surface but perpendicular to the first direction. In this way, a mesh structure can be formed on the substrate surface, that is, multiple first trenches and second trenches intersecting each other. The unetched areas form semiconductor columns perpendicular to the substrate surface, and these semiconductor columns can be used as the vertical channels of transistors, and then a transistor array can be formed.

[0081] In the embodiment of the present application, a first isolation layer is formed in the first trench and the second trench. The first isolation layer is composed of an insulating material, such as an oxide, a nitride, or other organic materials, etc. Since the first depth of the second trench is greater than the second depth of the second trench, the thickness of the first isolation layer in the first trench is different from that in the second trench.

[0082] There is a first gap between the first isolation layer in the first trench and the sidewalls on both sides of the first trench. For the relatively shallow second depth of the second trench, this first gap does not extend into the second trench. Then, a first conductive material of the substrate is formed at the bottom of the first gap. In this way, the conductive layer formed by the first conductive material will extend along the sidewalls on both sides of the first trench to form two bit lines. Each bottom of the first trench has two bit lines, thus forming a double-bit line structure of the semiconductor device. It should be noted that the first conductive material can be a metal material, a doped semiconductor material, or other conductive materials. For example, the first conductive material can be copper, tungsten, etc.

[0083] Since the first gap does not extend into the second trench, word lines can be formed on the conductive layer of the first trench and within the second trench. In fact, the word lines will extend along the second trench, i.e., along the second direction. However, since a portion of the material forming the word lines may be located within the first trench, it is necessary to form them within both the first trench and the second trench. Of course, adjacent word lines can be isolated from each other by an insulating material.

[0084] Thus, for semiconductor devices with vertical channels, embodiments of the present application provide a way to form buried word lines and bit lines within a substrate, and each transistor channel has a double-bit line structure, i.e., both sides have conductive layers formed by depositing a conductive material. In this way, on the one hand, compared with the bit lines formed by doping the semiconductor substrate, the bit lines formed by depositing the conductive material in the embodiments of the present application have higher conductivity, so the overall performance of the semiconductor device can be improved. On the other hand, by forming a parallel double-bit line structure within the first gaps on both sidewalls of the first trench, the integration degree of the semiconductor device can be improved, and the parasitic capacitance between the bit lines can be reduced.

[0085] In some embodiments, forming multiple second trenches extending in the second direction on the substrate having the first trench includes:

[0086] Covering the surface of the substrate with a first insulating material to form a first insulating layer; wherein, the first insulating layer covers the inner wall of the first trench;

[0087] Filling the first trench with a second insulating material to form a second insulating layer;

[0088] Forming the multiple second trenches extending in the second direction on the substrate.

[0089] In embodiments of the present application, after forming the first trench, a layer of first insulating material can be covered on the surface of the substrate by means of epitaxial growth or deposition, etc. For example, the above first insulating layer can be formed by means of chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), etc. Here, the first insulating material can be an oxide, a nitride, or other insulating materials, etc. The first insulating material can cover the entire inner wall of the first trench, including the bottom and sidewalls of the first trench. In addition, the area on the substrate surface outside the first trench will also be covered with the above first insulating material.

[0090] Figures 3A to 3CIt is a cross-sectional view covering the corresponding positions of the bb' cross-section, cc' cross-section, and dd' cross-section after covering the first insulating material; as Figures 3A to 3C shown, the surface of the entire substrate 100 and the inner surface of the first trench 110 are both covered with the first insulating material to form the first insulating layer 111.

[0091] Then, the second insulating material can be filled in the first trench so that all the first trenches are filled. Figures 4A to 4C It is a cross-sectional view covering the corresponding positions of the bb' cross-section, cc' cross-section, and dd' cross-section after filling the second insulating material, as Figures 4A to 4C shown, the second insulating layer 112 is filled on the first insulating layer 111 in the first trench. The second insulating material and the first insulating material are different insulating materials. For example, if the first insulating material is silicon nitride (SiN), the second insulating material can be silicon oxide (SiO). At this time, some planarization processes such as grinding can be performed to make the surface of the substrate and the surface of the second insulating material form a flat plane. The planarization process at this time can remove the first insulating material on the surface of the substrate or retain part of the first insulating material.

[0092] At this time, further etching can be performed on the above plane to form a plurality of second trenches extending in the second direction. It should be noted that the etching process needs to act on the silicon material of the substrate and the insulating material filled in the first trench synchronously, so that a complete second trench can be formed. Looking at the cross-section along the direction of the first trench, a plurality of adjacent concave regions are formed on the second insulating material in the first trench.

[0093] The cross-sectional views of the aa' cross-section, bb' cross-section, cc' cross-section, and dd' cross-section after forming the second trench 120 are as Figures 5A to 5D shown. Since the depth of the second trench 120 is less than that of the first trench 110, therefore, the shape of the bottom of the first trench 110 and the first insulating layers 111 and 112 can still be seen on the dd' cross-section along the second trench.

[0094] Of course, if the insulating material filled in the first trench is removed, the first trench and the second trench are two groups of straight trenches perpendicular to each other, and there is a common area at the intersection of each first trench and each second trench. Looking at the whole, the first trench and the second trench form a mesh structure, and the unetched substrate area is a semiconductor column perpendicular to the surface of the substrate.

[0095] In the application embodiment, the first depth of the first trench is greater than the second depth of the second trench. Therefore, after forming the second trench, a part of the first insulating layer and the second insulating layer extending in the first direction is still retained at the bottom of the first trench.

[0096] Thus, protected by the first insulating layer and the second insulating layer, the second trench can be formed after the first trench is formed, such that the first trench and the second trench have different depths, and the inner wall of the first trench will not be damaged during the formation of the second trench.

[0097] In some embodiments, forming the first isolation layer in the first trench and the second trench includes:

[0098] Filling the first insulating material in the second trench;

[0099] Simultaneously removing the first insulating material covering positions in the first trench and the second trench with a depth less than a third depth to form the first gap; wherein, the third depth is less than the first depth and greater than the second depth; the remaining first insulating layer and second insulating layer in the first trench and the second trench are the first isolation layer.

[0100] Here, the first isolation layer includes a structure composed of part of the first insulating material and part of the second insulating material, including the insulating material at the bottom of the first trench and the insulating material in the first trench that is not etched away when the second trench is formed.

[0101] There is a first gap between the first insulating material in the first trench and the sidewalls on both sides of the first trench. At least part of the first gap can be filled with a conductive material to form a conductive layer. Since the first gap extends along the sidewall of the first trench in a first direction, the conductive layer is a conductive wire covering at least part of the sidewall of the first trench and extending in the first direction. And since there are first gaps on both sides of the first trench, two conductive wires can be formed. In this way, for the transistor array in a semiconductor device, each column of transistors has two bit lines, that is, a buried double-bit line structure.

[0102] The buried double-bit line structure formed by depositing a conductive material in the first gap has a simple process and is beneficial to the design of high-integration semiconductor devices.

[0103] In some embodiments, after filling the first insulating material in the second trench, the method further includes:

[0104] Removing the first insulating material at a fourth depth to form a recessed area; the fourth depth is less than the second depth;

[0105] Covering the sidewall of the recessed area with the second insulating material to form a protective layer; wherein, the first gap formed after removing the first insulating material is located between the protective layer and the remaining first insulating layer in a direction perpendicular to the surface of the substrate.

[0106] After filling the first insulating material in the second trench, the first trench and the second trench are filled with insulating materials. The cross-sectional views of the aa’ cross-section, bb’ cross-section, cc’ cross-section, and dd’ cross-section after filling the first insulating material are as Figures 6A to 6D shown. As Figures 6C to 6D shown in [reference], the first insulating layer 111 covering the sidewall and the second insulating layer 112 filled in the first trench can be seen in the first trench 110. For Figure 6A and Figure 6B shown in [reference], the insulating layer 121 composed of the first insulating material is filled in the second trench 120.

[0107] Then, as Figures 7A to 7D shown, a recessed area 130 can be formed in the first trench 110 and the second trench 120 by etching back a part of the first insulating material. It should be noted that when removing the first insulating material here, it will not affect the second insulating material. Therefore, the second insulating material still remains flush with the top of the first trench, while a part of the first insulating material on the sidewall of the first trench is removed to form a recessed area with a fourth depth. Since the second trench is filled with the first insulating material, the overall depression in the second trench is the fourth depth.

[0108] After that, a layer of second insulating material is covered in the recessed area, so that the second insulating material in the first trench fills the first trench at the top. Figures 8A to 8C are the cross-sectional views of the aa’ cross-section, bb’ cross-section, and cc’ cross-section. The dd’ cross-section remains unchanged compared to Figure 7D shown in [reference], and a layer of second insulating material is formed on the inner wall of the recessed area 130 in the second trench 120. In this way, a protective layer 140 can be formed in the area at the top of the first trench 110 and the second trench 120. Among them, Figure 8B shown in the cross-section, the protective layer 140 is integrated with the second insulating material in the original first trench, so that the width of the recessed area 130 in this cross-section is reduced. The dd’ cross-section remains unchanged compared to Figure 7D shown in [reference], and can be referred to Figure 7D .

[0109] Exemplarily, a layer of silicon oxide can be grown in the recessed area by using the ALD method, and then etching back can be performed again to remove the silicon oxide at the bottom of the recessed area in the second trench, so that the first insulating material (such as silicon nitride) is exposed.

[0110] In this way, the top of the first trench is sealed by the second insulating material, while the surface of the first insulating material is exposed in the second trench, thus forming a protective layer. At this time, as Figures 9A to 9DAs shown, etching can be performed on the first insulating material while retaining the second insulating material. At this time, the top regions within the first trench 110 and the second trench 120 retain the above-mentioned protective layer 140, while the lower part is hollowed out, so that the above-mentioned first gap 150 can be formed in the part of the sidewall of the first trench 110 covered with the first insulating material.

[0111] In some embodiments, the step of simultaneously removing the first insulating material covering positions within the first trench and the second trench that are less than a third depth to form the first gap includes:

[0112] Using wet etching to remove the first insulating material to form the first gap.

[0113] The method of forming the above-mentioned first gap can use wet etching to clean the first insulating material, and the etching depth is less than the third depth. In this way, the first insulating material within the second trench will be removed, and at the same time, part of the first insulating material on both sides of the above-mentioned first isolation layer within the first trench will be removed, only retaining the first insulating layer at positions with a depth greater than the third depth at the bottom. Thus, a first gap is formed on the sidewall of the first trench.

[0114] In some embodiments, the first insulating material includes a silicon nitride material; the etching solution used for the wet etching includes a phosphoric acid solution.

[0115] When the above-mentioned first insulating material is a silicon nitride material, the phosphoric acid solution can corrode the first insulating material, thereby removing the first insulating material, but the phosphoric acid solution will not corrode oxides such as silicon oxide. Therefore, the second insulating material can be an oxide.

[0116] In some embodiments, the step of covering the surface of the substrate with the first insulating material to form the first insulating layer includes:

[0117] Using atomic layer deposition to deposit the first insulating material on the surface of the substrate to form the first insulating layer.

[0118] The first insulating layer formed by the ALD method has a uniform thickness. Therefore, the first gap formed after removing part of the first insulating material also has a uniform width.

[0119] In this way, depositing a conductive material in the first gap can form a uniform bit line, thereby reducing the impedance of the bit line and improving the conductive performance.

[0120] In some embodiments, after filling the second insulating material in the first trench to form the second insulating layer, the method further includes:

[0121] The second insulating layer and the first insulating layer on the substrate surface are planarized to expose the substrate surface in the regions other than the first trench and the second trench.

[0122] In the embodiment of the present application, after the insulating material is filled in the first trench to form the second insulating layer, some excess insulating material may cover the semiconductor pillar, thereby affecting the performance of the semiconductor device. Therefore, planarization can be performed by Chemical Mechanical Polishing (CMP).

[0123] In some embodiments, depositing a conductive layer of a first conductive material at the bottom of the first gap on both sides of the first trench to form two bit lines parallel to each other and extending along the first direction includes:

[0124] Filling the first conductive material in the first gap;

[0125] Removing part of the first conductive material in the first gap and retaining the first conductive material at the bottom of the first gap to form the bit line; wherein, the first conductive material at the bottom is the conductive layer.

[0126] Through the method in the above embodiments, a first gap can be formed between the first isolation layer and the sidewall of the first trench, and then the first conductive material can be filled in the first gap by a deposition method. For example, metal materials such as copper and tungsten, doped semiconductor materials or other conductive materials.

[0127] Figure 10A is a top view, Figure 10B and Figure 10C are cross-sectional views of the cc’ cross-section and the dd’ cross-section after the bit line is formed. The bit line formed by the conductive material cannot be seen in the aa’ cross-section and the bb’ cross-section, so there is no change, and reference can be made to Figure 9A and Figure 9B ; while the bit line 160 formed by the conductive material can be seen at the bottom of the first trench as shown in Figure 10B and Figure 10C .

[0128] Since the bit line extends along the direction of the first trench and the structure in the second trench is not affected by the bit line. Therefore, the bit line only needs to be formed in the part where the depth of the first trench is greater than that of the second trench. That is to say, the conductive layer to be formed for constituting the bit line can only cover a partial area at the bottom of the first trench, that is, a thin line can be formed. Therefore, part of the first conductive material in the first gap can be removed, and only the first conductive material at the bottom of the first gap is retained, thereby forming the bit line.

[0129] In some embodiments, forming a word line along the second direction on the conductive layer within the first trench and the second trench includes:

[0130] Removing the first isolation layer above the conductive layer within the first trench and the second trench to form a third trench;

[0131] Forming a second isolation layer at the bottom of the third trench; wherein the bottom of the second isolation layer is connected to the remaining first isolation layer between the two bit lines within the first trench, and the top of the second isolation layer is lower than the substrate surface in the area outside the first trench and the second trench;

[0132] Forming the word line within the third trench above the second isolation layer.

[0133] After forming the bit lines, the first trench is still filled with the above-mentioned first isolation layer and the protective layer. To form a word line along the direction of the second trench, part of the first isolation layer and the protective layer need to be removed so that a third trench is formed within the first trench and the second trench. Exemplarily, a part of the second insulating material remains at the bottom of the third trench and can serve as the second isolation layer.

[0134] In one embodiment, as Figures 11A to 11D shown, the second insulating material within the first trench and the second trench can be removed during the process of removing part of the first isolation layer, and then a layer of the first insulating material is covered again within the first trench 110 and the second trench 120 to cover the already formed bit lines, thereby forming the above-mentioned second isolation layer 170. To form the second isolation layer 170, the first insulating material can be filled to the top of the trench first, and then etched back by a certain depth as a whole. At this time, the remaining first insulating material is the above-mentioned second isolation layer. In one embodiment, all the insulating materials within the first trench and the second trench, including the first insulating material and the second insulating material, can also be removed, and then a kind of insulating material is filled again, which can be the first insulating material or the second insulating material, thereby forming the above-mentioned second isolation layer. Here, the first insulating material can be silicon oxide, and a layer of silicon oxide can also be covered on the sidewalls of the third trench, and this layer of silicon oxide can serve as the gate oxide layer.

[0135] In this way, the already formed bit lines are buried between the substrate and the insulating material and will not be exposed. At this time, the word line can be further formed within the third trench.

[0136] In some embodiments, forming the word line within the third trench above the second isolation layer includes:

[0137] Forming a gate oxide layer on the sidewalls of the first trench and the second trench on the second isolation layer;

[0138] A second conductive material is filled between the adjacent gate oxide layers to form a gate conductive layer;

[0139] Along the second direction, a fourth trench is formed on the second conductive material; wherein, the fourth trench separates the gate conductive layer in a cross-section in the first direction;

[0140] A first insulating material is filled in the fourth trench to form a third isolation layer; the gate conductive layers formed by the second conductive materials on both sides of the third isolation layer and connected to each other constitute the word line.

[0141] The word line is substantially formed by connecting gates surrounded by vertical channels formed by respective semiconductor columns in a straight line, and the gate includes a gate oxide layer and a gate conductive layer. Therefore, during the formation of the gate oxide layer, the gate oxide layer can be formed on the sidewalls of the regions within the first trench and within the second trench on the second isolation layer (i.e., the entire third trench), such that the gate oxide layer surrounds and covers the sidewalls of each semiconductor column.

[0142] The method for forming the gate oxide layer can deposit a layer of silicon oxide by using the above-mentioned ALD method, or the sidewalls of the semiconductor columns can be oxidized such that the sidewall surfaces of the semiconductor columns are oxidized into a uniform layer of silicon oxide.

[0143] Then, a second conductive material can be filled between the gate oxide layers, i.e., within the above-mentioned third trench after the sidewalls are covered with the gate oxide layer, to form a gate conductive layer. The second conductive material can be a metal material, such as metal copper, metal tungsten, etc. As Figures 12A to 12D shown, the gate conductive layer 181 made of a metal material is located between the gate oxide layer 182 and the above-mentioned second isolation layer 170. A second insulating material can also be further covered on the top of the gate conductive layer 201 to form a gate protection layer 183. In this way, the gate electrode is also buried inside the substrate and will not be exposed on the substrate surface.

[0144] In addition, since all the conductive materials deposited in the third trench are connected together, in order to form word lines extending along the second direction, a fourth trench also needs to be formed in the middle of the position where the second trench is located. As Figures 13A to 13D shown, the fourth trench 190 separates the conductive materials into a structure of multiple word lines 180 along the second direction. Then, an insulating material can be filled in the fourth trench 190. For example, through deposition methods such as CVD, ALD, or PVD, a third isolation layer 191 is formed. In Figure 13DAs shown in the dd' cross-section, when the third isolation layer 191 and the second isolation layer 170 are made of the same material, they are integrated. It should be noted that the third isolation layer can be the first insulating material or the second insulating material. If it is the second insulating material, the third isolation layer is integrated with the above-mentioned second isolation layer and the gate protection layer on the top.

[0145] In this way, the gate conductive layer between two adjacent third isolation layers forms a word line.

[0146] As Figure 14 shown ( Figure 14 including the cross-section along the first direction and the cross-section along the second direction), an embodiment of the present application provides a semiconductor device 200, including:

[0147] a substrate 201;

[0148] a plurality of first trenches 210 extending along the first direction and a plurality of second trenches 220 extending along the second direction on the substrate; wherein, the first direction is perpendicular to the second direction; the first depth of the first trench 210 is greater than the second depth of the second trench 220;

[0149] a first isolation layer 230 located in the first trench 210 and the second trench 220; in the cross-section along the second direction, the first isolation layer 230 has first gaps 240 with the side walls on both sides of the first trench 210 respectively; the depth of the first gap 240 is less than the first depth;

[0150] a conductive layer 250 of a first conductive material is deposited at the bottom of the first gaps 240 on both sides of the first trench, and the conductive layer forms two mutually parallel bit lines extending along the first direction;

[0151] a word line 260 extending along the second direction is provided on the first trench 210, the second trench 220 and the conductive layer 250.

[0152] In some embodiments, the first isolation layer includes:

[0153] a first insulating layer located at the bottom of the first trench and the second trench;

[0154] a second insulating layer located on the first insulating layer; the second insulating layer has the first gap with the side walls on both sides of the first trench.

[0155] In some embodiments, a second isolation layer is covered on the first isolation layer and the conductive layer in the first gap;

[0156] the word line extending along the second direction is provided on the second isolation layer.

[0157] In some embodiments, the semiconductor device further includes:

[0158] a gate oxide layer, located on the second isolation layer and covering the sidewalls of the first trench and the second trench;

[0159] the word line, including: a gate conductive layer located between adjacent gate oxide layers; the gate conductive layers are connected in the second direction;

[0160] a third isolation layer is provided between two adjacent word lines.

[0161] The structure of the above semiconductor device has been described in detail and exemplified in the embodiments of the forming method, and will not be elaborated here.

[0162] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics may be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the order of the above process numbers does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The serial numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0163] It should be noted that in this article, the term "comprising", "including" or any other variation thereof is intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the element.

[0164] In several embodiments provided by this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the displayed or discussed components can be through some interfaces. The indirect coupling or communication connection of devices or units can be electrical, mechanical, or other forms.

[0165] The units described above as separate components may or may not be physically separated. The components displayed as units may or may not be physical units. They can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0166] In addition, each functional unit in the embodiments of this application can be all integrated in a processing unit, or each unit can be separately used as a unit, or two or more units can be integrated in one unit. The above integrated units can be implemented in the form of hardware, or in the form of hardware plus software functional units.

[0167] The above is only the implementation mode of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device includes a substrate; the method includes: Forming a plurality of first trenches extending in a first direction on the substrate; Forming a plurality of second trenches extending in a second direction on the substrate on which the first trenches are formed; the first direction is perpendicular to the second direction; a first depth of the first trenches is greater than a second depth of the second trenches; Forming a first isolation layer in the first trenches and the second trenches; in a cross-section in the second direction, a first gap is respectively formed between the first isolation layer and side walls on both sides of the first trenches; a depth of the first gap is less than the first depth; Depositing a conductive layer of a first conductive material at bottoms of the first gaps on both sides of the first trenches to form two bit lines parallel to each other and extending in the first direction; Forming word lines extending in the second direction in the first trenches and the second trenches and on the conductive layer.

2. The method according to claim 1, wherein The forming a plurality of second trenches extending in the second direction on the substrate on which the first trenches are formed includes: Covering a first insulating material on a surface of the substrate to form a first insulating layer; wherein, the first insulating layer covers inner walls of the first trenches; Filling a second insulating material in the first trenches to form a second insulating layer; Forming the plurality of second trenches extending in the second direction on the substrate.

3. The method according to claim 2, wherein The forming a first isolation layer in the first trenches and the second trenches includes: Filling the first insulating material in the second trenches; Simultaneously removing the first insulating material covering positions in the first trenches and the second trenches with a depth less than a third depth to form the first gap; wherein, the third depth is less than the first depth and greater than the second depth; the remaining first insulating layer and the second insulating layer in the first trenches and the second trenches are the first isolation layer.

4. The method according to claim 3, characterized in that, After filling the first insulating material in the second trenches, the method further includes: Removing the first insulating material with a fourth depth to form a recessed area; the fourth depth is less than the second depth; Covering a second insulating material on side walls of the recessed area to form a protective layer; wherein, the first gap formed after removing the first insulating material is located between the protective layer and the remaining first insulating layer in a direction perpendicular to the surface of the substrate.

5. The method according to claim 3, characterized in that, The simultaneously removing the first insulating material covering positions in the first trenches and the second trenches with a depth less than a third depth to form the first gap includes: Removing the first insulating material by wet etching to form the first gap.

6. The method according to claim 5, wherein The first insulating material includes a silicon nitride material; an etching solution used for the wet etching includes a phosphoric acid solution.

7. The method according to claim 2, wherein The covering a first insulating material on a surface of the substrate to form a first insulating layer includes: Depositing the first insulating material on the surface of the substrate by atomic layer deposition to form the first insulating layer.

8. The method according to claim 2, wherein After filling a second insulating material in the first trenches to form a second insulating layer, the method further includes: The second insulating layer and the first insulating layer on the substrate surface are planarized to expose the substrate surface in areas other than the first trench and the second trench.

9. The method according to claim 1, wherein Depositing a conductive layer of a first conductive material at the bottom of the first gaps on both sides of the first trench to form two mutually parallel bit lines extending along the first direction, including: Filling the first conductive material in the first gaps; Removing a part of the first conductive material in the first gaps and retaining the first conductive material at the bottom of the first gaps to form the bit lines; wherein, the first conductive material at the bottom is the conductive layer.

10. The method according to claim 1, wherein Forming word lines along the second direction in the first trench and the second trench and on the conductive layer, including: Removing a part of the first isolation layer above the conductive layer in the first trench and the second trench to form a third trench; Forming a second isolation layer at the bottom of the third trench; wherein, the bottom of the second isolation layer is connected to the remaining first isolation layer between the two bit lines in the first trench, and the top of the second isolation layer is lower than the substrate surface in areas other than the first trench and the second trench; Forming the word lines in the third trench above the second isolation layer.

11. The method according to claim 10, characterized in that Forming the word lines in the third trench above the second isolation layer, including: Forming a gate oxide layer on the sidewalls of the first trench and the second trench on the second isolation layer; Filling a second conductive material between adjacent gate oxide layers to form a gate conductive layer; Forming a fourth trench along the second direction on the second conductive material; wherein, the fourth trench separates the gate conductive layer in the cross-section along the first direction; Filling a first insulating material in the fourth trench to form a third isolation layer; the gate conductive layers where the second conductive materials on both sides of the third isolation layer are connected form the word lines.

12. A semiconductor device, characterized in that, Including: A substrate; A plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction on the substrate; wherein, the first direction is perpendicular to the second direction; the first depth of the first trench is greater than the second depth of the second trench; A first isolation layer located in the first trench and the second trench; in the cross-section along the second direction, there are first gaps respectively between the first isolation layer and the sidewalls on both sides of the first trench; the depth of the first gaps is less than the first depth; A conductive layer of a first conductive material is deposited at the bottom of the first gaps on both sides of the first trench, and the conductive layer forms two mutually parallel bit lines extending along the first direction; Word lines extending along the second direction are provided in the first trench and the second trench and on the conductive layer.

13. The semiconductor device according to claim 12, wherein The first isolation layer includes: A first insulating layer located at the bottom of the first trench and the second trench; A second insulating layer located on the first insulating layer; there is the first gap between the second insulating layer and the sidewalls on both sides of the first trench.

14. The semiconductor device according to claim 13, wherein A second isolation layer is covered on the first isolation layer and the conductive layer in the first gaps; The word line extending in the second direction is provided on the second isolation layer.

15. The semiconductor device according to claim 14, wherein The semiconductor device further includes: a gate oxide layer, which is provided on the second isolation layer and covers the sidewalls of the first trench and the second trench; the word line, including: a gate conductive layer located between adjacent gate oxide layers; the gate conductive layers are connected in the second direction; a third isolation layer is provided between two adjacent word lines.

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