Fully isolated lateral double diffused semiconductor device and manufacturing method

Abstract

The present invention relates to the field of semiconductors and provides a fully isolated lateral double diffused semiconductor device and a manufacturing method. The fully isolated lateral double diffused semiconductor device includes a semiconductor substrate, a source body region, a drain drift region, a source, a drain, and a gate, and also includes: a first buried layer of the first type, a second buried layer, and a field oxygen isolation combination structure; the field oxygen isolation combination structure includes a shallow trench isolation structure and two LOCOS bird's beak structures that cover the wall corners on both sides of the shallow trench isolation structure; the drain drift region is connected to the first buried layer of the first type in the vertical direction, and the source body regions located on both sides of the drain drift region are connected to the first buried layer of the first type in the vertical direction to form a first isolation ring structure. The present invention adopts a field oxygen isolation combination structure that combines LOCOS and STI to improve the breakdown voltage of the device; the drain drift region is fully isolated by the first isolation ring structure to form a lateral conduction path and a vertical conduction path, thereby reducing the on-resistance and improving reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a fully isolated lateral double diffused semiconductor device and a method for manufacturing the fully isolated lateral double diffused semiconductor device. Background Art

[0002] LDMOS (Lateral Double-diffused MOSFET) devices are double-diffused power devices with high-voltage resistance, high-current drive capability, and extremely low power consumption. They are widely used in power management chips. Breakdown voltage (Vbv), specific on-resistance (Rsp), and reliability life are the three most important performance indicators of LDMOS devices, but there are conflicts and trade-offs between these three. To achieve a lower on-resistance (Rsp), it is difficult to increase the breakdown voltage (Vbv), and a lower Vbv also reduces reliability. Increasing Vbv improves reliability, but increases Rsp, resulting in lower switching speeds and increased power consumption, reducing overall performance. Therefore, LDMOS devices often cannot simultaneously meet the requirements of switching applications.

[0003] To address this common problem in LDMOS devices, existing technologies typically use shallow trench isolation (STI) field-based oxygen isolation technology to increase the breakdown voltage (Vbv). However, the longer STI sidewall path results in a higher on-resistance (Rsp). Furthermore, the higher charge density at the STI corners enhances hot carrier injection (HCI), reducing reliability and lifespan. Another existing technology uses local oxidation of silicon (LOCOS) field-based oxygen isolation technology to increase the breakdown voltage (Vbv), while leveraging the rounded shape of the LOCOS bird's beak to reduce HCI and Rsp. However, the LOCOS structure is less effective in increasing the breakdown voltage (Vbv) than the STI structure.

[0004] In summary, the existing technology has optimized and improved the breakdown voltage Vbv, on-resistance Rsp and reliability of LDMOS devices to a certain extent, but there are still certain limitations, and it is impossible to simultaneously increase the breakdown voltage and reduce the on-resistance. Summary of the Invention

[0005] The object of the present invention is to provide a fully isolated lateral double diffused semiconductor device and a manufacturing method thereof, so as to increase the breakdown voltage of the device and reduce the on-resistance at the same time.

[0006] In order to achieve the above-mentioned objectives, the present invention provides, on the one hand, a fully isolated lateral double-diffused semiconductor device, comprising a semiconductor substrate, a source body region, a drain drift region, a source, a drain and a gate, and also comprising: a first buried layer of the first type, a second buried layer and a field oxygen isolation combination structure; the field oxygen isolation combination structure comprises a shallow trench isolation structure and two LOCOS bird's beak structures respectively covering the wall corners on both sides of the shallow trench isolation structure; the drain drift region is vertically connected to the first buried layer of the first type, and the source body regions located on both sides of the drain drift region are vertically connected to the first buried layer of the first type to form a first isolation ring structure, and the first isolation ring structure is used to fully isolate the drain drift region, so that a lateral conduction path and a vertical conduction path are formed between the field oxygen isolation combination structure and the drain drift region.

[0007] In an embodiment of the present invention, a first-type well region is provided in a region of the source body region close to the source, and a second-type well region is provided in a region of the drain drift region close to the drain.

[0008] In an embodiment of the present invention, the fully isolated lateral double diffused semiconductor device further includes: a second type doped region located outside the source body region; the second type doped region and the second type buried layer are vertically connected to form a second isolation ring structure.

[0009] In an embodiment of the present invention, the second-type doping region includes a second-type first doping region and a second-type second doping region; the ion implantation depth of the second-type second doping region is less than the ion implantation depth of the second-type first doping region.

[0010] In an embodiment of the present invention, the fully isolated lateral double diffused semiconductor device further includes: a first type doped region located outside the second type doped region; the first type doped region is vertically connected to the semiconductor substrate through a first type second buried layer to form a third isolation ring structure.

[0011] In an embodiment of the present invention, the first type doping region includes a first type first doping region and a first type second doping region; the ion implantation depth of the first type second doping region is less than the ion implantation depth of the first type first doping region.

[0012] In an embodiment of the present invention, the semiconductor substrate is a P-type silicon substrate, the first type is P-type, and the second type is N-type; or the semiconductor substrate is an N-type silicon substrate, the first type is N-type, and the second type is P-type.

[0013] Another aspect of the present invention provides a method for manufacturing a fully isolated lateral double diffused semiconductor device, wherein the fully isolated lateral double diffused semiconductor device is the fully isolated lateral double diffused semiconductor device described above, the method comprising:

[0014] forming a second type buried layer and a first type buried layer in sequence on the semiconductor substrate, and forming an epitaxial layer on the first type buried layer;

[0015] Etching the epitaxial layer to form a shallow trench isolation structure and a LOCOS bird's beak structure;

[0016] forming a drain drift region, a source body region, a well region and an isolation ring structure in the epitaxial layer;

[0017] A gate, source, and drain are formed.

[0018] In an embodiment of the present invention, a second-type buried layer and a first-type buried layer are sequentially formed on a semiconductor substrate, and an epitaxial layer is formed on the first-type buried layer, including:

[0019] forming a second type buried layer and a first type second buried layer on the semiconductor substrate;

[0020] forming an epitaxial layer on the second type buried layer and the first type second buried layer;

[0021] A first buried layer of the first type is formed in a region of the epitaxial layer adjacent to the second buried layer.

[0022] In an embodiment of the present invention, the epitaxial layer is etched to form a shallow trench isolation structure and a LOCOS bird's beak structure, including: performing photolithography, etching and chemical mechanical polishing on the epitaxial layer to form the shallow trench isolation structure; performing photolithography, oxidation and etching on the areas near the sharp corners on both sides of the shallow trench isolation structure in the epitaxial layer to form the LOCOS bird's beak structure covering the wall corners on both sides of the shallow trench isolation structure.

[0023] In an embodiment of the present invention, a drain drift region, a source body region, a well region, and an isolation ring structure are formed in an epitaxial layer, including:

[0024] Performing photolithography and ion implantation on the epitaxial layer to form a drain drift region, a well region, and a source body region, so that the drain drift region is vertically connected to the first buried layer of the first type, and the source body region is vertically connected to the first buried layer of the first type, so as to form a first isolation ring structure;

[0025] Performing ion implantation on the area outside the source body region to form a second type first doped region vertically connected to the second type buried layer to form a second isolation ring structure;

[0026] Ion implantation is performed on the area outside the second type doping region to form a first type first doping region vertically connected to the first type second buried layer to form a third isolation ring structure.

[0027] In an embodiment of the present invention, a drain drift region, a source body region, a well region, and an isolation ring structure are formed in the epitaxial layer, further comprising:

[0028] Performing ion implantation in the first doping region of the second type to form a second doping region of the second type, wherein the ion implantation depth of the second doping region of the second type is less than the ion implantation depth of the first doping region of the second type;

[0029] Ion implantation is performed in the first doping region of the first type to form a second doping region of the first type, wherein the ion implantation depth of the second doping region of the first type is less than the ion implantation depth of the first doping region of the first type.

[0030] In an embodiment of the present invention, forming a source, a drain, and a gate includes:

[0031] forming a gate oxide layer and a gate structure between the source region and the drain region;

[0032] Ion implantation is performed in the source region and the drain region to form a source electrode and a drain electrode, and a first isolation ring output terminal, a second isolation ring output terminal and a third isolation ring output terminal are formed.

[0033] The present invention adopts a LOCOS+STI+LOCOS (LSL) field oxygen isolation structure that combines LOCOS and STI, greatly improving the breakdown voltage of the device. The LSL field oxygen isolation structure utilizes the smoothness of the LOCOS bird's beak structure to cover the LOCOS bird's beak structure at the sharp corners on both sides of the STI, which can effectively compensate for reliability issues caused by excessive charge density at the sharp corners of the STI. Moreover, the first isolation ring structure fully isolates the drain drift region, forming a lateral conduction path and a longitudinal conduction path between the field oxygen isolation structure and the drain drift region, which can compensate for the increased resistance caused by the LSL field oxygen isolation structure. The present invention reduces the on-resistance and improves reliability while increasing the breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present invention, but do not constitute a limitation of the embodiments of the present invention. In the accompanying drawings:

[0035] Figure 1 1 is a schematic structural diagram of a fully isolated NLDMOS device provided in Example 1 of the present invention;

[0036] Figure 2 1 is a schematic structural diagram of a fully isolated NLDMOS device provided in Embodiment 2 of the present invention;

[0037] Figure 3 1 is a schematic structural diagram of a fully isolated NLDMOS device provided in Embodiment 3 of the present invention;

[0038] Figure 4The present invention provides a flowchart of a method for manufacturing a fully isolated lateral double diffused semiconductor device.

[0039] Description of Reference Numerals

[0040] 101-P type silicon substrate, 102-N type buried layer, 103-P type first buried layer,

[0041] 104-N type drain drift region, 105-P type source body region, 106-N type well region,

[0042] 107-P-type well region, 108-shallow trench isolation structure, 109-LOCOS bird's beak structure,

[0043] 110 - gate, 111 - source, 112 - drain, 113 - first isolation ring output terminal,

[0044] 114- N-type first doping region, 115- N-type second doping region, 116- second isolation ring connection end,

[0045] 117- P-type first doping region, 118- P-type second doping region, 119- P-type second buried layer,

[0046] 120-The third isolation ring output terminal. DETAILED DESCRIPTION

[0047] The following describes the specific embodiments of the present invention in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention and are not intended to limit the present invention.

[0048] In the description herein, it should be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on this application. In this article, unless otherwise expressly specified and limited, terms such as "connected", "connected", and "connected" should be understood in a broad sense, for example, they can be directly connected, or indirectly connected through an intermediate medium, they can be internal connections between two structures or regions, or they can be interactions between two structures or regions. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0049] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0050] As described in the background technology, in the existing technology, the field oxygen isolation technology using STI can increase the breakdown voltage Vbv, but due to the long sidewall path of STI, the on-resistance Rsp is large. At the same time, due to the large charge density at the sharp corners of STI, the hot carrier injection effect (HCI) is enhanced, which reduces the reliability life; the field oxygen isolation technology using LOCOS can increase the breakdown voltage Vbv to a certain extent, and the smoothness of the LOCOS bird's beak can reduce HCI and Rsp, but the effect of the LOCOS structure on increasing the breakdown voltage Vbv is not significant compared with the STI structure.

[0051] In response to the defects existing in the prior art, the present invention provides a fully isolated lateral double diffused semiconductor device, comprising a semiconductor substrate, a source body region, a drain drift region, a source, a drain and a gate, and further comprising: a first buried layer of the first type, a second buried layer and a field oxygen isolation combination structure. The field oxygen isolation combination structure comprises a shallow trench isolation structure STI and two LOCOS bird's beak structures respectively covering the wall corners on both sides of the shallow trench isolation structure STI. The drain drift region is vertically connected to the first buried layer of the first type, and the source body regions located on both sides of the drain drift region are vertically connected to the first buried layer of the first type to form a first isolation ring structure. The first isolation ring structure is used to fully isolate the drain drift region, so that a lateral conduction path and a vertical conduction path are formed between the field oxygen isolation combination structure and the drain drift region, thereby reducing the on-resistance between the field oxygen isolation combination structure and the drain drift region. The present invention adopts a LOCOS+STI+LOCOS (LSL) field oxygen isolation structure that combines LOCOS and STI, greatly improving the breakdown voltage of the device. The LSL field oxygen isolation structure utilizes the smoothness of the LOCOS bird's beak structure to cover the LOCOS bird's beak structure at the sharp corners on both sides of the STI, which can effectively compensate for reliability issues caused by excessive charge density at the sharp corners of the STI. Moreover, the first isolation ring structure fully isolates the drain drift region, forming a lateral conduction path and a longitudinal conduction path between the field oxygen isolation structure and the drain drift region, which can compensate for the increased resistance caused by the LSL field oxygen isolation structure. The present invention reduces the on-resistance and improves reliability while increasing the breakdown voltage.

[0052] The aforementioned lateral double-diffused semiconductor devices include N-type LDMOS devices (NLDMOS for short) and P-type LDMOS devices (PLDMOS for short). In the above description, the first type and the second type refer to two carrier types: P-type (hole carriers) and N-type (electron carriers). In the aforementioned fully isolated lateral double-diffused semiconductor device, if the semiconductor substrate is a P-type silicon substrate, the first type is P-type and the second type is N-type, resulting in an NLDMOS semiconductor device. If the semiconductor substrate is an N-type silicon substrate, the first type is N-type and the second type is P-type, resulting in a PLDMOS semiconductor device. The following uses a fully isolated NLDMOS device as an example to illustrate the technical solution of the present invention.

[0053] Example 1

[0054] Figure 1 Schematic diagram of the structure of the fully isolated NLDMOS device provided by the first embodiment of the present invention. Figure 1 As shown, the fully isolated NLDMOS device provided in this embodiment includes a P-type silicon substrate 101, an N-type drain drift region 104, a P-type source body region 105, a gate 110, a source 111, and a drain 112. It also includes a field oxygen isolation structure, a P-type first buried layer 103, and an N-type buried layer 102. The field oxygen isolation structure includes a shallow trench isolation (STI) structure 108 and two LOCOS bird's beak structures 109 covering the corners of the shallow trench isolation structure. The N-type drain drift region 104 is vertically connected to the P-type first buried layer 103. The P-type source body regions 105 located on both sides of the N-type drain drift region 104 are vertically connected to the P-type first buried layer 103 to form a first isolation ring structure. The P-type source body region 105 is provided with a first isolation ring terminal 113 for connecting to a metal electrode. The first isolation ring structure fully isolates the N-type drain drift region 104, forming a lateral conduction path and a longitudinal conduction path between the field oxygen isolation structure and the N-type drain drift region 104. Since the LOCOS+STI+LOCOS field oxygen isolation structure increases the on-resistance between the field oxygen isolation structure and the N-type drain drift region 104, the first isolation ring structure fully encapsulates the N-type drain drift region 104 and the field oxygen isolation structure to achieve full isolation. The P-type first buried layer 103 pulls some carriers in the N-type drain drift region 104 downward in the vertical direction, forming a longitudinal conduction path. This makes the electric field in the N-type drain drift region 104 more uniform, thereby reducing the surface electric field and increasing the breakdown voltage. Simultaneously, the longitudinal conduction path reduces the resistance of the lateral conduction path, that is, reduces the on-resistance between the field oxygen isolation structure and the N-type drain drift region 104, thereby increasing the breakdown voltage while compensating for the increased on-resistance caused by the field oxygen isolation structure.

[0055] In this embodiment, an N-type well region 106 is provided in the region of the N-type drain drift region 104 near the drain 112. A P-type well region 107 is provided in the region of the P-type source body region 105 near the source 111. Because the N-type drain drift region 104 is vertically connected to the P-type first buried layer 103 and the longitudinal diffusion depth of the N-type drain drift region 104 is large, the N-type well region 106 is provided in the region near the drain 112 to ensure uniform longitudinal distribution of the N-type drain drift region 104. Based on the same principle, a P-type well region 107 is provided in the region near the source 111 to ensure uniform longitudinal distribution of the P-type source body region 105.

[0056] Example 2

[0057] Figure 2 Schematic diagram of the structure of the fully isolated NLDMOS device provided by the second embodiment of the present invention. Figure 2As shown, the fully isolated NLDMOS device provided in this embodiment includes a P-type silicon substrate 101, an N-type drain drift region 104, a P-type source body region 105, a gate 110, a source 111, and a drain 112. It also includes a field oxygen isolation structure, a P-type first buried layer 103, an N-type buried layer 102, and an N-type first doped region 114 located outside the P-type source body region 105. The field oxygen isolation structure includes a shallow trench isolation (STI) structure 108 and two LOCOS bird's beak structures 109 covering the corners of the STI structure. The N-type drain drift region 104 is vertically connected to the P-type first buried layer 103. The P-type source body regions 105 located on both sides of the N-type drain drift region 104 are vertically connected to the P-type first buried layer 103 to form a first isolation ring structure. The N-type first doped region 114 is vertically connected to the N-type buried layer 102 to form a second isolation ring structure. A first isolation ring terminal 113 for connecting to a metal electrode is provided on the P-type source body region 105, and a second isolation ring terminal 116 for connecting to a metal electrode is provided on the N-type first doped region 114. The first isolation ring structure fully isolates the N-type drain drift region 104, forming a lateral and vertical conductive path between the field oxygen isolation structure and the N-type drain drift region 104. Because the LOCOS+STI+LOCOS field oxygen isolation structure increases the on-resistance between the field oxygen isolation structure and the N-type drain drift region 104, the first isolation ring structure fully encapsulates the N-type drain drift region 104 and the field oxygen isolation structure to achieve full isolation. The P-type first buried layer 103 pulls a portion of the carriers in the N-type drain drift region 104 downward in the vertical direction, forming a vertical conduction path. This makes the electric field in the N-type drain drift region 104 more uniform, thereby reducing the surface electric field and increasing the breakdown voltage. At the same time, the vertical conduction path reduces the resistance of the lateral conduction path, that is, reduces the on-resistance between the field oxygen isolation structure and the N-type drain drift region 104. This improves the breakdown voltage while compensating for the increased on-resistance caused by the field oxygen isolation structure. The second isolation ring structure fully encapsulates the first isolation ring structure and the N-type drain drift region 104 and field oxygen isolation structure within it, enhancing the isolation effect and further reducing the on-resistance.

[0058] In this embodiment, an N-type second doping region 115 is disposed within the N-type first doping region 114. The ion implantation depth of the N-type second doping region 115 is less than the ion implantation depth of the N-type first doping region 114. Since the N-type first doping region 114 is vertically connected to the N-type buried layer 102, the longitudinal diffusion depth of the N-type first doping region 114 is large. The N-type second doping region 115 can compensate for the shallow diffusion area of ​​the N-type first doping region 114, thereby making the N-type first doping region 114 uniformly distributed in the longitudinal direction.

[0059] Example 3

[0060] Figure 3 Schematic diagram of the structure of the fully isolated NLDMOS device provided by the third embodiment of the present invention. Figure 3As shown, the fully isolated NLDMOS device provided in this embodiment includes a P-type silicon substrate 101, an N-type drain drift region 104, a P-type source body region 105, a gate 110, a source 111 and a drain 112, and also includes: a field oxygen isolation structure, a P-type first buried layer 103, an N-type buried layer 102, an N-type first doped region 114 located outside the P-type source body region 105, and a P-type first doped region 117 located outside the N-type first doped region 114. The field oxygen isolation structure includes a shallow trench isolation structure 108 (STI) and two LOCOS bird's beak structures 109 covering the corners of the shallow trench isolation structure on both sides; the N-type drain drift region 104 is vertically connected to the P-type first buried layer 103, and the P-type source body regions 105 located on both sides of the N-type drain drift region 104 are vertically connected to the P-type first buried layer 103 to form a first isolation ring structure. The N-type first doped region 114 is vertically connected to the N-type buried layer 102 to form a second isolation ring structure. The P-type first doped region 117 is vertically connected to the P-type silicon substrate 101 through the P-type second buried layer 119 to form a third isolation ring structure, wherein the P-type second buried layer 119 isolates the P-type first doped region 117 from the N-type buried layer 102. A first isolation ring terminal 113 for connecting to a metal electrode is provided on the P-type source body region 105, a second isolation ring terminal 116 for connecting to a metal electrode is provided on the N-type first doped region 114, and a third isolation ring terminal 120 for connecting to a metal electrode is provided on the P-type first doped region 117. The first isolation ring structure fully isolates the N-type drain drift region 104, forming a lateral and vertical conductive path between the field oxygen isolation structure and the N-type drain drift region 104. Because the LOCOS+STI+LOCOS field oxygen isolation structure increases the on-resistance between the field oxygen isolation structure and the N-type drain drift region 104, the first isolation ring structure fully encapsulates the N-type drain drift region 104 and the field oxygen isolation structure to achieve full isolation. The P-type first buried layer 103 pulls a portion of the carriers in the N-type drain drift region 104 downward in the vertical direction, forming a vertical conduction path. This makes the electric field in the N-type drain drift region 104 more uniform, thereby reducing the surface electric field and increasing the breakdown voltage. At the same time, the vertical conduction path reduces the resistance of the lateral conduction path, that is, reduces the on-resistance between the field oxygen isolation structure and the N-type drain drift region 104. This improves the breakdown voltage while compensating for the increased on-resistance caused by the field oxygen isolation structure. The second isolation ring structure fully encapsulates the first isolation ring structure and the N-type drain drift region 104 and field oxygen isolation structure within it, enhancing the isolation effect and further reducing the on-resistance. The third isolation ring structure completely covers the second isolation ring structure, further enhancing the isolation effect.

[0061] In this embodiment, an N-type second doping region 115 is disposed within the N-type first doping region 114. The ion implantation depth of the N-type second doping region 115 is less than the ion implantation depth of the N-type first doping region 114. Because the N-type first doping region 114 is vertically connected to the N-type buried layer 102, the N-type first doping region 114 has a large vertical diffusion depth. The N-type second doping region 115 can compensate for the shallow diffusion area of ​​the N-type first doping region 114, thereby ensuring a uniform distribution of the N-type first doping region 114 in the vertical direction. A P-type second doping region 118 is disposed within the P-type first doping region 117. The ion implantation depth of the P-type second doping region 118 is less than the ion implantation depth of the P-type first doping region 117. The P-type second doping region 118 can compensate for the shallow diffusion area of ​​the P-type first doping region 117, thereby ensuring a uniform distribution of the P-type first doping region in the vertical direction.

[0062] Figure 4 FIG. 1 is a flow chart of a method for manufacturing a fully isolated lateral double diffused semiconductor device according to an embodiment of the present invention. Figure 4 As shown, the method for manufacturing a fully isolated lateral double diffused semiconductor device provided by an embodiment of the present invention includes the following steps:

[0063] S410, forming a second type buried layer and a first type buried layer in sequence on a semiconductor substrate, and forming an epitaxial layer on the first type buried layer;

[0064] S420, etching the epitaxial layer to form a shallow trench isolation structure and a LOCOS bird's beak structure;

[0065] S430, forming a drain drift region, a source body region, a well region and an isolation ring structure in the epitaxial layer;

[0066] S440 , forming a gate, a source, and a drain.

[0067] In the above step S410, a second type buried layer and a first type second buried layer are formed on the semiconductor substrate, an epitaxial layer is formed on the second type buried layer and the first type second buried layer, and a first type first buried layer is formed in a region of the epitaxial layer close to the second type buried layer.

[0068] In the above step S420, the epitaxial layer is subjected to photolithography, etching and chemical mechanical polishing to form a shallow trench isolation structure, and the areas near the sharp corners on both sides of the shallow trench isolation structure in the epitaxial layer are subjected to photolithography, oxidation and etching to form a LOCOS bird's beak structure covering the wall corners on both sides of the shallow trench isolation structure.

[0069] In the above step S430, the epitaxial layer is subjected to photolithography and ion implantation to form a drain drift region, a well region and a source body region, so that the drain drift region is vertically connected to the first buried layer of the first type, and the source body region is vertically connected to the first buried layer of the first type, so as to form a first isolation ring structure; ion implantation is performed on the area outside the source body region to form a second type of first doped region vertically connected to the second type buried layer, so as to form a second isolation ring structure; ion implantation is performed on the area outside the second type of doped region to form a first type of first doped region vertically connected to the first type second buried layer, so as to form a third isolation ring structure.

[0070] Furthermore, ion implantation is performed in the first doping region of the second type to form a second doping region of the second type, wherein the ion implantation depth of the second doping region of the second type is less than the ion implantation depth of the first doping region of the second type; and ion implantation is performed in the first doping region of the first type to form a second doping region of the first type, wherein the ion implantation depth of the second doping region of the first type is less than the ion implantation depth of the first doping region of the first type.

[0071] In the above step S440, a gate oxide layer and a gate structure are formed between the source region and the drain region, ion implantation is performed in the source region and the drain region to form a source electrode and a drain electrode, and a first isolation ring terminal, a second isolation ring terminal and a third isolation ring terminal are formed.

[0072] In a typical example, a method for manufacturing a fully isolated NLDMOS device is provided to form the fully isolated NLDMOS device of the third embodiment. The method includes the following steps.

[0073] Step 1: Form an N-type buried layer and a P-type second buried layer on a P-type silicon substrate.

[0074] Step 2: forming an epitaxial layer on the N-type buried layer and the P-type second buried layer.

[0075] Step 3: performing photolithography, etching and chemical mechanical polishing on the epitaxial layer to form a shallow trench isolation structure.

[0076] Specifically, a groove is formed after photolithography on the epitaxial layer, a dielectric is filled in the groove and etched, and the filled dielectric is planarized by chemical mechanical polishing (CMP) to form a shallow trench isolation (STI) structure.

[0077] Step 4: Photolithography, oxidation, and etching are performed on the field oxygen region through a mask to form a LOCOS bird's beak structure. The shallow trench isolation structure STI and the LOCOS bird's beak structure form a field oxygen isolation combination structure of LOCOS+STI+LOCOS (LSL).

[0078] Step 5: Perform photolithography and ion implantation on the epitaxial layer to form an N-type drain drift region (Ndrift), an N-type well region (Nwell), a P-type source body region (Pbody), and a P-type well region (Pwell), as well as to form a first isolation ring structure, a second isolation ring structure, and a third isolation ring structure. The N-type well region and the P-type well region are implanted with N-type ions and P-type ions, respectively, and the order of their ion implantation can be interchanged; the N-type drain drift region and the P-type source body region are implanted with N-type ions and P-type ions, respectively, and the order of their ion implantation can be interchanged;

[0079] Step 6: Perform photolithography and P-type ion implantation under the N-type drain drift region and the P-type source body region through a mask to form a P-type first buried layer. The ion implantation depth of the P-type first buried layer is higher than the ion implantation depth of the N-type drain drift region, forming a complete isolation structure for the N-type drain drift region.

[0080] Step 7: forming a gate oxide layer and a gate structure between the source region and the drain region;

[0081] Step 8: N-type ions are injected into the source region, drain region and N-type isolation ring, and P-type ions are injected into the P-type source body region and P-type isolation ring to form an isolation ring terminal connected to the metal electrode.

[0082] In order to form a better field effect oxide layer combining LOCOS and STI (ie, a field oxygen isolation combined structure), the field effect oxide layer further includes oxide and nitride formed on the substrate, wherein the oxide is silicon dioxide and the nitride is silicon nitride.

[0083] According to the present invention, a fully isolated PLDMOS device can be manufactured using a process opposite to the aforementioned fully isolated NLDMOS device manufacturing method. Specifically, a buried layer and an epitaxial layer are first formed, followed by a drift region and a well region, and finally, an isolation structure is formed between the buried layer and the epitaxial layer. The type of ion source used in the ion implantation process is opposite to that used in the NLDMOS device.

[0084] Compared to the prior art, the manufacturing method for a fully isolated NLDMOS device and LDMOS power device provided by the present invention forms a LOCOS+STI+LOCOS (LSL) field oxygen isolation structure combining LOCOS and STI on a buried epitaxial layer, significantly improving the device's withstand voltage performance. The LSL field oxygen isolation structure leverages the smoothness of the LOCOS bird's beak and covers the left and right corners of the STI, effectively compensating for reliability issues caused by excessive charge density at the STI corners. Furthermore, the structural characteristics of the fully isolated device increase the longitudinal conductive path and overall reduce the on-resistance (Rsp). Furthermore, an N-type drain drift region, an N-type well region, a P-type source body region, a P-type well region, and a double-loop isolation ring structure are formed on the epitaxial layer. A P-type ion implantation region is formed below the N-type drain drift region and the P-type source body region to provide complete isolation from the N-type drain drift region. A gate oxide layer and gate structure are formed between the source and drain regions, resulting in a fully isolated LDMOS device. The present invention can significantly improve the performance of LDMOS in terms of breakdown voltage, on-resistance and reliability.

[0085] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0086] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A fully isolated lateral double diffused semiconductor device comprising a semiconductor substrate, a source body region, a drain drift region, a source, a drain and a gate, characterized in that: Also includes: A combined structure of a first buried layer of the first type, a second buried layer and field oxygen isolation; The field oxygen isolation composite structure includes a shallow trench isolation structure and two LOCOS bird's beak structures covering the corners on both sides of the shallow trench isolation structure, respectively. The two LOCOS bird's beak structures are independent of each other and cover the sharp corners of the corners on both sides of the shallow trench isolation structure. The smoothness of the LOCOS bird's beak structure is used to compensate for the excessive charge density at the sharp corners on both sides of the shallow trench isolation structure. The drain drift region is connected to the first buried layer of the first type in the vertical direction, and the source body regions located on both sides of the drain drift region are connected to the first buried layer of the first type in the vertical direction to form a first isolation ring structure. The first isolation ring structure is used to fully isolate the drain drift region, so that a lateral conduction path and a longitudinal conduction path are formed between the field oxygen isolation combination structure and the drain drift region to reduce the conduction resistance between the field oxygen isolation combination structure and the drain drift region.

2. The fully isolated lateral double diffused semiconductor device according to claim 1, characterized in that: A first-type well region is provided in a region of the source body region close to the source, and a second-type well region is provided in a region of the drain drift region close to the drain.

3. The fully isolated lateral double diffused semiconductor device according to claim 1, wherein: Also included: a second type doped region located outside the source body region; The second type doping region and the second type buried layer are connected in a vertical direction to form a second isolation ring structure.

4. The fully isolated lateral double diffused semiconductor device according to claim 3, characterized in that: The second type doping region includes a first doping region of a second type and a second doping region of a second type; The ion implantation depth of the second type second doping region is less than the ion implantation depth of the first type second doping region.

5. The fully isolated lateral double diffused semiconductor device according to claim 3, characterized in that: Also included: a first type doping region located outside the second type doping region; The first type doping region is vertically connected to the semiconductor substrate through the first type second buried layer to form a third isolation ring structure.

6. The fully isolated lateral double diffused semiconductor device according to claim 5, characterized in that: The first type doping region includes a first doping region of the first type and a second doping region of the first type; The ion implantation depth of the second first-type doping region is less than the ion implantation depth of the first first-type doping region.

7. The fully isolated lateral double diffused semiconductor device according to any one of claims 1 to 6, characterized in that: The semiconductor substrate is a P-type silicon substrate, the first type is P-type, and the second type is N-type; or the semiconductor substrate is an N-type silicon substrate, the first type is N-type, and the second type is P-type.

8. A method for manufacturing a fully isolated lateral double diffused semiconductor device, wherein the fully isolated lateral double diffused semiconductor device is the fully isolated lateral double diffused semiconductor device according to claim 1, characterized in that: The method comprises: forming a second type buried layer and a first type buried layer in sequence on the semiconductor substrate, and forming an epitaxial layer on the first type buried layer; Etching the epitaxial layer to form a shallow trench isolation structure and a LOCOS bird's beak structure; forming a drain drift region, a source body region, a well region and an isolation ring structure in the epitaxial layer; A gate, source, and drain are formed.

9. The method for manufacturing a fully isolated lateral double diffused semiconductor device according to claim 8, wherein: The method comprises the following steps: forming a second type buried layer and a first type buried layer in sequence on a semiconductor substrate, and forming an epitaxial layer on the first type buried layer. forming a second type buried layer and a first type second buried layer on the semiconductor substrate; forming an epitaxial layer on the second type buried layer and the first type second buried layer; A first buried layer of the first type is formed in a region of the epitaxial layer adjacent to the second buried layer.

10. The method for manufacturing a fully isolated lateral double diffused semiconductor device according to claim 9, wherein: The epitaxial layer is etched to form a shallow trench isolation structure and a LOCOS bird's beak structure, including: Performing photolithography, etching and chemical mechanical polishing on the epitaxial layer to form a shallow trench isolation structure; The regions near the sharp corners on both sides of the shallow trench isolation structure in the epitaxial layer are subjected to photolithography, oxidation and etching processes to form a LOCOS bird's beak structure covering the corners on both sides of the shallow trench isolation structure.

11. The method for manufacturing a fully isolated lateral double diffused semiconductor device according to claim 9, wherein: A drain drift region, a source body region, a well region, and an isolation ring structure are formed in the epitaxial layer, including: Performing photolithography and ion implantation on the epitaxial layer to form a drain drift region, a well region, and a source body region, so that the drain drift region is vertically connected to the first buried layer of the first type, and the source body region is vertically connected to the first buried layer of the first type, so as to form a first isolation ring structure; Performing ion implantation on the area outside the source body region to form a second type first doped region vertically connected to the second type buried layer to form a second isolation ring structure; Ion implantation is performed on the area outside the second type doping region to form a first type first doping region vertically connected to the first type second buried layer to form a third isolation ring structure.

12. The method for manufacturing a fully isolated lateral double diffused semiconductor device according to claim 11, wherein: A drain drift region, a source body region, a well region and an isolation ring structure are formed in the epitaxial layer, and further comprising: Performing ion implantation in the first doping region of the second type to form a second doping region of the second type, wherein the ion implantation depth of the second doping region of the second type is less than the ion implantation depth of the first doping region of the second type; Ion implantation is performed in the first doping region of the first type to form a second doping region of the first type, wherein the ion implantation depth of the second doping region of the first type is less than the ion implantation depth of the first doping region of the first type.

13. The method for manufacturing a fully isolated lateral double diffused semiconductor device according to claim 11, wherein: Forming the source, drain, and gate, including: forming a gate oxide layer and a gate structure between the source region and the drain region; Ion implantation is performed in the source region and the drain region to form a source electrode and a drain electrode, and a first isolation ring output terminal, a second isolation ring output terminal and a third isolation ring output terminal are formed.

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