Parameter adjustment method and device of parallel device and target circuit
By setting a capacitor compensation unit between the controlled end and the conducting end of a semiconductor device, the parasitic capacitance value is obtained and compensated to make them equal, thus solving the problem of switching speed mismatch of parallel semiconductor devices, simplifying the circuit structure and expanding the applicable scenarios.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SIRIUS CORE SEMICON (CHENGDU) CO LTD
- Filing Date
- 2022-05-24
- Publication Date
- 2026-05-19
AI Technical Summary
The different gate capacitances of parallel connected semiconductor devices can lead to a mismatch in switching speeds, resulting in excessive power consumption or oscillating current.
By setting a capacitor compensation unit between the controlled terminal and the on terminal of each semiconductor device, the parasitic capacitance value of each semiconductor device is obtained, the target capacitance value is determined, and capacitance compensation is performed through the capacitor compensation unit to make the total parasitic capacitance value of each semiconductor device equal.
It solves the problem of mismatch in switching speed characteristics between semiconductor devices, simplifies the circuit structure, reduces the size, and expands the applicable scenarios of high-current semiconductor devices.
Smart Images
Figure CN115940596B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a method, device and target circuit for adjusting the parameters of parallel devices. Background Technology
[0002] In the field of electronic circuits, high-current semiconductor devices are frequently required. Due to manufacturing cost considerations, in practical applications, several semiconductor devices are often connected in parallel to obtain a high-current semiconductor device. However, since the gate capacitances of different semiconductor devices are usually different, this can lead to a mismatch in the switching speed characteristics between different semiconductors. Consequently, the high-current semiconductor device obtained by connecting them in parallel may suffer from problems such as excessive switching power consumption or the generation of oscillating current.
[0003] To address the aforementioned issues, two common solutions are currently employed: one is to use a driver circuit to compensate for the capacitance of each parallel-connected semiconductor device. However, the design of the driver circuit is often complex, increasing the overall size of the high-current semiconductor device. The other solution is to use devices from the same batch of production for all parallel-connected semiconductor devices. However, even devices from the same batch may have performance differences, and the requirement to use devices from the same batch limits the applicable scenarios for high-current semiconductor devices. Summary of the Invention
[0004] In view of this, embodiments of the present invention provide a parameter adjustment method, apparatus and target circuit for parallel devices to solve the problem of mismatched switching speeds of existing parallel semiconductor devices, which leads to excessive switching power consumption or oscillating current in the high-current semiconductor devices obtained by parallel connection.
[0005] In a first aspect, embodiments of this application provide a parameter adjustment method for parallel devices, applied to a target circuit, the target circuit including multiple semiconductor devices connected in parallel; the target circuit also includes multiple capacitor compensation units, each capacitor compensation unit being connected between a controlled terminal and a conducting terminal of one of the semiconductor devices; the parameter adjustment method for the parallel devices includes:
[0006] Obtain the parasitic capacitance value between the controlled terminal and the on terminal of each of the semiconductor devices;
[0007] A target capacitance value is determined based on all the parasitic capacitance values; the target capacitance value is greater than or equal to the maximum value among all the parasitic capacitance values.
[0008] The difference between the parasitic capacitance value of the semiconductor device and the target capacitance value is determined as the compensation capacitance value of the semiconductor device.
[0009] The control unit performs capacitance compensation on the parasitic capacitance of the connected semiconductor device based on the compensation capacitance value of the connected semiconductor device.
[0010] In one optional implementation of the first aspect, the capacitor compensation unit includes a plurality of compensation capacitors, each of which is disposed between the controlled terminal and the on terminal of the corresponding semiconductor device using antifuse technology.
[0011] The control of the capacitance compensation unit to perform capacitance compensation on the parasitic capacitance value of the connected semiconductor device based on the compensation capacitance value of the connected semiconductor device includes:
[0012] The target compensation capacitor to be compensated is determined from the plurality of compensation capacitors based on the compensation capacitor values of the semiconductor devices connected to the capacitor compensation unit and the capacitance values of each compensation capacitor.
[0013] The capacitor compensation unit is controlled to melt the target compensation capacitor, thereby connecting the target compensation capacitor between the controlled terminal and the on terminal of the corresponding semiconductor device.
[0014] In one alternative implementation of the first aspect, all the compensation capacitors in the capacitor compensation unit have the same capacitance value;
[0015] The step of determining the target compensation capacitor to be compensated from the plurality of compensation capacitors based on the compensation capacitance value of the semiconductor device connected to the capacitor compensation unit and the capacitance value of each of the compensation capacitors includes:
[0016] Calculate the ratio of the compensation capacitance value of the semiconductor connected to the capacitor compensation unit to the capacitance value of the compensation capacitor;
[0017] The integer part of the ratio is determined as the number of target compensation capacitors to be compensated;
[0018] Any number of the plurality of compensation capacitors shall be determined as the target compensation capacitor.
[0019] In one alternative implementation of the first aspect, the target circuit further includes a plurality of capacitance measurement units, each of which is connected to one of the semiconductor devices by means of a wire; the capacitance measurement unit is used to measure the actual capacitance value of the corresponding semiconductor device;
[0020] The step of obtaining the parasitic capacitance value between the controlled terminal and the on terminal of each of the semiconductor devices includes:
[0021] For each of the semiconductor devices, the actual capacitance value between the controlled terminal and the on terminal of the semiconductor device is obtained from the capacitance measurement unit connected to the semiconductor device;
[0022] Obtain the equivalent capacitance value of the semiconductor device and the corresponding winding formed by the capacitor;
[0023] The sum of the actual capacitance value and the equivalent capacitance value is determined as the parasitic capacitance value between the controlled terminal and the on terminal of the semiconductor device.
[0024] In one alternative implementation of the first aspect, the number of semiconductor devices included in the target circuit is equal to the number of capacitor compensation units; each capacitor compensation unit is connected between a controlled terminal and a first conducting terminal of a semiconductor device, or each capacitor compensation unit is connected between a controlled terminal and a second conducting terminal of a semiconductor device.
[0025] In one optional implementation of the first aspect, the number of capacitor compensation units included in the target circuit is twice the number of semiconductor devices; a capacitor compensation unit is connected between the controlled terminal and the first conducting terminal of each semiconductor device, and a capacitor compensation unit is connected between the controlled terminal and the second conducting terminal of each semiconductor device.
[0026] Secondly, embodiments of this application provide a parameter adjustment device for parallel devices, applied to a target circuit, the target circuit including multiple semiconductor devices connected in parallel; the target circuit also includes multiple capacitor compensation units, each capacitor compensation unit being connected between a controlled terminal and a conducting terminal of one of the semiconductor devices; the parameter adjustment device for the parallel devices includes:
[0027] The first acquisition unit is used to acquire the parasitic capacitance value between the controlled terminal and the on terminal of each of the semiconductor devices;
[0028] The first determining unit is configured to determine a target capacitance value based on all the parasitic capacitance values; the target capacitance value is greater than or equal to the maximum value among all the parasitic capacitance values.
[0029] The second determining unit is used to determine the difference between the parasitic capacitance value of the semiconductor device and the target capacitance value as the compensation capacitance value of the semiconductor device.
[0030] The control unit is used to control the capacitor compensation unit to perform capacitor compensation on the parasitic capacitance value of the connected semiconductor device based on the compensation capacitance value of the connected semiconductor device.
[0031] In one optional implementation of the second aspect, the capacitor compensation unit includes multiple compensation capacitors, each of which is disposed between the controlled terminal and the on terminal of the corresponding semiconductor device using antifuse technology; the control unit is specifically used for:
[0032] The target compensation capacitor to be compensated is determined from the plurality of compensation capacitors based on the compensation capacitor values of the semiconductor devices connected to the capacitor compensation unit and the capacitance values of each compensation capacitor.
[0033] The capacitor compensation unit is controlled to melt the target compensation capacitor, thereby connecting the target compensation capacitor between the controlled terminal and the on terminal of the corresponding semiconductor device.
[0034] In an alternative implementation of the second aspect, the target circuit further includes a plurality of capacitance measurement units, each of which is connected to one of the semiconductor devices by means of a wire; the capacitance measurement unit is used to measure the actual capacitance value of the corresponding semiconductor device;
[0035] The first acquisition unit is specifically used for:
[0036] For each of the semiconductor devices, the actual capacitance value of the semiconductor device is obtained from the capacitance measurement unit connected to the semiconductor device;
[0037] Obtain the equivalent capacitance value formed by the semiconductor device and the winding used to connect the semiconductor device;
[0038] The parasitic capacitance value of the semiconductor device is determined by summing the actual capacitance value of the semiconductor device with the corresponding equivalent capacitance value.
[0039] Thirdly, embodiments of this application provide a target circuit for realizing a high-current device, the target circuit including a plurality of semiconductor devices connected in parallel; the target circuit further includes a plurality of capacitor compensation units and a parameter adjustment device; each of the capacitor compensation units is connected between a controlled terminal and a conducting terminal of one of the semiconductor devices, and the parameter adjustment device is used to perform the parameter adjustment method for parallel devices as described in the first aspect or any optional method of the first aspect.
[0040] The parameter adjustment method, apparatus, and target circuit for parallel devices provided in the embodiments of this application have the following beneficial effects:
[0041] The parameter adjustment method for parallel devices provided in this application is applied to a target circuit. The target circuit includes multiple semiconductor devices connected in parallel, as well as multiple capacitor compensation units. Each capacitor compensation unit is connected between the controlled terminal and the on terminal of a semiconductor device. Based on this, the parasitic capacitance value between the on terminal and the controlled terminal of each semiconductor device is obtained, and a target capacitance value is determined based on all parasitic capacitance values. Since the target capacitance value is greater than or equal to the maximum value among all parasitic capacitance values, the difference between the parasitic capacitance value of the semiconductor device and the target capacitance value is determined as the compensation capacitance value. The capacitor compensation unit is controlled to perform capacitance compensation on the parasitic capacitance value of the connected semiconductor device based on the compensation capacitance value of the connected semiconductor device. This makes the total parasitic capacitance value of each semiconductor device equal, i.e., equal to the target capacitance value, thereby solving the problem of mismatched switching speed characteristics among multiple semiconductor devices connected in parallel. Furthermore, since only one capacitor compensation unit needs to be set between the controlled terminal and the on terminal of each semiconductor device to compensate for the parasitic capacitance value of each semiconductor device, the structure of the target circuit is relatively simple and the size of the target circuit is reduced. Moreover, regardless of the performance of each semiconductor device, the total parasitic capacitance value of all semiconductor devices can be made equal by the above method. Therefore, it is less affected by the performance of the semiconductor devices themselves. That is, semiconductor devices with arbitrary performance can be used to realize high-current semiconductor devices, thereby expanding the applicable scenarios of high-current semiconductor devices. Attached Figure Description
[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0043] Figure 1 This application provides a schematic diagram of the structure of a target circuit for implementing a high-current device.
[0044] Figure 2 A schematic flowchart illustrating a parameter adjustment method provided in an embodiment of this application;
[0045] Figure 3 This is a schematic diagram illustrating the specific implementation process of S24 in a parameter adjustment method of this application;
[0046] Figure 4 This is a schematic diagram of a parameter adjustment device provided in an embodiment of this application. Detailed Implementation
[0047] It should be noted that the terminology used in the embodiments of this application is only for explaining specific embodiments of this application and is not intended to limit this application. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, "at least one" or "one or more" means one, two or more. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
[0048] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0049] This application first provides a target circuit for implementing a high-current device. Please refer to... Figure 1 , Figure 1 This application provides a circuit diagram for implementing a target circuit of a high-current device. (See diagram below.) Figure 1 As shown, the target circuit may include multiple semiconductor devices 11, multiple capacitor compensation units 12, and parameter adjustment device 13 connected in parallel.
[0050] Each capacitor compensation unit 12 is connected between the controlled terminal and the on terminal of a semiconductor device 11. All capacitor compensation units 12 are connected to a parameter adjustment device 13, which controls each capacitor compensation unit 12.
[0051] In one embodiment of this application, the number of capacitor compensation units 12 is equal to the number of semiconductor devices 11. Based on this, each capacitor compensation unit 12 can be connected between the controlled terminal and the first conducting terminal of a semiconductor device 11; or, each compensation unit 12 can be connected between the controlled terminal and the second conducting terminal of a semiconductor device 11.
[0052] In another embodiment of this application, the number of capacitor compensation units 12 is twice the number of semiconductor devices 11. Based on this, a capacitor compensation unit 12 is connected between the controlled terminal and the first conducting terminal of each semiconductor device 11, and a capacitor compensation unit 12 is also connected between the controlled terminal and the second conducting terminal of each semiconductor device 11.
[0053] In one embodiment of this application, the capacitor compensation unit 12 may include multiple compensation capacitors C1, each of which is disposed between the controlled terminal and the conductive terminal of the corresponding semiconductor device 11 using anti-fuse technology. Based on this, the parameter adjustment device 13 can be connected to each compensation capacitor C1 in each capacitor compensation unit 12 to achieve fuse control of each compensation capacitor C1. Specifically, when a compensation capacitor C1 is fused, its two ends are connected to the controlled terminal and the conductive terminal of the semiconductor device 11, respectively; that is, the compensation capacitor C1 is connected between the controlled terminal and the conductive terminal of the corresponding semiconductor device 11.
[0054] In one possible implementation, the capacitance values of all compensation capacitors C1 in the capacitor compensation unit 12 are equal. The specific capacitance value of the compensation capacitor C1 can be set according to actual needs, and is not specifically limited here.
[0055] In specific applications, the semiconductor device 11 can be an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a bipolar junction transistor (BJT), etc. The embodiments of this application do not particularly limit the type of semiconductor device.
[0056] Taking the semiconductor device 11 as a MOSFET as an example, the gate of the MOSFET can be the controlled terminal of the semiconductor device 11, the source of the MOSFET can be the first conducting terminal of the semiconductor device 11, and the drain of the MOSFET can be the second conducting terminal of the semiconductor device 11.
[0057] In another embodiment of this application, the target circuit further includes multiple capacitance measurement units (not shown), each of which is connected to a semiconductor device 11 by a wire, and all capacitance measurement units are connected to a parameter adjustment device 13 (not shown). The capacitance measurement unit 14 is used to measure the actual capacitance value between the controlled terminal and the on terminal of the semiconductor device 11 to which it is connected, and transmits the measured actual capacitance value to the parameter adjustment device 13.
[0058] It should be noted that since the capacitance measurement unit is connected between the controlled terminal and the conductive terminal of the semiconductor device 11 by a wire, the wire will inevitably form a capacitance with the connected semiconductor device 11. The equivalent capacitance value of the capacitance formed by the wire and the connected semiconductor device 11 can be obtained through pre-testing. This equivalent capacitance value can be pre-stored in the parameter adjustment device 13.
[0059] It should be noted that the specific structure and function of the parameter adjustment device 13 can be referred to the relevant description in the subsequent parameter adjustment device embodiments, and will not be repeated here.
[0060] Based on the target circuit provided in the above embodiments, this application also provides a parameter adjustment method for parallel devices applied to the target circuit, which is used to adjust the parasitic capacitance values of multiple parallel-connected semiconductor devices so that the switching speed characteristics of the multiple parallel-connected semiconductor devices are matched.
[0061] This application provides a method for adjusting the parameters of a parallel device, the execution subject of which can be... Figure 1 The parameter adjustment device 13 in the corresponding embodiment. In specific applications, a target script file can be configured on the parameter adjustment device 13, which describes the parameter adjustment method for parallel devices provided in the embodiments of this application. The parameter adjustment device 13 executes the target script file when it is necessary to match the switching speed characteristics of multiple parallel semiconductor devices, thereby executing the various steps in the parameter adjustment method provided in the embodiments of this application.
[0062] Please see Figure 2 , Figure 2 This is a schematic flowchart illustrating a parameter adjustment method provided in an embodiment of this application. Figure 2 As shown, the parameter adjustment method may include S21 to S24, which are detailed below:
[0063] S21: Obtain the parasitic capacitance value between the controlled terminal and the on terminal of each of the semiconductor devices.
[0064] In one embodiment of this application, when the capacitance compensation unit is connected between the controlled terminal and the first conducting terminal of the semiconductor device, i.e., when the capacitance compensation unit is only provided between the controlled terminal and the first conducting terminal of the semiconductor device, the parameter adjustment device can obtain the parasitic capacitance value between the controlled terminal and the first conducting terminal of the semiconductor device. In this embodiment, the parasitic capacitance value can be the total parasitic capacitance value between the controlled terminal and the first conducting terminal of the semiconductor device, including the actual capacitance value between the controlled terminal and the first conducting terminal of the semiconductor device and the equivalent capacitance value of the capacitance generated by the winding used to connect the capacitance measurement unit.
[0065] Based on this, S21 may specifically include the following steps:
[0066] For each semiconductor device, the actual capacitance value between the controlled terminal and the first conducting terminal of the semiconductor device is obtained from the capacitance measurement unit connected to the semiconductor device.
[0067] Obtain the equivalent capacitance value of the capacitor formed by the semiconductor device and the corresponding winding.
[0068] The sum of the actual capacitance value of the semiconductor device and the corresponding equivalent capacitance value is determined as the parasitic capacitance value between the controlled terminal and the first conducting terminal of the semiconductor device.
[0069] In another embodiment of this application, when the capacitance compensation unit is connected between the controlled terminal and the second conductive terminal of the semiconductor device, i.e., when the capacitance compensation unit is only provided between the controlled terminal and the second conductive terminal of the semiconductor device, the parameter adjustment device can obtain the parasitic capacitance value between the controlled terminal and the second conductive terminal of the semiconductor device. In this embodiment, the parasitic capacitance value can be the total parasitic capacitance value between the controlled terminal and the second conductive terminal of the semiconductor device, including the actual capacitance value between the controlled terminal and the second conductive terminal of the semiconductor device and the equivalent capacitance value of the capacitance generated by the winding used to connect the capacitance measurement unit.
[0070] Based on this, S21 may specifically include the following steps:
[0071] For each semiconductor device, the actual capacitance value between the controlled terminal and the second on terminal of the semiconductor device is obtained from the capacitance measurement unit connected to the semiconductor device.
[0072] Obtain the equivalent capacitance value of the capacitor formed by the semiconductor device and the corresponding winding.
[0073] The sum of the actual capacitance value of the semiconductor device and the corresponding equivalent capacitance value is determined as the parasitic capacitance value between the controlled terminal and the second conducting terminal of the semiconductor device.
[0074] In this embodiment, the winding corresponding to the semiconductor device refers to the winding used to connect the semiconductor device and the capacitance measurement unit. For example, if the first capacitance measurement unit is connected to the first semiconductor device using a first winding, then the winding corresponding to the first semiconductor device is the first winding.
[0075] The above scheme, in determining the parasitic capacitance value between the controlled and on terminals of the semiconductor device, considers not only the actual capacitance value between the controlled and on terminals of the semiconductor device, but also the equivalent capacitance value formed by the winding used to connect the capacitance measurement unit and the semiconductor device. Therefore, the obtained parasitic capacitance value between the controlled and on terminals of the semiconductor device is more accurate, providing an accurate basis for subsequently determining the compensation capacitance value of each semiconductor device, and making the switching speed characteristics of each semiconductor device after capacitance compensation more matched.
[0076] S22: Determine the target capacitance value based on all parasitic capacitance values.
[0077] In this embodiment of the application, the target capacitance value is greater than or equal to the maximum value among all parasitic capacitance values.
[0078] In one embodiment of this application, when the capacitor compensation unit is connected between the controlled terminal and the first conducting terminal of the semiconductor device, that is, when the capacitor compensation unit is only provided between the controlled terminal and the first conducting terminal of the semiconductor device, after the parameter adjustment device obtains the parasitic capacitance value between the controlled terminal and the first conducting terminal of the semiconductor device, it can compare the parasitic capacitance values between the controlled terminals and the first conducting terminals of all semiconductor devices, thereby determining the maximum value among the parasitic capacitance values between the controlled terminals and the first conducting terminals of all semiconductor devices.
[0079] Optionally, after the parameter adjustment device determines the maximum value among the parasitic capacitance values between the controlled terminal and the first conducting terminal of all semiconductor devices, the maximum value can be determined as the target capacitance value.
[0080] Optionally, after the parameter adjustment device determines the maximum value among the parasitic capacitance values between the controlled terminal and the first conducting terminal of all semiconductor devices, any capacitance value greater than that maximum value can be determined as the target capacitance value.
[0081] In another embodiment of this application, when the capacitor compensation unit is connected between the controlled terminal and the second conducting terminal of the semiconductor device, that is, when the capacitor compensation unit is only provided between the controlled terminal and the second conducting terminal of the semiconductor device, after the parameter adjustment device obtains the parasitic capacitance value between the controlled terminal and the second conducting terminal of the semiconductor device, it can compare the parasitic capacitance values between the controlled terminal and the second conducting terminal of all semiconductor devices, thereby determining the maximum value among the parasitic capacitance values between the controlled terminal and the second conducting terminal of all semiconductor devices.
[0082] Optionally, after the parameter adjustment device determines the maximum value among the parasitic capacitance values between the controlled terminal and the second conducting terminal of all semiconductor devices, the maximum value can be determined as the target capacitance value between the controlled terminal and the second conducting terminal of the semiconductor device.
[0083] Optionally, after the parameter adjustment device determines the maximum value among the parasitic capacitance values between the controlled terminal and the second conducting terminal of all semiconductor devices, any capacitance value greater than that maximum value can be determined as the target capacitance value between the controlled terminal and the second conducting terminal of the semiconductor device.
[0084] In another embodiment of this application, when a capacitor compensation unit is provided between the controlled terminal and the first conducting terminal of the semiconductor device and between the controlled terminal and the second conducting terminal of the semiconductor device, the parameter adjustment device can respectively determine the target capacitance value determined based on each parasitic capacitance value between the controlled terminal and the first conducting terminal of the semiconductor device as the first target capacitance value; and determine the target capacitance value determined based on each parasitic capacitance value between the controlled terminal and the second conducting terminal of the semiconductor device as the second target capacitance value.
[0085] S23: The difference between the parasitic capacitance value of the semiconductor device and the target capacitance value is determined as the compensation capacitance value of the semiconductor device.
[0086] In this embodiment of the application, after the parameter adjustment device determines the target capacitance value, it can perform a subtraction operation between the target capacitance value and the parasitic capacitance value between the controlled terminal and the conducting terminal of each semiconductor device to obtain the compensation capacitance value of each semiconductor device.
[0087] In one embodiment of this application, when the capacitor compensation unit is connected between the controlled terminal and the first conducting terminal of the semiconductor device, that is, when the capacitor compensation unit is only provided between the controlled terminal and the first conducting terminal of the semiconductor device, after the parameter adjustment device determines the target capacitance value, it can perform a subtraction operation between the target capacitance value and the parasitic capacitance value between the controlled terminal and the first conducting terminal of each semiconductor device to obtain the compensation capacitance value of each semiconductor device.
[0088] In another embodiment of this application, when the capacitor compensation unit is connected between the controlled terminal and the second conducting terminal of the semiconductor device, that is, when the capacitor compensation unit is only provided between the controlled terminal and the second conducting terminal of the semiconductor device, after the parameter adjustment device determines the target capacitance value, it can perform a subtraction operation between the target capacitance value and the parasitic capacitance value between the controlled terminal and the second conducting terminal of each semiconductor device to obtain the compensation capacitance value of each semiconductor device.
[0089] In another embodiment of this application, when a capacitor compensation unit is provided between the controlled terminal and the first conducting terminal of the semiconductor device, and between the controlled terminal and the second conducting terminal of the semiconductor device, the parameter adjustment device can perform a subtraction operation between the first target capacitance value and the parasitic capacitance value between the controlled terminal and the first conducting terminal of each semiconductor device to obtain the first compensation capacitance value between the controlled terminal and the first conducting terminal of each semiconductor device; and perform a subtraction operation between the second target capacitance value and the parasitic capacitance value between the controlled terminal and the second conducting terminal of each semiconductor device to obtain the second compensation capacitance value between the controlled terminal and the second conducting terminal of each semiconductor device.
[0090] S24: The control capacitor compensation unit performs capacitor compensation on the parasitic capacitance value of the connected semiconductor device based on the compensation capacitance value of the connected semiconductor device.
[0091] In one embodiment of this application, when the capacitor compensation unit is connected between the controlled terminal and the first conducting terminal of the semiconductor device, that is, when the capacitor compensation unit is only provided between the controlled terminal and the first conducting terminal of the semiconductor device, after the parameter adjustment device determines the compensation capacitance value between the controlled terminal and the first conducting terminal of the semiconductor device, it can control the capacitor compensation unit to perform capacitor compensation on the parasitic capacitance value between the controlled terminal and the first conducting terminal of the connected semiconductor device based on the compensation capacitance value between the controlled terminal and the first conducting terminal of the semiconductor device.
[0092] In another embodiment of this application, when the capacitor compensation unit is connected between the controlled terminal and the second conducting terminal of the semiconductor device, that is, when the capacitor compensation unit is only provided between the controlled terminal and the second conducting terminal of the semiconductor device, after the parameter adjustment device determines the compensation capacitance value between the controlled terminal and the second conducting terminal of the semiconductor device, it can control the capacitor compensation unit to perform capacitor compensation on the parasitic capacitance value between the controlled terminal and the second conducting terminal of the connected semiconductor device based on the compensation capacitance value between the controlled terminal and the second conducting terminal of the semiconductor device.
[0093] In another embodiment of this application, when a capacitor compensation unit is provided between the controlled terminal and the first conducting terminal of the semiconductor device, and between the controlled terminal and the second conducting terminal of the semiconductor device, the parameter adjustment device can control the capacitor compensation unit connected between the controlled terminal and the first conducting terminal of the semiconductor device to perform capacitor compensation on the parasitic capacitance value between the controlled terminal and the first conducting terminal of the connected semiconductor device based on the first compensation capacitance value between the controlled terminal and the first conducting terminal of the semiconductor device; and control the capacitor compensation unit connected between the controlled terminal and the second conducting terminal of the semiconductor device to perform capacitor compensation on the parasitic capacitance value between the controlled terminal and the second conducting terminal of the connected semiconductor device based on the second compensation capacitance value between the controlled terminal and the second conducting terminal of the semiconductor device.
[0094] In one specific embodiment of this application, when the capacitor compensation unit includes multiple compensation capacitors disposed between the controlled terminal and the on terminal of the semiconductor device using anti-fuse technology, S24 can be specifically implemented as follows: Figure 3 The implementations of S241 to S242 shown are described in detail below:
[0095] S241: Determine the target compensation capacitor to be compensated from multiple compensation capacitors based on the compensation capacitor values of the semiconductor devices connected to the capacitor compensation unit and the capacitance values of each compensation capacitor.
[0096] S242: The control capacitor compensation unit melts the target compensation capacitor to connect the target compensation capacitor between the controlled terminal and the on terminal of the corresponding semiconductor device.
[0097] In this embodiment, the capacitance values of each compensation capacitor can be pre-stored in the parameter adjustment device.
[0098] Based on this, the parameter adjustment device can first obtain the capacitance values of each pre-stored compensation capacitor, and then determine the target compensation capacitor to be compensated from multiple compensation capacitors according to the compensation capacitance value of the semiconductor device connected to each capacitor compensation unit and the capacitance value of each compensation capacitor.
[0099] It should be noted that the number of target compensation capacitors can be one or more.
[0100] In one possible implementation, when the capacitance values of the various compensation capacitors in the capacitor compensation unit are equal, S241 may include the following steps:
[0101] Calculate the ratio of the compensation capacitance value to the capacitance value of the semiconductor device connected to the capacitor compensation unit.
[0102] The integer part of the ratio is determined as the number of target compensation capacitors to be compensated.
[0103] Any number of compensation capacitors from a plurality of compensation capacitors are selected as the target compensation capacitors.
[0104] For example, if the ratio of the compensation capacitance value to the capacitance value of the semiconductor device connected to the capacitor compensation unit is 5.4, then 5 is determined as the number of target compensation capacitors. Based on this, the parameter adjustment device can determine any 5 compensation capacitors in the capacitor compensation unit as target compensation capacitors.
[0105] The above scheme sets up compensation capacitors with equal capacitance values in the capacitor compensation unit, calculates the ratio of the compensation capacitor value of the semiconductor device connected to the capacitor compensation unit to the capacitance value of the compensation capacitor, determines the integer part of the ratio as the number of target capacitors to be compensated, and determines any number of such compensation capacitors as the target compensation capacitors. This method can efficiently determine the target capacitors in the capacitor compensation units of each semiconductor device, and the logic is simple and easy to implement.
[0106] As can be seen from the above, the parameter adjustment method provided in this embodiment is applied to the target circuit. In addition to multiple semiconductor devices connected in parallel, the target circuit also includes multiple capacitor compensation units. Each capacitor compensation unit is connected between the controlled terminal and the on terminal of a semiconductor device. Based on this, by obtaining the parasitic capacitance value between the on terminal and the controlled terminal of each semiconductor device, the target capacitance value is determined based on all parasitic capacitance values. Since the target capacitance value is greater than or equal to the maximum value among all parasitic capacitance values, the difference between the parasitic capacitance value of the semiconductor device and the target capacitance value is determined as the compensation capacitance value. The capacitor compensation unit is controlled to perform capacitor compensation on the parasitic capacitance value of the connected semiconductor device based on the compensation capacitance value of the connected semiconductor device. This can make the total parasitic capacitance value of each semiconductor device equal, that is, equal to the target capacitance value, thereby solving the problem of mismatch in switching speed characteristics between multiple semiconductor devices connected in parallel. Furthermore, since only one capacitor compensation unit needs to be set between the controlled terminal and the on terminal of each semiconductor device to compensate for the parasitic capacitance value of each semiconductor device, the structure of the target circuit is relatively simple and the size of the target circuit is reduced. Moreover, regardless of the performance of each semiconductor device, the total parasitic capacitance value of all semiconductor devices can be made equal by the above method. Therefore, it is less affected by the performance of the semiconductor devices themselves. That is, semiconductor devices with arbitrary performance can be used to realize high-current semiconductor devices, thereby expanding the applicable scenarios of high-current semiconductor devices.
[0107] Based on the parameter adjustment method provided in the above embodiments, this invention further provides an embodiment of a parameter adjustment device for implementing the above method embodiments. Please refer to... Figure 4 This is a schematic diagram of a parameter adjustment device provided in an embodiment of this application. For ease of explanation, only the parts relevant to this embodiment are shown. Figure 4 As shown, the parameter adjustment device 40 may include: a first acquisition unit 41, a first determination unit 432, a second determination unit 43, and a control unit 44. Wherein:
[0108] The first acquisition unit 41 is used to acquire the parasitic capacitance value between the controlled terminal and the on terminal of each of the semiconductor devices.
[0109] The first determining unit 42 is used to determine a target capacitance value based on all the parasitic capacitance values; the target capacitance value is greater than or equal to the maximum value among all the parasitic capacitance values.
[0110] The second determining unit 43 is used to determine the difference between the parasitic capacitance value of the semiconductor device and the target capacitance value as the compensation capacitance value of the semiconductor device.
[0111] The control unit 44 is used to control the capacitor compensation unit to perform capacitor compensation on the parasitic capacitance value of the connected semiconductor device based on the compensation capacitance value of the connected semiconductor device.
[0112] Optionally, the capacitor compensation unit includes multiple compensation capacitors, each of which is disposed between the controlled terminal and the conducting terminal of the corresponding semiconductor device using anti-fuse technology; the control unit 44 includes a second determining unit and a fuse unit. Wherein:
[0113] The second determining unit is used to determine the target compensation capacitor to be compensated from the plurality of compensation capacitors based on the compensation capacitor value of the semiconductor device connected to the capacitor compensation unit and the capacitance value of each of the compensation capacitors.
[0114] The fuse unit is used to control the capacitor compensation unit to fuse the target compensation capacitor, so as to connect the target compensation capacitor between the controlled terminal and the on terminal of the corresponding semiconductor device.
[0115] Optionally, all the compensation capacitors in the capacitor compensation unit have the same capacitance value; the second determining unit is specifically used for:
[0116] Calculate the ratio of the compensation capacitance value of the semiconductor connected to the capacitor compensation unit to the capacitance value of the compensation capacitor.
[0117] The integer part of the ratio is determined as the number of target compensation capacitors to be compensated.
[0118] Any number of the plurality of compensation capacitors shall be determined as the target compensation capacitor.
[0119] Optionally, the target circuit further includes multiple capacitance measurement units, each of which is connected to one of the semiconductor devices via a wire; the capacitance measurement units are used to measure the actual capacitance value of the corresponding semiconductor device; the first acquisition unit 41 is specifically used for:
[0120] For each of the semiconductor devices, the actual capacitance value of the semiconductor device is obtained from the capacitance measurement unit connected to the semiconductor device;
[0121] Obtain the equivalent capacitance value formed by the semiconductor device and the winding used to connect the semiconductor device;
[0122] The parasitic capacitance value of the semiconductor device is determined by summing the actual capacitance value of the semiconductor device with the corresponding equivalent capacitance value.
[0123] It should be noted that the information interaction and execution process between the above-mentioned units are based on the same concept as the method embodiments of this application. Their specific functions and technical effects can be referred to the method embodiments section, and will not be repeated here.
[0124] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units is merely an example. In practical applications, the above functions can be assigned to different functional units as needed, that is, the internal structure of the power supply control device can be divided into different functional units to complete all or part of the functions described above. The functional units in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0125] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.
[0126] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0127] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.
Claims
1. A method for adjusting the parameters of parallel devices, applied to a target circuit, said target circuit comprising multiple semiconductor devices connected in parallel; characterized in that, The target circuit also includes multiple capacitor compensation units, each of which is connected between the controlled terminal and the on terminal of one of the semiconductor devices; The parameter adjustment method for the parallel devices includes: Obtain the parasitic capacitance value between the controlled terminal and the on terminal of each of the semiconductor devices; A target capacitance value is determined based on all the parasitic capacitance values; the target capacitance value is greater than or equal to the maximum value among all the parasitic capacitance values. The difference between the parasitic capacitance value of the semiconductor device and the target capacitance value is determined as the compensation capacitance value of the semiconductor device. The control unit performs capacitance compensation on the parasitic capacitance of the connected semiconductor device based on the compensation capacitance value of the connected semiconductor device.
2. The parameter adjustment method for parallel devices according to claim 1, characterized in that, The capacitor compensation unit includes multiple compensation capacitors, and each compensation capacitor is disposed between the controlled terminal and the conducting terminal of the corresponding semiconductor device using anti-fuse technology. The control of the capacitance compensation unit to perform capacitance compensation on the parasitic capacitance value of the connected semiconductor device based on the compensation capacitance value of the connected semiconductor device includes: The target compensation capacitor to be compensated is determined from the plurality of compensation capacitors based on the compensation capacitor values of the semiconductor devices connected to the capacitor compensation unit and the capacitance values of each compensation capacitor. The capacitor compensation unit is controlled to melt the target compensation capacitor, thereby connecting the target compensation capacitor between the controlled terminal and the on terminal of the corresponding semiconductor device.
3. The parameter adjustment method for parallel devices according to claim 2, characterized in that, All the compensation capacitors in the capacitor compensation unit have the same capacitance value; The step of determining the target compensation capacitor to be compensated from the plurality of compensation capacitors based on the compensation capacitance value of the semiconductor device connected to the capacitor compensation unit and the capacitance value of each of the compensation capacitors includes: Calculate the ratio of the compensation capacitance value of the semiconductor connected to the capacitor compensation unit to the capacitance value of the compensation capacitor; The integer part of the ratio is determined as the number of target compensation capacitors to be compensated; Any number of the plurality of compensation capacitors are determined as the target compensation capacitor.
4. The parameter adjustment method for parallel devices according to claim 1, characterized in that, The target circuit also includes multiple capacitance measurement units, each of which is connected to one of the semiconductor devices by a wire winding; the capacitance measurement unit is used to measure the actual capacitance value of the corresponding semiconductor device. The step of obtaining the parasitic capacitance value between the controlled terminal and the on terminal of each of the semiconductor devices includes: For each of the semiconductor devices, the actual capacitance value between the controlled terminal and the on terminal of the semiconductor device is obtained from the capacitance measurement unit connected to the semiconductor device; Obtain the equivalent capacitance value of the semiconductor device and the corresponding winding formed by the capacitor; The sum of the actual capacitance value and the equivalent capacitance value is determined as the parasitic capacitance value between the controlled terminal and the on terminal of the semiconductor device.
5. The parameter adjustment method for parallel devices according to any one of claims 1 to 4, characterized in that, The number of semiconductor devices included in the target circuit is equal to the number of capacitor compensation units; each capacitor compensation unit is connected between a controlled terminal and a first conducting terminal of a semiconductor device, or each capacitor compensation unit is connected between a controlled terminal and a second conducting terminal of a semiconductor device.
6. The parameter adjustment method for parallel devices according to any one of claims 1 to 4, characterized in that, The number of capacitor compensation units included in the target circuit is twice the number of semiconductor devices; a capacitor compensation unit is connected between the controlled terminal and the first conducting terminal of each semiconductor device, and a capacitor compensation unit is connected between the controlled terminal and the second conducting terminal of each semiconductor device.
7. A parameter adjustment device for parallel devices, characterized in that, The method is applied to a target circuit, which includes multiple semiconductor devices connected in parallel; characterized in that the target circuit further includes multiple capacitance compensation units, each of which is connected between a controlled terminal and a conducting terminal of one of the semiconductor devices; the parameter adjustment device for the parallel devices includes: The first acquisition unit is used to acquire the parasitic capacitance value between the controlled terminal and the on terminal of each of the semiconductor devices; The first determining unit is configured to determine a target capacitance value based on all the parasitic capacitance values; the target capacitance value is greater than or equal to the maximum value among all the parasitic capacitance values. The second determining unit is used to determine the difference between the parasitic capacitance value of the semiconductor device and the target capacitance value as the compensation capacitance value of the semiconductor device. The control unit is used to control the capacitor compensation unit to perform capacitor compensation on the parasitic capacitance value of the connected semiconductor device based on the compensation capacitance value of the connected semiconductor device.
8. The parameter adjustment device for parallel devices according to claim 7, characterized in that, The capacitor compensation unit includes multiple compensation capacitors, each of which is disposed between the controlled terminal and the on terminal of the corresponding semiconductor device using antifuse technology; the control unit specifically includes: The second determining unit is used to determine the target compensation capacitor to be compensated from the plurality of compensation capacitors based on the compensation capacitor value of the semiconductor device connected to the capacitor compensation unit and the capacitance value of each of the compensation capacitors. A fuse unit is used to control the capacitor compensation unit to fuse the target compensation capacitor, so as to connect the target compensation capacitor between the controlled terminal and the on terminal of the corresponding semiconductor device.
9. The parameter adjustment device for parallel devices according to claim 8, characterized in that, The target circuit also includes multiple capacitance measurement units, each of which is connected to one of the semiconductor devices by a wire winding; the capacitance measurement unit is used to measure the actual capacitance value of the corresponding semiconductor device. The first acquisition unit is specifically used for: For each of the semiconductor devices, the actual capacitance value of the semiconductor device is obtained from the capacitance measurement unit connected to the semiconductor device; Obtain the equivalent capacitance value formed by the semiconductor device and the winding used to connect the semiconductor device; The parasitic capacitance value of the semiconductor device is determined by summing the actual capacitance value of the semiconductor device with the corresponding equivalent capacitance value.
10. A target circuit for realizing a high-current device, the target circuit comprising a plurality of semiconductor devices connected in parallel; characterized in that, The target circuit further includes multiple capacitor compensation units and parameter adjustment devices; each capacitor compensation unit is connected between the controlled terminal and the on terminal of one of the semiconductor devices, and the parameter adjustment device is used to perform the method as described in any one of claims 1-6.