FMCW phase-locked loop system based on two-point modulation multi-subband voltage-controlled oscillator

Abstract

The present invention discloses an FMCW phase-locked loop (PLL) system based on a two-point modulation multi-subband voltage-controlled oscillator (VCO). The system includes a phase frequency detector (PFD), a charge pump, a loop filter, a VCO, a digital-to-analog conversion (DAC) module, an injection-locked frequency divider, a frequency divider module, a multi-mode frequency divider, a ΔΣ modulator, an FMCW multi-function module, a sub-band compensation module, a system linearity calibration module, and a switched capacitor array. The system uses multi-subband oscillator (MSO) technology to broaden the frequency bandwidth of the frequency source; employs two-point modulation technology to mitigate the loop bandwidth of the PLL loop, ensuring a stable fast chirp state; combines a D / A conversion module with a multi-subband oscillator to achieve ultra-low frequency resolution and reduce RMS frequency error; employs frequency compensation technology to eliminate the impact of the multi-subband oscillator on fast chirps; and employs system linearity calibration technology to eliminate the impact of nonlinearities in the oscillator and D / A conversion module on the PLL.

Description

Technical Field

[0001] The present invention relates to the technical field of FMCW phase-locked loops, and in particular to an FMCW phase-locked loop system based on a two-point modulation multi-subband voltage-controlled oscillator. Background Art

[0002] Wireless communication technology has experienced rapid development in recent years. Its widespread application in both civilian and military applications has propelled the wireless communications industry to become one of the world's most important industries. Wireless communication technologies, represented by radio frequency (RF) technology, are widely used in various fields. Short-range wireless communication technologies such as Bluetooth, wireless local area networks (WLAN), and Zigbee, as well as broadband, multi-standard wireless communication technologies compatible with 2G / 3G / 4G protocols, have greatly facilitated people's work and lives.

[0003] The introduction of 5G will usher in a world of interconnectedness, enabling all applications to be hosted in the cloud while still providing a personal desktop experience. Radar technology has also entered the public eye, with applications such as automotive radar and radar systems in mobile devices. The phase-locked loop (PLL) frequency source is the heart of wireless communications and radar. However, current technology, primarily based on charge pump PLLs, struggles to meet civilian and even military requirements. Key challenges include: difficulty in simultaneously meeting the specifications of both the FMCW source and the communication source; the phase-locked loop's frequency bandwidth is relatively narrow; the frequency sweep speed is too slow, and the chirp speed affects radar resolution. Summary of the Invention

[0004] The purpose of the present invention is to address the technical defects existing in the prior art and provide an FMCW phase-locked loop system based on a two-point modulation multi-subband voltage-controlled oscillator, which can realize an ultra-wideband frequency source system, can meet the needs of both communication and radar, can achieve fast chirp and have extremely small frequency error.

[0005] The technical solution adopted to achieve the purpose of the present invention is:

[0006] An FMCW phase-locked loop system based on a two-point modulation multi-sub-band voltage-controlled oscillator, comprising a frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a digital-to-analog conversion module, an injection-locked frequency divider, a frequency divider module, a multi-mode frequency divider, a ΔΣ modulator, an FMCW multi-function module, a sub-band compensation module, a system linearity calibration module, and a switched capacitor array;

[0007] The output end of the frequency and phase detector is connected to the input end of the charge pump, the output end of the charge pump is connected to the input end of the loop filter, the output end of the loop filter is connected to the filter signal input end of the voltage-controlled oscillator, the analog signal input end of the voltage-controlled oscillator is connected to the output end of the DAC digital-to-analog conversion module, and the signal input end of the voltage-controlled oscillator switch array is connected to the output end of the switch capacitor array;

[0008] One output of the FMCW multifunctional module system is connected to the input of the system linear calibration module, another output is connected to an input of the sub-band compensation module, a third output is connected to the ΔΣ modulator, the output of the ΔΣ modulator is connected to one input of the multimode frequency divider, the output of the multimode frequency divider is connected to the input of the frequency detector and phase detector, another input of the multimode frequency divider is connected to the output of the frequency divider module, the input of the frequency divider module is connected to the output of the injection-locked frequency divider, and the input of the injection-locked frequency divider is connected to the output of the voltage-controlled oscillator;

[0009] A multi-subband VCO is combined with a digital-to-analog conversion module to increase system bandwidth and improve VCO accuracy. A two-point modulation scheme is adopted. The divider link of the phase-locked loop (PLL) is a low-pass path, and the digital-to-analog conversion module path is a high-pass path. Linear calibration and sub-band compensation calibration are used to achieve system calibration.

[0010] The switched capacitor array voltage-controlled oscillator is used to generate a waveform output of a specific frequency from the voltage signal of the digital loop filter, adopts a Class-F structure, and uses a transformer and tail inductor to control the second and third harmonics to optimize phase noise;

[0011] Among them, the primary coil L of the transformer P and fixed capacitor C D Connected between the drain of transistors M1 and M2, the tail inductor L TAIL Connected between the source of transistors M1 and M2 and ground, the secondary coil L of the transformer S The switch capacitor array and the variable capacitor are connected between the gates of transistors M1 and M2. The 6-bit switch capacitor array consists of 3 groups of switch capacitors C1 with the same large capacitance and 15 groups of switch capacitors C2 with the same small capacitance. The switch capacitor is connected to the DAC. The two groups of variable capacitors C V1 、C V2 The capacitance values are respectively determined by V CTRL1 、V CTRL2 control, where V CTRL1 Connected to the system filter, V CTRL2 High-order connection to the system's connected adder.

[0012] The present invention widens the frequency bandwidth of a frequency source through a multi-sub-band oscillator (VCO) technology; adopts a two-point modulation technology to reduce the loop bandwidth of a PLL loop, thereby ensuring a fast chirp steady state; adopts a technology combining a digital-to-analog converter (DAC) module with a multi-sub-band oscillator (VCO) to achieve ultra-small frequency division resolution and reduce the RMS error of the frequency; adopts a frequency compensation technology to eliminate the influence of the multi-sub-band oscillator (VCO) on the fast chirp; and adopts a system linear calibration technology to eliminate the influence of the nonlinearity of the oscillator (VCO) and the digital-to-analog converter (DAC) on the PLL. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of the FMCW phase-locked loop system based on a two-point modulation multi-subband voltage-controlled oscillator of the present invention.

[0014] Figure 2 FIG. 1 is a diagram of a multi-subband two-point modulation (TPM) VCO architecture according to the present invention.

[0015] Figure 3 It is a flow chart of the low-pass and high-pass path matching of two-point modulation (TPM) of the present invention.

[0016] Figure 4 It is a fixed-point output flow chart of the present invention.

[0017] Figure 5 This is a flow chart of chirp waveform output of the present invention. DETAILED DESCRIPTION

[0018] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0019] like Figure 1 As shown, the FMCW phase-locked loop system based on a two-point modulation multi-sub-band voltage-controlled oscillator according to an embodiment of the present invention includes a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage-controlled oscillator (VCO), a DAC digital-to-analog conversion module, an injection-locked frequency divider (ILFD), a frequency divider module (CML), a multi-mode frequency divider, a ΔΣ modulator, an FMCW multi-function module, a sub-band compensation module (OC), a system linearity calibration module (LM), and a switched capacitor array;

[0020] When performing compensation, the sub-band compensation module (OC) first tests the frequency of overlap between sub-bands and calculates the value of the digital control word to compensate each sub-band based on the frequency accuracy. This information is sent to the sub-band compensation module (OC) by the FMCW multi-function module. The sub-band compensation module (OC) compensates the chirp control word at different times to eliminate VOC sub-band overlap.

[0021] The system linearity calibration module (LM) is used to calibrate the nonlinearity of the DAC and VCO externally. The FMCW multifunction module then transmits this information to the system linearity calibration module (LM), which then implements compensation based on system requirements.

[0022] After the outputs of the system linear calibration module (LM) and the sub-band compensation module (OC) are summed, the overall calibrated control word is obtained. The final control word is given to the two modules respectively. The high bit of the control word is given to the switched capacitor array and the low bit is given to the DAC module to achieve BW (frequency bandwidth) / 2 18 frequency control accuracy.

[0023] The phase frequency detector (PFD) compares the reference clock and the feedback clock to determine the input phase difference, while the charge pump (CP) converts the input phase difference into voltage or current.

[0024] In the embodiments of the present invention, the loop filter can, on the one hand, filter out high-frequency signal components generated by a phase frequency detector (PFD) and, on the other hand, limit the impact of noise generated external to the phase-locked loop (PLL). Furthermore, the loop filter can also regulate the PLL. By adjusting the parameters of the loop filter, the PLL voltage spectrum can be controlled, thereby improving the stability of the PLL system.

[0025] The voltage controlled oscillator (VCO) is used to generate a waveform output of a specific frequency from the voltage signal of the loop filter. Figure 2 , VCO uses Figure 2 The Class-F structure shown in the figure uses a transformer and tail inductor to control second and third harmonics to optimize phase noise. Compared to traditional VCOs, this solution achieves tuning through a 6-bit switched capacitor array and two pairs of variable capacitors. This solution reduces the system's DAC and bit requirements, reduces design complexity, and reduces overall system power consumption and area.

[0026] This VCO achieves a 25% relative tuning range and a phase noise of -108dBc / Hz at a 1MHz frequency offset. Tuning is accomplished using a 6-bit switched capacitor array and two pairs of variable capacitors. Compared to traditional two-point modulation architectures, this solution reduces the system's DAC bit requirements while achieving equivalent tuning accuracy. This reduces design complexity, leaving margins for system area and power consumption, optimizing the system and improving overall chip performance.

[0027] Among them, the primary coil L of the transformer P and fixed capacitor CD Connected between the drain of transistors M1 and M2, the tail inductor L TAIL Connected between the source of transistors M1 and M2 and ground, the secondary coil L of the transformer S The 6-bit switched capacitor array consists of 3 groups of identical large-capacitance switched capacitors C1 and 15 groups of identical small-capacitance switched capacitors C2. The switched capacitors are connected to the DAC. V1 、C V2 The capacitance values are respectively determined by V CTRL1 、V CTRL2 control, where V CTRL1 Connected to the system filter, V CTRL2 High-order connection to the system's connected adder.

[0028] An injection-locked frequency divider (ILFD) divides the VCO output frequency by 2; a frequency divider module (CML) divides the ILFD output frequency by 8; a multi-mode frequency divider is used to implement a multi-mode frequency divider by combining a P / S counter with a 2 / 3 frequency divider; and a ΔΣ modulator is used to control the multi-mode frequency divider to achieve fractional frequency division and push the fractional noise to high frequency.

[0029] Among them, the FMCW multi-function module is used to realize a multi-function frequency source by identifying the modulation signal. It can achieve fixed-point frequency output within 24.8GHz to 31.5GHz, and can also realize multiple modes, multiple chirp times, OC compensation, and LM calibration mode, so that the system can achieve ultra-low RSM frequency error and very ideal linearity.

[0030] Specifically, the output end of the phase frequency detector (PFD) is connected to the input end of the charge pump, the output end of the charge pump is connected to the input end of the loop filter, the output end of the loop filter is connected to the filter signal input end of the voltage controlled oscillator, the analog signal input end of the voltage controlled oscillator is connected to the output end of the DAC digital-to-analog conversion module, and the signal input end of the voltage controlled oscillator switch array is connected to the output end of the switch capacitor array;

[0031] Among them, one output of the FMCW multi-function module system is connected to the corresponding input end of the system linear calibration module, another output is connected to one input of the sub-band compensation module, and the third output is connected to the ΔΣ modulator. The output of the ΔΣ modulator is connected to one input of the multi-mode divider, the output of the multi-mode divider is connected to the input of the phase frequency detector (PFD), and another input of the multi-mode divider is connected to the output of the divider module. The input of the divider module is connected to the output of the injection-locked divider, and the input of the injection-locked divider is connected to the output of the voltage-controlled oscillator.

[0032] See also Figure 1 As shown, in this embodiment, a phase modulation signal is injected into the digital input terminal of the DSM that controls the multi-mode divider and the input terminal of the voltage-controlled oscillator (VCO) (the multi-mode divider is controlled by the DSM to achieve fractional frequency division), where the former is a low-pass channel and the latter is a high-pass channel.

[0033] In addition, since the FMCW multi-function module signal is usually a digital signal, a digital-to-analog converter is required for the high-pass channel to generate an analog voltage signal, which is then injected into the voltage-controlled oscillator input.

[0034] In addition, if the final phase-locked loop output is a phase-modulated signal, then the signals injected at the above two points should be frequency-modulated signals, because the input voltage of the voltage-controlled oscillator directly controls the frequency, and similarly, the input digital signal of the frequency divider DSM also controls the frequency. Therefore, in the high-pass path FMCW multi-function module, the phase-modulated signal must first be converted into a frequency-modulated signal through differentiation.

[0035] This invention combines a multi-subband VCO with a DAC to increase system bandwidth and VCO accuracy. Using a two-point modulation scheme, the phase-locked loop (PLL) divider chain is a low-pass path, while the DAC chain is a high-pass path. System calibration is achieved through linear calibration and OC calibration (sub-band offset calibration).

[0036] The FMCW phase-locked loop system based on two-point modulation multi-subband voltage-controlled oscillator disclosed in the present invention has the following working steps: Figure 3-Figure 5 The flowchart shown.

[0037] Figure 3 Flowchart of the calibration method of the high-pass path and the low-pass path of the present invention, the steps are as follows:

[0038] The first step is to disconnect the two-point modulated phase-locked loop from the input of the voltage-controlled oscillator (i.e., disconnect the filter from the voltage-controlled oscillator first). Then, apply a suitable fixed voltage (usually half the power supply voltage) to the input of the voltage-controlled oscillator to ensure that the output signal frequency of the voltage-controlled oscillator is close to the normal operating frequency (i.e., adjust Vtune1 to the center voltage of the Vtune1 voltage range).

[0039] Assume that the gain of the high-pass path is K in the initial state. h0 ;

[0040] In the second step, the FMCW multi-function module inputs the minimum digital signal (usually all 0s) to the DAC of the high-pass path, modulating the DAC input to the maximum. The VCO selects the lowest frequency sub-band and calculates the frequency through testing:

[0041] Assume that the output signal frequency of the lowest sub-band of the voltage-controlled oscillator is fLv0 , through a suitable division ratio N L0 Divide the signal to near f0, and get the lowest signal frequency of the lowest sub-band of the voltage-controlled oscillator as f Lv0 =N L0 ·f0.

[0042] The third step is to find the highest f of the lowest sub-band of the voltage controlled oscillator by the same method. Hv0 =N H0 f0;

[0043] The fourth step is to switch the sub-band and use the same method to test and calculate the highest and lowest frequency information of each sub-band.

[0044] The fifth step is to calculate the DAC gain of the high-pass path based on the measured frequency information, modulate the calculated information to the high-pass and low-pass paths, and match the high-pass and low-pass paths to meet the following requirements:

[0045] K h ·K vco =K l ·f ref

[0046] Among them, K h is the high-pass path gain, K l is the low-pass path gain, K vco is the tuning gain of the oscillator, f ref is the reference clock frequency

[0047] As an embodiment, the system of the present invention also has the function of fixed-point output frequency, which is also to determine the output frequency. The operation can be seen in Figure 4 :

[0048] The first step is to turn on the fixed output option by controlling the FMCW multi-function module; specifically, set the modulation signal to make the FWCW multi-function module enter the fixed-point output mode

[0049] The second step is to determine the frequency control method or the adopted method:

[0050] If it is method 1, the fixed-point output is achieved by controlling the low-pass path: by controlling the modulation signal, changing the frequency division information of the multi-mode divider, determining the VCO sub-band, the frequency division number is Nf, so that the final output frequency f = f ref Nf, output fixed-point frequency;

[0051] If it is method 2, fixed-point output is achieved by controlling the high-pass path: by controlling the modulation signal, changing the frequency division information of the multi-mode divider, determining the VCO sub-band, modulating the VCO based on the first method of changing the frequency division number to Nf and the DAC path control signal, and achieving fixed-point frequency output by changing the information of the high-pass path.

[0052] The present invention adopts a multi-subband VCO to realize two-point modulation of a frequency source. The multi-subband VCO can reduce Kvco, which is beneficial to reducing phase noise. The multi-subband VCO can increase the frequency bandwidth.

[0053] By comparing existing technologies, the phase noise of a traditional single-subband VCO architecture with a center frequency of 28GHz is approximately -103dBc / Hz (@1MHz), while the multi-subband architecture can achieve -107dBc / Hz (@1MHz) (its performance is jointly influenced by factors such as the number of subbands and the size of Kvco). In terms of bandwidth, this architecture expands from the original 4.5GHz to 6.8GHz, a 51% increase in bandwidth.

[0054] The present invention uses DAC and multi-subband VCO to perform modulation in the system high-pass path, which can achieve ultra-high precision modulation. Using 12-bit DAC and 6-bit VCO can achieve an accuracy of:

[0055]

[0056] Among them, f LSB Indicates the minimum frequency resolution of the frequency, f 带宽 Indicates the sweep bandwidth;

[0057] This invention improves system calibration accuracy and enables precise control of the system through a digital control scheme. Specifically, it achieves ultra-low RSM frequency error. According to the following formula: This invention reduces the system's RMS frequency error, improving system performance. RMS frequency error is one of the most critical performance indicators of an FMCW source. This architecture can reduce RSM frequency error by at least two to three orders of magnitude, representing a significant technological breakthrough. The combination of a DAC and VCO reduces both VCO and DAC requirements.

[0058] The system of the present invention can achieve an RSM frequency error of 14 kHz. The current technology in this frequency range has an RSM error of more than 1 MHz, which is not as wide as the frequency bandwidth of the present invention.

[0059]

[0060] Among them, f rms_rse The frequency RMS error, Δf is the frequency resolution, T is the frequency sweep period, Δt is the time step of the frequency sweep, and k is the frequency sweep speed (Hz / s).

[0061] In the embodiment of the present invention, the chirp waveform output process is as follows: Figure 5As shown, start by setting the modulation signal, turning off the fixed-point output mode of the FWCW multi-function module, adjusting the DAC path to lock the PLL, and making the voltage of Vtune1 of the divider path near the center position, turning on the chirp function, and starting to sweep to achieve triangular wave and sawtooth wave.

[0062] The basic principles, main features and advantages of the present invention are shown and described above. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments and that the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention.

[0063] Therefore, from any point of view, the embodiments should be regarded as illustrative and non-restrictive, and the scope of the invention is limited by the appended claims rather than the above description. Therefore, it is intended that all changes that fall within the meaning and range of equivalent elements of the claims are included in the present invention, and any figure signs in the claims should not be regarded as limiting the claims involved.

[0064] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. An FMCW phase-locked loop system based on a two-point modulation multi-subband voltage-controlled oscillator, characterized in that: Including frequency detector, charge pump, loop filter, voltage controlled oscillator, digital-to-analog conversion module, injection locked frequency divider, frequency divider module, multi-mode frequency divider, ΔΣ modulator, FMCW multi-function module, sub-band compensation module, system linearity calibration module, switched capacitor array; The output end of the frequency and phase detector is connected to the input end of the charge pump, the output end of the charge pump is connected to the input end of the loop filter, the output end of the loop filter is connected to the filter signal input end of the voltage-controlled oscillator, the analog signal input end of the voltage-controlled oscillator is connected to the output end of the DAC digital-to-analog conversion module, and the signal input end of the voltage-controlled oscillator switch array is connected to the output end of the switch capacitor array; One output of the FMCW multifunctional module system is connected to the input of the system linear calibration module, another output is connected to an input of the sub-band compensation module, a third output is connected to the ΔΣ modulator, the output of the ΔΣ modulator is connected to one input of the multimode frequency divider, the output of the multimode frequency divider is connected to the input of the frequency detector and phase detector, another input of the multimode frequency divider is connected to the output of the frequency divider module, the input of the frequency divider module is connected to the output of the injection-locked frequency divider, and the input of the injection-locked frequency divider is connected to the output of the voltage-controlled oscillator; A multi-subband VCO is combined with a digital-to-analog conversion module to increase system bandwidth and improve VCO accuracy. A two-point modulation scheme is adopted. The divider link of the phase-locked loop (PLL) is a low-pass path, and the digital-to-analog conversion module path is a high-pass path. Linear calibration and sub-band compensation calibration are used to achieve system calibration.

2. The FMCW phase-locked loop system based on two-point modulation multi-subband voltage-controlled oscillator according to claim 1, characterized in that: The switched capacitor array voltage-controlled oscillator is used to generate a waveform output of a specific frequency from the voltage signal of the digital loop filter. It adopts a Class-F structure and uses a transformer and tail inductor to control the second and third harmonics to optimize phase noise. Among them, the primary coil L of the transformer P and fixed capacitor C D Connected between the drain of transistors M1 and M2, the tail inductor L TAIL Connected between the source of transistors M1 and M2 and ground, the secondary coil L of the transformer S The switch capacitor array and the variable capacitor are connected between the gates of transistors M1 and M2. The 6-bit switch capacitor array consists of 3 groups of switch capacitors C1 with the same large capacitance and 15 groups of switch capacitors C2 with the same small capacitance. The switch capacitor is connected to the DAC. The two groups of variable capacitors C V1 、C V2 The capacitance values are respectively determined by V CTRL1 、V CTRL2 control, where V CTRL1 Connected to the system filter, V CTRL2 High-order connection to the system's connected adder.

3. The FMCW phase-locked loop system based on two-point modulation multi-subband voltage-controlled oscillator according to claim 1, characterized in that: The FMCW multifunctional module realizes a multifunctional frequency source by identifying the modulation signal, can achieve fixed-point frequency output within 24.8GHz to 31.5GHz, and realizes multiple modes, multiple chirp times, sub-band compensation, and system linear calibration mode, so that the system can achieve ultra-low RSM frequency error and required linearity.

4. The FMCW phase-locked loop system based on two-point modulation multi-subband voltage-controlled oscillator according to claim 1, characterized in that: During sub-band compensation calibration, the frequency of overlap between sub-bands is first measured. The value of the digital control word to compensate each sub-band is calculated based on the frequency accuracy. The value of the digital control word is sent by the FMCW multi-function module to the sub-band compensation module. The sub-band compensation module compensates the chirp control word at different times to eliminate VOC sub-band overlap.

5. The FMCW phase-locked loop system based on two-point modulation multi-subband voltage-controlled oscillator according to claim 1, characterized in that: System linearity calibration is an external calibration used to calibrate the nonlinearity of DAC and VCO. During system linearity calibration, the nonlinearity difference is obtained based on the nonlinearity of the external test. The nonlinearity difference is then given by the FMCW multi-function module to the system linearity calibration module. The system linearity calibration module will compensate for it in the system according to system requirements.

6. The FMCW phase-locked loop system based on two-point modulation multi-subband voltage-controlled oscillator according to claim 3, characterized in that: The function of outputting a fixed frequency can be realized by controlling the frequency. The operation steps include: By controlling the FMCW multi-function module, turn on the fixed output option; set the modulation signal to make the FWCW multi-function module enter the fixed-point output mode; Determine the frequency control method, and then use one of the methods to achieve fixed-point output: One is to achieve fixed-point output by controlling the low-pass path: by controlling the modulation signal, changing the frequency division information of the multi-mode divider, determining the VCO sub-band, the frequency division number is Nf, and the final output frequency f = f ref Nf, output fixed-point frequency; The second is to achieve fixed-point output by controlling the high-pass path: by controlling the modulation signal, changing the frequency division information of the multi-mode divider, determining the VCO sub-band, and modulating the VCO based on the first method of changing the frequency division number to Nf and the DAC path control signal, and achieving fixed-point frequency output by changing the information of the high-pass path.

7. The FMCW phase-locked loop system based on two-point modulation multi-subband voltage-controlled oscillator according to claim 1, characterized in that: in, The calibration method for the high-pass path and the low-pass path is as follows: The first step is to disconnect the two-point modulated phase-locked loop from the input of the voltage-controlled oscillator and apply a fixed voltage to the input of the voltage-controlled oscillator to keep the output signal frequency of the voltage-controlled oscillator close to the normal operating frequency. In other words, adjust Vtune1 to the center voltage of the Vtune1 voltage range. In the second step, the FMCW multi-function module inputs the minimum digital signal to the DAC of the high-pass path, modulating the DAC's input to the maximum. The VCO selects the lowest frequency sub-band and calculates the frequency through testing: Assume that the output signal frequency of the lowest sub-band of the voltage-controlled oscillator is f Lv0 , through the corresponding frequency division ratio N L0 Divide the signal to near f0, and get the lowest signal frequency of the lowest sub-band of the voltage-controlled oscillator as f Lv0 =N L0 f0; The third step is to find the highest f of the lowest sub-band of the voltage controlled oscillator by the same method. Hv0 =N H0 f0; The fourth step is to switch sub-bands. The above method is used to test and calculate the highest and lowest frequency information of each sub-band; The fifth step is to calculate the DAC gain of the high-pass path based on the measured frequency information, modulate the calculated information to the high-pass and low-pass paths, and match the high-pass and low-pass paths to meet the following requirements: K h ·K vco =K l ·f ref Among them, K h is the high-pass path gain, K l is the low-pass path gain, K vco is the tuning gain of the oscillator, f ref is the reference clock frequency.

8. The FMCW phase-locked loop system based on two-point modulation multi-subband voltage-controlled oscillator according to claim 1, characterized in that: in, Control the chirp waveform output, including the following steps: Set the modulation signal, turn off the fixed-point output mode of the FWCW multi-function module, adjust the digital-to-analog converter path so that the phase-locked loop (PLL) is locked, and the voltage of Vtune1 of the divider path is near the center position. Turn on the chirp function and start sweeping to achieve triangular and sawtooth waves.

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