Data receiving circuit and semiconductor device

Abstract

The embodiment of the present disclosure provides a data receiving circuit and a semiconductor device. The data receiving circuit comprises a plurality of data paths. The i-th data path comprises: an amplification circuit configured to amplify a voltage difference between a voltage of input data and a reference voltage and output a first signal pair; a sampling circuit configured to receive a corresponding sampling clock, sample the first signal pair and output a second signal pair; a first circuit configured to receive the second signal pairs output by N data paths, output a corresponding tap control signal based on all the received second signal pairs, the tap control signal being a multi-bit signal, and N being less than or equal to M; and a second circuit configured to receive the tap control signal and adjust a level of the first signal pair in the i-th data path by a corresponding adjustment value of the tap control signal in response to the tap control signal. The embodiment of the present disclosure is at least beneficial to reduce circuit complexity, reduce load and improve input data transmission speed.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a data receiving circuit and a semiconductor device. Background Art

[0002] In memory applications, as signal transmission rates increase and clock frequencies rise, input data channel losses increasingly impact signal quality, easily leading to intersymbol interference (ISI). ISI refers to the phenomenon where previously transmitted input data affects the transmission of currently transmitted input data due to bandwidth limitations of the input data channel. Currently, equalization circuits are commonly used to compensate for the input data channel in order to reduce the adverse effects of intersymbol interference. Equalization circuits can be selected from CTLE (Continuous Time Linear Equalizer) or DFE (Decision Feedback Equalizer).

[0003] However, the current equalization circuit is relatively complex, which affects the input data transmission speed. Summary of the Invention

[0004] The embodiments of the present disclosure provide a data receiving circuit and a semiconductor device, which are at least beneficial in reducing inter-symbol interference problems while reducing circuit complexity and improving input data transmission speed.

[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present disclosure provides a data receiving circuit, comprising: multiple data paths, each of the multiple data paths receives input data and a sampling clock, and the phase of the sampling clock received by each data path is different, the multiple data paths comprising: a 1st data path to an Mth data path numbered in ascending order of natural numbers, the i-th data path being any one of the multiple data paths, 1≤i≤M, M≥2, and the phase difference between the sampling clocks received by any two consecutively numbered data paths from the 1st data path to the Mth data path is the same; wherein the i-th data path comprises: an amplifying circuit, The circuit is configured to amplify the voltage difference between the voltage of the input data and the reference voltage and output a first signal pair; the sampling circuit is configured to receive the corresponding sampling clock, sample the first signal pair and output a second signal pair; the first circuit is configured to receive the second signal pairs output by N data paths, and output a corresponding tap control signal based on all the received second signal pairs, wherein the tap control signal is a multi-bit signal, N≤M; the second circuit is configured to receive the tap control signal and, in response to the tap control signal, adjust the level of the first signal pair in the i-th data path with an adjustment value corresponding to the tap control signal.

[0006] In some embodiments, the first circuit of the i-th data path receives the second signal pair output by at least two of the data paths except the i-1-th data path, and the first circuit of the 1-th data path receives the second signal pair output by at least two of the data paths except the M-th data path; wherein, 1<i≤M, M≥3.

[0007] In some embodiments, the first circuit of the i-1th data path receives the second signal pair output by the i-1th data path and the second signal pair output by the i-th data path; the first circuit of the Mth data path receives the second signal pair output by the 1st data path and the second signal pair output by the Mth data path.

[0008] In some embodiments, the first circuit of the Mth data path receives the second signal pair output by the 1st data path and the second signal pair output by the 2nd data path; the first circuit of the (i-1)th data path receives the second signal pair output by the ith data path and the second signal pair output by the (i+1)th data path, i+1<M; the first circuit of the (M-1)th data path receives the second signal pair output by the 1st data path and the second signal pair output by the Mth data path.

[0009] In some embodiments, M is 4 and the phase difference is 90°.

[0010] In some embodiments, the first circuit of the i-th data path receives the second signal pair including the output of the i-th data path, and the first circuit of the first data path receives the second signal pair including the output of the first data path; wherein 1<i≤M, M≥3.

[0011] In some embodiments, N=M.

[0012] In some embodiments, the second signal pair includes a second data signal and a second complementary data signal, the second data signal and the second complementary data signal are inverted signals of each other, and the second data signal is used to characterize the received input data; the tap control signal includes a first control signal and a second control signal, the adjustment value includes a first adjustment value and a second adjustment value, the first control signal corresponds to the first adjustment value, the second control signal corresponds to the second adjustment value, and the first control signal and the second control signal are both multi-bit signals; wherein the first circuit is further configured to: output the corresponding first control signal based on all the second data signals received; output the corresponding second control signal based on all the second complementary data signals received.

[0013] In some embodiments, the first circuit is further configured to receive a zeroing signal and N tap signals, wherein one tap signal corresponds to one second signal pair; in any second signal pair, the second data signal corresponds to a first sub-signal, and the second complementary data signal corresponds to a second sub-signal, the first sub-signal is one of the zeroing signal and the tap signal, and the second sub-signal is the other of the zeroing signal and the tap signal; wherein the first control signal is obtained by adding the first sub-signals corresponding to all received second data signals; and the second control signal is obtained by adding the second sub-signals corresponding to all received second complementary data signals.

[0014] In some embodiments, each bit of the zero-setting signal is 0, and at least one bit of the tap signal is 1; if the second data signal is 0 and the second complementary data signal is 1, then the first sub-signal is the zero-setting signal, and the second sub-signal is the tap signal; if the second data signal is 1 and the second complementary data signal is 0, then the first sub-signal is the tap signal, and the second sub-signal is the zero-setting signal.

[0015] In some embodiments, the first circuit is further configured to: based on all the second data signals received, select the zeroing signal and / or call the corresponding tap signal from the N tap signals as the first sub-signal, and add all the selected first sub-signals to output the first control signal; based on all the second complementary data signals received, select the zeroing signal and / or call the corresponding tap signal from the N tap signals as the second sub-signal, and add all the selected second sub-signals to output the second control signal.

[0016] In some embodiments, the data receiving circuit further includes: N mode registers, each of the tap signals is stored in a corresponding mode register.

[0017] In some embodiments, the data receiving circuit further includes: a register, in which a plurality of different first control signals and a plurality of different second control signals are stored; the first circuit includes: a selector, configured to call the corresponding first control signal from the register based on all received second data signals and provide the first control signal to the first circuit, and to call the corresponding second control signal from the register based on the received second complementary data signal and provide the second control signal to the first circuit.

[0018] In some embodiments, the data receiving circuit also includes: an adder, configured to obtain 2N tap control signals and store the tap control signals in the register; wherein each tap control signal is an addition operation performed on N zero-setting signals and N signals arbitrarily selected from the N tap signals, and different tap control signals are obtained by adding different N signals.

[0019] In some embodiments, the first signal pair includes a first data signal and a first reference data signal, the amplification circuit includes a first node and a second node, the first node outputs the first data signal, and the second node outputs the first reference data signal; the second circuit includes: a first control circuit, connected between the first node and the ground, turned on or off according to the second control signal, and the first control circuit adjusts the level of the first signal pair with the second adjustment value during the conduction period; a second control circuit, connected between the second node and the ground, turned on or off according to the first control signal, and the second control circuit adjusts the level of the first signal pair with the first adjustment value during the conduction period.

[0020] In some embodiments, the first control circuit includes: a plurality of first NMOS transistors connected in parallel, the gate of each first NMOS transistor receiving one bit of data in the second control signal, and the first NMOS transistors connected between the first node and the ground terminal; the second control circuit includes: a plurality of second NMOS transistors connected in parallel, the gate of each second NMOS transistor receiving one bit of data in the first control signal, and the second NMOS transistors connected between the second node and the ground terminal.

[0021] In some embodiments, the i-th data path further includes: a first adjustment circuit, configured to receive the second signal pair output by the i-1th data path, and adjust the first signal pair in the i-th data path in response to the received second signal pair, wherein if the i-th data path is the 1st data path, the i-1th data path is the Mth data path.

[0022] In some embodiments, the first regulation circuit includes: a first switching circuit and a first compensation circuit, the first switching circuit is connected between the amplification circuit and the first compensation circuit, the first switching circuit is turned on or off according to the received second signal pair, and during the period when the first switching circuit is turned on, the first compensation circuit receives a first tap signal and adjusts the first signal pair with an adjustment value corresponding to the first tap signal.

[0023] In some embodiments, the i-th data path also includes: a second adjustment circuit, configured to receive the second signal pair output by the i-2th data path, and adjust the first signal pair in the i-th data path in response to the received second signal pair, wherein if the i-th data path is the 2nd data path, the i-2nd data path is the M-th data path, and if the i-th data path is the 1st data path, the i-2nd data path is the M-1th data path.

[0024] In some embodiments, the second adjustment circuit includes: a second switching circuit and a second compensation circuit, the second switching circuit is connected between the amplification circuit and the second compensation circuit, the second switching circuit is turned on or off according to the received second signal pair, and during the period when the second switching circuit is turned on, the second compensation circuit receives a second tap signal and adjusts the first signal pair with an adjustment value corresponding to the second tap signal.

[0025] According to some other embodiments of the present disclosure, another aspect of the present disclosure further provides a semiconductor device, comprising the data receiving circuit provided by any of the aforementioned embodiments.

[0026] In some embodiments, the semiconductor device includes a memory chip.

[0027] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0028] In a technical solution for a data receiving circuit provided in an embodiment of the present disclosure, multiple data paths receive sampling clocks with different phases to transmit input data. Each data path includes an amplifier circuit, a sampling circuit, a first circuit, and a second circuit. The first circuit receives the second signal pairs output by the N data paths and outputs corresponding tap control signals. The tap control signals are multi-bit signals that not only indicate the impact of the second signal pairs output by the N data paths on the inter-symbol interference of the currently transmitted input data, but also adjust the level of the first signal pair using the tap control signals in a manner that varies based on the values ​​of different bits in the tap control signals. Therefore, in an embodiment of the present disclosure, the second circuit adjusts the level of the first signal pair output by the amplifier circuit in response to the tap control signals, i.e., performs decision feedback equalization (DFE) to reduce the impact of previously transmitted input data on currently transmitted input data, thereby ensuring the accuracy of input data transmission. Furthermore, the second circuit can also change the step size of the DFE, thus enabling the data receiving circuit to have different DFE capabilities. In addition, compared with the solution of designing a switching circuit and a compensation circuit for each second signal pair, the second circuit of the embodiment of the present disclosure is less complex and the area required for the second circuit is correspondingly smaller, which is beneficial to reducing the load of the data receiving circuit, improving the input data transmission rate, reducing power consumption and transmission delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 is a functional block diagram of a data receiving circuit including a 4-tap equalization circuit;

[0031] Figure 2 for Figure 1 A corresponding architecture diagram;

[0032] Figure 3 for Figure 1 A circuit structure diagram of a 4-tap equalization circuit;

[0033] Figure 4 A functional block diagram of a data receiving circuit provided in an embodiment of the present disclosure;

[0034] Figure 5 for Figure 4 A functional block diagram of the i-th data path in ;

[0035] Figure 6 Another functional block diagram of a data path in a data receiving circuit;

[0036] Figure 7 It is another functional block diagram of a data path in a data receiving circuit;

[0037] Figure 8 Another functional block diagram of a data path in a data receiving circuit;

[0038] Figure 9 Another functional block diagram of a data path in a data receiving circuit;

[0039] Figures 10 to 13 Several different architecture diagrams of data receiving circuits;

[0040] Figure 14 A schematic diagram of a circuit structure of an amplifier circuit and a second circuit in any data path;

[0041] Figure 15 for Figure 14 A circuit structure diagram of the first control circuit and the second control circuit;

[0042] Figure 16 is another circuit structure schematic diagram of the first control circuit and the second control circuit;

[0043] Figure 17 is another circuit structure schematic diagram of the amplifying circuit and the second circuit in any data path;

[0044] Figure 18 A circuit structure diagram of a sampling circuit. DETAILED DESCRIPTION

[0045] Depending on the number of bits of previously transmitted input data participating in the DFE, the equalization circuit in the data receiving circuit can be divided into 1-tap, 2-tap, 3-tap, and 4-tap equalization circuits. The equalization circuit can even have more taps (i.e., the number of taps can be greater than 4). A tap is a tap. It can be understood that the equalization circuit can include multiple tap adjustment circuits, each of which corresponds to a tap signal, and a tap signal corresponds to a bit of data. The currently transmitted input data is adjusted according to the tap signal. Among them, 1-tap refers to the participation of 1 bit of previously transmitted data in the DFE; 2-tap refers to the participation of 2 bits of previously transmitted data in the DFE; 3-tap refers to the participation of 3 bits of previously transmitted data in the DFE; and 4-tap refers to the participation of 4 bits of previously transmitted data in the DFE.

[0046] Typically, each tap adjustment circuit in an equalizer circuit requires a corresponding circuit design. The more taps there are in the equalizer circuit, the larger the circuit volume required for the equalizer circuit, and the corresponding load of the equalizer circuit will also be greater, affecting the DFE feedback speed and increasing the DFE delay. The following will take a 4-tap equalizer circuit as an example to explain. Figure 1 This is a functional block diagram of a data receiving circuit including a 4-tap equalization circuit. Figure 2 for Figure 1 A corresponding architecture diagram, Figure 3 for Figure 1 A circuit structure diagram of a 4-tap equalization circuit.

[0047] refer to Figure 1 and Figure 2 Taking the example of a data receiving circuit sampling and transmitting input data sequentially based on sampling phases of an input data sampling clock DQS of 0°, 90°, 180°, and 270°, the data receiving circuit includes four data paths, each of which includes an amplifier circuit 11, an equalizer circuit 12, and a sampling circuit 13. The amplifier circuit 11 and the equalizer circuit 12 can be integrated into the same module 10. T1, T2, T3, and T4 represent the tap signals of the tap adjustment circuit corresponding to the previous first bit of data, the second bit of data, the third bit of data, and the fourth bit of data, respectively. "Previous" here refers to the currently transmitted input data. The amplifier circuit 11 receives input data IN and a reference voltage VREF. The four sampling circuits 13 output OUT_0, OUT_90, OUT_180, and OUT_270, respectively.

[0048] For the first data path, the sampling phase of the sampling clock DQS is 0°, T1, T2, T3 and T4 are OUT_270, OUT_180, OUT_90 and OUT_0[n-1] respectively, OUT_0[n-1] refers to the input data output by the sampling circuit 13 in the previous clock cycle in response to the sampling clock with a sampling phase of 0°, wherein the previous clock cycle is relative to the sampling moment corresponding to the input data currently transmitted by the first data path; for the second data path, the sampling phase is 90°, T1, T2, T3 and T4 are OUT_0, OUT_270, OUT_180 and OUT_90[n-1] respectively, OUT_90[n-1] refers to the sampling time corresponding to the sampling circuit 13 in response to the sampling clock with a sampling phase of 90°. The sampling phase is 180°, and T1, T2, T3, and T4 are OUT_90, OUT_0, OUT_270, and OUT_180[n-1], respectively. OUT_180[n-1] refers to the input data output by the sampling circuit 13 in the previous clock cycle in response to the sampling clock with a sampling phase of 180°. For the fourth data path, the sampling phase is 270°, and T1, T2, T3, and T4 are OUT_180, OUT_90, OUT_0, and OUT_270[n-1], respectively. OUT_270[n-1] refers to the input data output by the sampling circuit 13 in the previous clock cycle in response to the sampling clock with a sampling phase of 270°.

[0049] Take the equalization circuit of the fourth data path as an example, combined with the reference Figures 1 to 3 The amplifier circuit 11 has a first node N1 and a second node N2. The equalization circuit 12 includes four tap adjustment circuits 4. Each tap adjustment circuit 4 includes: a switch circuit 1 including a first NMOS transistor and a second NMOS transistor, each having a gate that receives one of two differential signals in the input data output by the sampling circuit 13, and a drain that is connected to the first node N1 and the second node N2; a compensation circuit 2 including a third NMOS transistor group and a fourth NMOS transistor group. The third NMOS transistor group includes a plurality of third NMOS transistors connected in parallel, and the fourth NMOS transistor group includes a plurality of fourth NMOS transistors connected in parallel. The gates of the third and fourth NMOS transistors each receive one bit of data in the tap signal. The third NMOS transistor group is connected between the first NMOS transistor and ground, and the fourth NMOS transistor group is connected between the second NMOS transistor and ground. It is understood that in some examples, the third NMOS transistor group and the fourth NMOS transistor group may also be the same NMOS transistor group.

[0050] Among them, for the tap adjustment circuit 4 corresponding to T1, the two differential signals are Tap1_data and Tap1_datab, and the tap signal is Tap1_coeffi<5:0>. Accordingly, the tap signal Tap1_coeffi<5:0> simultaneously controls the third NMOS transistor group and the fourth NMOS transistor group. The tap signal Tap1_coeffi<5:0> is 6-bit data, and each bit controls whether the third NMOS transistor and the fourth NMOS transistor are turned on or off. For the tap adjustment circuit 4 corresponding to T2, the two differential signals are Tap2_data and Tap2_datab, and the tap signal is Tap2_coeffi<4:0>. Accordingly, the tap signal Tap2_coeffi<4:0> simultaneously controls the third NMOS transistor group and the fourth NMOS transistor group. The tap signal Tap2_coeffi<4:0> is 5-bit data, and each bit controls whether the third NMOS transistor and the fourth NMOS transistor are turned on or off. No; for the tap adjustment circuit 4 corresponding to T3, the two differential signals are Tap3_data and Tap3_datab, and the tap signal is Tap3_coeffi<4:0>. Accordingly, the tap signal Tap3_coeffi<4:0> simultaneously controls the third NMOS transistor group and the fourth NMOS transistor group. The tap signal Tap3_coeffi<4:0> is 5-bit data, and each bit controls whether the third NMOS transistor and the fourth NMOS transistor are turned on or off. For the tap adjustment circuit 4 corresponding to T4, the two differential signals are Tap4_data and Tap4_datab, and the tap signal is Tap4_coeffi<3:0>. Accordingly, the tap signal Tap4_coeffi<3:0> simultaneously controls the third NMOS transistor group and the fourth NMOS transistor group. The tap signal Tap4_coeffi<3:0> is 4-bit data, and each bit controls whether the third NMOS transistor and the fourth NMOS transistor are turned on or off. Figure 3 The specific circuit structure of the NMOS transistors controlled by the data bits in Tap3_coeffi<4:0> and Tap4_coeffi<3:0> is also shown. For the convenience of illustration, they are marked with 01 and 02.

[0051] From the above analysis, it can be seen that for any data path, the number of tap adjustment circuits 4 required is the same as the number of bits of input data participating in the DFE. The more bits of input data participating in the DFE, the larger the number of corresponding tap adjustment circuits 4, and the larger the area occupied by the corresponding tap adjustment circuits 4 in the data receiving circuit. This will affect the transmission speed of the input data and slow the speed of DFE feedback, that is, the DFE delay will also increase. In addition, the total number of third NMOS transistor groups and fourth NMOS transistor groups in the corresponding tap adjustment circuit will also increase, increasing the load on the data receiving circuit, which will also affect the transmission speed of the input data of the data receiving circuit. In addition, the third NMOS transistor group and fourth NMOS transistor group in each compensation circuit 2 include multiple parallel NMOS transistors for adjusting the amplitude (step) of the DFE. When the number of NMOS transistors is large, the load of the data receiving circuit is affected, resulting in a corresponding increase in the power consumption of the data receiving circuit.

[0052] Embodiments of the present disclosure provide a data receiving circuit that outputs a corresponding tap control signal based on multiple bits of previously transmitted input data. The tap control signal is a multi-bit signal. A second circuit, in response to the tap control signal, performs decision feedback equalization on the currently transmitted input data to reduce the impact of inter-symbol interference (ISI). This reduces the complexity of the circuits required to implement DFE, thereby reducing circuit area and circuit load, thereby reducing power consumption of the data receiving circuit and improving input data transmission speed. Furthermore, because the tap control signal is a multi-bit signal, each bit of the tap control signal can be flexibly set to be 0 or 1. Adjustment of the DFE value for the first signal pair, i.e., the amplitude of the DFE, can be adjusted based on the adjustment of different bits of data.

[0053] Figure 4 A functional block diagram of a data receiving circuit provided in an embodiment of the present disclosure is shown. Figure 5 for Figure 4 A functional block diagram of the i-th data path in .

[0054] refer to Figure 4 and Figure 5In an embodiment of the present disclosure, a data receiving circuit includes: a plurality of data paths 100, each of which receives input data IN and a sampling clock CLK, and the sampling clock CLK received by each data path 100 has a different phase. The plurality of data paths 100 include: a 1st data path to an Mth data path numbered in ascending order of natural numbers, the i-th data path being any data path 100 in the plurality of data paths 100, 1≤i≤M, M≥2, and the phase difference between the sampling clock CLK received by any two consecutively numbered data paths 100 from the 1st data path to the Mth data path is the same; wherein the i-th data path includes: an amplifier circuit 101 configured to amplify the voltage of the input data IN and a reference voltage VREF and output the first signal pair OUT1; the sampling circuit 102 is configured to receive the corresponding sampling clock CLK, sample the first signal pair OUT1 and output the second signal pair OUT2; the first circuit 103 is configured to receive the second signal pair OUT2 output by N data paths, and output the corresponding tap control signal TapA based on all the received second signal pairs OUT2, the tap control signal TapA is a multi-bit signal, N≤M; the second circuit 104 is configured to receive the tap control signal TapA, and in response to the tap control signal TapA, adjust the level of the first signal pair OUT1 in the i-th data path with an adjustment value corresponding to the tap control signal TapA.

[0055] In the aforementioned data receiving circuit, for any data path 100, the second signal pair OUT2 output by the N data paths 100 is the previously transmitted input data IN. The N previously transmitted input data IN can participate in adjusting the first signal pair OUT1 transmitted by the data path 100 to reduce interference of the previously transmitted input data IN on the data path 100 currently transmitting the input data IN, thereby implementing the DFE function. In addition, the first circuit 103 receives the second signal pair OUT2 output by the N data paths 100 and outputs the tap control signal TapA, so that the influence of the previously transmitted N input data IN on the currently transmitted input data IN is converted into the influence of the tap control signal TapA on the currently transmitted input data IN, and the numerical value of the multi-bit signal of the tap control signal TapA is adjustable, so that the adjustment value corresponding to the tap control signal TapA is adjustable, and thus the ability of the second circuit 104 to perform decision feedback equalization on the first signal pair OUT in response to the tap control signal TapA is adjustable; accordingly, the second circuit 104 responds to the tap control signal TapA to adjust the first signal pair OUT1 in the data path 100 of the currently transmitted input data IN, thereby reducing the inter-code interference of the previously transmitted N input data IN on the data path 100 of the currently transmitted input data IN, and improving the accuracy of the input data IN transmission. Second circuit 104 can adjust data in response to multiple previously transmitted input data IN. This eliminates the need for designing a separate switching circuit for each previously transmitted input data IN that requires DFE. This reduces the complexity and size of the circuitry required to implement the DFE function, thereby reducing the load on second circuit 104, improving the adjustment speed of first signal pair OUT1, and reducing the delay in adjusting the first signal pair OUT1. This ensures that all previously transmitted multiple bits of input data IN participate in DFE, thereby improving the transmission accuracy of the input data IN, while also reducing the load on the data receiving circuit and increasing the transmission speed of the input data IN. Furthermore, in the disclosed embodiment, for multiple previously transmitted input data, since tap control signal TapA is a multi-bit signal, each bit of the multi-bit signal is adjustable. Therefore, the same second circuit 104 can be used to adjust the first signal pair OUT1 using different adjustment values. This eliminates the need for a compensation circuit for adjusting the DFE amplitude for each received input data IN. This reduces the number of compensation circuits, further reducing the complexity of the data receiving circuit, further reducing the load, and consequently, further reducing power consumption.

[0056] The data receiving circuit provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0057] The data receiving circuit can be applied to a memory, which can be a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). In some embodiments, the data receiving circuit can be applied to an SDRAM (Synchronous Dynamic Random Access Memory), which can be a DDR (Double Data Rate) SDRAM, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory.

[0058] refer to Figure 5 In some embodiments, the second signal pair OUT2 includes a second data signal OUT2_O and a second complementary data signal OUT2_E, and the second data signal OUT2_O and the second complementary data signal OUT2_E are mutually inverted signals. The second data signal OUT2_O is used to represent the received input data IN. In other words, the level of the second data signal OUT2_O is used to reflect the level of the input data IN. That is, if the input data IN is 0, the second data signal OUT2_O is 0, and if the input data IN is 1, the second data signal OUT2_O is 1. Accordingly, the tap control signal TapA includes a first control signal TapA1 and a second control signal TapA2. The adjustment value includes a first adjustment value and a second adjustment value. The first control signal corresponds to the first adjustment value, and the second control signal corresponds to the second adjustment value. Both the first control signal and the second control signal are multi-bit signals.

[0059] In some examples, reference Figure 5The first signal pair OUT1 may include a first data signal OUT1_O and a first reference data signal OUT1_E. Accordingly, the amplifier circuit 101 includes a first node net1 and a second node net2. The first node net1 outputs the first data signal OUT1_O, and the second node net2 outputs the first reference data signal OUT1_E. If the input data IN is 1, the voltage (also called the level) of the input data IN is greater than the reference voltage VREF, the voltage of the first data signal OUT1_O is less than the voltage of the first reference data signal OUT1_E, and the corresponding voltage of the second data signal OUT2_O is greater than the voltage of the second complementary data signal OUT2_E. If the input data IN is 0, the voltage of the input data IN is less than the reference voltage, the voltage of the first data signal OUT1_O is greater than the voltage of the first reference data signal OUT1_E, and the corresponding voltage of the second data signal OUT2_O is less than the voltage of the second complementary data signal OUT2_E. The second circuit 104 adjusts the voltage of the second node net2 in response to the first control signal TapA1, that is, the second circuit 104 adjusts the first reference data signal OUT1_E in response to the first control signal TapA1; the second circuit 104 adjusts the voltage of the first node net1 in response to the second control signal TapA2, that is, the second circuit 104 adjusts the first data signal OUT1_O in response to the second control signal TapA2.

[0060] It will be appreciated that, in a specific embodiment, the amplifier circuit 101 can be configured to discharge between the first node net1 and ground in response to input data IN, i.e., the voltage of the first node net1 (the voltage of the first data signal OUT1_O) is pulled down. The higher the voltage of the input data IN, the faster the first node net1 is pulled down, i.e., the faster the discharge rate between the first node net1 and ground. The amplifier circuit 101 can also be configured to amplify between the second node net2 and ground in response to a reference voltage VREF, i.e., the voltage of the second node net2 (the voltage of the first reference data signal OUT1_E) is pulled down. The reference voltage VREF can be a fixed value. Accordingly, if the second circuit 104 does not adjust the second node net2, the reference voltage VREF has no effect on the discharge rate between the second node net2 and ground. It will be appreciated that, before the first node net1 and the second node net2 are discharged, the voltage levels of the first node net1 and the second node net2 are the same, or the difference is negligible. In other words, the voltage levels of the first node net1 and the second node net2 before discharge are comparable.

[0061] Accordingly, the second circuit 104 can adjust the level of the second node net2 in response to the first control signal TapA1. In other words, the second circuit 104 can control the speed at which the level of the second node net2 is pulled down in response to the first control signal TapA1. The second circuit 104 can also adjust the level of the first node net1 in response to the second control signal TapA2. In other words, the second circuit can control the speed at which the level of the first node net1 is pulled down in response to the second control signal TapA2. In this way, the level difference between the first node net1 and the second node net2 can be further widened, thereby improving the accuracy of input data IN transmission.

[0062] In another specific embodiment, the amplifier circuit 101 can be configured to charge the first node net1 in response to input data IN, i.e., the voltage of the first node net1 (the voltage of the first data signal OUT1_O) is pulled high. The lower the voltage of the input data IN, the faster the first node net1 is pulled high, i.e., the faster the first node net1 is charged. The amplifier circuit 101 can also be configured to charge the second node net2 in response to a reference voltage VREF, i.e., the voltage of the second node net2 (the voltage of the first reference data signal OUT1_E) is pulled high. The reference voltage VREF can be a fixed value. Accordingly, if the second circuit 104 does not adjust the second node net2, the charging speed of the second node net2 remains unchanged. It is understood that before the first node net1 and the second node net2 are charged, the voltage levels of the first node net1 and the second node net2 are the same, or the difference is negligible. In other words, the voltage levels of the first node net1 and the second node net2 before charging are comparable.

[0063] Accordingly, the second circuit 104 can adjust the voltage level of the second node net2 in response to the first control signal TapA1. In other words, the second circuit 104 can control the speed at which the voltage level of the second node net2 is pulled up in response to the first control signal TapA1. The second circuit 104 can also adjust the voltage level of the first node net1 in response to the second control signal TapA2. In other words, the second circuit can control the speed at which the voltage level of the first node net1 is pulled up in response to the second control signal TapA2. In this way, the voltage level difference between the first node net1 and the second node net2 can be further widened, thereby improving the accuracy of input data IN transmission.

[0064] The first circuit 103 can also be configured to output a corresponding first control signal TapA1 based on all received second data signals OUT2_O, and to output a corresponding second control signal TapA2 based on all received second complementary data signals OUT2_E. In other words, the first control signal TapA1 is derived based on the received second data signals OUT2_O, and the second control signal TapA2 is derived based on the received second complementary data signals OUT2_E.

[0065] The first circuit 103 can also be configured to receive a zero signal and N tap signals, wherein the tap signal corresponds to a second signal pair OUT2; in any second signal pair OUT2, the second data signal OUT2_O corresponds to the first sub-signal, and the second complementary data signal OUT2_E corresponds to the second sub-signal, the first sub-signal is one of the zero signal and the tap signal, and the second sub-signal is the other of the zero signal and the tap signal. The tap signal is a multi-bit signal, and the number of bits in different tap signals can be the same or different. If the value of each bit in the tap signal changes, the ability to adjust the decision feedback equalization performed on the first signal pair OUT1 will change.

[0066] The first control signal TapA1 is obtained by adding the first sub-signals corresponding to all received second data signals OUT2_O; the second control signal TapA2 is obtained by adding the second sub-signals corresponding to all received second complementary data signals OUT2_E.

[0067] The second circuit 104 can be turned off in response to each bit of data in the zeroing signal, and can be turned on in response to at least one bit of data in the tap signal. In other words, the bit data of the zeroing signal can be appropriately set based on the specific circuit structure of the second circuit 104. If the second circuit 104 is composed of an NMOS transistor, the bit data of the zeroing signal is all 0, and the corresponding at least one bit of data in the tap signal is 1. If the second circuit 104 is composed of a PMOS transistor, the bit data of the zeroing signal is all 1, and the corresponding at least one bit of data in the tap signal is 0.

[0068] In some examples, each bit of the zero-set signal can be 0, and at least one bit of the tap signal can be 1. That is, the second circuit 104 is turned off in response to a "0" in the zero-set signal, and is turned on in response to a "1" in the tap signal. It will be appreciated that if the second data signal OUT2_O is 0 and the second complementary data signal OUT2_E is 1, the first sub-signal is the zero-set signal and the second sub-signal is the tap signal. If the second data signal OUT2_O is 1 and the second complementary data signal OUT2_E is 0, the first sub-signal is the tap signal and the second sub-signal is the zero-set signal.

[0069] In other examples, each bit of the zero-set signal can be 1, and at least one bit of the tap signal can be 0. That is, the second circuit 104 is turned off in response to a "1" in the zero-set signal, and is turned on in response to a "1" in the tap signal. It will be appreciated that if the second data signal OUT2_O is 1 and the second complementary data signal OUT2_E is 0, the first sub-signal is the zero-set signal and the second sub-signal is the tap signal; if the second data signal OUT2_O is 0 and the second complementary data signal OUT2_E is 1, the first sub-signal is the tap signal and the second sub-signal is the zero-set signal.

[0070] The following describes the relationship between the first control signal, the second control signal, the zeroing signal, and the tap signal by taking an example in which each bit of data in the zeroing signal is 0 and at least one bit of data in the tap signal is 1.

[0071] Refer to Tables 1 through 3-2. The second data signals OUT2_O in the second signal pairs OUT2 output by the four different data paths are defined as Tap1_data, Tap2_data, Tap3_data, and Tap4_data, respectively. Code0 is a zero signal, and Code1, Code2, Code3, and Code4 are the corresponding tap signals when Tap1_data, Tap2_data, Tap3_data, and Tap4_data are 1, respectively. Taking Tap3_data as an example, if the second data signal Tap3_data is 0, the first sub-signal is the zero signal Code0, and the second sub-signal is the tap signal Code3. If the second data signal Tap3_data is 1, the first sub-signal is the tap signal Code3, and the second sub-signal is the zero signal Code0. For details on the first and second sub-signals corresponding to Tap1_data, Tap2_data, and Tap4_data, refer to the description of Tap3_data. In the following tables, "+" indicates addition.

[0072] Referring to Table 1, taking N=2 as an example, the first circuit of the i-th data path receives two second signal pairs, and Tap3+Tap4 are four different situations of the second data signals of the two second signal pairs:

[0073] Table 1

[0074]

[0075] As can be seen from Table 1, when the two received second data signals are 00, the first sub-signals corresponding to Tap3_data and Tap4_data are both zero signals code0, the corresponding two second complementary data signals are 11, and the corresponding second sub-signals are code3 and code4, respectively. Then the first control signal TapA1 is code0+code0, and the second control signal TapA2 is code3+code4; when the two received second data signals are 01, the first sub-signal corresponding to Tap3_data is code0, and the first sub-signal corresponding to Tap4_data is code4, the corresponding two second complementary data signals are 10, and the corresponding second sub-signals are code3 and code0, respectively. Then the first control signal TapA1 is code0+code4, and the second control signal TapA2 is code3+code0; If the two received second data signals are 10, the first sub-signal corresponding to Tap3_data is code3, the first sub-signal corresponding to Tap4_data is code0, the corresponding two second complementary data signals are 01, and the corresponding second sub-signals are code0 and code4 respectively. Then the first control signal TapA1 is code3+code0, and the second control signal TapA2 is code0+code4; if the two received second data signals are 11, the first sub-signal corresponding to Tap3_data is code3, the first sub-signal corresponding to Tap4_data is code4, the corresponding two second complementary data signals are 00, and the corresponding second sub-signals are code0 and code0 respectively. Then the first control signal TapA1 is code3+code4, and the second control signal TapA2 is code0+code0.

[0076] In addition, Table 1 also provides a specific example, where code 3 is 00010 and code 4 is 00001, and provides specific signals of the corresponding first control signal TapA1 and the second control signal TapA2.

[0077] Referring to Table 2-1 and Table 2-2, taking N=3 as an example, the first circuit of the i-th data path receives three second signal pairs, and Tap2+Tap3+Tap4 are multiple different situations of the second data signals of the three second signal pairs:

[0078] Table 2-1

[0079]

[0080] Table 2-2

[0081]

[0082] Referring to Table 3-1 and Table 3-2, taking N=4 as an example, the first circuit of the i-th data path receives four second signal pairs, and Tap1+Tap2+Tap3+Tap4 are multiple different situations of the second data signals of the four second signal pairs:

[0083] Table 3-1

[0084]

[0085] Table 3-2

[0086]

[0087]

[0088] For specific circuit implementation of obtaining the first control signal TapA1 and the second control signal TapA2 based on the received N second signal pairs OUT2 and N tap signals, please refer to the subsequent detailed description.

[0089] Figure 6 Another disclosed block diagram of any data path in a data receiving circuit. Figure 6 In some embodiments, the first circuit 103 of the i-th data path 100 is configured to select a zero signal and / or call a corresponding tap signal from N tap signals as a first sub-signal based on all received second data signals OUT2_O, and add all the selected first sub-signals to output a first control signal TapA1; and is also configured to select a zero signal and / or call a corresponding tap signal from N tap signals as a second sub-signal based on all received second complementary data signals OUT2_E, and add all the selected second sub-signals to output a second control signal TapA2.

[0090] For the principles for obtaining the first sub-signal and the second sub-signal, please refer to the detailed description above and will not be repeated here. In a specific example, if a second data signal OUT2_O is 0, the first sub-signal corresponding to this second data signal OUT2_O is a zero signal, and the corresponding second complementary data signal OUT2_E is 1, then the second sub-signal corresponding to this second complementary data signal OUT2_E is a corresponding tap signal; if another second data signal OUT2_O is 1, then the first sub-signal corresponding to this second data signal OUT2_O is a corresponding tap signal, and the corresponding second complementary data signal OUT2_E is 0, then the second sub-signal corresponding to this second complementary data signal OUT2_E is a zero signal. In other words, the first circuit 103 of the i-th data path can select an appropriate zero signal and / or tap signal based on the received N second signal pairs OUT2 and perform an addition operation to obtain the corresponding first control signal TapA1 and second control signal TapA2.

[0091] refer to Figure 6 The data receiving circuit may further include: N mode registers 106 , each tap signal being stored in a corresponding mode register 106 .

[0092] refer to Figure 7 In other examples, the data receiving circuit may further include: a register 107, wherein the register 107 stores a plurality of different first control signals TapA1 and a plurality of different second control signals TapA2; the first circuit 103 may include a selector 108, wherein the selector 108 is configured to call the corresponding first control signal TapA1 from the register 107 based on all received second data signals OUT2_O and provide the first control signal TapA1 to the first circuit 103, and call the corresponding second control signal TapA2 from the register 107 based on the received second complementary data signal OUT2_E and provide the second control signal TapA2 to the first circuit 103.

[0093] Since the different first control signals TapA1 and second control signals TapA2 are pre-stored in register 107, first circuit 103 only needs to use selector 108 to call the corresponding first control signals TapA1 and second control signals TapA2 and output the called first control signals TapA1 and second control signals TapA2 to second circuit 104. This can save time for addition operations, thereby further improving the feedback speed of the DFE and the transmission speed of the input data IN. It will be understood that in some examples, selector 107 and first circuit 103 can be independent circuit modules, and in other examples, selector 107 and first circuit 103 can also be the same circuit module.

[0094] Continue to refer Figure 7 The data receiving circuit may further include: an adder 109 configured to obtain 2 N A tap control signal TapA is generated and the tap control signal TapA is stored in register 107; wherein each tap control signal TapA is obtained by adding N zero-set signals and N signals arbitrarily selected from the N tap signals, and different tap control signals TapA are obtained by adding different N signals.

[0095] That is, 2 N The tap control signal TapA includes the aforementioned multiple different first control signals TapA1 and multiple different second control signals TapA2 stored in register 107. Taking N as an example, adder 109 will obtain four tap control signals; taking N as an example, adder 109 will obtain eight tap control signals; taking N as an example, adder 109 will obtain 16 tap control signals. The following will explain the principle of how second circuit 104 adjusts the first signal pair OUT1:

[0096] Specifically, if all received second data signals OUT2_O are 0, all corresponding received second complementary data signals OUT2_E are 1, each bit of the first control signal TapA1 is 0, at least one bit of the second control signal TapA2 is 1, and the second circuit 104 can be active as a high-level signal, then the second circuit 104 adjusts the level of the first node net1 in response to the second control signal TapA2. Under this premise, there are two situations:

[0097] If the input data IN received by the i-th data path is 0, all second data signals OUT2_O received by the first circuit 103 are identical to the currently transmitted input data IN. Although no inter-symbol interference is caused, in this case, the second circuit 104 still adjusts the level of the first node net1 in response to the second control signal TapA2, lowering the level of the first data signal OUT1_O at the first node net1 by a second adjustment value. The second adjustment value is related to each bit of the second control signal TapA2. Alternatively, the input data IN received by the i-th data path is 1, that is, the currently transmitted input data is different from all second data signals OUT2_O received by the first circuit 103. In this case, decision feedback equalization adjustment is required. The second circuit 104 adjusts the level of the first node net1 in response to the second control signal TapA2 to lower the level of the first data signal OUT1_O. That is, the speed at which the level of the first node net1 is lowered is accelerated, thereby further widening the level difference between the first data signal OUT1_O and the first reference data signal OUT1_E, so that the input data "1" is transmitted more accurately. In addition, the second circuit 104 lowers the level of the first data signal OUT1_O at the first node net1 by a second adjustment value. The second adjustment value is related to each bit data of the second control signal TapA2. The size of the second adjustment value can be changed according to whether the each bit data of the second control signal TapA2 is adjusted to 0 or 1, that is, the ability to perform decision feedback equalization can be changed.

[0098] If all received second data signals OUT2_O are 1, then all corresponding received second complementary data signals OUT2_E are 0, at least one bit of the first control signal TapA1 is 1, and every bit of the second control signal TapA2 is 0, the second circuit 104 can be active as a high-level signal. In this case, the second circuit 104 adjusts the level of the second node net2 in response to the first control signal TapA1. Under this premise, there are two situations:

[0099] The input data IN received by the i-th data path is 0, i.e., the currently transmitted input data is different from all second data signals OUT2_O received by the first circuit 103. Decision feedback equalization adjustment is required at this time. The second circuit 104 adjusts the level of the second node net2 in response to the first control signal TapA1, and adjusts the level of the second node net2 by a first adjustment value corresponding to the first control signal TapA1, so that the level of the first reference data signal OUT1_E becomes lower. That is, the voltage of the second node net2 is pulled down faster, thereby further widening the level difference between the first data signal OUT1_O and the first reference data signal OUT1_E, so that the input data "0" is transmitted more accurately. Moreover, the first adjustment value is related to each bit of the first control signal TapA1. Depending on whether the adjusted bits of the first control signal TapA1 are 0 or 1, the magnitude of the first adjustment value can be changed, that is, the ability to perform decision feedback equalization can be changed. Alternatively, if the input data IN received by the i-th data path is 1, that is, the currently transmitted input data is the same as all the second data signals OUT2_O received by the first circuit 103, then all the second data signals OUT2_O received by the first circuit 103 will not cause inter-symbol interference. In this case, the second circuit 104 will still pull down the level of the second node net2 in response to the first control signal TapA1.

[0100] If all received second data signals OUT2_O contain at least one 1 and at least one 0, then all corresponding received second complementary data signals OUT2_E contain at least one 1 and at least one 0, at least one bit of data in the first control signal TapA1 is 1, at least one bit of data in the second control signal TapA2 is 1, and the second circuit 104 can be active high, then the second circuit 104 adjusts the level of the second node net2 by the corresponding first adjustment value in response to the first control signal TapA1, and the second circuit 104 adjusts the level of the first node net1 by the corresponding second adjustment value in response to the second control signal TapA2. Under this premise, the following two situations exist:

[0101] The input data IN received by the i-th data path is 0, i.e., the currently transmitted input data IN is different from at least one of all second data signals OUT2_O received by the first circuit 103. In response to the first control signal TapA1, the second circuit 104 adjusts the level of the second node net2 by the corresponding first adjustment value, thereby accelerating the rate at which the voltage of the second node net2 is pulled down. Furthermore, in response to the second control signal TapA2, the second circuit 104 adjusts the level of the first node net1 by the corresponding second adjustment value, thereby accelerating the rate at which the level of the first node net1 is pulled down. By properly setting the bits of data in the first control signal TapA1 and the second control signal, i.e., properly setting the first adjustment value and the second adjustment value, the speed difference is increased while ensuring that the level of the first node net1 is pulled down slower than the level of the second node net2. This ensures that the level of the first data signal OUT1_O is greater than the level of the first reference data signal OUT1_E, while also increasing the voltage difference between the first data signal OUT1_O and the first reference data signal OUT1_E, thereby more accurately transmitting the input data "0."

[0102] Alternatively, the input data IN received by the i-th data path is 1, i.e., the currently transmitted input data is different from at least one of all second data signals OUT2_O received by the first circuit 103. In response to the first control signal TapA1, the second circuit 104 adjusts the level of the second node net2 by the first adjustment value, thereby accelerating the speed at which the level of the second node net2 is pulled down. Furthermore, in response to the second control signal TapA2, the second circuit 104 adjusts the level of the first node net1 by the second adjustment value, thereby also accelerating the speed at which the level of the first node net1 is pulled down. By properly setting the bits of data in the first control signal TapA1 and the second control signal TapA2, i.e., properly setting the first adjustment value and the second adjustment value, the speed difference is increased while ensuring that the speed at which the level of the first node net1 is pulled down is greater than the speed at which the level of the second node net2 is pulled down. Thus, while ensuring that the level of the first data signal OUT1_O is less than the level of the first reference data signal OUT1_E, the voltage difference between the first data signal OUT1_O and the first reference data signal OUT1_E is increased, thereby more accurately transmitting the input data "1."

[0103] It can be understood that if the first control signal TapA1 and the second control signal TapA2 are both 1, the speed at which the levels of the first node net1 and the second node net2 are pulled down becomes faster, which is beneficial to improving the transmission speed of the input data IN, that is, reducing the time required for the sampling circuit 102 to output the second signal pair OUT2.

[0104] The above-mentioned "0" means that the level of the corresponding signal is a low level, which is defined as logic "0", and "1" means that the level of the corresponding signal is a high level, which is defined as logic "1". In addition, "low level" and "high level" are level values ​​relative to a reference level, that is, a level higher than the reference level is a high level, and a level lower than the reference level is a low level.

[0105] In some embodiments, the data receiving circuit may be a two-ended transmission circuit, i.e., the second signal pair OUT2 output by the data receiving circuit includes a second data signal OUT2_O and a second complementary data signal OUT2_E, which are mutually inverted. It will be appreciated that in other embodiments, the data receiving circuit may also be a single-ended transmission circuit, and accordingly, the second signal pair may also include a second data signal and a second complementary data signal, wherein the second data signal is the signal actually output by the sampling circuit, and the second complementary data signal is a signal obtained by inverting the output second data signal. Accordingly, the i-th data path may also include an inverting circuit for generating a second complementary data signal based on the second data signal.

[0106] The data receiving circuit includes M data paths, where M is greater than or equal to 2. For example, the data receiving circuit may include two data paths having two sampling clocks with different phases, three data paths having three sampling clocks with different phases, four data paths having four sampling clocks with different phases, or six or eight data paths having six or eight sampling clocks with different phases.

[0107] In some embodiments, the first circuit 103 of the (i)th data path 100 can receive the second signal pair OUT2 output by at least two data paths 100 other than the (i-1)th data path 100, and the first circuit 103 of the (1)th data path 100 can receive the second signal pair OUT2 output by at least two data paths 100 other than the (M)th data path 100, where 1<i≤M, and M≥3. Because the second signal pair OUT2 output by the (i-1)th data path 100 is the input data signal closest in time to the currently transmitted input data, the second signal pair OUT2 output by the (i-1)th data path 100 causes the most severe inter-symbol interference (ISI) on the input data IN to be transmitted by the (i)th data path 100. Therefore, an independent first adjustment circuit can be designed for the second signal pair OUT2 output by the (i-1)th data path 100. The first adjustment circuit adjusts the first signal pair OUT1 of the (i)th data path 100 in response to the second signal pair OUT2 output by the (i-1)th data path 100, thereby further improving the effectiveness of eliminating ISI.

[0108] In a specific example, M=3, the first circuit 103 of the second data path 100 can receive the second signal pair OUT2 outputted by the second data path 100 and the third data path 100, respectively. The first circuit 103 of the third data path 100 can receive the second signal pair OUT2 outputted by the first data path 100 and the third data path 100, respectively. It is understood that the first circuit 103 of the third data path 100 can receive the second signal pair OUT2 outputted by the first data path 100 and the third data path 100, respectively. The third data path 100 receives the input data signal at the current moment, while the first circuit 103 receives the second signal pair OUT2 outputted by the third data path 100 in the previous clock cycle. For example, the third data path 100 receives input data IN to be sampled and outputted during the sampling phase of the second clock cycle, while the first circuit 103 of the third data path 100 receives the second signal pair OUT2 sampled and outputted during the sampling phase of the first clock cycle. It should be noted that subsequent similar descriptions can refer to the description herein and will not be repeated here.

[0109] In some examples, M≥4, the first circuit 103 of the i-th data path 100 receives the second signal pairs OUT2 output by all data paths 100 except the (i-1)-th data path 100, and the first circuit 103 of the first data path 100 receives the second signal pairs OUT2 output by all data paths 100 except the (M)-th data path 100. That is, except for the second signal pair OUT2 output by the (i-1)-th data path 100, the second signal pairs OUT2 output by all other data paths 100 are used to generate the tap control signal TapA corresponding to the i-th data path 100; except for the second signal pair OUT2 output by the (M)-th data path 100, the second signal pairs OUT2 output by all other data paths 100 are used to generate the tap control signal TapA corresponding to the first data path 100. In a specific example, M=4, the first circuit 103 of the second data path 100 can receive the three second signal pairs OUT2 outputted by the second data path 100, the third data path 100 and the fourth data path 100 respectively; the first circuit 103 of the third data path 100 can receive the second signal pairs OUT2 outputted by the first data path 100, the third data path 100 and the fourth data path 100 respectively; the first circuit 103 of the fourth data path 100 can receive the second signal pairs OUT2 outputted by the first data path 100, the second data path 100 and the fourth data path 100 respectively.

[0110] In other examples, the first circuit 103 of the (i-1)th data path 100 receives the second signal pair OUT2 output by the (i-1)th data path 100 and the second signal pair OUT2 output by the (i)th data path 100; the first circuit 103 of the (M)th data path 100 receives the second signal pair OUT2 output by the (1)th data path 100 and the second signal pair OUT2 output by the (M)th data path 100. The benefits of such a setting include: for the i-1th data path 100, compared with the remaining data paths 100, the second signal pair OUT2 output by the i-1th data path 100 and the i-th data path 100 causes less inter-code interference to the i-1th data path 100, and therefore the two second signal pairs OUT2 with smaller inter-code interference are selected to obtain the tap control signal TapA, which is conducive to further ensuring that the ability to improve inter-code interference is further improved while reducing the complexity of the equalization circuit. For the i-1th data path 100, an independent adjustment circuit can be designed for the second signal pair OUT2 output by the remaining data paths 100 other than the i-1th data path 100 and the i-th data path 100, and the adjustment circuit adjusts the first signal pair OUT1 of the i-1th data path 100 in response to the received second signal pair OUT2.

[0111] For example, M=4, and the first circuit 103 of the second data path 100 can receive the second signal pair OUT2 outputted by the second data path 100 and the third data path 100 , respectively. The benefits of this arrangement include: compared to the fourth data path 100, the second signal pair OUT2 output by the second data path 100 and the third data path 100 causes less inter-symbol interference on the second data path 100. Therefore, selecting the two second signal pairs OUT2 with less inter-symbol interference to obtain the tap control signal TapA helps further ensure that the ability to improve inter-symbol interference is further improved while reducing circuit complexity. For the second data path 100, an independent first adjustment circuit can be designed for the second signal pair OUT2 output by the first data path 100, and an independent second adjustment circuit can be designed for the second signal pair OUT2 output by the fourth data path 100. The first adjustment circuit adjusts the first signal pair OUT1 of the second data path 100 in response to the second signal pair OUT2 output by the first data path 100, and the second adjustment circuit adjusts the first signal pair OUT1 of the second data path 100 in response to the second signal pair OUT2 output by the fourth data path 100. It can be understood that the first circuit 103 of the second data path 100 can receive any two second signal pairs OUT2 of the three second signal pairs OUT2 output by the second data path 100, the third data path 100 and the fourth data path 100 respectively. For example, the first circuit 103 of the second data path 100 can also receive the second signal pairs OUT2 output by the second data path 100 and the fourth data path 100 respectively, or receive the second signal pairs OUT2 output by the third data path 100 and the fourth data path 100 respectively, or receive the second signal pairs OUT2 output by the second data path 100 and the third data path 100 respectively.

[0112] M=4, the first circuit 103 of the third data path 100 can receive any two second signal pairs OUT2 of the three second signal pairs OUT2 outputted respectively by the first data path 100, the third data path 100 and the fourth data path 100, for example, the first circuit 103 of the fourth data path 100 can receive the second signal pairs OUT2 outputted respectively by the third data path 100 and the fourth data path 100; the first circuit 103 of the fourth data path 100 can receive the second signal pairs OUT2 outputted respectively by the first data path 100, the second data path 100 and the fourth data path 100. Any two second signal pairs OUT2 among the three second signal pairs OUT2 can be received, for example, the second signal pairs OUT2 outputted by the first data path 100 and the fourth data path 100, respectively. The first circuit 103 of the first data path 100 can receive any two second signal pairs OUT2 among the three second signal pairs OUT2 outputted by the first data path 100, the second data path 100, and the third data path 100, respectively. For example, the second signal pairs OUT2 outputted by the first data path 100 and the second data path 100 can be received. For the effects of this configuration, please refer to the corresponding description in the previous paragraph and will not be repeated here.

[0113] It will be appreciated that in the above example, for any data path 100, the previously transmitted 4-bit data can all participate in the decision feedback equalization of the currently transmitted input data, i.e., the data receiving circuit has a 4-tap equalization circuit. In other examples, for any data path 100, the previously transmitted 3-bit data can also be set to participate in the decision feedback equalization of the currently transmitted input data, i.e., the data receiving circuit has a 3-tap equalization circuit. Accordingly, the first circuit 103 of the i-th data path 100 can receive the second signal pair OUT2 output by the two data paths 100 other than the (i-1)th data path 100 and the i-th data path 100, and the first circuit 103 of the first data path 100 can receive the second signal pair OUT2 output by the two data paths 100 other than the first data path 100 and the M-th data path 100.

[0114] In some embodiments, the first circuit 103 of the Mth data path 100 can receive the second signal pair OUT2 output by the second data path 100 and the second signal pair OUT2 output by the third data path 100; the first circuit 103 of the (i-1)th data path 100 receives the second signal pair OUT2 output by the i-th data path 100 and the second signal pair OUT2 output by the (i+1)th data path 100, where i+1 < M; and the first circuit 103 of the (M-1)th data path 100 receives the second signal pair OUT2 output by the first data path 100 and the second signal pair OUT2 output by the Mth data path 100. The sampling clock CLK can still have four different phases, i.e., M can be 4.

[0115] Regarding the solution in which the data receiving circuit has a 3-tap equalization circuit and has four data paths 100, in a specific example, the first circuit 103 of the first data path 100 can receive the second signal pair OUT2 outputted by the second data path 100 and the third data path 100, respectively. The first data path 100 can further include a first adjustment circuit, which can receive the second signal pair OUT2 outputted by the fourth data path 100 to adjust the first signal pair OUT1 outputted by the first data path 100; the first circuit 103 of the second data path 100 receives the second signal pair OUT2 outputted by the third data path 100 and the fourth data path 100, respectively. The second data path 100 can further include a first adjustment circuit, which can receive the second signal pair OUT2 outputted by the first data path 100 to adjust the second signal pair OUT1 outputted by the second data path 100. The first circuit 103 of the third data path 100 can receive the second signal pair OUT2 output by the first data path 100 and the fourth data path 100 respectively. The third data path 100 may further include a first adjustment circuit, which receives the second signal pair OUT2 output by the second data path 100 to adjust the first signal pair OUT1 output by the first data path 100; the first circuit 103 of the fourth data path 100 receives the second signal pair OUT2 output by the second data path 100 and the third data path 100 respectively. The fourth data path 100 may further include a first adjustment circuit, which receives the second signal pair OUT2 output by the third data path 100 to adjust the first signal pair OUT1 output by the fourth data path 100.

[0116] It is understandable that in some embodiments, N may also be equal to M, that is, the first circuit 103 of the i-th data path 100 may receive the second signal pair OUT2 output by all data paths 100 to obtain the tap control signal TapA. In this way, without considering high anti-inter-symbol interference capability, the equalization circuit required by the data receiving circuit can be further simplified, the load can be further reduced, and the input data transmission speed can be further improved.

[0117] As analyzed above, in some embodiments, M can be 4, and the phase difference between the sampling clocks received by any two consecutive numbered data paths is 90°. For example, the phase of the sampling clock received by the first data path is 0°, the phase of the sampling clock received by the second data path is 90°, the phase of the sampling clock received by the third data path is 180°, and the phase of the sampling clock received by the fourth data path is 270°. In other embodiments, the phase difference between the sampling clocks received by any two consecutive numbered data paths can also be 45°. For example, the phase of the sampling clock received by the first data path is 0°, the phase of the sampling clock received by the second data path is 45°, the phase of the sampling clock received by the third data path is 90°, the phase of the sampling clock received by the fourth data path is 135°, and the phase of the sampling clock received by the fifth data path is 180°.

[0118] The first circuit 103 of the i-th data path 100 can receive the second signal pair OUT2 output by the i-th data path 100, and the first circuit 103 of the first data path 100 can receive the second signal pair OUT2 output by the first data path 100, where 1<i≤M, and M≥3. It can be understood that the i-th data path 100 receives input data at the current moment, and the second signal pair OUT2 output by the first circuit 103 of the i-th data path 100 is the second signal pair OUT2 output by the i-th data path in the previous time period compared to the current moment. For example, if the i-th data path 100 receives input data during the fourth clock cycle, i.e., the current moment is the fourth clock cycle (or, the i-th data path 100 receives input data to be sampled and output during the sampling phase of the fourth clock cycle), the first circuit 103 of the i-th data path 100 receives the second signal pair OUT2 sampled and output by the i-th data path 100 during the sampling phase of the third clock cycle. It can be understood that, for the i-th data path 100, the time interval between the moment when the input data was previously transmitted by the i-th data path 100 and the moment when the input data is currently transmitted by the i-th data path 100 is longer than the interval between the moment when the other data paths 100 transmit input data and the moment when the i-th data path 100 currently transmits input data. That is, the impact of the inter-symbol interference caused by the input data previously transmitted by the i-th data path 100 on the currently transmitted input data is relatively small. Using the input data previously transmitted by the i-th data path 100 as one of the input data for obtaining the tap control signal TapA can not only ensure that the input data with the least impact on the inter-symbol interference can participate in decision feedback equalization to adjust the first signal pair OUT1, but also reduce the complexity of the circuit required to participate in decision feedback equalization.

[0119] In some specific embodiments, the first circuit 103 of the i-th data path 100 receives the second signal pair OUT2 output by at least two data paths 100 except the (i-1)-th data path 100, and the first circuit 103 of the 1st data path 100 receives the second signal pair OUT2 output by at least two data paths 100 except the M-th data path 100; in addition, the first circuit 103 of the i-th data path 100 may receive the second signal pair OUT2 including the output of the i-th data path 100, and the first circuit 103 of the 1st data path 100 receives the second signal pair OUT2 including the output of the 1st data path 100, where 1<i≤M, M≥3.

[0120] Figure 8 This is another functional block diagram of the data path in the data receiving circuit. Figure 8 The i-th data path 100 may further include a first adjustment circuit 115 configured to receive the second signal pair OUT2 output by the (i-1)th data path 100 and adjust the first signal pair OUT1 in the i-th data path 100 in response to the received second signal pair OUT2. If the i-th data path 100 is the (i-1)th data path 100, then the (i-1)th data path 100 is the (M)th data path 100. As can be seen from the above analysis, the second signal pair OUT2 output by the (i-1)th data path 100 is the input data that has the greatest impact on the input data currently being transmitted by the i-th data path 100. That is, the previously transmitted first bit of data has the greatest impact on the inter-symbol interference (ISI) of the currently being transmitted input data. Therefore, an independent first adjustment circuit 115 may be provided, such that the first adjustment circuit 115 is responsive to the second signal pair OUT2 output by the (i-1)th data path 100 to adjust the first signal pair OUT1 of the i-th data path 100, thereby reducing the impact of the ISI caused by the previously transmitted bit of data on the currently being transmitted input data and further improving the accuracy of input data transmission.

[0121] In a specific example, taking a 4-tap equalization circuit as an example, the first adjustment circuit 115 of the first data path 100 receives the second signal pair OUT2 output by the fourth data path 100, the second adjustment circuit of the second data path 100 receives the second signal pair OUT2 output by the first data path 100, the first adjustment circuit 115 of the third data path 100 receives the second signal pair OUT2 output by the second data path 100, and the second adjustment circuit of the fourth data path 100 receives the second signal pair OUT2 output by the third data path 100.

[0122] Figure 9 Another functional block diagram of the data path in the data receiving circuit is shown in FIG. Figure 9The i-th data path 100 may further include a second adjustment circuit 116 configured to receive the second signal pair OUT2 output by the (i-2)th data path 100 and adjust the first signal pair OUT1 in the i-th data path 100 in response to the received second signal pair OUT2. If the i-th data path 100 is the second data path 100, the (i-2)th data path 100 is the M-th data path 100; if the i-th data path 100 is the first data path 100, the (i-2)th data path 100 is the M-th data path 100. For currently transmitted input data, the intersymbol interference (ISI) caused by the previously transmitted second bit data is also significantly affected. Therefore, an independent second adjustment circuit 116 may be provided. The second adjustment circuit 116 is responsive to the second signal pair OUT2 output by the (i-2)th data path 100 to adjust the first signal pair OUT1 in the i-th data path 100, thereby reducing the impact of the ISI caused by the previously transmitted second bit data on the currently transmitted input data and further improving the accuracy of input data transmission.

[0123] In a specific example, taking a 4-tap equalization circuit as an example, the second conditioning circuit 116 of the first data path 100 receives the second signal pair OUT2 output by the third data path 100, the second conditioning circuit 116 of the second data path 100 receives the second signal pair OUT2 output by the fourth data path 100, the second conditioning circuit 116 of the third data path 100 receives the second signal pair OUT2 output by the first data path 100, and the second conditioning circuit 116 of the fourth data path 100 receives the second signal pair OUT2 output by the second data path 100.

[0124] It is understood that, in a specific example, the i-th data path 100 may include both the first and second regulating circuits. In another specific example, the i-th data path 100 may include one of the first and second regulating circuits.

[0125] Figures 10 to 13Figures 1 and 2 illustrate several different architectures of a data receiving circuit. Taking M=4 as an example, the sampling clocks CLK corresponding to the first data path 100 to the fourth data path 100 are defined as DQS_0, DQS_90, DQS_180, and DQS_270, respectively. The second signal pairs OUT2 output by the first data path 100 to the fourth data path 100 are defined as OUT_0, OUT_90, OUT_180, and OUT_270, respectively. OUT_0[n-1] is the second signal pair output by the first data path in the previous clock cycle, and OUT_90[n-1] is the second signal pair output by the second data path in the previous clock cycle. The second signal pair output during a clock cycle, OUT_180[n-1], is the second signal pair output by the third data path during the previous clock cycle, and OUT_270[n-1] is the second signal pair output by the fourth data path during the previous clock cycle. The amplifier circuit, the first circuit, and the second circuit are collectively designated 20. T1, T2, T3, and T4 respectively represent control signals participating in the DFE. For the second circuit 104, the control signal is the corresponding tap control signal TapA. For the first and second regulation circuits, the control signal is the corresponding received second signal pair OUT2. The following describes several different implementations of the data receiving circuit in conjunction with the accompanying drawings. The "+" below refers to the formation of a binary value:

[0126] Combined with reference table 1, Figure 4 、 Figure 5 、 Figure 9 as well as Figure 10In one example, for the sampling clock DQS_0, i.e., the first data path 100, OUT_270 serves as the control signal T1 for the first conditioning circuit 115, OUT_180 serves as the control signal T2 for the second conditioning circuit 116, and OUT_90+OUT_0[n-1] corresponds to the tap control signal TapA of the second circuit 104. That is, T3+T4 is derived based on OUT_90+OUT_0[n-1] and serves as the tap control signal TapA. For the sampling clock DQS_90, i.e., the second data path 100, OUT_0 serves as the control signal T1 for the first conditioning circuit 115, OUT_270 serves as the control signal T2 for the second conditioning circuit 116, and OUT_180+OUT_90[n-1] corresponds to the tap control signal TapA of the second circuit 104. That is, T3+T4 is derived based on OUT_180+OUT_90[n-1] and serves as the tap control signal TapA. For the third data path 100 with a sampling clock of DQS_180, OUT_90 serves as the control signal T1 for the first conditioning circuit 115, OUT_0 serves as the control signal T2 for the second conditioning circuit 116, and OUT_270 + OUT_180[n-1] corresponds to the tap control signal TapA for the second circuit 104. That is, T3 + T4 are derived based on OUT_270 + OUT_180[n-1] and serve as the tap control signal TapA. For the fourth data path 100 with a sampling clock of DQS_270, OUT_180 serves as the control signal T1 for the first conditioning circuit 115, OUT_90 serves as the control signal T2 for the second conditioning circuit 116, and OUT_0 + OUT_270[n-1] corresponds to the tap control signal TapA for the second circuit 104. That is, T3 + T4 are derived based on OUT_0 + OUT_270[n-1] and serve as the tap control signal TapA.

[0127] Combined with reference to Table 2-1, Table 2-2, Figure 4 、 Figure 8 as well as Figure 11In another example, for the first data path 100, OUT_270 serves as the control signal T1 of the first regulation circuit 115, and OUT_90+OUT_180+OUT_0[n-1] corresponds to the tap control signal TapA of the second circuit 104. That is, T2+T3+T4 is derived based on OUT_90+OUT_180+OUT_0[n-1] and serves as the tap control signal TapA. For the second data path 100, OUT_0 serves as the control signal T1 of the first regulation circuit 115, and OUT_270+OUT_180+OUT_90[n-1] corresponds to the tap control signal TapA of the second circuit 104. That is, T2+T3+T4 is derived based on OUT_270+OUT_180+OUT_90[n-1] and serves as the tap control signal TapA. For the third data path 100, OUT_90 serves as the control signal T1 for the first regulation circuit 115, and OUT_0+OUT_270+OUT_180[n-1] corresponds to the tap control signal TapA of the second circuit 104. That is, T2+T3+T4 is derived based on OUT_0+OUT_270+OUT_180[n-1] and serves as the tap control signal TapA. For the fourth data path 100, OUT_180 serves as the control signal T1 for the first regulation circuit 115, and OUT_90+OUT_0+OUT_270[n-1] corresponds to the tap control signal TapA of the second circuit 104. That is, T2+T3+T4 is derived based on OUT_90+OUT_0+OUT_270[n-1] and serves as the tap control signal TapA.

[0128] Combined with reference to Table 3-1, Table 3-2, Figure 4 、 Figure 5 as well as Figure 12In another example, for the first data path 100, OUT_270+OUT_180+OUT_90+OUT_0[n-1] corresponds to the tap control signal TapA of the second circuit 104, that is, T1+T2+T3+T4 is obtained based on OUT_270+OUT_180+OUT_90+OUT_0[n-1] and serves as the tap control signal TapA. For the second data path 100, OUT_0+OUT_270+OUT_180+OUT_90[n-1] corresponds to the tap control signal TapA of the second circuit 104, that is, T1+T2+T3+T4 is obtained based on OUT_0+OUT_270+OUT_180+OUT_90[n-1] and serves as the tap control signal TapA. For the third data path 100, OUT_90+OUT_0+OUT_270+OUT_180[n-1] corresponds to the tap control signal TapA of the second circuit 104. That is, T1+T2+T3+T4 is derived based on OUT_90+OUT_0+OUT_270+OUT_180[n-1] and serves as the tap control signal TapA. For the fourth data path 100, OUT_180+OUT_90+OUT_0+OUT_270[n-1] corresponds to the tap control signal TapA of the second circuit 104. That is, T1+T2+T3+T4 is derived based on OUT_180+OUT_90+OUT_0+OUT_270[n-1] and serves as the tap control signal TapA.

[0129] Combined with reference Figure 4 、 Figure 5 as well as Figure 13In another example, the i-th data path 100 may have two first circuits 103 and two second circuits 104, and each first circuit 103 corresponds to a second circuit 104. For the first data path 100, OUT_90+OUT_0[n-1] corresponds to the tap control signal TapA of one second circuit 104, that is, T3+T4 is obtained based on OUT_90+OUT_0[n-1] and serves as the tap control signal TapA, and OUT_270+OUT_180 corresponds to the tap control signal TapA of another second circuit 104, that is, T1+T2 is obtained based on OUT_90+OUT_0[n-1] and serves as another tap control signal TapA. For the second data path 100, OUT_180+OUT_90[n-1] corresponds to the tap control signal TapA of the second circuit 104, that is, T3+T4 is obtained based on OUT_180+OUT_90[n-1] and serves as the tap control signal TapA. OUT_0+OUT_270 corresponds to the tap control signal TapA of another second circuit 104, that is, T1+T2 is obtained based on OUT_0+OUT_270 and serves as another tap control signal TapA. For the third data path 100, OUT_270+OUT_180[n-1] corresponds to the tap control signal TapA of a second circuit 104. That is, T3+T4 is derived based on OUT_270+OUT_180[n-1] and serves as the tap control signal TapA. OUT_90+OUT_0 corresponds to the tap control signal TapA of another second circuit 104. T1+T2 is derived based on OUT_90+OUT_0 and serves as another tap control signal TapA. For the fourth data path 100, OUT_0+OUT_270[n-1] corresponds to the tap control signal TapA of a second circuit 104, that is, T3+T4 is obtained based on OUT_0+OUT_270[n-1] and serves as the tap control signal TapA, and OUT_180+OUT_90 corresponds to the tap control signal TapA of another second circuit 104, that is, T1+T2 is obtained based on OUT_180+OUT_90 and serves as another tap control signal TapA.

[0130] Figure 14 is a circuit structure diagram of the amplifier circuit and the second circuit 104 in any data path 100, Figure 15 for Figure 14 A circuit structure diagram of the first control circuit and the second control circuit, Figure 16 FIG. 1 is another circuit structure diagram of the amplifier circuit and the second circuit 104 in any data path 100 .

[0131] refer to Figure 14The first signal pair OUT1 includes a first data signal OUT1_O and a first reference data signal OUT1_E, and the amplifier circuit includes a first node net1 and a second node net2. The first node net1 outputs the first data signal OUT1_O, and the second node net2 outputs the first reference data signal OUT1_E. The second circuit 104 includes: a first control circuit 14, connected between the first node net1 and the ground, turned on or off according to the second control signal TapA2, and the first control circuit 14 adjusts the level of the first signal pair OUT1 with the second adjustment value during the conduction period; a second control circuit 24, connected between the second node net2 and the ground, turned on or off according to the first control signal TapA1, and the second control circuit 24 adjusts the level of the first signal pair OUT1 with the first adjustment value during the conduction period.

[0132] The first control circuit 14 forms a first equivalent resistor between the first node net1 and the ground, and the second control circuit 24 forms a second equivalent resistor between the second node net2 and the ground. The first resistance of the first equivalent resistor and the second resistance of the second equivalent resistor are both adjustable.

[0133] In some examples, both the first control circuit and the second control circuit are formed by NMOS transistors. When at least one bit of the second control signal TapA2 is 1, the first control circuit 14 is turned on, thereby connecting the transmission path between the first node net1 and the ground. Depending on whether different bits of the second control signal TapA2 are 1, the first resistance of the first equivalent resistor is different. The first resistance is negatively correlated with the second adjustment value: a larger first resistance value indicates a smaller second adjustment value, and a smaller first resistance value indicates a larger second adjustment value. If every bit of the second control signal TapA2 is 0, the first control circuit 14 is turned off, thereby closing the transmission path between the first node net1 and the ground via the first control circuit 14.

[0134] If at least one bit of the first control signal TapA1 is 1, the second control circuit 24 is turned on, thereby connecting the transmission path between the second node net2 and the ground. The second resistance of the second equivalent resistor varies depending on whether different bits of the first control signal TapA1 are 1. This second resistance is negatively correlated with the first adjustment value: a larger second resistance value indicates a smaller first adjustment value, and a smaller second resistance value indicates a larger first adjustment value. If every bit of the first control signal TapA1 is 0, the second control circuit 24 is turned off, thereby disconnecting the transmission path between the second node net2 and the ground via the second control circuit 24.

[0135] In some examples, the first control circuit 14 may include: a plurality of first NMOS transistors MN1 connected in parallel, each of which has a gate receiving one-bit data from the second control signal TapA2, and each of which is connected between a first node net1 and ground. The second control circuit 24 may include: a plurality of second NMOS transistors MN2 connected in parallel, each of which has a gate receiving one-bit data from the first control signal TapA1, and each of which is connected between a second node net2 and ground. The drain of the first NMOS transistor MN1 is connected to the first node net1, and the source is connected to ground. The drain of the second NMOS transistor MN2 is connected to the second node net2, and the source is connected to ground.

[0136] It should be noted that for the convenience of illustration, Figure 14 In the figure, a single first NMOS transistor MN1 is used to illustrate multiple first NMOS transistors MN1 connected in parallel, a single second NMOS transistor MN2 is used to illustrate multiple second NMOS transistors MN2 connected in parallel, and the number of bits of the first control signal TapA1 and the second control signal TapA2 is a as an example. Figure 15 The diagram shows a plurality of first NMOS transistors MN1 connected in parallel, wherein the gate of each first NMOS transistor MN1 is controlled by TapA2[a-1] to TapA2[0] respectively. Figure 15 A plurality of second NMOS transistors MN2 connected in parallel are also shown, and the gate of each second NMOS transistor MN2 is controlled by TapA1[a-1] to TapA1[0], respectively. TapA1[a-1] to TapA1[0] correspond to the highest bit data to the lowest bit data of the first control signal TapA1, respectively, and TapA2[a-1] to TapA2[0] correspond to the highest bit data to the lowest bit data of the second control signal TapA2, respectively.

[0137] In addition, the channel width-to-length ratio of the first NMOS transistor MN1 controlled by different bit data of the second control signal TapA2 can be different. For the first NMOS transistor MN1, its equivalent resistance is negatively correlated with the channel width-to-length ratio, that is, the larger the channel width-to-length ratio, the smaller the equivalent resistance. By setting the channel width-to-length ratio of each first NMOS transistor MN1, the equivalent resistance value of different first NMOS transistors MN1 can be set, thereby adjusting the first adjustment value for the first control circuit 14 to adjust the level of the first signal pair. Therefore, the channel width-to-length ratio of different first NMOS transistors MN1 can be reasonably set according to needs. In some examples, the channel width-to-length ratio of the first NMOS transistor MN1 controlled by the high-bit data in the second control signal TapA2 is the first width-to-length ratio, and the channel width-to-length ratio of the first NMOS transistor MN1 controlled by the low-bit data is the second width-to-length ratio. The first width-to-length ratio can be greater than the first width-to-length ratio. In other examples, the channel width-to-length ratios of the first NMOS transistors MN1 controlled by different bit data in the second control signal TapA2 may also be the same, or the channel width-to-length ratios of at least two first NMOS transistors MN1 may be the same.

[0138] Similarly, the channel width-to-length ratios of the second NMOS transistor MN2 controlled by different bits of the first control signal TapA1 can be different. In some examples, the channel width-to-length ratio of the second NMOS transistor MN2 controlled by the high-bit data in the first control signal TapA1 is a third width-to-length ratio, and the channel width-to-length ratio of the second NMOS transistor MN2 controlled by the low-bit data is a fourth width-to-length ratio. The third width-to-length ratio can be greater than the fourth width-to-length ratio. In other examples, the channel width-to-length ratios of the second NMOS transistors MN2 controlled by different bits of the first control signal TapA1 can also be the same, or the channel width-to-length ratios of at least two second NMOS transistors MN2 can be the same.

[0139] It is understood that in other cases, reference Figure 16 The first control circuit 14 and the second control circuit 24 may also both be composed of PMOS transistors, the gates of the corresponding PMOS transistors being turned on in response to a low-level signal, and the first resistance value of the first equivalent resistor being different depending on whether different bits of data in the second control signal TapA2 are 0, and the second resistance value of the second equivalent resistor being different depending on whether different bits of data in the first control signal TapA1 are 0. Specifically, referring to Figure 16The first control circuit 14 may include a plurality of fifth PMOS transistors MP5 connected in parallel, each of which has a gate receiving one-bit data from the second control signal TapA2, and the fifth PMOS transistors MP5 are connected between the first node net1 and the ground. The second control circuit 24 may include a plurality of sixth PMOS transistors MP6 connected in parallel, each of which has a gate receiving one-bit data from the first control signal TapA1, and the sixth PMOS transistors MP6 are connected between the second node net2 and the ground. The source of the fifth PMOS transistor MP5 is connected to the first node net1, and the drain is connected to the ground. The source of the sixth PMOS transistor MP6 is connected to the second node net2, and the drain is connected to the ground.

[0140] refer to Figure 14 The first adjustment circuit 115 may include: a first switching circuit 15 and a first compensation circuit 25. The first switching circuit 15 is connected between the amplifying circuit 101 and the first compensation circuit 25. The first switching circuit 15 is turned on or off according to the received second signal OUT2. During the period when the first switching circuit 15 is turned on, the first compensation circuit 25 receives the first tap signal Tap1 and adjusts the first signal OUT1 with an adjustment value corresponding to the first tap signal Tap1.

[0141] Specifically, refer to Figure 14 The first switch circuit 15 may include: an eleventh NMOS transistor MN11. In the first switch circuit 15 of the (i+1)th data path, the gate of the eleventh NMOS transistor MN11 receives the second data signal OUT2_O in the second signal pair OUT2 output by the i-th data path, and the eleventh NMOS transistor MN11 is connected between the second node net2 and the ground terminal; and a twelfth NMOS transistor MN12. In the first switch circuit 15 of the (i+1)th data path, the gate of the twelfth NMOS transistor MN12 receives the second complementary data signal OUT2_E in the second signal pair OUT2 output by the i-th data path, and the twelfth NMOS transistor MN12 is connected between the first node net1 and the ground terminal.

[0142] refer to Figure 14The first compensation circuit 25 may include a first sub-compensation circuit and a second sub-compensation circuit. The first sub-compensation circuit is connected between the source of the eleventh NMOS transistor MN11 and the ground terminal, and the second sub-compensation circuit is connected between the source of the twelfth NMOS transistor MN12 and the ground terminal. Both the first sub-compensation circuit and the second sub-compensation circuit include a plurality of third NMOS transistors MN3 connected in parallel. The number of third NMOS transistors MN3 in the first sub-compensation circuit and the number of third NMOS transistors MN3 in the second sub-compensation circuit are the same and correspond to each other. The gates of the third NMOS transistors MN3 in the first sub-compensation circuit and the corresponding third NMOS transistors MN3 in the second sub-compensation circuit both receive one bit of data in the first tap signal Tap1 and are turned on or off in response to the received one bit of data. For ease of illustration, Figure 14 A single third NMOS transistor MN3 is used to illustrate a plurality of third NMOS transistors MN3 connected in parallel.

[0143] Among them, the number of third NMOS transistors MN3 connected in parallel in the first sub-compensation circuit is the same as the number of bits of the first tap signal Tap1. The first tap signal Tap1 can be a 6-bit signal of <5:0>. Accordingly, the first sub-compensation circuit is composed of 6 third NMOS transistors MN3 connected in parallel, and the second sub-compensation circuit is composed of 6 third NMOS transistors MN3 connected in parallel.

[0144] Furthermore, the channel width-to-length ratios of the third NMOS transistors MN3 controlled by different bits of the first tap signal Tap1 can be different. For the third NMOS transistors MN3, their equivalent resistance is negatively correlated with the channel width-to-length ratio; that is, the larger the channel width-to-length ratio, the smaller the equivalent resistance. By setting the channel width-to-length ratio of each third NMOS transistor MN3, the equivalent resistance values ​​of different third NMOS transistors MN3 can be set, thereby adjusting the amplitude of the first compensation circuit's adjustment of the level of the first signal pair. Generally, the smaller the equivalent resistance value of the third NMOS transistor MN3, the greater the ability of the branch circuit containing the third NMOS transistor MN3 to adjust the level of the first signal pair OUT1. Therefore, the channel width-to-length ratios of different third NMOS transistors MN3 can be appropriately set as needed. In some examples, the channel width-to-length ratio of the third NMOS transistor MN3 controlled by the high-bit data in the first tap signal Tap1 is a first width-to-length ratio, while the channel width-to-length ratio of the third NMOS transistor MN3 controlled by the low-bit data is a second width-to-length ratio. The first width-to-length ratio can be greater than the first width-to-length ratio.

[0145] In addition, it should be noted that the first sub-compensation circuit and the second sub-compensation circuit are different circuits, that is, they are respectively composed of different NMOS tube groups. In other embodiments, the first sub-compensation circuit and the second sub-compensation circuit can also be the same circuit, that is, they share the same parallel NMOS tube group.

[0146] refer to Figure 14 The second adjustment circuit 116 may include: a second switching circuit 16 and a second compensation circuit 26. The second switching circuit 16 is connected between the amplifying circuit 101 and the second compensation circuit 26. The second switching circuit 16 is turned on or off according to the received second signal OUT2. During the period when the second switching circuit 16 is turned on, the second compensation circuit 26 receives the second tap signal Tap2 and adjusts the first signal OUT2 with an adjustment value corresponding to the second tap signal Tap2.

[0147] Continue to refer Figure 14 The second switch circuit 16 may include: a thirteenth NMOS transistor MN13; in the second switch circuit 16 of the (i+1)th data path, a gate of the thirteenth NMOS transistor MN13 receives the second data signal OUT2_O in the second signal pair OUT2 output by the (i-1)th data path, and the thirteenth NMOS transistor MN13 is connected between the second node net2 and the ground; and a fourteenth NMOS transistor MN14; in the second switch circuit 16 of the (i+1)th data path, a gate of the fourteenth NMOS transistor MN14 receives the second complementary data signal OUT2_E in the second signal pair OUT2 output by the i data path, and the fourteenth NMOS transistor MN14 is connected between the first node net1 and the ground.

[0148] The second compensation circuit 26 may include a third sub-compensation circuit and a fourth sub-compensation circuit. The third sub-compensation circuit is connected between the source of the thirteenth NMOS transistor MN13 and the ground terminal, and the fourth sub-compensation circuit is connected between the source of the fourteenth NMOS transistor MN14 and the ground terminal. The third sub-compensation circuit and the fourth sub-compensation circuit each include a plurality of fifteenth NMOS transistors MN15 connected in parallel. The number of the fifteenth NMOS transistors MN15 in the third sub-compensation circuit and the fifteenth NMOS transistors MN15 in the fourth sub-compensation circuit are the same and correspond to each other. The gates of the fifteenth NMOS transistors MN15 in the third sub-compensation circuit and the corresponding fifteenth NMOS transistors MN15 in the fourth sub-compensation circuit both receive one bit of data in the second tap signal Tap2 and are turned on or off in response to the received one bit of data. For ease of illustration, Figure 14 In the figure, a single fifteenth NMOS transistor MN15 is used to illustrate multiple fifteenth NMOS transistors MN15 connected in parallel. The number of fifteenth NMOS transistors MN15 connected in parallel is equal to the number of bits in the first tap signal Tap1. The second tap signal Tap2 can be a 5-bit signal with a structure of <4:0>. Accordingly, the third sub-compensation circuit is composed of five fifteenth NMOS transistors MN15 connected in parallel, and the fourth sub-compensation circuit is composed of five fifteenth NMOS transistors MN15 connected in parallel. Similarly, the second compensation circuit can also be composed of the same group of parallel NMOS transistors.

[0149] Combined with reference Figure 10 and Figure 14 For the first data path, OUT2_O and OUT2_E in the first adjustment circuit 115 are two differential signals in OUT_270, and OUT2_O and OUT2_E in the second adjustment circuit 116 are two differential signals in OUT_180; for the second data path, OUT2_O and OUT2_E in the first adjustment circuit 115 are two differential signals in OUT_0, and OUT2_O and OUT2_E in the second adjustment circuit 116 are two differential signals in OUT_270. number; for the third data path, OUT2_O and OUT2_E in the first adjustment circuit 15 are two differential signals in OUT_90, respectively, and OUT2_O and OUT2_E in the second adjustment circuit 116 are two differential signals in OUT_0, respectively; for the fourth data path, OUT2_O and OUT2_E in the first adjustment circuit 115 are two differential signals in OUT_180, respectively, and OUT2_O and OUT2_E in the second adjustment circuit 116 are two differential signals in OUT_90, respectively.

[0150] Continue to refer Figure 14 The amplifier circuit 101 may include: a fourth NMOS transistor MN4, wherein the gate of the fourth NMOS transistor MN4 receives input data IN, the drain is connected to the working power supply VDD through the first resistor R1, the drain of the fourth NMOS transistor MN4 is connected to the first node net1 and outputs the first data signal OUT1_O, and the source is coupled to the ground; a fifth NMOS transistor MN5, wherein the gate of the fifth NMOS transistor MN5 receives the reference voltage VREF, the drain is connected to the working power supply VDD through the second resistor R2, the drain of the fifth NMOS transistor MN5 is connected to the second node net2 and outputs the first reference data signal OUT1_E, and the source is coupled to the ground, and the first reference data signal OUT1_E and the first data signal OUT1_O constitute a first signal pair OUT1. The resistance values ​​of the first resistor R1 and the second resistor R2 are the same or nearly the same. Continue to refer to Figure 14 The amplifier circuit 101 may further include a sixth NMOS transistor MN6. The gate of the sixth NMOS transistor MN6 receives a bias signal Bias, the drain of the sixth NMOS transistor MN6 is connected to the source of the fourth NMOS transistor MN4 and the source of the fifth NMOS transistor MN5, and the source of the sixth NMOS transistor MN6 is connected to ground. During operation of the amplifier circuit 101, the bias signal Bias is a high-level signal, i.e., the sixth NMOS transistor MN6 is turned on.

[0151] Figure 17 Schematic diagram of another structure of the amplifier circuit, the second circuit, the first regulating circuit and the second regulating circuit in any data path. Figure 17In other embodiments, the amplifier circuit 101 may include: a current source I0 having one end connected to an operating power supply VDD; a third PMOS transistor MP3 connected between the other end of the current source I0 and a first node net1, with a gate of the third PMOS transistor MP3 receiving input data IN; and a fourth PMOS transistor MP4 connected between the other end of the current source I0 and a second node net2, with a gate of the fourth PMOS transistor MP4 receiving a reference voltage VREF. In other words, the drain of the third PMOS transistor MP3 is connected to the first node net1, and the drain of the fourth PMOS transistor MP4 is connected to the second node net2.

[0152] It should be noted that the different levels of the input data IN and the reference voltage VREF cause the third PMOS transistor MP3, which receives the input data IN, to turn on at a different time than the fourth PMOS transistor MP4, which receives the reference voltage VREF. Furthermore, at the same time, the degree of conduction of the third PMOS transistor MP3 is different from that of the fourth PMOS transistor MP4. It is understood that, because the degree of conduction of the third PMOS transistor MP3 is different from that of the fourth PMOS transistor MP4, the third and fourth PMOS transistors MP3 and MP4 have different capabilities for shunting the current provided by the current source I0, resulting in a different level at the first node net1 than at the second node net2.

[0153] In one example, when the level of the input data IN is lower than the level of the reference voltage VREF, the conduction level of the third PMOS transistor MP3 is greater than that of the fourth PMOS transistor MP4, causing more current provided by the current source I0 to flow into the path where the third PMOS transistor MP3 is located, resulting in a current at the first node net1 being greater than the current at the second node net2. This further causes the level of the first data signal output from the first node net1 to be high, and the level of the first reference data signal output from the second node net2 to be low. In other words, when the level of the input data IN is lower than the level of the reference voltage VREF, the level of the first data signal is higher than the level of the first reference data signal. In another example, when the level of the input data IN is higher than the level of the reference voltage VREF, the level of the first data signal is lower than the level of the first reference data signal.

[0154] Accordingly, reference Figure 17 The second circuit 104, the first regulating circuit 115 and the second regulating circuit 116 can also be composed of PMOS transistors. The working principles of the second circuit 104, the first regulating circuit 115 and the second regulating circuit 116 are roughly the same as those of the aforementioned related circuits composed of NMOS transistors. The main difference is that the gate of the PMOS transistor is turned on in response to a low-level signal, while the gate of the NMOS transistor is turned on in response to a high-level signal.

[0155] It is understandable that a suitable amplifier circuit can be selected according to the maximum level of the input data IN. For example, if the maximum level of the input data IN is relatively large, the following amplifier circuit can be used: Figure 14 That is, the gate of the NMOS tube receives the input data IN amplifier circuit. If the maximum level of the input data IN is relatively small, the following is adopted: Figure 17 That is, the gate of the PMOS tube receives the input data IN of the amplifier circuit.

[0156] Figure 18 This is a circuit diagram of a sampling circuit, refer to Figure 18 The sampling circuit 102 may include: a seventh NMOS transistor MN7, having a gate connected to the first node net1 and a source connected to the ground; an eighth NMOS transistor MN8, having a gate connected to the second node net2 and a source connected to the ground; a latch formed by a first PMOS transistor MP1, a second PMOS transistor MP2, a ninth NMOS transistor MN9, and a tenth NMOS transistor MN10, wherein the drain of the seventh NMOS transistor MN7 is connected to the source of the ninth NMOS transistor MN9, and the drain of the ninth NMOS transistor MN9 outputs the second data signal OUT2_O; the drain of the eighth NMOS transistor MN8 is connected to the source of the tenth NMOS transistor MN10, and the drain of the tenth NMOS transistor MN10 outputs the second complementary data signal OUT2_E; and two reset PMOS transistors MP0, wherein the gate of the reset PMOS transistor MP0 receives the sampling clock CLK and the source is connected to the working power supply VDD, and the drain of the reset PMOS transistor MP0 is connected to the drain of the ninth NMOS transistor MN9 and the drain of the tenth NMOS transistor MN10.

[0157] When the sampling signal CLK is a high level signal, the sampling circuit 102 outputs a valid second data signal OUT2_O and a second complementary data signal OUT2_E. When the sampling signal CLK is a low level signal, the second data signal OUT2_O and the second complementary data signal OUT2_E are both reset to high level signals.

[0158] The following will be combined Figure 14 and Figure 18 The working principles of the amplifier circuit and sampling circuit are explained:

[0159] The input data IN of the fourth data path 100 is 0, i.e., a low-level signal. The voltage of the input data IN is lower than the reference voltage VREF, and the conductivity of the fourth NMOS transistor MN4 is lower than that of the fifth NMOS transistor MN5. The first node net1 is discharged via the fourth NMOS transistor MN4, i.e., the voltage of the first node net1 is pulled down. The second node net2 is discharged via the fifth NMOS transistor MN5, also pulling down the voltage of the second node net2. Because the conductivity of the fourth NMOS transistor MN4 is lower than that of the fifth NMOS transistor MN5, the discharge rate of the first node net1 is lower than the discharge rate of the second node net2. i.e., the first node net1 is pulled down at a lower rate than the second node net2. Therefore, the voltage of the first data signal OUT1_O output by the first node net1 is higher than the voltage of the first reference data signal OUT1_E output by the second node net2. Correspondingly, the conduction degree of the seventh NMOS transistor is greater than that of the eighth NMOS transistor, so that the ninth NMOS transistor is turned on before the tenth NMOS transistor. The drain of the ninth NMOS transistor outputs a low-level signal, and the drain of the tenth NMOS transistor outputs a high-level signal. Ultimately, the drain of the ninth NMOS transistor outputs the second data signal OUT2_O, and the drain of the tenth NMOS transistor outputs the second complementary data signal OUT2_E. The second data signal OUT2_O is 0, and the second complementary data signal OUT2_E is 1.

[0160] The input data IN of the fourth data path 100 is 1, i.e., a high-level signal. The voltage of the input data IN is greater than the reference voltage VREF, and the conductivity of the fourth NMOS transistor MN4 is greater than that of the fifth NMOS transistor MN5. The first node net1 is discharged via the fourth NMOS transistor MN4, i.e., the voltage of the first node net1 is pulled down. The second node net2 is discharged via the fifth NMOS transistor MN5, also pulling down the voltage of the second node net2. Because the conductivity of the fourth NMOS transistor MN4 is greater than that of the fifth NMOS transistor MN5, the first node net1 discharges faster than the second node net2, i.e., the first node net1 is pulled down faster than the second node net2. Therefore, the voltage of the first data signal OUT1_O output by the first node net1 is lower than the voltage of the first reference data signal OUT1_E output by the second node net2. Correspondingly, the conduction degree of the seventh NMOS transistor is lower than that of the eighth NMOS transistor, so that the ninth NMOS transistor is turned on later than the tenth NMOS transistor, the drain of the tenth NMOS transistor outputs a low-level signal, and the drain of the ninth NMOS transistor outputs a high-level signal. Ultimately, the drain of the ninth NMOS transistor outputs the second data signal OUT2_O, and the drain of the tenth NMOS transistor outputs the second complementary data signal OUT2_E, and the second data signal OUT2_O is 1, and the second complementary data signal OUT2_E is 0.

[0161] For the principle of decision feedback equalization performed by the second circuit 104 , please refer to the above corresponding description, which will not be repeated here.

[0162] The data receiving circuit provided in the above-mentioned embodiment can compensate for currently transmitted input data based on multiple previously transmitted input data, thereby implementing decision feedback equalization to improve inter-symbol interference. To achieve this goal, the number of adjustment circuits required is less than the number of input data participating in the DFE. Compared to a solution in which an adjustment circuit corresponds one-to-one with each bit of data participating in the DFE, the disclosed embodiment can reduce the complexity of the adjustment circuit, thereby reducing the load on the data receiving circuit, increasing the speed of input data transmission, reducing the power consumption of the data receiving circuit, and reducing DFE latency. For example, in some examples, it can save more reaction time for 1-tap, enabling better 1-tap compensation for currently transmitted input data, further improving input data transmission accuracy. Here, 1-tap refers to the process in which the input data one bit before the currently transmitted input data participates in the DFE.

[0163] In addition, the data receiving circuit provided by the embodiment of the present disclosure can adjust the adjustment value of the first signal pair according to the change of each bit data in the tap control signal, so that the level of the first signal pair can be adjusted in different step amounts. Furthermore, the embodiment of the present disclosure can save at least one compensation circuit and at least two switch circuits. A second circuit can be used to perform decision feedback equalization in response to the N received second signal pairs with the corresponding adjustment value, without the need to set up an independent switch circuit and compensation circuit for each received second signal pair, thereby further reducing the load of the data receiving circuit and further reducing the power consumption of the data receiving circuit. For example, if N is 2, one compensation circuit and two switch circuits can be saved; if N is 3, two compensation circuits and three switch circuits can be saved; if N is 4, three compensation circuits and four switch circuits can be saved.

[0164] Accordingly, an embodiment of the present disclosure further provides a semiconductor device, comprising the data receiving circuit provided by the above embodiment.

[0165] The semiconductor device may be a wafer, a chip, or a system. Furthermore, the semiconductor device may be a memory device, which may be a DRAM or an SRAM. The DRAM may be an SDRAM, which may be a DDR SDRAM, such as DDR4, DDR5, DDR6, LPDDR4, LPDDR5, or LPDDR6. In some embodiments, the semiconductor device may be a memory chip, which may be a DRAM chip or an SRAM chip. Furthermore, the input data may be DQ input data.

[0166] From the above analysis, it can be seen that the semiconductor device can reduce circuit complexity, save the area required for the circuit, reduce the load caused by the circuit, and improve the input data transmission speed while improving the inter-symbol interference problem.

[0167] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A data receiving circuit, characterized in that: include: Multiple data paths, each of which receives input data and a sampling clock, and each data path receives a different phase of the sampling clock, the multiple data paths including: a first data path to an Mth data path numbered in ascending order of natural numbers, the i-th data path being any one of the multiple data paths, 1≤i≤M, M≥2, and the phase difference between the sampling clocks received by any two consecutively numbered data paths from the first data path to the Mth data path being the same; wherein the i-th data path includes: an amplifier circuit configured to amplify a voltage difference between a voltage of the input data and a reference voltage and output a first signal pair; a sampling circuit configured to receive the corresponding sampling clock, sample the first signal pair, and output a second signal pair; A first circuit is configured to receive the second signal pairs output by N data paths, and output a corresponding tap control signal based on all received second signal pairs, wherein the tap control signal is a multi-bit signal, where N≤M; The second circuit is configured to receive the tap control signal and, in response to the tap control signal, adjust the level of the first signal pair in the i-th data path by an adjustment value corresponding to the tap control signal.

2. The data receiving circuit according to claim 1, wherein: The second signal pair includes a second data signal and a second complementary data signal, the second data signal and the second complementary data signal are mutually inverted signals, and the second data signal is used to represent the received input data; the tap control signal includes a first control signal and a second control signal, the adjustment value includes a first adjustment value and a second adjustment value, the first control signal corresponds to the first adjustment value, the second control signal corresponds to the second adjustment value, and the first control signal and the second control signal are both multi-bit signals; wherein the first circuit is further configured to: outputting corresponding first control signals based on all received second data signals; Based on all received second complementary data signals, corresponding second control signals are output.

3. The data receiving circuit according to claim 2, wherein: The first circuit is further configured to receive a zeroing signal and N tap signals, wherein one of the tap signals corresponds to one of the second signal pairs; in any of the second signal pairs, the second data signal corresponds to a first sub-signal, the second complementary data signal corresponds to a second sub-signal, the first sub-signal is one of the zeroing signal and the tap signal, and the second sub-signal is the other of the zeroing signal and the tap signal; wherein, The first control signal is obtained by adding the first sub-signals corresponding to all received second data signals; The second control signal is obtained by adding the second sub-signals corresponding to all received second complementary data signals.

4. The data receiving circuit according to claim 3, wherein: Each bit of the zero-setting signal is 0, and at least one bit of the tap signal is 1; if the second data signal is 0 and the second complementary data signal is 1, then the first sub-signal is the zero-setting signal and the second sub-signal is the tap signal; if the second data signal is 1 and the second complementary data signal is 0, then the first sub-signal is the tap signal and the second sub-signal is the zero-setting signal.

5. The data receiving circuit according to claim 3, wherein: The first circuit is further configured to: Based on all received second data signals, select the zeroing signal and / or call the corresponding tap signal from the N tap signals as the first sub-signal, and perform an addition operation on all selected first sub-signals to output the first control signal; Based on all received second complementary data signals, the zeroing signal is selected and / or the corresponding tap signal is called from the N tap signals as the second sub-signal, and all selected second sub-signals are added to output the second control signal.

6. The data receiving circuit according to claim 5, wherein: The data receiving circuit further includes: There are N mode registers, and each of the tap signals is stored in a corresponding mode register.

7. The data receiving circuit according to claim 3, wherein: The data receiving circuit further includes: a register, wherein the register stores a plurality of different first control signals and a plurality of different second control signals; The first circuit includes: The selector is configured to call the corresponding first control signal from the register based on all the second data signals received and provide the first control signal to the first circuit, and call the corresponding second control signal from the register based on the second complementary data signal received and provide the second control signal to the first circuit.

8. The data receiving circuit according to claim 7, wherein: The data receiving circuit further includes: an adder configured to obtain 2N tap control signals and store the tap control signals in the register; Each of the tap control signals is obtained by performing an addition operation on N zero-setting signals and N signals randomly selected from the N tap signals, and different tap control signals are obtained by performing an addition operation based on different N signals.

9. The data receiving circuit according to claim 2, wherein: The first signal pair includes a first data signal and a first reference data signal, the amplifying circuit includes a first node and a second node, the first node outputs the first data signal, and the second node outputs the first reference data signal; The second circuit includes: a first control circuit, connected between the first node and the ground, and turned on or off according to the second control signal, and adjusting the level of the first signal pair by the second adjustment value during the on-state period; The second control circuit is connected between the second node and the ground terminal, and is turned on or off according to the first control signal. During the on period, the second control circuit adjusts the level of the first signal pair according to the first adjustment value.

10. The data receiving circuit according to claim 9, wherein: The first control circuit includes: a plurality of first NMOS transistors connected in parallel, wherein a gate of each first NMOS transistor receives one bit of data in the second control signal, and the first NMOS transistor is connected between the first node and the ground; The second control circuit includes: A plurality of second NMOS transistors are connected in parallel, the gate of each second NMOS transistor receives one bit of data in the first control signal, and the second NMOS transistor is connected between the second node and the ground terminal.

11. The data receiving circuit according to claim 1, wherein: The i-th data path further includes: The first adjustment circuit is configured to receive the second signal pair output by the (i-1)th data path and adjust the first signal pair in the (i)th data path in response to the received second signal pair, wherein if the (i)th data path is the (1)th data path, the (i-1)th data path is the (M)th data path.

12. The data receiving circuit according to claim 11, wherein: The first regulating circuit includes: A first switching circuit and a first compensation circuit, wherein the first switching circuit is connected between the amplifying circuit and the first compensation circuit, the first switching circuit is turned on or off according to the received second signal pair, and when the first switching circuit is turned on, the first compensation circuit receives a first tap signal and adjusts the first signal pair with an adjustment value corresponding to the first tap signal.

13. The data receiving circuit according to claim 1 or 11, wherein: The i-th data path further includes: The second adjustment circuit is configured to receive the second signal pair output by the i-2 data path and adjust the first signal pair in the i-th data path in response to the received second signal pair, wherein if the i-th data path is the second data path, the i-2 data path is the M-th data path, and if the i-th data path is the first data path, the i-2 data path is the M-1 data path.

14. The data receiving circuit according to claim 13, wherein: The second regulating circuit includes: A second switching circuit and a second compensation circuit, wherein the second switching circuit is connected between the amplifying circuit and the second compensation circuit, the second switching circuit is turned on or off according to the second signal pair received, and during the period when the second switching circuit is turned on, the second compensation circuit receives a second tap signal and adjusts the first signal pair with an adjustment value corresponding to the second tap signal.

15. The data receiving circuit according to claim 1, wherein: The first circuit of the i-th data path receives the second signal pair output by at least two of the data paths except the (i-1)-th data path, and the first circuit of the 1st data path receives the second signal pair output by at least two of the data paths except the M-th data path; wherein 1<i≤M, M≥3.

16. The data receiving circuit according to claim 15, wherein: The first circuit of the i-1th data path receives the second signal pair output by the i-1th data path and the second signal pair output by the i-th data path; the first circuit of the Mth data path receives the second signal pair output by the 1st data path and the second signal pair output by the Mth data path.

17. The data receiving circuit according to claim 15, wherein: The first circuit of the Mth data path receives the second signal pair output by the 1st data path and the second signal pair output by the 2nd data path; the first circuit of the (i-1)th data path receives the second signal pair output by the ith data path and the second signal pair output by the (i+1)th data path, i+1<M; the first circuit of the (M-1)th data path receives the second signal pair output by the 1st data path and the second signal pair output by the Mth data path.

18. The data receiving circuit according to claim 16 or 17, wherein: M is 4, and the phase difference is 90°.

19. The data receiving circuit according to claim 1, wherein: The first circuit of the i-th data path receives the second signal pair output by the i-th data path, and the first circuit of the first data path receives the second signal pair output by the first data path; wherein 1<i≤M, M≥3.

20. The data receiving circuit according to claim 1, wherein: N=M.

21. A semiconductor device, characterized in that: include: The data receiving circuit according to any one of claims 1 to 20.

22. The semiconductor device according to claim 21, wherein The semiconductor device includes a memory chip.

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