Power management chip and low voltage drop linear regulator based on zero compensation

Abstract

The present invention discloses a power management chip based on zero-point compensation and a low voltage difference linear regulator. The power management chip includes an error amplification circuit and a compensation circuit. The error amplification circuit includes an amplification unit, a source follower unit and a feedback unit. The amplification unit is used to adjust the error according to the input voltage V IN and feedback voltage V FB An amplified signal is generated, and the source follower unit is used to follow the output voltage in the amplification unit; the compensation circuit is used to generate a number of zero points to compensate for the poles generated inside and outside the power management chip. The present invention can generate an extremely low-frequency zero point and an additional zero-pole pair by adding a compensation circuit and using the compensation circuit and the output circuit outside the chip to form a zero-point compensation circuit, thereby compensating the low-frequency pole of the LDO circuit well, improving the stability of the multi-stage LDO loop, and meeting the stability design requirements of the multi-stage high-voltage LDO.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit compensation, and in particular to a power management chip based on zero-point compensation and a low-voltage difference linear regulator. Background Art

[0002] In the battery management chip, the chip needs to provide voltage to drive the off-chip power tube to generate the power supply voltage required by the chip. The off-chip power tube and the on-chip drive circuit together constitute a low dropout regulator (LDO). In order to reduce the temperature of the chip, the LDO power tube that generates high power consumption is usually placed outside the chip, and a driving voltage is provided to drive the power tube (the base of the BJT or the gate of the MOS tube), thereby generating a power supply voltage to power the inside of the chip.

[0003] In the prior art, common LDO circuits usually have the following structural designs: one is to set the voltage feedback point at the base of the off-chip power tube BJT, such as Figure 1 As shown in the figure, the advantage of this design is that the loop is simple and stability is easy to achieve; the disadvantage is that the output voltage of the off-chip power tube cannot be accurately monitored. Another structure is to set the voltage feedback point at the emitter of the off-chip power tube BJT, such as Figure 2 As shown, the advantage of this design is that it can accurately monitor the output voltage of the off-chip power tube, but the disadvantage is that the loop is complex and stability is difficult to achieve.

[0004] In the above structure, if the output of the error amplifier on the chip directly drives the power tube outside the chip, there will be a large capacitance at the output pin (power supply voltage PAD) and the drive pin (drive voltage PAD) of the chip, which is easy to produce low-frequency poles, and the first-stage output of the error amplifier also has a lower frequency pole. Under the action of multiple poles, it brings great difficulties to the stability design of the internal high-voltage LDO. Therefore, it is necessary to add a compensation circuit to solve the problem of multi-stage LDO stability design.

[0005] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0006] The object of the present invention is to provide a power management chip and a low voltage dropout linear regulator based on zero point compensation, which are used to solve the problem of multi-stage LDO loop instability.

[0007] To achieve the above object, an embodiment of the present invention provides a power management chip based on zero point compensation, the power management chip comprising:

[0008] The error amplifier circuit includes an amplifier unit, a source follower unit and a feedback unit. The amplifier unit is connected between a power supply voltage AVDD and a ground potential AVSS to generate an error signal according to an input voltage V IN and feedback voltage V FB Generate an amplified signal, the source follower unit is connected between the output end of the amplifying unit and the driving pin to follow the output voltage in the amplifying unit, and the feedback unit is connected between the output pin and the output end of the amplifying unit;

[0009] The compensation circuit includes the tenth MOS tube M10, the resistor R C and capacitor C F The tenth MOS tube M10 is respectively connected to the power supply voltage AVDD, the source follower unit and the resistor R C The first end is connected to the resistor R C The second end of the capacitor is connected to the drive pin, and the capacitor C F The first electrode plate is connected to the tenth MOS tube M10, and the second electrode plate is connected to the feedback unit;

[0010] The compensation circuit is used to generate a plurality of zero points to compensate for the poles generated inside and outside the power management chip.

[0011] In one or more embodiments of the present invention, the source follower unit includes a ninth MOS tube M9, which is an NMOS tube. The gate of the ninth MOS tube M9 is respectively connected to the amplification unit and the tenth MOS tube M10, the drain of the ninth MOS tube M9 is connected to the power supply voltage AVDD, and the source is connected to the driving pin.

[0012] In one or more embodiments of the present invention, the tenth MOS transistor M10 is an NMOS transistor, the drain of the tenth MOS transistor M10 is connected to the power supply voltage AVDD, and the source is connected to the resistor R C The first end and capacitor C F The gate of the tenth MOS tube M10 is connected to the gate of the ninth MOS tube M9;

[0013] The tenth MOS tube M10 and the ninth MOS tube M9 form a current mirror, and the mirror ratio of the tenth MOS tube M10 to the ninth MOS tube M9 is 1:K.

[0014] In one or more embodiments of the present invention, the source follower unit includes a ninth MOS tube M9, which is a PMOS tube. The gate of the ninth MOS tube M9 is respectively connected to the amplification unit and the tenth MOS tube M10, the source of the ninth MOS tube M9 is connected to the power supply voltage AVDD, and the drain is connected to the driving pin.

[0015] In one or more embodiments of the present invention, the tenth MOS transistor M10 is a PMOS transistor, the source of the tenth MOS transistor M10 is connected to the power supply voltage AVDD, and the drain is connected to the resistor R C The first end and capacitor C F The gate of the tenth MOS tube M10 is connected to the gate of the ninth MOS tube M9.

[0016] In one or more embodiments of the present invention, the amplification unit includes a common source and common gate amplifier and a capacitor C EA , the capacitor C EA The first electrode plate is respectively connected to the output end of the common-source common-gate amplifier and the gate of the ninth MOS transistor M9, and the second electrode plate is connected to the ground potential AVSS.

[0017] In one or more embodiments of the present invention, the cascode amplifier is a telescopic cascode structure or a folded cascode structure, and the input tube of the cascode amplifier is an NMOS tube or a PMOS tube.

[0018] In one or more embodiments of the present invention, the feedback unit includes a first feedback resistor R connected between the output pin and the feedback node. F1 , and a second feedback resistor R connected between the feedback node and the ground potential AVSS F2 The feedback node of the feedback unit is connected to the common source and common gate amplifier and the capacitor C F The second electrode plate is connected to the

[0019] In one or more embodiments of the present invention, the compensation circuit introduces a first zero point to compensate for the pole generated in the error amplifier circuit, and the magnitude of the first zero point is:

[0020] In another aspect of the present invention, a low voltage drop linear regulator based on zero point compensation is provided, the low voltage drop linear regulator comprising an output circuit and a power management chip as described above, the output circuit comprising a power tube, the power tube being driven by the voltage on the driving pin of the power management chip and generating an output voltage on the output pin of the power management chip.

[0021] In one or more embodiments of the present invention, the power tube is a triode BJT, the base of the triode BJT is connected to the driving pin, the collector is connected to the power supply voltage AVDD, and the emitter is connected to the output pin.

[0022] In one or more embodiments of the present invention, the output circuit further includes a capacitor C LOAD , resistor R LOAD and the equivalent series resistance RESR , the resistor R LOAD and the equivalent series resistance R ESR The first end is connected to the output pin, the equivalent series resistance R ESR The second end of the capacitor C LOAD The first plate is connected to the resistor R LOAD The second end and capacitor C LOAD The second plates of the transistors are connected to the ground potential AVSS.

[0023] In one or more embodiments of the present invention, the compensation circuit introduces a second zero point to compensate for the pole generated in the output circuit, and the magnitude of the second zero point is: Among them, β is the current amplification factor of the transistor BJT, which is the ratio of the collector current to the base current; R π is the base resistance of the transistor BJT.

[0024] In one or more embodiments of the present invention, the power tube is a MOS tube, a gate of the MOS tube is connected to a driving pin, a drain is connected to a power supply voltage AVDD, and a source is connected to an output pin.

[0025] Compared with the prior art, the power management chip and low voltage difference linear regulator based on zero point compensation according to the embodiment of the present invention can generate an extremely low frequency zero point and an additional zero-pole pair by adding a compensation circuit and using the compensation circuit and an output circuit outside the chip to form a zero point compensation circuit, thereby compensating the low frequency pole of the LDO circuit well, improving the stability of the multi-stage LDO loop, and meeting the stability design requirements of the multi-stage high voltage LDO. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a circuit schematic diagram of the first low voltage drop linear regulator in the prior art;

[0027] Figure 2 It is a circuit schematic diagram of a second low voltage difference linear regulator in the prior art;

[0028] Figure 3 This is a circuit diagram of a power management chip in Embodiment 1 of the present invention;

[0029] Figure 4 This is a circuit diagram of a power management chip in Embodiment 2 of the present invention;

[0030] Figure 5 This is a circuit diagram of a power management chip in Embodiment 3 of the present invention;

[0031] Figure 6 This is a circuit diagram of a power management chip in Embodiment 4 of the present invention;

[0032] Figure 7 This is a circuit diagram of a power management chip in Embodiment 5 of the present invention;

[0033] Figure 8 1 is a circuit schematic diagram of a low voltage dropout linear regulator in Embodiment 7 of the present invention;

[0034] Fig. 9 This is a diagram showing the compensation effect after the compensation circuit is introduced into the low voltage difference linear regulator in the embodiment of the present invention. DETAILED DESCRIPTION

[0035] The specific implementation modes of the present invention are described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific implementation modes.

[0036] Unless explicitly stated otherwise, throughout the specification and claims, the term “comprise” or variations such as “include” or “comprising”, etc., will be understood to include the stated elements or components but not to exclude other elements or components.

[0037] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element, or "connected to" another element, or an element / circuit is said to be "connected between" two nodes, it may be directly coupled or connected to another element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0038] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0039] Embodiment 1

[0040] like Figure 3 As shown, this embodiment discloses a power management chip based on zero point compensation, which includes:

[0041] The error amplifier circuit 100 includes an amplifier unit 101, a source follower unit 102, and a feedback unit 103. The amplifier unit 101 is connected between a power supply voltage AVDD and a ground potential AVSS to generate an error signal according to an input voltage V IN and feedback voltage V FB Generate an amplified signal, the source follower unit 102 is connected between the output terminal of the amplifying unit 101 and the driving pin to follow the output voltage of the amplifying unit 101, and the feedback unit 103 is connected between the output pin and the output terminal of the amplifying unit 101;

[0042] The compensation circuit 200 includes a tenth MOS tube M10, a resistor R C and capacitor C F The tenth MOS tube M10 is respectively connected to the power supply voltage AVDD, the source follower unit 102 and the resistor R C The first end is connected to the resistor R C The second end of the capacitor is connected to the drive pin, and the capacitor C F The first electrode plate is connected to the tenth MOS tube M10, and the second electrode plate is connected to the feedback unit 103;

[0043] The compensation circuit 200 is used to generate a plurality of zero points to compensate for the poles generated inside and outside the power management chip.

[0044] The error amplifier circuit 100 in this embodiment is a two-stage amplifier structure. The first stage is an amplifier unit 101 that provides a certain gain; the second stage is a source follower unit 102 that provides a sufficiently strong driving capability.

[0045] Specifically, the source follower unit 102 in this embodiment includes a ninth MOS transistor M9, which is an NMOS transistor, and the gate of the ninth MOS transistor M9 is respectively connected to the amplification unit 101 and the tenth MOS transistor M10, the drain of the ninth MOS transistor M9 is connected to the power supply voltage AVDD, and the source is connected to the driving pin.

[0046] The source follower unit 102 in this embodiment further includes a capacitor C P , capacitor C P The first electrode plate is connected to the source of the ninth MOS tube M9, and the second electrode plate is connected to the ground potential AVSS.

[0047] The tenth MOS transistor M10 in this embodiment is an NMOS transistor. The drain of the tenth MOS transistor M10 is connected to the power supply voltage AVDD, and the source is connected to the resistor R C The first end and capacitor C F The gate of the tenth MOS tube M10 is connected to the gate of the ninth MOS tube M9.

[0048] The tenth MOS tube M10 and the ninth MOS tube M9 form a current mirror, and the mirror ratio of the tenth MOS tube M10 to the ninth MOS tube M9 is 1:K, that is, the tenth MOS tube M10 can copy the output current of the ninth MOS tube M9 at a set ratio.

[0049] Furthermore, the source follower unit 102 can also play the role of output current limiting. Specifically, the source follower unit 102 also includes a twenty-fourth MOS tube M24, a twenty-fifth MOS tube M25, a twenty-sixth MOS tube M26, and a twenty-seventh MOS tube M27 that play the role of current limiting. The twenty-fourth MOS tube M24, the twenty-fifth MOS tube M25, the twenty-sixth MOS tube M26, and the twenty-seventh MOS tube M27 are all PMOS tubes, wherein:

[0050] The twenty-fourth MOS tube M24 and the twenty-fifth MOS tube M25 are connected in common gate, and the gate is connected to the amplification unit 101 at the same time, the source of the twenty-fourth MOS tube M24 and the twenty-fifth MOS tube M25 are both connected to the power supply voltage AVDD, the drain of the twenty-fourth MOS tube M24 is connected to the source of the twenty-sixth MOS tube M26, the drain of the twenty-fifth MOS tube M25 is connected to the source of the twenty-seventh MOS tube M27, the twenty-sixth MOS tube M26 and the twenty-seventh MOS tube M27 are connected in common gate, and the gate is connected to the amplification unit 101 at the same time, the drain of the twenty-sixth MOS tube M26 is connected to the drain of the ninth MOS tube M9, and the drain of the twenty-seventh MOS tube M27 is connected to the drain of the tenth MOS tube M10.

[0051] The amplifying unit 101 in this embodiment includes a common-source common-gate amplifier and a capacitor C EA , capacitor C EA The first plate is connected to the output terminal V EA and the gate of the ninth MOS tube M9, the capacitor C EA The second plate is connected to the ground potential AVSS.

[0052] In this embodiment, the cascode amplifier adopts a telescopic cascode structure, which includes a first MOS transistor M1, a second MOS transistor M2, an eleventh MOS transistor M11, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7 and an eighth MOS transistor M8, wherein:

[0053] The first MOS tube M1 and the second MOS tube M2 are used as input tubes of the common-source and common-gate amplifiers, and are both NMOS tubes;

[0054] The third MOS tube M3, the fourth MOS tube M4, the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8 form a sleeve structure of the input tube. The third MOS tube M3 and the fourth MOS tube M4 are NMOS tubes, and the fifth MOS tube M5, the sixth MOS tube M6, the seventh MOS tube M7 and the eighth MOS tube M8 are PMOS tubes.

[0055] Specifically, the gate of the first MOS tube M1 is connected to the input voltage V IN Drive, the gate of the second MOS tube M2 is driven by the feedback voltage V FB The source electrodes of the first MOS tube M1 and the second MOS tube M2 are connected to the drain electrode of the eleventh MOS tube M11, and the gate electrode of the eleventh MOS tube M11 is driven by the first bias voltage V BN The eleventh MOS transistor M11 is a NMOS transistor.

[0056] The third MOS tube M3 and the fourth MOS tube M4 are connected to each other via a common gate, and the source of the third MOS tube M3 is connected to the drain of the second MOS tube M2 , and the source of the fourth MOS tube M4 is connected to the drain of the first MOS tube M1 .

[0057] The fifth MOS tube M5 and the sixth MOS tube M6 are connected to the same gate, and the gate and drain of the fifth MOS tube M5 and the gate of the sixth MOS tube M6 are connected to the drain of the third MOS tube M3, and the drain of the sixth MOS tube M6 is connected to the drain of the fourth MOS tube M4 and is also connected to the capacitor C. EA The first plate.

[0058] The seventh MOS tube M7 and the eighth MOS tube M8 are connected with a common gate, and the gate and drain of the seventh MOS tube M7 and the gate of the eighth MOS tube M8 are connected to the source of the fifth MOS tube M5, the drain of the eighth MOS tube M8 is connected to the source of the sixth MOS tube M6, and the sources of the seventh MOS tube M7 and the eighth MOS tube M8 are connected to the power supply voltage AVDD.

[0059] In this embodiment, the output terminal V EA The first pole P1 is generated on the surface, and the size of the first pole P1 is Among them, R EA represents the output impedance of the telescopic amplifier, C EA Represents capacitance C EA capacity.

[0060] The feedback unit 103 in this embodiment includes a first feedback resistor R connected between the output pin and the feedback node F. F1 , and a second feedback resistor R connected between the feedback node F and the ground potential AVSS F2 , and the feedback node F of the feedback unit 103 is respectively connected to the common source and common gate amplifier and the capacitor C F The second electrode plate is connected to the

[0061] In this embodiment, to compensate the output terminal V of the common-source common-gate amplifier EAThe first pole P1 is generated on the chip, and the compensation circuit 200 introduces a first zero point Z1 by means of an off-chip power tube. The magnitude of the first zero point Z1 is: Among them, R F1 Represents the first feedback resistor R F1 The resistance value, C F Represents capacitance C F capacity.

[0062] According to the actual application, appropriate zero point parameters can be selected to make the loop of the low-dropout linear regulator obtain better stability.

[0063] Embodiment 2

[0064] like Figure 4 As shown, the power management chip in this embodiment is substantially the same as the power management chip in the first embodiment, except that:

[0065] The source follower unit 102 in this embodiment includes a ninth MOS transistor M9, which is a PMOS transistor, and a gate of the ninth MOS transistor M9 is respectively connected to the amplification unit 101 and the tenth MOS transistor M10, a source of the ninth MOS transistor M9 is connected to the power supply voltage AVDD, and a drain is connected to the driving pin.

[0066] The tenth MOS transistor M10 in this embodiment is a PMOS transistor. The source of the tenth MOS transistor M10 is connected to the power supply voltage AVDD, and the drain is connected to the resistor R C The first end and capacitor C F The gate of the tenth MOS tube M10 is connected to the gate of the ninth MOS tube M9.

[0067] The working principles of the ninth MOS transistor M9 and the tenth MOS transistor M10 in this embodiment are the same as those in the first embodiment, and are not described again here.

[0068] Embodiment 3

[0069] like Figure 5 As shown, the power management chip in this embodiment is substantially the same as the power management chip in the first embodiment, except that:

[0070] In this embodiment, the cascode amplifier adopts a telescopic cascode structure, and the input tube of the cascode amplifier is a PMOS tube.

[0071] Specifically, the input tubes of the cascode amplifier include a first MOS tube M1 and a second MOS tube M2, and both the first MOS tube M1 and the second MOS tube M2 are PMOS tubes.

[0072] The gate of the first MOS tube M1 is connected by the input voltage V INDrive, the gate of the second MOS tube M2 is driven by the feedback voltage V FB The source electrodes of the first MOS tube M1 and the second MOS tube M2 are connected to the drain electrode of the eleventh MOS tube M11, and the gate electrode of the eleventh MOS tube M11 is driven by the second bias voltage V BP The eleventh MOS tube M11 is a PMOS tube.

[0073] The sleeve structure of the input tube is composed of a twelfth MOS tube M12, a thirteenth MOS tube M13, a fourteenth MOS tube M14 and a fifteenth MOS tube M15, and the twelfth MOS tube M12, the thirteenth MOS tube M13, the fourteenth MOS tube M14 and the fifteenth MOS tube M15 are all NMOS tubes.

[0074] The twelfth MOS tube M12 and the thirteenth MOS tube M13 are connected to the same gate, and the gate and drain of the twelfth MOS tube M12 and the gate of the thirteenth MOS tube M13 are connected to the drain of the first MOS tube M1, and the drain of the thirteenth MOS tube M13 is connected to the drain of the second MOS tube M2 and is also connected to the capacitor C. EA The first plate.

[0075] The fourteenth MOS tube M14 and the fifteenth MOS tube M15 are connected to the same gate, and the gate and drain of the fourteenth MOS tube M14 and the gate of the fifteenth MOS tube M15 are connected to the source of the twelfth MOS tube M12, the drain of the fifteenth MOS tube M15 is connected to the source of the thirteenth MOS tube M13, and the sources of the fourteenth MOS tube M14 and the fifteenth MOS tube M15 are connected to the ground potential AVSS.

[0076] The other structures are the same as those in the first embodiment and will not be described again here.

[0077] Embodiment 4

[0078] like Figure 6 As shown, the power management chip in this embodiment is substantially the same as the power management chip in the first embodiment, except that:

[0079] In this embodiment, the cascode amplifier adopts a folded cascode structure, which includes a first MOS tube M1, a second MOS tube M2, an eleventh MOS tube M11, a sixteenth MOS tube M16, a seventeenth MOS tube M17, an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, a twenty-first MOS tube M21, a twenty-second MOS tube M22 and a twenty-third MOS tube M23, wherein:

[0080] The first MOS tube M1, the second MOS tube M2 and the eleventh MOS tube M11 are used as input tubes of the common-source common-gate amplifier, and are all NMOS tubes;

[0081] The sixteenth MOS tube M16, the seventeenth MOS tube M17, the eighteenth MOS tube M18 and the nineteenth MOS tube M19 are all PMOS tubes, and the twentieth MOS tube M20, the twenty-first MOS tube M21, the twenty-second MOS tube M22 and the twenty-third MOS tube M23 are all NMOS tubes.

[0082] Specifically, the gate of the first MOS tube M1 is connected to the input voltage V IN Drive, the gate of the second MOS tube M2 is driven by the feedback voltage V FB The source electrodes of the first MOS tube M1 and the second MOS tube M2 are connected to the drain electrode of the eleventh MOS tube M11, and the gate electrode of the eleventh MOS tube M11 is driven by the first bias voltage V BN Driver, the source is connected to the ground potential AVSS.

[0083] The sixteenth MOS tube M16 and the seventeenth MOS tube M17 are connected at the same gate, the sources of the sixteenth MOS tube M16 and the seventeenth MOS tube M17 are connected to the power supply voltage AVDD, the drain of the sixteenth MOS tube M16 is respectively connected to the source of the eighteenth MOS tube M18 and the drain of the first MOS tube M1, and the drain of the seventeenth MOS tube M17 is respectively connected to the source of the nineteenth MOS tube M19 and the drain of the second MOS tube M2.

[0084] The eighteenth MOS tube M18 and the nineteenth MOS tube M19 are connected in common gate. The twentieth MOS tube M20 and the twenty-first MOS tube M21 are connected in common gate. The gate and drain of the twentieth MOS tube M20 and the gate of the twenty-first MOS tube M21 are connected to the drain of the eighteenth MOS tube M18, and the drain of the twenty-first MOS tube M21 is connected to the drain of the nineteenth MOS tube M19 and is also connected to the capacitor C. EA The first plate.

[0085] The twenty-second MOS tube M22 and the twenty-third MOS tube M23 are connected to the same gate, the gate and drain of the twenty-second MOS tube M22 and the gate of the twenty-third MOS tube M23 are connected to the source of the twentieth MOS tube M20, the drain of the twenty-third MOS tube M23 is connected to the source of the twenty-first MOS tube M21, and the sources of the twenty-second MOS tube M22 and the twenty-third MOS tube M23 are connected to the ground potential AVSS.

[0086] The other structures are the same as those in the first embodiment and will not be described again here.

[0087] Embodiment 5

[0088] like Figure 7 As shown, the power management chip in this embodiment is substantially the same as the power management chip in the first embodiment, except that:

[0089] In this embodiment, the cascode amplifier adopts a folded cascode structure, which includes a first MOS tube M1, a second MOS tube M2, an eleventh MOS tube M11, a sixteenth MOS tube M16, a seventeenth MOS tube M17, an eighteenth MOS tube M18, a nineteenth MOS tube M19, a twentieth MOS tube M20, a twenty-first MOS tube M21, a twenty-second MOS tube M22 and a twenty-third MOS tube M23, wherein:

[0090] The first MOS tube M1 and the second MOS tube M2 are used as input tubes of the common-source and common-gate amplifiers, and are both PMOS tubes;

[0091] The sixteenth MOS tube M16, the seventeenth MOS tube M17, the eighteenth MOS tube M18 and the nineteenth MOS tube M19 are all PMOS tubes, and the twentieth MOS tube M20, the twenty-first MOS tube M21, the twenty-second MOS tube M22 and the twenty-third MOS tube M23 are all NMOS tubes.

[0092] Specifically, the gate of the first MOS tube M1 is connected to the input voltage V IN Drive, the gate of the second MOS tube M2 is driven by the feedback voltage V FB The source electrodes of the first MOS tube M1 and the second MOS tube M2 are connected to the drain electrode of the eleventh MOS tube M11, and the gate electrode of the eleventh MOS tube M11 is driven by the second bias voltage V BP The eleventh MOS tube M11 is a PMOS tube.

[0093] The sixteenth MOS tube M16 and the seventeenth MOS tube M17 are connected to the same gate, the sources of the sixteenth MOS tube M16 and the seventeenth MOS tube M17 are connected to the power supply voltage AVDD, the gate and the drain of the sixteenth MOS tube M16 and the gate of the seventeenth MOS tube M17 are connected to the source of the eighteenth MOS tube M18, and the drain of the seventeenth MOS tube M17 is connected to the source of the nineteenth MOS tube M19.

[0094] The eighteenth MOS tube M18 and the nineteenth MOS tube M19 are connected to the same gate, the gate and drain of the eighteenth MOS tube M18 and the gate of the nineteenth MOS tube M19 are connected to the drain of the twentieth MOS tube M20, the drain of the nineteenth MOS tube M19 is connected to the drain of the twenty-first MOS tube M21, and are also connected to the capacitor C EA The first plate.

[0095] The twentieth MOS tube M20 and the twenty-first MOS tube M21 are connected to the same gate, the source of the twentieth MOS tube M20 is respectively connected to the drain of the first MOS tube M1 and the drain of the twenty-second MOS tube M22, the source of the twenty-first MOS tube M21 is respectively connected to the drain of the second MOS tube M2 and the drain of the twenty-third MOS tube M23.

[0096] The twenty-second MOS transistor M22 and the twenty-third MOS transistor M23 are connected at the same gate, and the sources of the twenty-second MOS transistor M22 and the twenty-third MOS transistor M23 are both connected to the ground potential AVSS.

[0097] The other structures are the same as those in the first embodiment and will not be described again here.

[0098] Embodiment 6

[0099] The present embodiment discloses a low voltage difference linear regulator based on zero point compensation, which includes an output circuit 300 and the above-mentioned power management chip, wherein the output circuit 300 includes a power tube, which is driven by the voltage on the driving pin of the power management chip and generates an output voltage on the output pin of the power management chip.

[0100] In this embodiment, the power tube adopts a triode BJT, the base of the triode BJT is connected to the driving pin, the collector is connected to the power supply voltage AVDD, and the emitter is connected to the output pin.

[0101] Furthermore, the output circuit also includes a capacitor C LOAD , resistor R LOAD and the equivalent series resistance R ESR , resistor R LOAD and the equivalent series resistance R ESR The first end of each is connected to the output pin, and the equivalent series resistance R ESR The second end of the capacitor C LOAD The first plate is connected to the resistor R LOAD The second end and capacitor C LOAD The second plates of the transistors are connected to the ground potential AVSS.

[0102] In this embodiment, the output circuit 300 includes a first output terminal V O1 and the second output terminal V O2 , where the first output terminal V O1 Connected to the drive pin to drive the power tube outside the chip. The second output terminal V O2 Connected to the output pin to provide output voltage inside the chip.

[0103] The first output terminal V O1 A second pole P2 is generated on the surface, and the size of the second pole P2 is Among them, R O1 represents the output impedance on the drive pin, and C P represents the capacitance of capacitor C P .

[0104] A third pole P3 is generated on the second output terminal V O2 , and the magnitude of the third pole P3 is Among them, R L represents the equivalent output impedance on the output pin, that is, the resistance R LOAD in parallel with the first feedback resistor R F1 and the second feedback resistor R F2 , and C L represents the capacitance of capacitor C LOAD . The resistor R LOAD is a variable resistor. Therefore, the third pole P3 is a variable pole, and its magnitude changes with the change of the resistance value of the resistor R LOAD .

[0105] In this embodiment, to compensate for the poles generated in the output circuit 300, the compensation circuit 200 introduces a second zero point Z2 by means of an off-chip power transistor, and the magnitude of the second zero point Z2 is Among them, β is the current amplification factor of the bipolar junction transistor BJT, and its magnitude is the ratio of the collector current to the base current; R π is the base resistance of the bipolar junction transistor BJT

[0106] At the same time, the compensation circuit 200 also introduces a fourth pole P4 by means of an off-chip power transistor, and the magnitude of the fourth pole P4 is Among them, R F1 is the resistance value of the first feedback resistor R F1 , R F2 is the resistance value of the second feedback resistor R F2 , and C F is the capacitance of capacitor C F .

[0107] Generally, each pole and zero point satisfy: P1, P3 < Z2 < Z1 < P2, P4. When the resistance value of the resistor R LOAD is different, the changes of the first pole P1 and the second pole P2 are relatively small compared with the change of the third pole P3, and the fourth pole P4 is basically unchanged

[0108] The compensation circuit compensates the LDO loop by generating zero points with parameters such as β and R π of the off-chip power transistor BJT and the capacitance C LOAD , and the compensation effect is as shown in Fig. 9 . Fig. 9The upper part shows the frequency gain (Loop Gain) and frequency phase (Loop Gain Phase) curves before compensation, and the lower part shows the frequency gain (Loop Gain) and frequency phase (Loop Gain Phase) curves after compensation. Fig. 9 It can be seen that the phase margin before compensation is -36° (reflected by point M6 in the figure), and the loop is unstable. The phase margin after compensation is 47° (reflected by point M9 in the figure), which can make the LDO loop obtain better stability.

[0109] Embodiment 7

[0110] like Figure 8 As shown, the low voltage dropout linear regulator in this embodiment is substantially the same as the low voltage dropout linear regulator in the sixth embodiment, except that:

[0111] The power tube in this embodiment is an NMOS tube, a gate of the NMOS tube is connected to a driving pin, a drain is connected to a power supply voltage AVDD, and a source is connected to an output pin.

[0112] The other structures are the same as those in the sixth embodiment and will not be described again here.

[0113] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.

Claims

1. A power management chip based on zero point compensation, characterized in that: The power management chip comprises: The error amplifier circuit includes an amplifier unit, a source follower unit and a feedback unit. The amplifier unit is connected between a power supply voltage AVDD and a ground potential AVSS to generate an error signal according to an input voltage V IN and feedback voltage V FB Generate an amplified signal, the source follower unit is connected between the output end of the amplifying unit and the driving pin to follow the output voltage in the amplifying unit, and the feedback unit is connected between the output pin and the output end of the amplifying unit; The compensation circuit includes the tenth MOS tube M10, the resistor R C and capacitor C F The tenth MOS tube M10 is respectively connected to the power supply voltage AVDD, the source follower unit and the resistor R C The first end is connected to the resistor R C The second end of the capacitor is connected to the drive pin, F The first electrode plate is connected to the tenth MOS tube M10, and the second electrode plate is connected to the feedback unit; The compensation circuit is used to generate a plurality of zero points to compensate for the poles generated inside and outside the power management chip.

2. The power management chip based on zero point compensation as claimed in claim 1, characterized in that: The source follower unit includes a ninth MOS tube M9, which is an NMOS tube. The gate of the ninth MOS tube M9 is respectively connected to the amplification unit and the tenth MOS tube M10, the drain of the ninth MOS tube M9 is connected to the power supply voltage AVDD, and the source is connected to the driving pin.

3. The power management chip based on zero point compensation as claimed in claim 2, characterized in that: The tenth MOS transistor M10 is an NMOS transistor. The drain of the tenth MOS transistor M10 is connected to the power supply voltage AVDD, and the source is connected to the resistor R C The first end and capacitor C F The gate of the tenth MOS tube M10 is connected to the gate of the ninth MOS tube M9; The tenth MOS tube M10 and the ninth MOS tube M9 form a current mirror, and the mirror ratio of the tenth MOS tube M10 to the ninth MOS tube M9 is 1:K.

4. The power management chip based on zero point compensation as claimed in claim 1, characterized in that: The source follower unit includes a ninth MOS tube M9, which is a PMOS tube. The gate of the ninth MOS tube M9 is respectively connected to the amplification unit and the tenth MOS tube M10, the source of the ninth MOS tube M9 is connected to the power supply voltage AVDD, and the drain is connected to the driving pin.

5. The power management chip based on zero point compensation as claimed in claim 4, characterized in that: The tenth MOS transistor M10 is a PMOS transistor. The source of the tenth MOS transistor M10 is connected to the power supply voltage AVDD, and the drain is connected to the resistor R C The first end and capacitor C F The gate of the tenth MOS tube M10 is connected to the gate of the ninth MOS tube M9.

6. The power management chip based on zero point compensation as claimed in claim 2 or 4, characterized in that: The amplification unit includes a common source and common gate amplifier and a capacitor C EA , the capacitor C EA The first electrode plate is respectively connected to the output end of the common-source common-gate amplifier and the gate of the ninth MOS transistor M9, and the second electrode plate is connected to the ground potential AVSS.

7. The power management chip based on zero point compensation as claimed in claim 6, characterized in that: The cascode amplifier is a telescopic cascode structure or a folded cascode structure, and the input tube of the cascode amplifier is an NMOS tube or a PMOS tube.

8. The power management chip based on zero point compensation as claimed in claim 6, characterized in that: The feedback unit includes a first feedback resistor R connected between the output pin and the feedback node. F1 , and a second feedback resistor R connected between the feedback node and the ground potential AVSS F2 The feedback node of the feedback unit is respectively connected to the common source and common gate amplifier and the capacitor C F The second electrode plate is connected to the 9. The power management chip based on zero point compensation as claimed in claim 8, characterized in that: The compensation circuit introduces a first zero point to compensate for the pole generated in the error amplifier circuit. The magnitude of the first zero point is: Among them, R F1 Represents the first feedback resistor R F1 The resistance value, C F Represents capacitance C F capacity.

10. A low-dropout linear regulator based on zero-point compensation, characterized in that: The low voltage difference linear regulator includes an output circuit and a power management chip as described in any one of claims 1 to 9, wherein the output circuit includes a power tube, which is driven by the voltage on the driving pin of the power management chip and generates an output voltage on the output pin of the power management chip.

11. The low-dropout linear regulator based on zero-point compensation according to claim 10, characterized in that: The power tube adopts a triode BJT, the base of the triode BJT is connected to the driving pin, the collector is connected to the power supply voltage AVDD, and the emitter is connected to the output pin.

12. The low-dropout linear regulator based on zero-point compensation according to claim 11, characterized in that: The output circuit also includes a capacitor C LOAD , resistor R LOAD and the equivalent series resistance R ESR , the resistor R LOAD and the equivalent series resistance R ESR The first end is connected to the output pin, the equivalent series resistance R ESR The second end of the capacitor C LOAD The first plate is connected to the resistor R LOAD The second end and capacitor C LOAD The second plates of the transistors are connected to the ground potential AVSS.

13. The low-dropout linear regulator based on zero-point compensation according to claim 12, characterized in that: The compensation circuit introduces a second zero point to compensate for the pole generated in the output circuit. The magnitude of the second zero point is: Among them, β is the current amplification factor of the transistor BJT, which is the ratio of the collector current to the base current; R π is the base resistance of the transistor BJT.

14. The low-dropout linear regulator based on zero-point compensation according to claim 10, characterized in that: The power tube is a MOS tube, a gate of the MOS tube is connected to a driving pin, a drain is connected to a power supply voltage AVDD, and a source is connected to an output pin.

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