Dither signal generation method, circuit and sigma delta modulator
By designing a Dither signal generation circuit in the Sigma Delta modulator and generating seven Dither levels using a specific transfer function, the Idle Tone problem was solved, hardware overhead was reduced, and the quantization accuracy of the modulator was improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI BEILING
- Filing Date
- 2022-12-27
- Publication Date
- 2026-05-19
AI Technical Summary
Existing Sigma Delta modulators suffer from Idle Tone when a DC signal is input, which reduces quantization accuracy. Furthermore, traditional Dither signal generation methods have high hardware overhead, and the Dither signal contains errors during D/A conversion, which impairs the modulator's accuracy.
A Dither signal generation circuit is used to generate Dither signals by combining a random number generation unit, a delay unit, and an adder unit. Using the transfer function T(z)=(1-z-1)(1+3z-1) or T(z)=1+2z-1-3z-2, seven Dither levels are generated, reducing hardware requirements and providing a built-in first-order shaping effect.
It reduces the impact of Dither signal errors in D/A conversion, improves the quantization accuracy of the Sigma Delta modulator, reduces hardware overhead, and mitigates modulator accuracy loss.
Smart Images
Figure CN115951862B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design, and in particular to a method, circuit, and SigmaDelta modulator for generating Dither signals. Background Technology
[0002] In the consumer electronics market, there is a constant pursuit of lower power consumption and higher performance. Sigma Delta analog-to-digital converters (ADCs) are favored by ADC designers due to their low power consumption and high accuracy. The Sigma Delta modulator is the core of the Sigma Delta ADC. In a Sigma Delta modulator, when the input signal is DC, the output signal exhibits an idle tone, which is visually represented by the output signal cycling every few periods. Consequently, the output signal's spectrum includes harmonic signals other than DC (not part of the input signal), significantly reducing the quantization accuracy of the Sigma Delta modulator for DC signals. Therefore, reducing or eliminating the idle tone in the Sigma Delta modulator is necessary. Injecting dither (a type of jitter, an additional pseudo-random signal) can disrupt the modulator's periodic output and is an efficient method for eliminating the idle tone, widely used in Sigma Delta modulators.
[0003] The modulator's function is to quantize an analog input signal into a digital output signal. The dither signal injected at the front end of the quantizer can disrupt the periodic output, thus eliminating idle tones. However, to maintain the accuracy of the quantization result, the previously injected dither signal must be subtracted at the back end of the quantizer. But due to errors in the digital dither signal during D / A conversion, the dither signal injected at the front end and the dither signal subtracted at the back end are not equal. The final result is that the modulator output (Out) contains residual dither signal, which will impair the modulator's quantization accuracy. Therefore, reducing the residual dither signal is necessary.
[0004] Furthermore, traditional Dither generation methods directly represent Dither levels using binary random codes. One bit of binary random code can generate two Dither levels, two bits can generate four, and three bits can generate eight. It is evident that when multiple random levels are required, a larger number of bits of binary random code are needed, resulting in significant hardware overhead for generating binary random codes. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to overcome the above-mentioned defects in the prior art and provide a method, circuit and Sigma Delta modulator for generating Dither signals.
[0006] The present invention solves the above-mentioned technical problems through the following technical solution:
[0007] This invention provides a Dither signal generation circuit, which is applied in a SigmaDelta modulator. The Dither signal generation circuit includes a random number generation unit, a first delay unit, a first adder unit, a first gain unit, a second delay unit, and a second adder unit.
[0008] The random number generation unit generates a random number signal and transmits it to the first delay unit. The first delay unit performs a one-cycle delay on the random number signal and then transmits it to the first adder unit to obtain a first signal. The first gain unit performs a three-fold gain on the first signal and then transmits it to the second delay unit. The second delay unit performs a one-cycle delay on the first signal after the gain processing and then transmits it to the second adder unit. The second adder unit outputs the Dither signal.
[0009] Preferably, the output terminal of the random number generation unit is connected to the input terminal of the first delay unit and the input terminal of the first adder unit, respectively. The output terminal of the first delay unit is connected to the input terminal of the first adder unit. The output terminal of the first adder unit is connected to the input terminal of the first gain unit and the input terminal of the second adder unit, respectively. The output terminal of the first gain unit is connected to the input terminal of the second delay unit. The input terminal of the second delay unit is connected to the input terminal of the second adder unit. The output terminal of the second adder unit outputs the Dither signal.
[0010] Preferably, the first delay unit includes a delay unit z. -1 The second delay unit includes a delay unit z. -1 .
[0011] Preferably, the random number generation unit includes a linear feedback shift register.
[0012] This invention provides a method for generating a Dither signal, wherein the Dither signal generation method is implemented using the Dither generation circuit described above;
[0013] The method for generating the Dither signal includes:
[0014] Generate a random number signal;
[0015] After delaying the random number signal for one cycle, an adder is used to calculate the first signal.
[0016] The first signal is processed by performing a 3x gain operation and a 1-cycle delay operation, and then the Dither signal is output by using an adder again.
[0017] This invention provides a Dither signal generation circuit, characterized in that the Dither signal generation circuit is applied in a Sigma Delta modulator, and the Dither signal generation circuit includes a random number generation unit, a second gain unit, a third gain unit, a third delay unit, a fourth delay unit, and a third adder unit;
[0018] The random number generation unit generates random number signals and transmits them to the second gain unit and the third gain unit respectively. The second gain unit performs a 2x gain processing on the random number signal and then transmits it to the third delay unit. The third delay unit performs a one-cycle delay processing on the amplified random number signal and then inputs it to the third adder unit. The third gain unit performs a 3x gain processing on the random number signal and then transmits it to the fourth delay unit. The fourth delay unit performs a two-cycle delay processing on the amplified random number signal and then inputs it to the third adder unit. The third adder unit outputs a Dither signal.
[0019] Preferably, the output terminal of the random number generation unit is connected to the input terminal of the second gain unit, the input terminal of the third gain unit, and the input terminal of the third adder unit, respectively. The output terminal of the second gain unit is connected to the input terminal of the third delay unit. The output terminal of the third gain unit is connected to the input terminal of the fourth delay unit. The output terminals of the third delay unit and the fourth delay unit are respectively connected to the input terminal of the third adder unit. The output terminal of the third adder unit outputs the Dither signal.
[0020] Preferably, the third delay unit includes a delay unit z. -1 The fourth delay unit includes delay unit z. -2 .
[0021] The present invention also provides a method for generating a Dither signal, wherein the method for generating a Dither signal is implemented using the Dither generation circuit described above;
[0022] The method for generating the Dither signal includes:
[0023] Generate a random number signal;
[0024] The random number signal is processed by doubling the gain and then delayed for one cycle before being passed to the adder.
[0025] The random number signal is processed by a 3x gain and a 2-cycle delay before being passed to the adder.
[0026] The Dither signal is output using an adder.
[0027] The present invention provides a Sigma Delta modulator, which includes a loop filter, a quantizer, a first D / A converter, a second D / A converter, a first analog adder, a second analog adder, a digital adder, and a Dither generation circuit as described above.
[0028] Based on common knowledge in the field, the above-mentioned preferred conditions can be combined arbitrarily to obtain various preferred embodiments of this application.
[0029] The positive and progressive effects of this invention are as follows: the Dither signal generation circuit of this invention can generate 7 Dither levels with only 1 bit of random number, which reduces the design requirements of random number and thus saves hardware costs. In addition, the transfer function of the control code is cleverly designed so that the Dither signal has a first-order shaping effect, which greatly reduces the modulator accuracy loss caused by Dither D / A conversion error. Attached Figure Description
[0030] Figure 1 This is a schematic diagram of the first module of the Dither signal generation circuit provided in this embodiment.
[0031] Figure 2 This is a schematic diagram of the first process of the Dither signal generation method provided in this embodiment.
[0032] Figure 3 This is a schematic diagram of the second module of the Dither signal generation circuit provided in this embodiment.
[0033] Figure 4 This is a schematic diagram of the second process of the Dither signal generation method provided in this embodiment.
[0034] Figure 5 This is a schematic diagram of the Sigma Delta modulator module provided in this embodiment. Detailed Implementation
[0035] The present invention will be further illustrated by way of embodiments below, but the present invention is not limited to the scope of the embodiments described herein.
[0036] To more clearly illustrate the technical solutions of the embodiments in this specification, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of this specification. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.
[0037] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application can be combined with other embodiments.
[0038] It should be understood that the terms “system,” “device,” “unit,” and / or “module” used herein are one way to distinguish different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they may be replaced by other expressions.
[0039] As indicated in this specification, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of expressly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.
[0040] In a Sigma Delta modulator, when the input signal is DC, the output signal will exhibit Idle Tone, which greatly reduces the quantization accuracy of the Sigma Delta modulator for DC signals. Therefore, it is necessary to reduce or eliminate Idle Tone in the Sigma Delta modulator. Injecting Dither can disrupt the periodic output of the modulator and is an efficient method to eliminate Idle Tone, which is widely used in Sigma Delta modulators.
[0041] However, due to errors in the digital dither signal during D / A conversion, the dither injected at the front end of the quantizer and the dither subtracted at the back end are not equal. The end result is that the modulator output (Out) contains residual dither signal, which impairs the quantization accuracy of the modulator. Therefore, reducing the residual dither signal is necessary.
[0042] For the reasons mentioned above, this embodiment provides a Dither signal generation circuit, such as... Figure 1 As shown, the Dither signal generation circuit of this embodiment is applied in a Sigma Delta modulator. The Dither generation circuit includes a random number generation unit random_num, a first delay unit 101, a first adder unit 102, a first gain unit 103, a second delay unit 104, and a second adder unit 105.
[0043] The random number generation unit random_num generates a random number signal and passes it to the first delay unit 101. The first delay unit 101 performs a one-cycle delay on the random number signal and then passes it to the first adder unit 102 to obtain the first signal. The first gain unit 103 performs a three-fold gain on the first signal and then passes it to the second delay unit 104. The second delay unit 104 performs a one-cycle delay on the first signal after the gain processing and then passes it to the second adder unit 105. The second adder unit 105 outputs the Dither signal.
[0044] The output of the random number generation unit random_num is connected to the input of the first delay unit 101 and the input of the first adder unit 102, respectively. The output of the first delay unit 101 is connected to the input of the first adder unit 102. The output of the first adder unit 102 is connected to the input of the first gain unit 103 and the input of the second adder unit 105, respectively. The output of the first gain unit 103 is connected to the input of the second delay unit 104. The input of the second delay unit 104 is connected to the input of the second adder unit 105. The output of the second adder unit 105 outputs a Dither signal.
[0045] As an optional implementation of this embodiment, the random number generation unit random_num includes a linear feedback shift register, and the output of the random number generation unit random_num generates a 1-bit random number every cycle.
[0046] Optionally, the first delay unit 101 includes a delay unit z. -1 The second delay unit 104 includes delay unit z -1 .
[0047] The signal transmission of the random number generation unit random_num, the first delay unit 101, the first adder unit 102, the first gain unit 103, the second delay unit 104, and the second adder unit 105 constructs a digital operation process, the corresponding transfer function of which is T(z)=(1-z) -1 (1+3z) -1Therefore, it can be concluded that Dither contains (1-z) -1 The first-order shaping function can greatly reduce the modulator accuracy loss caused by Dither D / A conversion error.
[0048] Corresponding to the above implementation method, such as Figure 2 As shown, this embodiment also provides a Dither signal generation method, which is implemented using the Dither generation circuit described above.
[0049] Methods for generating Dither signals include:
[0050] S101. Generate a random number signal.
[0051] S102. After delaying the random number signal for one cycle, use an adder to calculate and obtain the first signal.
[0052] S103. After performing a 3x gain processing and a 1-cycle delay processing on the first signal, the adder is used again to calculate and output the Dither signal.
[0053] As another optional implementation method of this embodiment, such as Figure 3 As shown, this embodiment also provides a Dither signal generation circuit, which includes a random number generation unit random_num, a second gain unit 201, a third gain unit 202, a third delay unit 203, a fourth delay unit 204, and a third adder unit 205.
[0054] The random number generation unit random_num generates a random number signal and passes it to the second gain unit 201 and the third gain unit 202 respectively. The second gain unit 201 performs a gain of 2 on the random number signal and passes it to the third delay unit 203. The third delay unit 203 performs a one-cycle delay on the amplified random number signal and then inputs it to the third adder unit 205. The third gain unit 202 performs a gain of 3 on the random number signal and then passes it to the fourth delay unit 204. The fourth delay unit 204 performs a two-cycle delay on the amplified random number signal and then inputs it to the third adder unit 205. The third adder unit 205 outputs a Dither signal.
[0055] The output of the random number generation unit random_num is connected to the input of the second gain unit 201, the input of the third gain unit 202, and the input of the third adder unit 205, respectively. The output of the second gain unit 201 is connected to the input of the third delay unit 203. The output of the third gain unit 202 is connected to the input of the fourth delay unit 204. The outputs of the third delay unit 203 and the fourth delay unit 204 are connected to the input of the third adder unit 205, respectively. The output of the third adder unit 205 outputs a Dither signal.
[0056] As an optional implementation of this embodiment, the random number generation unit random_num includes a linear feedback shift register, and the output of the random number generation unit random_num generates a 1-bit random number every cycle.
[0057] Optionally, the third delay unit 203 includes delay unit z. -1 The fourth delay unit 204 includes delay unit z -2 .
[0058] The signal transmission of the random number generation unit random_num, the second gain unit 201, the third gain unit 202, the third delay unit 203, the fourth delay unit 204, and the third adder unit 205 constructs a digital operation process, the corresponding transfer function of which is T(z)=1+2z. -1 -3z -2 And T(z) = 1 + 2z -1 -3z -2 It is T(z)=(1-z) -1 (1+3z) -1 The expansion of ) thus, Dither contains (1-z -1 The first-order shaping function can greatly reduce the modulator accuracy loss caused by Dither D / A conversion error.
[0059] It should be noted that regardless of the transformation, as long as it can ultimately be simplified to 1 + 2z... -1 -3z -2 All forms thereof are included within the scope of this embodiment.
[0060] Corresponding to the above implementation method, such as Figure 4 As shown, this embodiment also provides a Dither signal generation method, which is implemented using the Dither generation circuit described above.
[0061] The Dither signal generation method in this embodiment includes:
[0062] S201. Generate a random number signal.
[0063] S202. The random number signal is processed by doubling the gain and then delayed for one cycle before being passed to the adder.
[0064] S203. The random number signal is processed by a 3x gain and a 2-cycle delay before being transmitted to the adder.
[0065] S204. Calculate and output the Dither signal using an adder.
[0066] Therefore, the expression for the Dither signal generated in this embodiment includes (1-z) -1 The resulting Dither has a built-in first-order shaping effect (in a sigma delta modulator, the sampling frequency is usually much higher than the signal frequency, so 1-z-1≈0, and the accumulated residual Dither noise is very small), which greatly reduces the Dither residue caused by D / A conversion error, thereby avoiding the loss of modulator quantization accuracy.
[0067] Traditional Dither generation methods directly represent Dither levels using binary random codes. As shown in Table 1, 1-bit binary random code can generate 2 Dither levels, 2-bit binary random code can generate 4 random levels, and 3-bit binary random code can generate 8 random levels. It is evident that when multiple random levels are required, a larger number of bits of binary random code are needed, resulting in significant hardware overhead for generating binary random codes.
[0068] Table 1. Dither Levels Corresponding to Traditional Random Codes
[0069]
[0070] Based on the above considerations, in one implementation, the transfer function T(z) = (1-z) -1 (1+3z) -1 Expanding this, we get T(z) = 1 + 2z -1 -3z -2 , z -1 This indicates that the input random code has a delay of one cycle, z. -2 This indicates that the input random code has a delay of 2 cycles. Assume the input random code for the Nth cycle is D. N Then the random codes for the (N-1)th and (N-2)th periods are D respectively. N-1 D N-2 Here, D3 represents the random code for the current period, while D2 and D1 represent the previous and previous two periods, respectively. Therefore, the transfer function T(z) = 1 + 2z -1 -3z-2 In this context, the constant term represents the input D3 for the current cycle. -1 This represents the input D2 from the previous cycle. -2 This represents the input D1 from the cycle two weeks prior. "+" and "-" represent the 1-bit random code D. N Represents positive unit voltage and negative unit voltage.
[0071] Therefore, the following table can be derived.
[0072]
[0073]
[0074] In the table above, the first column lists all possibilities of D3D2D1. The second column represents the transfer function T(z) = 1 + 2z. -1 -3z -2 The calculation process is shown in the third column. The third column shows the result of the transfer function calculation, i.e., the generated Dither level.
[0075] As shown in the table above, seven Dither levels with voltages of 0, ±2, ±4, and ±6 units were generated. If the represented voltage is halved, the Dither voltage values that can be represented are 0, ±1, ±2, and ±3 units.
[0076] Furthermore, compared to the traditional 3-bit random code representing 8 Dither levels (as shown in Table 1), the Dither signal generation circuit in this embodiment only needs to generate 1-bit random code to represent 7 Dither levels, reducing the design requirements for random numbers and thus saving hardware overhead. At the same time, the transfer function of the control code is cleverly designed, so that the Dither signal has a built-in first-order shaping effect, which greatly reduces the modulator accuracy loss caused by Dither D / A conversion error.
[0077] like Figure 5 As shown, this embodiment also provides a Sigma Delta modulator, which includes a loop filter, a quantizer, a first D / A converter, a second D / A converter, a first analog adder, a second analog adder, a digital adder, and the Dither generation circuit as described above.
[0078] Furthermore, compared to traditional Sigma Delta modulators, it not only ensures the quantization accuracy of DC signals, but also greatly reduces the modulator accuracy loss caused by Dither D / A conversion errors by leveraging the first-order shaping effect inherent in Dither.
[0079] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of the present invention is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of the present invention, but all such changes and modifications fall within the scope of protection of the present invention.
Claims
1. A Dither signal generation circuit, characterized in that, The Dither signal generation circuit is applied in the SigmaDelta modulator. The Dither signal generation circuit includes a random number generation unit, a first delay unit, a first adder unit, a first gain unit, a second delay unit, and a second adder unit. The random number generation unit generates a random number signal and transmits it to the first delay unit. The first delay unit performs a one-cycle delay on the random number signal and then transmits it to the first adder unit to obtain a first signal. The first gain unit performs a three-fold gain on the first signal and then transmits it to the second delay unit. The second delay unit performs a one-cycle delay on the first signal after the gain processing and then transmits it to the second adder unit. The second adder unit outputs the Dither signal. The output of the random number generation unit is connected to the input of the first delay unit and the first input of the first adder unit, respectively. The output of the first delay unit is connected to the second input of the first adder unit. The output of the first adder unit is connected to the input of the first gain unit and the first input of the second adder unit, respectively. The output of the first gain unit is connected to the input of the second delay unit. The input of the second delay unit is connected to the second input of the second adder unit. The output of the second adder unit outputs the Dither signal.
2. The Dither signal generation circuit as described in claim 1, characterized in that, The first delay unit includes a delay unit. The second delay unit includes a delay unit. .
3. The Dither signal generation circuit as described in claim 1, characterized in that, The random number generation unit includes a linear feedback shift register.
4. A method for generating a Dither signal, wherein the Dither signal generation method is implemented using a Dither signal generation circuit as described in any one of claims 1-3; The method for generating the Dither signal includes: Generate a random number signal; After delaying the random number signal for one cycle, an adder is used to calculate the first signal. The first signal is processed by performing a 3x gain operation and a 1-cycle delay operation, and then the Dither signal is output by calculating again using an adder.
5. A Dither signal generation circuit, characterized in that, The Dither signal generation circuit is applied in the SigmaDelta modulator. The Dither signal generation circuit includes a random number generation unit, a second gain unit, a third gain unit, a third delay unit, a fourth delay unit, and a third adder unit. The random number generation unit generates random number signals and transmits them to the third adder unit, the second gain unit, and the third gain unit respectively. The second gain unit performs a 2x gain processing on the random number signal and then transmits it to the third delay unit. The third delay unit performs a 1-cycle delay processing on the amplified random number signal and then inputs it to the third adder unit. The third gain unit performs a 3x gain processing on the random number signal and then transmits it to the fourth delay unit. The fourth delay unit performs a 2-cycle delay processing on the amplified random number signal and then inputs it to the third adder unit. The third adder unit outputs a Dither signal. The output of the random number generation unit is connected to the input of the second gain unit, the input of the third gain unit, and the first input of the third adder unit. The output of the second gain unit is connected to the input of the third delay unit. The output of the third gain unit is connected to the input of the fourth delay unit. The outputs of the third delay unit and the fourth delay unit are connected to the second and third inputs of the third adder unit, respectively. The output of the third adder unit outputs the Dither signal.
6. The Dither signal generation circuit as described in claim 5, characterized in that, The third delay unit includes a delay unit. The fourth delay unit includes a delay unit. .
7. A method for generating a Dither signal, wherein the Dither signal generation method is implemented using the Dither signal generation circuit as described in claim 5 or 6; The method for generating the Dither signal includes: Generate a random number signal; The random number signal is processed by doubling the gain and then delayed for one cycle before being passed to the adder. The random number signal is processed by a 3x gain and a 2-cycle delay before being passed to the adder. The Dither signal is output using an adder.
8. A Sigma Delta modulator, characterized in that, The Sigma Delta modulator includes a loop filter, a quantizer, a first D / A converter, a second D / A converter, a first analog adder, a second analog adder, a digital adder, and a Dither signal generation circuit as described in any one of claims 1-3 or as described in claim 5 or 6.