Electronic device and method of operating the same

Abstract

An electronic device and an operating method thereof are provided. The electronic device can include a crossbar array including a plurality of first memory cells, a plurality of second memory cells, a plurality of row lines, a plurality of first column lines, and a second column line, and a plurality of analog-to-digital converters respectively coupled to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage. Each of the plurality of analog-to-digital converters determines an allowed maximum value of an analog signal voltage based on the reference voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0133461, filed with the Korean Intellectual Property Office on October 7, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The various embodiments of this disclosure generally relate to an electronic device, and more specifically, to an electronic device and a method of operating the electronic device. Background Technology

[0004] In neural networks, artificial neurons, obtained by simplifying the function of biological neurons, can be used, and these artificial neurons can be connected to each other via connection lines with connection weights. Connection weights are parameters of the neural network. Connection weights can be specific values ​​for the connection lines and can indicate the strength of the connection. Neural networks can use artificial neurons to perform human cognitive actions or learning processes. Artificial neurons can also be referred to as nodes.

[0005] A neural network can include multiple layers. For example, a neural network can include an input layer, hidden layers, and an output layer. The input layer receives input data for performing learning and passes the learned data to the hidden layers. The output layer generates the neural network's output data based on signals received from nodes in the hidden layers. The hidden layer can be positioned between the input and output layers and can modify the learned data passed from the input layer into easily predictable values. Nodes in the input and hidden layers can be connected to each other via weighted connections, and nodes in the hidden and output layers can also be connected to each other via weighted connections. Each of the input, hidden, and output layers can include multiple nodes.

[0006] A neural network can include multiple hidden layers. A neural network with multiple hidden layers is called a deep neural network, and training a deep neural network is called deep learning. The nodes included in a hidden layer are called hidden nodes. In the following text, it can be understood that training a neural network is to allow the neural network to learn the parameters of the neural network. Further, a trained neural network can be understood as a neural network that has applied the learned parameters.

[0007] Here, a pre-defined loss function can be used as an indicator to train the neural network. The loss function can be an indicator used to allow the neural network to learn and determine the optimal weight parameters. The neural network can be trained to minimize the result obtained using the pre-defined loss function.

[0008] This type of neural network refers to a computational architecture used to model the biological brain. Recently, with the development of neural network technology, research has been actively underway on techniques for extracting useful information from input data based on one or more neural network models in various types of electronic systems. Convolution operations account for a significant portion of the computation required by neural network models.

[0009] On the other hand, an analog-to-digital converter (ADC) can be a device used to convert analog signals into digital signals. Such an ADC can be used to implement neural network models. For example, a neural network model can perform multiply-accumulate (MAC) operations between matrices and vectors using analog signal processing schemes. In this case, the ADC can be used to convert the result of the MAC operation into a digital signal. Summary of the Invention

[0010] Various embodiments of this disclosure relate to an electronic device and a method of operating the electronic device that can reduce errors in the quantization operation of an analog-to-digital converter by adjusting the input range of the analog-to-digital converter according to input data.

[0011] Embodiments of this disclosure may provide an electronic device. The electronic device may include a crossbar array comprising: a plurality of first memory cells storing a plurality of conductance values; a plurality of second memory cells storing a maximum conductance value determined among the plurality of conductance values; a plurality of row lines connected to the plurality of first memory cells and the plurality of second memory cells, supplying a plurality of input voltages to the plurality of first memory cells and the plurality of second memory cells; a plurality of first column lines connected to the plurality of first memory cells and configured to output a plurality of output currents generated using the plurality of input voltages and the plurality of conductance values; and a second column line connected to the plurality of second memory cells and configured to output a maximum output current generated using the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells. The electronic device may also include: a plurality of analog-to-digital converters connected to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage and an analog signal voltage corresponding to each of the plurality of output currents, and configured to generate a digital signal corresponding to the analog signal voltage based on the reference voltage, the reference voltage being generated according to the maximum output current. Each of the multiple analog-to-digital converters determines the maximum allowable analog signal voltage based on a reference voltage.

[0012] Embodiments of this disclosure may provide an electronic device. The electronic device may include a crossbar switch array comprising: a plurality of first memory cells storing a plurality of conductance values; a plurality of second memory cells storing the maximum conductance value among the plurality of conductance values; a plurality of row lines connected to the plurality of first memory cells and the plurality of second memory cells, supplying a plurality of input voltages to the plurality of first memory cells and the plurality of second memory cells; a plurality of first column lines connected to the plurality of first memory cells and configured to output a plurality of output currents generated using the plurality of input voltages and the plurality of conductance values; and a second column line connected to the plurality of second memory cells and configured to output a maximum output current generated using the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells. The electronic device may also include: a plurality of analog-to-digital converters connected to the plurality of first column lines, each of the plurality of analog-to-digital converters receiving a reference voltage and an analog signal voltage corresponding to each of the plurality of output currents, and configured to convert the analog signal voltage into a digital signal corresponding to the analog signal voltage by applying a gain corresponding to the reference voltage to the analog signal voltage, the reference voltage being generated based on the maximum output current.

[0013] Embodiments of this disclosure may provide a method of operating an electronic device including a crossbar switch array, the crossbar switch array including multiple row lines, multiple first column lines, second column lines, multiple first memory cells connected to the multiple row lines and the multiple first column lines, and multiple second memory cells connected to the multiple row lines and the multiple second column lines. The method may include: receiving multiple input voltages through the multiple row lines; generating a maximum output current based on a maximum conductance value stored in each of the multiple second memory cells and the multiple input voltages, the maximum conductance value corresponding to the maximum conductance value among the multiple conductance values ​​stored in the multiple first memory cells; converting the maximum output current into a reference voltage; and determining, based on the reference voltage, a permissible maximum value of an analog signal voltage input to each of a plurality of analog-to-digital converters respectively connected to the multiple first column lines. Attached Figure Description

[0014] Figures 1A to 1D A neural network according to an embodiment of the present disclosure is shown.

[0015] Figure 2A An electronic device according to an embodiment of the present disclosure is shown.

[0016] Figure 2B An electronic device according to another embodiment of the present disclosure is shown.

[0017] Figure 3 A cross switch array according to an embodiment of the present disclosure is shown.

[0018] Figure 4 A cross switch array according to an embodiment of the present disclosure is shown.

[0019] Figures 5A to 5D The memory cells of the crossbar switch array are shown.

[0020] Figures 6A to 6C It shows Figure 4 Operations on the cross switch array.

[0021] Figure 7 An analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0022] Figure 8 It shows Figure 7 The operation of the analog-to-digital converter.

[0023] Figures 9A to 9E The input range of an analog-to-digital converter according to an embodiment of the present disclosure is shown.

[0024] Figure 10 An electronic device according to an embodiment of the present disclosure is shown.

[0025] Figures 11A to 11D An embodiment according to this disclosure is shown. Figure 10 The second column line.

[0026] Figures 12A to 12D The operation of an analog-to-digital converter according to an embodiment of the present disclosure is illustrated.

[0027] Figure 13 An electronic device according to another embodiment of the present disclosure is shown.

[0028] Figure 14 and Figure 15 This is a diagram illustrating a voltage buffer according to an embodiment of the present disclosure.

[0029] Figure 16 An electronic device according to yet another embodiment of the present disclosure is shown.

[0030] Figure 17A and Figure 17B A digital signal controller according to an embodiment of the present disclosure is shown.

[0031] Figure 18A and Figure 18B The operation of a digital signal controller according to an embodiment of the present disclosure is illustrated.

[0032] Figure 19 A neural network operation using multiple electronic devices is illustrated according to an embodiment of the present disclosure.

[0033] Figure 20This is a flowchart illustrating a method of operating an electronic device according to an embodiment of the present disclosure.

[0034] Figure 21 This is a flowchart illustrating a method of operating an electronic device according to another embodiment of the present disclosure.

[0035] Figure 22 This is a flowchart illustrating a method for outputting multiple output currents through multiple first column lines according to an embodiment of the present disclosure.

[0036] Figure 23 This is a flowchart illustrating a method for outputting maximum output current via a second column of lines according to an embodiment of the present disclosure.

[0037] Figure 24 This is a flowchart illustrating a method for outputting a digital signal via an analog-to-digital converter according to an embodiment of the present disclosure.

[0038] Figure 25 This is a flowchart illustrating a method for performing digital signal processing operations according to an embodiment of the present disclosure.

[0039] Figure 26 A computing system according to an embodiment of the present disclosure is shown.

[0040] Figure 27 It shows Figure 26 Neural network processor.

[0041] Figure 28 It shows Figure 27 The controller.

[0042] Figure 29 It shows Figure 27 The computing circuit.

[0043] Figure 30 It shows Figure 29 The subarray.

[0044] Figure 31 A cross switch array with a hierarchical structure according to an embodiment of the present disclosure is shown.

[0045] Figure 32 A neural network processor according to an embodiment of the present disclosure is shown.

[0046] Figure 33 The connection between a first neuron and a second neuron according to an embodiment of the present disclosure is shown.

[0047] Figure 34 It is shown Figure 33 The graph shows the operational characteristics of the memristor included in the synapse.

[0048] Figure 35 and Figure 36 It shows in Figure 33 The characteristics of the current flowing between the first and second neurons and the relationship between the difference in the number of spikes during a typical STDP operation and the change in synaptic weights.

[0049] Figure 37 A neural network processor according to an embodiment of the present disclosure is shown.

[0050] Figure 38 An embodiment according to this disclosure is shown. Figure 37 One of the multiple synapses included in the synaptic array.

[0051] Figure 39 An embodiment according to this disclosure is shown. Figure 37 The second neuron. Detailed Implementation

[0052] The specific structural or functional descriptions of embodiments of this disclosure incorporated in this specification or application are exemplified as describing embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be practiced in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0053] Figures 1A to 1D A neural network according to an embodiment of the present disclosure is shown.

[0054] Reference Figure 1A The neural network can be a deep neural network (DNN) or an n-layer neural network. A deep neural network (DNN) or an n-layer neural network can correspond to a convolutional neural network (CNN), a recurrent neural network (RNN), a deep belief network (DBN), a restricted Boltzmann machine (RBM), etc. For example, in this embodiment, the neural network can be implemented as, but is not limited to, a convolutional neural network (CNN).

[0055] Although Figure 1A The diagram shows that a convolutional neural network (CNN) includes multiple convolutional layers, but in addition to multiple convolutional layers, a CNN can further include pooling layers, fully connected layers, etc.

[0056] Neural networks can be implemented as an architecture with multiple layers, including input data, feature maps, and output data. In a neural network, a first convolution operation is performed on the input data using filters called weights, and the output feature map is the result of this first convolution operation. The resulting output feature map can then be used as the input feature map to perform a second convolution operation using the weights, thus outputting a new feature map as the result of the second convolution operation. As a result of repeatedly performing this convolution operation, the final output data is the feature map that the neural network uses to identify the features of the input data.

[0057] Reference Figure 1B This can explain the relationship between the input feature map and the output feature map in a neural network.

[0058] In any layer of a neural network, a first feature map FM1 can correspond to an input feature map, and a second feature map FM2 can correspond to an output feature map. Each feature map can indicate a dataset representing various features of the input data. Each of the first feature map FM1 and the second feature map FM2 can have elements in the form of a two-dimensional (2D) matrix or a three-dimensional (3D) matrix, and pixel values ​​can be defined in each element. In a 3D matrix, each of the first feature map FM1 and the second feature map FM2 has a width W (or referred to as a "column"), a height H (or referred to as a "row"), and a depth D. Here, the depth D can correspond to the number of channels. Therefore, multiple rows, multiple columns, and multiple channels can form a 3D matrix for each of the first feature map FM1 and the second feature map FM2.

[0059] A convolution operation can be performed on a first feature map FM1 and weights, and a second feature map FM2 can be generated as a result of the convolution operation. The weights can be used to perform the convolution operation using the first feature map FM1, and thus can filter the features included in the first feature map FM1. The weights can be used to perform the convolution operation using windows (or "tiles") of the first feature map FM1 while moving a sliding window along the first feature map FM1 in a sliding window manner. That is, windows of the first feature map FM1 are generated by moving a sliding window along the first feature map FM1. The windows of the first feature map FM1 partially overlap each other, and therefore these windows can be called "overlapping windows." During each movement operation, the weights can be multiplied and added to each pixel value in each of the overlapping windows in the first feature map FM1. Due to the convolution of the first feature map FM1 and the weights, one channel of the second feature map FM2 can be generated. Although in Figure 1B The diagram shows a single weight, but in practice, multiple weights can be convolved individually with the first feature map FM1, and thus a second feature map FM2 with multiple channels can be generated.

[0060] On the other hand, the second feature map FM2 can correspond to the input feature map of the next layer. For example, the second feature map FM2 can be used as the input feature map of the next layer, such as the pooling (or subsampling) layer. (See reference...) Figure 1C A neural network can include an input layer IL, multiple hidden layers HL1 and HL2, and an output layer OL. Although Figure 1C Two hidden layers are shown, but the number of hidden layers can vary depending on the embodiment. Figure 1C In the middle, one can interpret the reference. Figure 1A and Figure 1B The relationships between the described layers.

[0061] The input layer IL may include two input nodes x1 and x2, and input data IDATA may be input to each of input nodes x1 and x2. On the other hand, the number of input nodes included in the input layer IL may vary depending on the embodiment.

[0062] Hidden layer HL1 may include three hidden nodes h11, h12, and h13, and hidden layer HL2 may include three hidden nodes h21, h22, and h23. On the other hand, the number of hidden layers included in each hidden layer is not limited to three and may vary depending on the embodiment.

[0063] The output layer OL may include two output nodes y1 and y2, and can output the result of processing the input data IDAT as output data ODATA. On the other hand, the number of output nodes included in the output layer OL may vary depending on the embodiment.

[0064] Figure 1C The neural network architecture shown may include connections (or branches) between nodes, each connection indicated by a straight line between two nodes in two consecutive layers, although not shown in the figures, and may also include weights used in the various branches. In this case, nodes in a layer may not be connected to each other, and nodes in two consecutive layers may be connected to each other.

[0065] Reference Figure 1C A node (e.g., h11) can receive the output of a previous node (e.g., x1), perform a computation on the output of the previous node (e.g., x1), and output the result to a subsequent node (e.g., h21). Here, a node (e.g., h11) can compute the value to be output by applying the input value to a specific function, such as a nonlinear function.

[0066] Typically, the architecture of a neural network is predetermined, and the weights corresponding to the connections (or branches) between nodes are determined using data, i.e., their known labels (answers), to have appropriate values. The multiple pieces of data already acquired in this way, i.e., the labels, are called "learning data," and the process of determining the weights is called "learning." Further, a set of independently learnable structures and weights can be assumed to be a "model," and the process of allowing the model to determine its weights to predict the category to which the input data belongs and output its predicted value can be called the "testing" process.

[0067] Figure 1D It shows the result of Figure 1C The operation performed by one of the nodes shown is ND. Assume that n inputs a1, a2, ..., an are provided to node ND.

[0068] In this embodiment, node ND can generate an output value by multiplying the n inputs a1, a2, ..., an by the n weights w1, w2, ..., wn respectively, summing the multiplication results, adding the bias b to the summation value, and applying the summation value with bias b added to it to a specific function σ. Here, the specific function σ can be an activation function.

[0069] when Figure 1C When a layer in the neural network shown contains m nodes ND, the output value of a layer can be obtained using the following equation (1):

[0070] W*A=Z (1)

[0071] In equation (1), “W” can represent the weights of all the connections included in a layer, and can be implemented as an m*n matrix. “A” can represent the n inputs a1, a2, ..., an received by a layer, and can be implemented as an n*1 matrix. “Z” can represent the m outputs from a layer, and can be implemented as an m*1 matrix.

[0072] exist Figures 1A to 1D For ease of description, only a schematic architecture of the neural network is shown in the figures. However, those skilled in the art will understand that, unlike the architecture shown, neural networks can be implemented with more or fewer layers, feature maps, or weights than those shown in the figures, and their size can vary in various forms.

[0073] Figure 2A An electronic device 200a according to an embodiment of the present disclosure is shown.

[0074] Electronic device 200a may be used for implementing reference Figures 1A to 1D The apparatus described is a neural network.

[0075] Reference Figure 2A The electronic device 200a may include a cross switch array 210, multiple current-to-voltage converters (IVCs) 220 and multiple analog-to-digital converters (ADCs) 230.

[0076] The crossbar switch array 210 may include multiple memory cells arranged in a matrix, each memory cell including a resistive element. Here, each memory cell may be a resistive memory cell. Each of the multiple memory cells may be connected to one of a plurality of row lines and one of a plurality of column lines. Referring then to... Figure 3 and Figure 4 Describe the detailed structure of the cross switch array 210.

[0077] The crossbar switch array 210 stores multiple weight data. For example, multiple weight data can be stored in multiple memory cells using the resistance variation of resistive elements included in each of the multiple memory cells. Furthermore, the crossbar switch array 210 can generate multiple output currents Iout based on multiple input voltages Vin and multiple weight data.

[0078] For example, multiple input voltages Vin can be input to the crossbar switch array 210 via multiple row lines. Multiple weight data can be provided to and stored in multiple memory cells via multiple column lines.

[0079] In embodiments, electronic device 200a can be included in various types of electronic devices, such as personal computers (PCs), server devices, mobile devices, and embedded devices. Electronic device 200a can correspond to hardware components included in, for example, smartphones, tablets, augmented reality (AR) devices, Internet of Things (IoT) devices, autonomous vehicles, robots, or medical devices. Electronic device 200a can use neural networks to perform speech recognition, image recognition, image classification, etc. That is, electronic device 200a can correspond to a dedicated hardware (HW) accelerator installed in the aforementioned electronic devices, and can be, but is not limited to, a hardware accelerator such as a neural processing unit (NPU), tensor processing unit (TPU), neural engine, TrueNorth, or Loihi for driving dedicated modules of neural networks.

[0080] In an embodiment, electronic device 200a can be used to drive any neural network system, such as an artificial neural network (ANN) system, a convolutional neural network (CNN) system, a deep neural network (DNN) system, or a deep learning system and / or a machine learning system.

[0081] For example, various types of services and applications, such as image classification services, biometric-based user authentication services, advanced driver assistance systems (ADAS) services, voice assistant services, and automatic speech recognition (ASR) services, can be operated and processed by electronic device 200a. In this case, the data stored in the crossbar switch array 210 can be multiple weight data included in multiple layers constituting a neural network, and multiple output currents Iout and multiple signal voltages Vsig can represent the result of a multiply-accumulate (MAC) operation performed by the neural network. In other words, electronic device 200a can perform data storage operations and computation operations simultaneously.

[0082] Multiply-accumulate operations can be used in a variety of applications. For example, given an audio or video signal, a user might need to filter the signal, perform a Fast Fourier Transform (FFT), or process the analog or digital signal in other ways. In these examples, multiply-accumulate operations can be used to perform such processing. Given the widespread use of multiply-accumulate operations in discrete-time or discrete-space signal processing, this optimization may be an ideal solution for improving the efficiency of digital signal processing.

[0083] Although not shown in detail, the cross switch array 210 can drive multiple row lines based on a row line selection signal for selecting at least one of the multiple row lines and a row line drive voltage for driving at least one of the multiple row lines.

[0084] Although not shown in detail, the cross switch array 210 can drive multiple column lines based on a column line selection signal for selecting at least one of the multiple column lines and a column line drive voltage for driving at least one of the multiple column lines.

[0085] Each memory cell included in the crossbar switch array 210 can correspond to a synapse or connection in a neural network and can store one weight data. Therefore, the m*n weight data stored in the crossbar switch array 210 can correspond to the weights described above. Figures 1A to 1D The weight matrix is ​​implemented in the form of an m*n matrix in one of the layers, that is, W in the above equation (1).

[0086] The input voltage Vin applied through multiple lines can correspond to, for example... Figures 1A to 1D The n inputs a1, a2, ..., an received by a layer are shown, and can correspond to an input matrix implemented in the form of an n*1 matrix, i.e., A in the above equation (1).

[0087] The output current Iout from multiple column lines can correspond to, for example: Figures 1A to 1DThe m outputs shown are from a layer and can correspond to the output matrix implemented in the form of an m*1 matrix, i.e., Z in the above equation (1).

[0088] In other words, when multiple weight data in the form of an m*n matrix are stored in multiple memory cells to implement a cross-switch array 210, when an input voltage Vin corresponding to the input data is input through multiple row lines, the output current Iout output through multiple column lines can be the result of a multiplication-accumulation operation performed in the neural network. When all the multiple layers of the neural network are implemented in this way, an electronic device 200a that performs data storage operations and computation operations simultaneously can be implemented.

[0089] Multiple current-to-voltage converters (IVCs) 220 can be connected between the cross switch array 210 and multiple analog-to-digital converters 230. The multiple current-to-voltage converters 220 can convert multiple output currents Iout into multiple analog signal voltages Vsig. In other words, the electronic device 200a can use the cross switch array 210 and the multiple current-to-voltage converters 220 to perform multiplication-accumulation operations on multiple input voltages Vin and multiple weighted data, and can generate individual analog signal voltages Vsig to be input to the multiple analog-to-digital converters 230 based on the results of the multiplication-accumulation operations. Each of the multiple current-to-voltage converters 220 can be implemented as a trans-impedance amplifier (TIA).

[0090] Multiple analog-to-digital converters 230 can receive various analog signal voltages Vsig and convert the analog signal voltages Vsig into multiple digital signals DS respectively.

[0091] Figure 2B An electronic device 200b according to another embodiment of the present disclosure is shown.

[0092] Reference Figure 2B The electronic device 200b may include a cross switch array 210, multiple current-to-voltage converters (IVCs) 220 and an analog-to-digital converter (ADC) 230'.

[0093] because Figure 2B The cross switch array 210 and multiple current-to-voltage converters 220 have the same characteristics as... Figure 2A Since the configuration is the same, repeated descriptions of it will be omitted.

[0094] exist Figure 2BIn the illustrated embodiment, multiple column lines can share a single analog-to-digital converter 230'. The advantage in this case is that the number of analog-to-digital converters can be reduced, thus decreasing the area occupied by the converters compared to embodiments employing multiple converters.

[0095] In the following description, for ease of description, the electronic device will be described assuming that it includes multiple analog-to-digital converters. However, this is merely an example, and the configuration and operation of the electronic device described below can also be applied to electronic devices that share a single analog-to-digital converter.

[0096] Figure 3 A cross switch array 210 according to an embodiment of the present disclosure is shown. Figure 3 The cross switch array 210 shown can correspond to Figure 2A and Figure 2B Each of the cross switch arrays 210.

[0097] For ease of description, Figure 3 The diagram shows 4 column lines and 3 row lines, but the number of column lines and row lines is not limited to this.

[0098] Reference Figure 3 The crossbar switch array 210 may include row lines arranged sequentially along the row direction. Furthermore, the crossbar switch array 210 may include column lines arranged sequentially along the column direction. Further, the crossbar switch array 210 may include multiple memory cells disposed at the intersections of the row lines and column lines. The number, shape, conductive material, etc., of the row lines and column lines may vary depending on the embodiment.

[0099] For example, row lines can be arranged perpendicular to column lines. Row and column lines can form a grid or crossover. At the intersection of row and column lines, row lines can be positioned above and in close contact with column lines. In embodiments, row and column lines can have rectangular, square, circular, or elliptical cross-sections or more complex cross-sections at each intersection, and column lines can vary depending on the embodiment. Furthermore, row and column lines can have different widths or diameters, as well as different crossover ratios or eccentricities.

[0100] At the intersection, the memory cell can be configured to connect column lines and row lines to each other. In one embodiment, the memory cell may include physical contact between the column lines and row lines. In other embodiments, the memory cell may not include physical contact between the column lines and row lines.

[0101] Furthermore, the cross switch array 210 may have the following properties: Figure 3 The array shown is a stacked structure with multiple vertical stacks.

[0102] Figure 4 A cross switch array 210 according to an embodiment of the present disclosure is shown. Figure 4 The cross switch array 210 shown can correspond to Figure 2A , Figure 2B and Figure 3 Each of the cross switch arrays 210.

[0103] For ease of description, Figure 4 The diagram shows 3 column lines and 3 row lines, but the number of column lines and row lines is not limited to this.

[0104] Reference Figure 4 The crossbar switch array 210 may include multiple memory cells arranged in a matrix, each memory cell including a resistive element. The resistive element has a resistance value that varies with the write voltage applied to it, and the multiple memory cells can use this resistance variation to store data.

[0105] In this embodiment, each memory cell can store data based on the conductance value of a resistive element, and the conductance value can correspond to the conductive state of the resistive element. The memory cell can indicate various logic values ​​and store individual data bits by updating the conductance values.

[0106] Furthermore, resistive elements can be used to indicate multiple bits. For example, a resistive element with a first conductance value can indicate the logic value "0". A resistive element with a second conductance value can indicate the logic value "1". By changing the conductance value of the resistive element, different data can be stored in the memory cell. The conductance value can be changed by applying voltage to the column and row lines connected to the memory cell.

[0107] In an embodiment, each memory cell (CELL) can be implemented to include any memory cell, such as a phase-change random access memory (PRAM) cell, a resistive random access memory (RRAM) cell, a magnetic RAM (MRAM) cell, or a ferroelectric random access memory (FRAM) cell. Each of the plurality of memory cells (CELLs) can be connected to one of a plurality of row lines and one of a plurality of column lines.

[0108] The crossbar switch array 210 stores multiple weight data in multiple memory cells. Here, the multiple weight data can correspond to the conductance values ​​G11, G12, G13, G21, G22, G23, G31, G32, and G33 of the multiple memory cells, respectively. For example, the multiple weight data can be stored in the multiple memory cells using the resistance variation of the resistive element included in each of the multiple memory cells.

[0109] Furthermore, the cross switch array 210 can perform multiplication and accumulation operations on multiple input voltages and multiple weighted data. For example, multiple input voltages can be input to the cross switch array 210 through multiple row lines.

[0110] The cross switch array 210 can output multiple output currents as the result of a multiplication and accumulation operation. For example, multiple output currents can be output through multiple column lines.

[0111] Figures 5A to 5D The memory cells of the crossbar switch array are shown.

[0112] Reference Figure 5A A memory cell can be connected to a row line and a column line.

[0113] The memory cell can have resistive elements.

[0114] The memory cell can use resistive elements to store the conductance value G11 corresponding to a weighted data. For example, the memory cell can receive the conductance value G11 through column lines and can store the conductance value G11 therein.

[0115] The memory cell (CELL) can receive the input voltage Vin via row lines. The memory cell (CELL) can output the output current Ir by performing a multiplication operation on the input voltage Vin and the conductance value G11.

[0116] Reference Figure 5B In an embodiment, the resistive element included in the memory cell (CELL) can be implemented as a memristor. A memristor is a combination of memory and register, and is a memory element that remembers all previous states. Because a memristor stores the direction and amount of current flowing through it immediately before the power interruption, even when the power supply is interrupted, the memristor's previous state can be restored when the power supply is restored. Resistive elements such as memristors can use resistance levels to indicate specific logic values ​​such as 1 or 0. When a memristor is used as a resistive element in a memory cell (CELL), by applying activation energy such as voltage pulses with different values ​​or polarities, the memristor is placed in a low-resistance state associated with a logic value such as 1, thereby accumulating digital operations. Furthermore, voltage pulses with different polarities or values ​​may place the memristor in a high-resistance state associated with another logic value such as "0".

[0117] Memristors can possess the characteristics of electronic components known as memristors. A memristor can have a switching voltage, so a current flowing through it and generating a voltage lower than the switching voltage does not change the memristor's state. When the applied voltage is blocked and the flow of charge stops, the memristor can remember its last resistance, and when the flow of charge resumes, the memristor can have the resistance it had when it was last activated. A memristor can be a variable resistor device. A memristor can have a resistance value that varies with the write voltage applied to it, and a memory cell (CELL) that includes a memristor can use this resistance variation to store data.

[0118] exist Figure 5C In the middle, the word line WL and the bit line BL can correspond to Figure 4 The row lines, and the source line SL can correspond to Figure 4 The column lines.

[0119] A memory cell (CELL) may include a cell transistor (CT) and a resistive element (RE). Here, the resistive element RE may be implemented as a memristor. The memory cell (CELL) may be connected to one of a plurality of word lines (WL), one of a plurality of bit lines (BL), and one of a plurality of source lines (SL). For example, the cell transistor (CT) may include a first electrode connected to the source line (SL), a gate electrode connected to the word line (WL), and a second electrode. The resistive element RE may be connected and disposed between the second electrode of the cell transistor (CT) and the bit line (BL).

[0120] For example, when a power supply voltage is applied to the word line WL, a write voltage is applied to the bit line BL, and a ground voltage is applied to the source line, the data "1" can be stored in the memory cell CELL. Furthermore, when a power supply voltage is applied to the word line WL, a ground voltage is applied to the bit line BL, and a write voltage is applied to the source line SL, the data "0" can be stored in the memory cell CELL. Additionally, when a power supply voltage is applied to the word line WL, a read voltage is applied to the bit line BL, and a ground voltage is applied to the source line SL, the data stored in the memory cell CELL can be read.

[0121] Reference Figure 5D A memory cell (CELL) may include a cell transistor (CT) and a phase change material (PCM) element. The CT may have a drain terminal connected to ground, a gate terminal connected to a row line, and a source terminal connected to the PCM element. The PCM element may have a first terminal connected to the source terminal of the CT and a second terminal connected to a column line. The PCM element can store data using changes in its resistance.

[0122] On the other hand, although the crossbar switch array 210 has been described in the above embodiments as being formed in a two-dimensional (2D) array structure, the embodiments are not limited thereto. According to another embodiment, the crossbar switch array 210 can be formed in a three-dimensional (3D) array structure. According to the embodiments, the structure of the memory cells can also be changed.

[0123] Figures 6A to 6C It shows Figure 4 Operations of the cross switch array 210.

[0124] Reference Figure 6A The cross switch array 210 can store multiple conductance values ​​G11 to G33 corresponding to multiple weight data.

[0125] For example, the multiple memory cells CELL included in the cross switch array 210 can store multiple conductance values ​​G11 to G33 respectively.

[0126] In this embodiment, the crossbar switch array 210 can receive a matrix consisting of multiple conductance values ​​G11 to G33 via multiple column lines. Here, the size of the matrix can be equal to the size of the crossbar switch array 210, which consists of multiple memory cells.

[0127] Reference Figure 6B The cross switch array 210 can perform multiplication and accumulation operations on multiple input voltages V1 to V3 and multiple weight data G11 to G33.

[0128] For example, the cross switch array 210 can receive multiple input voltages V1 to V3 corresponding to the input data through multiple row lines. Figure 5A and 5B As shown, the crossbar switch array 210 can perform multiplication operations on the conductance values ​​G11 to G33 stored in the memory cells and the input voltages V1 to V3. For example, the memory cells connected to the first column of multiple columns can perform multiplication operations on the first input voltage V1 and the conductance value G11, on the second input voltage V2 and the conductance value G21, and on the third input voltage V3 and the conductance value G31. For example, the memory cells connected to the second column of multiple columns can perform multiplication operations on the first input voltage V1 and the conductance value G12, on the second input voltage V2 and the conductance value G22, and on the third input voltage V3 and the conductance value G32. For example, a memory cell connected to the third column line among multiple column lines can perform a multiplication operation on the first input voltage V1 and conductance value G13, a multiplication operation on the second input voltage V2 and conductance value G23, and a multiplication operation on the third input voltage V3 and conductance value G33.

[0129] Furthermore, the cross switch array 210 can perform an accumulation operation on the results of multiplication of the conductance values ​​G11 to G33 of each column line with the input voltages V1 to V3. For example, for the first column line among the multiple columns, the accumulation operation is performed on the results of multiplication of the first input voltage V1 and conductance value G11, the results of multiplication of the second input voltage V2 and conductance value G21, and the results of multiplication of the third input voltage V3 and conductance value G31. Therefore, as a result of the multiplication accumulation operation, the first column line can output a first output current I1 (=V1xG11+V2xG21+V3xG31). For example, for the second column line among the multiple columns, the accumulation operation is performed on the results of multiplication of the first input voltage V1 and conductance value G12, the results of multiplication of the second input voltage V2 and conductance value G22, and the results of multiplication of the third input voltage V3 and conductance value G32. As a result of the multiplication and accumulation operation, the second column line can output a second output current I2 (=V1xG12+V2xG22+V3xG32). For example, for the third column line among multiple column lines, an accumulation operation is performed on the results of the multiplication operation of the first input voltage V1 and conductance value G13, the multiplication operation of the second input voltage V2 and conductance value G23, and the multiplication operation of the third input voltage V3 and conductance value G33. As a result of the multiplication and accumulation operation, the third column line can output a third output current I3 (=V1xG13+V2xG23+V3xG33).

[0130] Reference Figure 6C The cross switch array 210 can output output currents I1 to I3 by performing a multiplication operation on a matrix consisting of conductance values ​​G11 to G33 and a vector consisting of input voltages V1 to V3.

[0131] Figure 7 An analog-to-digital converter according to an embodiment of the present disclosure is shown. Figure 7 The analog-to-digital converter shown can correspond to Figure 2A The analog-to-digital converter 230.

[0132] Reference Figure 7 The analog-to-digital converter 230 may include a voltage provider 231, a comparator 232, and an encoder 233. The analog-to-digital converter 230 may be connected to the aforementioned cross switch array 210.

[0133] Voltage provider 231 can receive a reference voltage Vref. Voltage provider 231 can determine multiple comparison voltages Vc based on the reference voltage Vref and the resolution set in analog-to-digital converter 230. Here, resolution can indicate the number of bits constituting the digital signal DS output from analog-to-digital converter 230. Resolution can also be referred to as resolving power. Voltage provider 231 can provide multiple comparison voltages Vc to comparator 232.

[0134] Comparator 232 can compare each of the plurality of comparison voltages Vc with the analog signal voltage Vsig, and can provide the comparison result to encoder 233. This comparison result can be information indicating whether the analog signal voltage Vsig is greater than or less than each of the plurality of comparison voltages Vc.

[0135] The encoder 233 can output a digital signal DS corresponding to the analog signal voltage Vsig based on the comparison result of the comparator 232.

[0136] Figure 8 An embodiment according to this disclosure is shown. Figure 7 Analog-to-digital converter.

[0137] Although Figure 8 The analog-to-digital converter 230 is shown to have a resolution of 2 bits, but according to embodiments, the resolution of the analog-to-digital converter 230 may be set to more or less than two bits.

[0138] Reference Figure 8 Voltage provider 231 may include multiple resistors R connected in series between the voltage supply terminal of the supplied reference voltage Vref and the ground terminal. Voltage provider 231 may use the multiple resistors R to determine multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref. Voltage provider 231 may provide the multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref to comparator 232.

[0139] Comparator 232 can compare each of the multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref with the analog signal voltage Vsig.

[0140] For example, comparator 232 can compare the analog signal voltage Vsig with the comparison voltage 1 / 2Vref.

[0141] When the analog signal voltage Vsig is greater than the comparison voltage 1 / 2Vref, comparator 232 can compare the analog signal voltage Vsig with the comparison voltage 3 / 4Vref. When the analog signal voltage Vsig is greater than the comparison voltage 3 / 4Vref, comparator 232 can provide the corresponding comparison result to encoder 233. In this case, refer to... Figure 9A The encoder 233 can output a digital signal DS with a value of "11" based on the corresponding comparison result. In contrast, when the analog signal voltage Vsig is less than the comparison voltage 3 / 4Vref, the comparator 232 can provide the corresponding comparison result to the encoder 233. In this case, refer to... Figure 9A The encoder 233 can output a digital signal DS with "10" based on the corresponding comparison result.

[0142] On the other hand, when the analog signal voltage Vsig is less than the comparison voltage 1 / 2Vref, comparator 232 can compare the analog signal voltage Vsig with the comparison voltage 1 / 4Vref. When the analog signal voltage Vsig is greater than the comparison voltage 1 / 4Vref, comparator 232 can provide the corresponding comparison result to encoder 233. In this case, refer to... Figure 9A The encoder 233 can output a digital signal DS with "0" or "1" based on the corresponding comparison result. In contrast, when the analog signal voltage Vsig is less than 1 / 4 Vref, the comparator 232 can provide the corresponding comparison result to the encoder 233. In this case, refer to... Figure 9A The encoder 233 can output a digital signal DS with "00" based on the corresponding comparison result.

[0143] Figures 9A to 9E An example is shown. Figure 7 The input range of the analog-to-digital converter 230.

[0144] The input range of the analog-to-digital converter 230 can be the maximum dynamic range that prevents the analog-to-digital converter 230 from overloading. In embodiments, the term "input range" can be specified as "quantization range".

[0145] Figure 9A and Figure 9B The analog-to-digital converter 230 is shown to have a resolution of 2 bits. However, according to an embodiment, the resolution of the analog-to-digital converter can be set to another value.

[0146] Reference Figure 9A The input range of the analog-to-digital converter 230 can indicate a range from a minimum value of "0" to a maximum value of the reference voltage Vref.

[0147] Moreover, as referenced above Figure 7 and Figure 8 The analog-to-digital converter 230 can determine multiple comparison voltages based on the reference voltage Vref and the resolution. For example, when the resolution is 2 bits, the analog-to-digital converter 230 can output a digital signal indicating a digital value of any one of "00", "01", "10", and "11". Because the analog-to-digital converter 230 can output digital signals, each corresponding to one of the four digital values, multiple comparison voltages that identify the four digital values ​​can be determined within the input range. That is, the input range is divided into four segments by multiple comparison voltages, and each of the four segments corresponds to one of the four digital values.

[0148] For example, the analog-to-digital converter 230 can determine multiple comparison voltages, including a reference voltage Vref, a voltage corresponding to 3 / 4 of the reference voltage Vref (i.e., 3 / 4Vref), a voltage corresponding to 1 / 2 of the reference voltage Vref (i.e., 1 / 2Vref), a voltage corresponding to 1 / 4 of the reference voltage Vref (i.e., 1 / 4Vref), and a voltage of 0. In this case, when an analog signal voltage Vsig exists between the reference voltage Vref and the voltage corresponding to 3 / 4 of the reference voltage Vref (i.e., 3 / 4Vref), the analog-to-digital converter 230 can output a digital signal indicating "11". Furthermore, when an analog signal voltage Vsig exists between the voltage corresponding to 3 / 4 of the reference voltage Vref (i.e., 3 / 4Vref) and the voltage corresponding to 1 / 2 of the reference voltage Vref (i.e., 1 / 2Vref), the analog-to-digital converter 230 can output a digital signal indicating "10". Furthermore, when an analog signal voltage Vsig exists between a voltage corresponding to half the reference voltage Vref (i.e., 1 / 2Vref) and a voltage corresponding to one-quarter of the reference voltage Vref (i.e., 1 / 4Vref), the analog-to-digital converter 230 can output a digital signal indicating "01". Conversely, when an analog signal voltage Vsig exists between a voltage corresponding to one-quarter of the reference voltage Vref (i.e., 1 / 4Vref) and a voltage that is zero, the analog-to-digital converter 230 can output a digital signal indicating "00".

[0149] Reference Figure 9B Unlike Figure 9A In one embodiment, the input range of the analog-to-digital converter 230 can be a range from the minimum value corresponding to the negative value of the reference voltage Vref to the maximum value corresponding to the positive value of the reference voltage Vref.

[0150] Moreover, as referenced above Figure 7 and Figure 8The analog-to-digital converter 230 can determine multiple comparison voltages based on the reference voltage Vref and the resolution. For example, when the resolution is 2 bits, the analog-to-digital converter 230 can output a digital signal indicating any one of "00", "01", "10", and "11". Because the analog-to-digital converter 230 can output digital signals corresponding to four different cases, multiple comparison voltages that identify the four cases can be determined within the input range.

[0151] For example, the analog-to-digital converter 230 can determine multiple comparison voltages, including a reference voltage Vref, a voltage corresponding to half the magnitude of the reference voltage Vref (i.e., 1 / 2Vref), a voltage of 0, a negative voltage corresponding to half the magnitude of the reference voltage Vref (i.e., -1 / 2Vref), and a negative reference voltage -Vref. In this case, when there is an analog signal voltage Vsig located between the reference voltage Vref and the voltage corresponding to half the magnitude of the reference voltage Vref (i.e., 1 / 2Vref), the analog-to-digital converter 230 can output a digital signal indicating "11". Furthermore, when there is an analog signal voltage Vsig located between the voltage corresponding to half the magnitude of the reference voltage Vref (i.e., 1 / 2Vref) and a voltage of 0, the analog-to-digital converter 230 can output a digital signal indicating "10". Furthermore, when an analog signal voltage Vsig exists between a voltage of 0 and a negative voltage (i.e., -1 / 2Vref) corresponding to half the reference voltage Vref, the analog-to-digital converter 230 can output a digital signal indicating "01". Further, when an analog signal voltage Vsig exists between a negative voltage (i.e., -1 / 2Vref) corresponding to half the reference voltage Vref and the negative reference voltage -Vref, the analog-to-digital converter 230 can output a digital signal indicating "00".

[0152] For ease of description, the following text will be presented assuming the minimum value of the input range is 0. However, this is merely an example, and the configuration and operation of the electronic device described below can also be applied to the case where the minimum value of the input range is a negative value of the reference voltage Vref (i.e., -Vref).

[0153] In detail, Figure 9C The distribution of the analog signal voltage input to the analog-to-digital converter 230 according to an embodiment of the present disclosure is shown. Figure 9C In the diagram, the waveform indicated by the solid line can represent the distribution A of the analog signal voltage corresponding to the first input data, and the waveform indicated by the dashed line can represent the distribution B of the analog signal voltage corresponding to the second input data.

[0154] In this embodiment, the cross switch array 210 can receive an input voltage corresponding to the input data, and can output an analog signal voltage by performing a multiplication-accumulation operation on the input voltage and the conductance value stored in the cross switch array 210. Here, the distribution of the analog signal voltage may vary depending on the input data.

[0155] For example, the distribution A of the analog signal voltage corresponding to the first input data can have an amplitude V1 as its maximum value. In contrast, the distribution B of the analog signal voltage corresponding to the second input data can have an amplitude V2 as its maximum value. That is, the maximum value that the analog signal voltage can have may vary with the corresponding input data.

[0156] Figure 9D It is a graph showing the analog signal voltage falling within the input range of the analog-to-digital converter 230 according to an embodiment of the present disclosure.

[0157] exist Figure 9D In the graph, the vertical axis represents the amplitude of the analog signal voltage, and the horizontal axis represents time.

[0158] Reference Figure 9D The input range of the analog-to-digital converter 230 can be set from 0 to the reference voltage Vref.

[0159] In this embodiment, the analog signal voltage may fall within the input range of the analog-to-digital converter 230. For example, the maximum value of the analog signal voltage may be less than the reference voltage Vref. In this case, the probability of errors occurring during the quantization operation of the analog signal voltage may be low.

[0160] Figure 9E It is a graph showing the analog signal voltage beyond the input range of the analog-to-digital converter 230 according to an embodiment of the present disclosure.

[0161] exist Figure 9E In the graph, the vertical axis represents the amplitude of the analog signal voltage, and the horizontal axis represents time.

[0162] Reference Figure 9E The input range of the analog-to-digital converter 230 can be set from 0 to the reference voltage Vref.

[0163] In this embodiment, the analog signal voltage may exceed the input range of the analog-to-digital converter 230. For example, the maximum value of the analog signal voltage may be greater than the reference voltage Vref. In this case, the probability of errors occurring during the quantization operation of the analog signal voltage may be higher.

[0164] As described above, the analog-to-digital converter 230 can quantize voltage cycles within the input range using a preset resolution. Here, when the result of the multiplication-accumulation operation using the crossbar switch array 210 falls within the input range of the analog-to-digital converter 230, Figure 2A or Figure 2B The illustrated electronic devices 200a or 200b can reduce errors caused by quantization operations. For example, a neural network can use training data to perform learning. Here, when determining the input range of the analog-to-digital converter 230 based on a reference voltage according to the training data, errors caused by quantization operations may increase because the distribution of input data corresponding to various types of services applied to the trained neural network changes. Therefore, a scheme is needed for determining the input range of the analog-to-digital converter 230 based on the input data.

[0165] Figure 10 An electronic device 1000a according to an embodiment of the present disclosure is shown.

[0166] Reference Figure 10 The electronic device 1000a may include a cross switch array 1010, multiple current-to-voltage converters (IVCs) 1020 and multiple analog-to-digital converters (ADCs) 1030.

[0167] exist Figure 10 In this context, multiple current-to-voltage converters 1020 and multiple analog-to-digital converters 1030 can respectively correspond to Figure 2A and Figure 2B The system includes multiple current-to-voltage converters 220 and multiple analog-to-digital converters 230. Therefore, repeated descriptions of the multiple current-to-voltage converters 1020 and multiple analog-to-digital converters 1030 will be omitted.

[0168] The crossbar switch array 1010 may include multiple row lines, multiple first column lines, second column lines, and multiple memory cells.

[0169] Although Figure 10 Three row lines and three first column lines are shown, but the number of row lines and column lines can be applied in various ways according to the embodiment.

[0170] Each memory cell in the first part of the multiple memory cell CELL can be connected to a corresponding row line and a corresponding first column line. Each memory cell in the second part of the multiple memory cell CELL can be connected to a corresponding row line and a second column line.

[0171] Multiple rows can receive multiple input voltages corresponding to the input data. Figure 10 In this system, input voltages V1 to V3 can be supplied to multiple memory cells connected to each row line.

[0172] Each of the multiple first column lines can be connected to multiple memory cells connected to the multiple row lines. The first portion of the multiple memory cells connected to the multiple first column lines can store multiple conductance values ​​G11 to G33, each corresponding to multiple weight data. The first column lines can be referenced above. Figure 2A The described multiple column lines are implemented in the same way.

[0173] In this embodiment, the cross switch array 1010 can perform multiplication and accumulation operations on multiple input voltages V1 to V3 and multiple conductance values ​​G11 to G33, and output multiple output currents I1 to I3 respectively through multiple first column lines. Specifically, multiplication operations can be performed on the multiple input voltages V1 to V3 and the multiple conductance values ​​G11 to G33. Subsequently, accumulation operations can be performed on the results of the multiplication operations on each of the multiple first column lines. Therefore, as a result of performing multiplication and accumulation operations on the multiple input voltages V1 to V3 and the multiple conductance values ​​G11 to G33, multiple first column lines can respectively output multiple output currents I1 to I3.

[0174] The second column line can be connected to a second portion of multiple memory cells connected to multiple row lines. In an embodiment, each memory cell connected to the second column line can store a maximum conductance value Gmax. Here, the maximum conductance value Gmax can correspond to the largest conductance value among multiple conductance values ​​G11 to G33. For example, when the 22nd conductance value G22 has the largest size, the maximum conductance value Gmax can be determined to be the same as the 22nd conductance value G22.

[0175] On the other hand, although the above example describes the assumption that all memory cells connected to the second column line store the maximum conductance value Gmax, the embodiments are not limited thereto. In another embodiment, each memory cell connected to the second column line may store the maximum conductance value selected from the conductance values ​​stored in the corresponding memory cells connected to one of the multiple row lines, which are connected to each memory cell connected to the second column line. For example, the conductance value of the memory cell connected and disposed between the first row line and the second column line may correspond to the largest conductance value among the conductance values ​​G11, G12, and G13 stored in the memory cell connected and disposed between the first row line and the multiple first column lines. Similarly, the conductance value of the memory cell connected and disposed between the second row line and the second column line may correspond to the largest conductance value among the conductance values ​​G21, G22, and G23 stored in the memory cell connected and disposed between the second row line and the multiple first column lines. The conductance value of the memory cell CELL connected to and disposed between the third row line and the second column line can correspond to the conductance value G31, G32 and G33 stored in the memory cell CELL connected to and disposed between the third row line and multiple first column lines, which has the largest conductance value.

[0176] In the following text, for ease of description, it will be described under the assumption that all memory cells connected to the second column store the same maximum conductance value Gmax.

[0177] In this embodiment, the second column line can output the maximum output current Imax based on the result of a multiplication-accumulation operation performed on a plurality of input voltages V1 to V3 and the maximum conductance value Gmax. Specifically, a multiplication operation is performed on each of the plurality of input voltages V1 to V3 and the maximum conductance value Gmax stored in each of the memory cells CELLs connected to the second column line. Subsequently, an accumulation operation is performed on the results of each multiplication operation. The second column line can output the maximum output current Imax as the result of the multiplication-accumulation operation performed on the plurality of input voltages V1 to V3 and the maximum conductance value Gmax.

[0178] Each of the multiple current-to-voltage converters 1020 can be connected to a corresponding one or a second column of multiple first column lines.

[0179] In this embodiment, multiple current-to-voltage converters 1020 can be respectively connected to multiple first column lines and second column lines, converting multiple output currents I1 to I3 from the multiple first column lines into multiple analog signal voltages Vsig, and converting the maximum output current Imax from the second column line into a reference voltage Vref. For example, a current-to-voltage converter 1020 connected to any one of the multiple first column lines can convert a corresponding one of the multiple output currents I1 to I3 into a corresponding one of the multiple analog signal voltages Vsig. Further, a current-to-voltage converter 1020 connected to the second column line can convert the maximum output current Imax into the reference voltage Vref.

[0180] Furthermore, multiple current-to-voltage converters 1020 can be respectively connected to multiple analog-to-digital converters 1030, and can provide multiple analog signal voltages Vsig and a reference voltage Vref to the multiple analog-to-digital converters 1030. For example, an IVC 1020 among the multiple current-to-voltage converters 1020 connected to one of the multiple first column lines can provide a corresponding one of the multiple analog signal voltages Vsig to the analog-to-digital converter 1030 connected thereto. Moreover, an IVC 1020 among the multiple current-to-voltage converters 1020 connected to the second column line can provide the reference voltage Vref to the multiple analog-to-digital converters 1030.

[0181] Multiple analog-to-digital converters 1030 can be connected to multiple first column lines respectively.

[0182] In this embodiment, multiple analog-to-digital converters 1030 can convert multiple analog signal voltages Vsig into multiple digital signals DS, respectively.

[0183] For example, each of the plurality of analog-to-digital converters 1030 can receive an analog signal voltage Vsig corresponding to the output current of a corresponding output from one of the plurality of output currents I1 to I3 in the first column line. Furthermore, the plurality of analog-to-digital converters 1030 can receive a reference voltage Vref from IVC 1020 connected to the second column line.

[0184] Additionally, each of the plurality of analog-to-digital converters 1030 can convert the analog signal voltage Vsig into a digital signal DS based on an input range determined according to a reference voltage Vref. In an embodiment, as... Figure 9A As shown, each of the plurality of analog-to-digital converters 1030 can determine the reference voltage Vref as the maximum value of the input range and can determine the 0 value as the minimum value of the input range.

[0185] In another embodiment, such as Figure 9BAs shown, the multiple analog-to-digital converters 1030 can determine the negative value of the reference voltage Vref as the minimum value of the input range, and the positive value of the reference voltage Vref as the maximum value of the input range. Here, the maximum value of the input range can correspond to the maximum value of the analog signal voltage Vsig input to the multiple analog-to-digital converters 1030. Further, the minimum value of the input range can correspond to the minimum value of the analog signal voltage Vsig input to the multiple analog-to-digital converters 1030.

[0186] In this embodiment, multiple analog-to-digital converters 1030 can output individual digital signals DS based on comparison results between a reference voltage Vref and individual analog signal voltages Vsig. For example, the multiple analog-to-digital converters 1030 can determine multiple comparison voltages based on the reference voltage Vref and a preset resolution. The multiple analog-to-digital converters 1030 can output digital signals DS determined based on comparison results between the multiple comparison voltages and the analog signal voltages Vsig.

[0187] In this embodiment, when the magnitude of the analog signal voltage Vsig is greater than the magnitude of the reference voltage Vref, the multiple analog-to-digital converters 1030 can change the magnitude of the analog signal voltage Vsig to be the same as the magnitude of the reference voltage Vref. The multiple analog-to-digital converters 1030 can output a digital signal DS based on the comparison result between the reference voltage Vref and the magnitude-changed analog signal voltage Vsig.

[0188] In this embodiment, multiple analog-to-digital converters 1030 can apply a gain corresponding to a reference voltage Vref to an analog signal voltage Vsig, and then convert the gained analog signal voltage Vsig into a digital signal DS. For example, the multiple analog-to-digital converters 1030 can use automatic gain control (AGC) technology to optimize the operation of converting the analog signal voltage Vsig into the digital signal DS. Therefore, the multiple analog-to-digital converters 1030 can reduce errors that may occur in the operation of converting the analog signal voltage Vsig into the digital signal DS.

[0189] In an embodiment, multiple analog-to-digital converters 1030 can output a digital signal DS based on a comparison result between multiple comparison voltages and an analog signal voltage Vsig with a gain corresponding to a reference voltage Vref.

[0190] Furthermore, the multiple analog-to-digital converters 1030 can control their gains based on the reference voltage Vref, and then optimize the input range of the analog-to-digital converters 1030 based on the gains. In an embodiment, when the magnitude of the analog signal voltage Vsig is greater than the magnitude of the reference voltage Vref, the multiple analog-to-digital converters 1030 can control their gains such that the magnitude of the analog signal voltage Vsig to which the gain is applied is less than or equal to the magnitude of the reference voltage Vref.

[0191] On the other hand, although the application of automatic gain control technology to the analog-to-digital converter 1030 has been described in the above embodiments, the embodiments are not limited thereto. For example, the electronic device may further include a voltage buffer for buffering the analog signal voltage Vsig input to the analog-to-digital converter 1030. See below for further details. Figure 13 Describe this configuration in detail.

[0192] Therefore, according to embodiments of this disclosure, the reference voltage Vref can be determined based on the input data, and the input range of the analog-to-digital converter 1030 changes based on the reference voltage Vref, thereby reducing errors that may occur during quantization operations.

[0193] Figures 11A to 11D A second column line is shown according to an embodiment of the present disclosure.

[0194] Figure 11A The cross switch array 1010a shows Figure 10 Example of a cross switch array 1010.

[0195] Reference Figure 11A The crossbar switch array 1010a may include a plurality of memory cells 1101a to 1103a connected to the second column line. Here, the plurality of memory cells 1101a to 1103a may be resistive memory cells. For example, the plurality of memory cells 1101a to 1103a may include resistive elements. The resistive elements included in the memory cells 1101a to 1103a may be implemented as memristors. The resistive elements may have a resistance value that varies with the write voltage applied to them, and each of the memory cells 1101a to 1103a may use this resistance variation to store data.

[0196] Each of the multiple memory cells 1101a to 1103a can store the maximum conductance value Gmax.

[0197] For example, the cross switch array 1010a can store multiple conductance values ​​G11 to G33 and a maximum conductance value Gmax.

[0198] For example, multiple memory cells CELL connected to multiple first column lines of cross switch array 1010a can store multiple conductance values ​​G11 to G33 respectively. Each of the multiple memory cells 1101a to 1103a connected to the second column lines can store the maximum conductance value Gmax.

[0199] In an embodiment, the cross switch array 1010a can receive multiple conductance values ​​G11 to G33 and a maximum conductance value Gmax in the form of a matrix through multiple column lines including multiple first column lines and second column lines.

[0200] Figure 11B The cross switch array 1010b is shown Figure 10 Example of a cross switch array 1010.

[0201] Reference Figure 11B The crossbar switch array 1010b may include multiple memory cells 1101b to 1103b connected to the second column line.

[0202] For example, the multiple memory cells 1101b to 1103b may include multiple resistors, each with a fixed conductance value. The conductance values ​​of the multiple resistors may be equal to each other and may be greater than the conductance values ​​G11 to G33 stored in the cross switch array 1010b. For example, the conductance value of the multiple resistors may be the maximum conductance value Gmax. In an embodiment, the conductance values ​​of the multiple resistors may be set during the design phase of the cross switch array 1010b.

[0203] For example, the crossbar switch array 1010b can receive multiple conductance values ​​G11 to G33 in matrix form through multiple first column lines. Multiple memory cells CELL connected to the multiple first column lines can store the multiple conductance values ​​G11 to G33 respectively.

[0204] Each of the multiple memory cells 1101b to 1103b connected to the second column line can have a maximum conductivity value Gmax.

[0205] Figure 11C The multiple memory units 1101 to 1103 can respectively correspond to Figure 11A The multiple memory cells 1101a to 1103a. The description of the multiple memory cells 1101a to 1103a can also be applied to... Figure 11C Multiple memory units 1101 to 1103.

[0206] Reference Figure 11C Each of the multiple memory cells 1101 to 1103 can store the maximum conductance value Gmax.

[0207] Multiple memory cells 1101 to 1103 connected to the second column line can each receive multiple input voltages V1 to V3 from the multiple row lines connected to them. Each of the memory cells 1101 to 1103 can perform a multiplication operation on a corresponding one of the input voltages V1 to V3 and a maximum conductance value Gmax. For example, the first memory cell 1101 can receive a first input voltage V1. The first memory cell 1101 can perform a multiplication operation on the first input voltage V1 and the maximum conductance value Gmax. Further, the second memory cell 1102 can receive a second input voltage V2. The second memory cell 1102 can perform a multiplication operation on the second input voltage V2 and the maximum conductance value Gmax. Further, the third memory cell 1103 can receive a third input voltage V3. The third memory cell 1103 can perform a multiplication operation on the third input voltage V3 and the maximum conductance value Gmax.

[0208] Subsequently, the second column of lines can perform an accumulation operation on the results of multiplication operations performed on multiple memory cells 1101 to 1103. For example, the second column of lines can perform an accumulation operation on the results of multiplication operations on the first input voltage V1 and the maximum conductance value Gmax, the results of multiplication operations on the second input voltage V2 and the maximum conductance value Gmax, and the results of multiplication operations on the third input voltage V3 and the maximum conductance value Gmax. The second column of lines can output the maximum current Imax as the result of the accumulation operation.

[0209] The IVC 1020 connected to the second column line can convert the maximum output current Imax into a reference voltage Vref.

[0210] Figure 11D The cross switch array 1010c is shown Figure 10 Example of a cross switch array 1010.

[0211] Unlike Figure 11A and Figure 11B The cross switch arrays 1010a and 1010b shown are... Figure 11D The cross switch array 1010c may have different conductance values ​​Gmax1, Gmax2 and Gmax3 stored in multiple memory cells 1101c, 1102c and 1103c connected to the second column line, respectively.

[0212] In an embodiment, the cross switch array 1010c can receive multiple conductance values ​​G11 to G33, Gmax1, Gmax2 and Gmax3 in a matrix form through multiple column lines including multiple first column lines and second column lines.

[0213] The cross switch array 1010c can store multiple conductance values ​​G11 to G33, Gmax1, Gmax2 and Gmax3.

[0214] Multiple memory cells connected to multiple first column lines can store multiple conductance values ​​G11 to G33 respectively.

[0215] Multiple memory cells 1101c to 1103c connected to the second column line can store conductance values ​​Gmax1, Gmax2, and Gmax3, respectively. For example, memory cell 1101c connected to and disposed between the first row line and the second column line can store conductance value Gmax1, which corresponds to the largest conductance value among conductance values ​​G11, G12, and G13 stored in memory cells CELL connected to and disposed between the first row line and multiple first column lines. Memory cell 1102c connected to and disposed between the second row line and the second column line can store conductance value Gmax2, which corresponds to the largest conductance value among conductance values ​​G21, G22, and G23 stored in memory cells CELL connected to and disposed between the second row line and multiple first column lines. The memory cell 1103c connected to and disposed between the third row line and the second column line can store a conductance value Gmax3, which corresponds to the largest conductance value among the conductance values ​​G31, G32 and G33 stored in the memory cell CELL connected to and disposed between the third row line and multiple first column lines.

[0216] Figures 12A to 12D The operation of an analog-to-digital converter 1030 according to an embodiment of the present disclosure is illustrated. The analog-to-digital converter 1030 can correspond to... Figure 10 The 1020 analog-to-digital converter.

[0217] The analog-to-digital converter 1030 may include a voltage provider 1031, a comparator 1032, and an encoder 1033.

[0218] Figures 12A to 12D The voltage provider 1031, comparator 1032, and encoder 1033 shown can be used with Figure 7 and Figure 8 The voltage provider 231, comparator 232 and encoder 233 shown are implemented in the same manner.

[0219] Furthermore, Figures 12A to 12D The analog-to-digital converter 1030 shown can have a resolution of 2 bits.

[0220] Reference Figure 12AVoltage provider 1031 can receive a 10mV reference voltage Vref from a current-to-voltage converter coupled to the second column line. In an embodiment, voltage provider 1031 can determine multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref based on the reference voltage Vref and 2-bit resolution. Voltage provider 1031 can provide the multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref to comparator 1032.

[0221] Comparator 1032 can receive an analog signal voltage Vsig of 10mV.

[0222] Comparator 1032 can compare multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref with the analog signal voltage Vsig. Comparator 1032 can provide the comparison result to encoder 1033.

[0223] The encoder 1033 can output a digital signal DS corresponding to the 10mV analog signal voltage Vsig based on the comparison result. Since the comparison result determines that the 10mV analog signal voltage Vsig is greater than the comparison voltage 3 / 4Vref, the analog signal voltage Vsig can be a voltage located between the comparison voltage Vref and the comparison voltage 3 / 4Vref, that is, it falls within the first voltage segment closest to the maximum value Vref of the input range of the analog-to-digital converter 1030. Therefore, referring to... Figure 9A The encoder 1033 can output the maximum value "11" among the values ​​represented by 2 bits as a digital signal DS.

[0224] Reference Figure 12B Voltage provider 1031 can receive a 10mV reference voltage Vref from a current-to-voltage converter coupled to the second column line. In an embodiment, voltage provider 1031 can determine multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref based on the reference voltage Vref and 2-bit resolution. Voltage provider 1031 can provide the multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref to comparator 1032.

[0225] Comparator 1032 can receive an analog signal voltage Vsig of 6mV.

[0226] Comparator 1032 can compare multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref with the analog signal voltage Vsig. Comparator 1032 can provide the comparison result to encoder 1033.

[0227] The encoder 1033 can output a digital signal DS corresponding to the 6mV analog signal voltage Vsig based on the comparison result. Because, according to the comparison result, the 6mV analog signal voltage Vsig is less than the comparison voltage 3 / 4Vref and greater than the comparison voltage 1 / 2Vref, the analog signal voltage Vsig can be a voltage located between the comparison voltages 3 / 4Vref and 1 / 2Vref, that is, it falls within the second voltage segment of the input range of the analog-to-digital converter 1030. Therefore, referring to... Figure 9A The encoder 1033 can output "10" as a digital signal DS.

[0228] Reference Figure 12C Voltage provider 1031 can receive a 5mV reference voltage Vref from a current-to-voltage converter coupled to the second column line. In an embodiment, voltage provider 1031 can determine multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref based on the reference voltage Vref and 2-bit resolution. Voltage provider 1031 can provide the multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref to comparator 1032.

[0229] Comparator 1032 can receive an analog signal voltage Vsig of 5mV.

[0230] Comparator 1032 can compare multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref with the analog signal voltage Vsig. Comparator 1032 can provide the comparison result to encoder 1033.

[0231] The encoder 1033 can output a digital signal DS corresponding to the 5mV analog signal voltage Vsig based on the comparison result. Since the 5mV analog signal voltage Vsig is greater than the comparison voltage 3 / 4Vref according to the comparison result, the analog signal voltage Vsig can be a voltage located between the comparison voltage Vref and the comparison voltage 3 / 4Vref, that is, within the first voltage segment closest to the maximum value of the input range of the analog-to-digital converter 1030. Therefore, referring to... Figure 9A The encoder 1033 can output the maximum value "11" among the values ​​represented by 2 bits as a digital signal DS.

[0232] Figure 12A and Figure 12CThe analog signal voltages Vsig are shown to have different voltage levels, but their digital signals are equal. Therefore, according to embodiments of this disclosure, since the maximum output current Imax is calculated based on the input voltage corresponding to the input data, and the voltage corresponding to the maximum output current Imax is set as the reference voltage Vref, the input range of the analog-to-digital converter is determined based on the input data.

[0233] Reference Figure 12D Voltage provider 1031 can receive a 10mV reference voltage Vref from a current-to-voltage converter coupled to the second column line. In an embodiment, voltage provider 1031 can determine multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref based on the reference voltage Vref and 2-bit resolution. Voltage provider 1031 can provide the multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref to comparator 1032.

[0234] Comparator 1032 can receive an analog signal voltage Vsig of 11mV. Because the magnitude of the analog signal voltage Vsig is greater than the magnitude of the reference voltage Vref, comparator 1032 can change the magnitude of the analog signal voltage Vsig to be the same as the magnitude of the reference voltage Vref.

[0235] Comparator 1032 can compare multiple comparison voltages Vref, 3 / 4Vref, 1 / 2Vref, and 1 / 4Vref with the analog signal voltage Vsig after its magnitude has been changed. Comparator 1032 can provide the comparison result to encoder 1033.

[0236] The encoder 1033 can output a digital signal DS corresponding to the 11mV analog signal voltage Vsig based on the comparison result. Since, according to the comparison result, the 11mV analog signal voltage Vsig is greater than the comparison voltage 3 / 4Vref, the analog signal voltage Vsig can be a voltage located between the comparison voltage Vref and the comparison voltage 3 / 4Vref, that is, it falls within the first voltage segment closest to the maximum value Vref of the input range of the analog-to-digital converter 1030. Therefore, referring to... Figure 9A The encoder 1033 can output "11" as a digital signal DS.

[0237] Figure 12D The analog signal voltage Vsig is shown to have a voltage level greater than the reference voltage Vref, but the analog-to-digital converter 1030 can adjust the magnitude of the analog signal voltage Vsig so that the analog signal voltage Vsig falls within the input range determined according to the reference voltage Vref.

[0238] Figure 13An electronic device 1000b according to another embodiment of the present disclosure is shown.

[0239] Reference Figure 13 ,and Figure 10 Compared to the illustrated electronic device 1000a, electronic device 1000b further includes a plurality of voltage buffers 1040. Figure 13 In this configuration, the cross switch array 1010, multiple current-to-voltage converters (IVCs) 1020, and multiple analog-to-digital converters (ADCs) 1030 are... Figure 10 The cross switch array 1010, multiple current-to-voltage converters (IVCs) 1020 and multiple analog-to-digital converters (ADCs) 1030 are the same, so their description is omitted.

[0240] Each of the plurality of voltage buffers 1040 can be connected to and positioned between a corresponding one of the plurality of current-to-voltage converters 1020 and a corresponding one of the plurality of ADCs 1030. Each of the plurality of voltage buffers 1040 can be connected to a corresponding one of the plurality of first column lines.

[0241] In an embodiment, each of the plurality of voltage buffers 1040 may receive an analog signal voltage Vsig from a first column line connected thereto. For example, the plurality of voltage buffers 1040 may each receive a plurality of analog signal voltages Vsig from a respective IVC 1020 connected thereto.

[0242] In this embodiment, each of the plurality of voltage buffers 1040 can buffer the analog signal voltage Vsig and output the buffered analog signal voltage Vsig'. During the input of the analog signal voltage Vsig to the ADC 1030, noise may be included in the analog signal voltage Vsig. Each of the plurality of voltage buffers 1040 can eliminate the noise included in the analog signal voltage Vsig by buffering it.

[0243] In this embodiment, the plurality of voltage buffers 1040 can determine the maximum value of the output voltage based on a reference voltage Vref. Here, the output voltage can be a buffered analog signal voltage Vsig'. For example, the plurality of voltage buffers 1040 can receive the reference voltage Vref from the IVC 1020 connected to the second column line.

[0244] Each of the plurality of voltage buffers 1040 can compare the magnitude of the reference voltage Vref with the magnitude of the corresponding analog signal voltage Vsig. When the magnitude of the analog signal voltage Vsig is not greater than the magnitude of the reference voltage Vref, each of the plurality of voltage buffers 1040 can output a buffered analog signal voltage Vsig' based on the voltage gain. On the other hand, when the magnitude of the analog signal voltage Vsig is greater than the magnitude of the reference voltage Vref, each of the plurality of voltage buffers 1040 can output a buffered analog signal voltage Vsig' with the same magnitude as the reference voltage Vref to the corresponding one of the plurality of ADCs 1030. That is, when the magnitude of the analog signal voltage Vsig is greater than the magnitude of the reference voltage Vref, the magnitude of the buffered analog signal voltage Vsig' can be equal to the magnitude of the reference voltage Vref.

[0245] Multiple ADCs 1030 can each receive buffered analog signal voltages Vsig' from multiple voltage buffers 1040. Furthermore, the multiple ADCs 1030 can receive a reference voltage Vref from the IVC 1020 connected to the second column line. The multiple ADCs 1030 can output individual digital signals DS based on a comparison between the reference voltage Vref and the buffered analog signal voltages Vsig.

[0246] Therefore, according to embodiments of this disclosure, the input range of each ADC 1030 can be additionally controlled by a corresponding voltage buffer 1040, thus reducing errors in the quantization operation of the ADC 1030 by using the corresponding voltage buffer 1040 to determine the input range of the ADC 1030.

[0247] Figure 14 and Figure 15 This is a diagram illustrating a voltage buffer 1040a and its operation according to an embodiment of the present disclosure.

[0248] Figure 14 The voltage buffer 1040a shown can represent Figure 13 An example of a voltage buffer 1040 is shown.

[0249] Reference Figure 14 The voltage buffer 1040a can be implemented using a source follower. The voltage buffer 1040a may include a MOS transistor and a resistor Rs connected in series between the power supply and ground terminals.

[0250] For example, the voltage buffer 1040a can be configured such that a common terminal connected to the power supply is connected to the common drain of the MOS transistor. Here, the reference voltage Vref can be set to the power supply voltage provided by the power supply.

[0251] Reference Figure 15 When the analog signal voltage Vsig input to the gate of the MOS transistor is less than the threshold voltage Vth, the MOS transistor is turned off, and therefore the output voltage Vout (or Vsig') can be 0. When the analog signal voltage Vsig input to the voltage buffer 1040a is equal to or greater than the threshold voltage Vth, the output voltage Vout (or Vsig') corresponding to the analog signal voltage Vsig can be output while current flows through the resistor Rs. When the analog signal voltage Vsig is equal to or greater than the reference voltage Vref, the output voltage Vout (or Vsig') can be equal to the reference voltage Vref.

[0252] On the other hand, the voltage gain of the voltage buffer 1040a can have a value close to "1", but according to the embodiment, it can be set to one of a variety of values.

[0253] For example, when the magnitude of the analog signal voltage Vsig is not greater than the magnitude of the threshold voltage Vth, the MOS transistor is turned off, so the voltage buffer 1040a can not output any voltage. That is, the output voltage Vout (or Vsig') is 0V.

[0254] On the other hand, when the magnitude of the analog signal voltage Vsig is equal to or greater than the magnitude of the threshold voltage Vth and not greater than the magnitude of the reference voltage Vref, the MOS transistor is turned on, so the output voltage Vout (or Vsig') can have a voltage level corresponding to the magnitude of the analog signal voltage Vsig.

[0255] When the magnitude of the analog signal voltage Vsig is greater than the magnitude of the reference voltage Vref, the output voltage Vout (or Vsig') can have the same magnitude as the reference voltage Vref.

[0256] In other words, the maximum value of the output voltage Vout (or Vsig') from the voltage buffer 1040a can be set to the reference voltage Vref. Therefore, even if an analog signal voltage Vsig higher than the reference voltage Vref is applied to the voltage buffer 1040a, the magnitude of the output voltage Vout (or Vsig') can be no greater than the magnitude of the reference voltage Vref.

[0257] For example, when voltage buffer 1040a receives a reference voltage Vref of 10mV, the maximum value output from voltage buffer 1040a can be 10mV. When voltage buffer 1040a receives an analog signal voltage Vsig of 10mV, because the magnitude of analog signal voltage Vsig is greater than the magnitude of threshold voltage Vth and not greater than the magnitude of reference voltage Vref, voltage buffer 1040a can output an output voltage Vout (or Vsig') where the voltage gain of voltage buffer 1040a is applied to analog signal voltage Vsig.

[0258] In another example, when voltage buffer 1040a receives a reference voltage Vref of 10mV, the maximum value output from voltage buffer 1040a can be 10mV. When voltage buffer 1040a receives an analog signal voltage Vsig of 5mV, because the magnitude of analog signal voltage Vsig is greater than the magnitude of threshold voltage Vth and not greater than the magnitude of reference voltage Vref, voltage buffer 1040a can output an output voltage Vout (or Vsig') where voltage gain is applied to analog signal voltage Vsig.

[0259] In another example, when voltage buffer 1040a receives a reference voltage Vref of 10mV, the maximum value output from voltage buffer 1040a can be 10mV. When voltage buffer 1040a receives an analog signal voltage Vsig of 11mV, because the magnitude of the analog signal voltage Vsig is greater than the magnitude of the reference voltage Vref, voltage buffer 1040a can output an output voltage Vout (or Vsig') with a maximum value of 10mV.

[0260] Figure 16 An electronic device 1000c according to yet another embodiment of the present disclosure is shown.

[0261] Reference Figure 16 ,and Figure 13 Compared to the illustrated electronic device 1000b, the electronic device 1000c further includes a digital signal processor 1050. Figure 16 In this configuration, the cross switch array 1010, multiple current-to-voltage converters (IVCs) 1020, multiple analog-to-digital converters (ADCs) 1030, and multiple voltage buffers 1040 are connected to... Figure 13 The cross switch array 1010, multiple current-to-voltage converters (IVCs) 1020, multiple analog-to-digital converters (ADCs) 1030 and multiple voltage buffers 1040 are the same, so their description is omitted.

[0262] The digital signal processor 1050 can be connected to multiple ADCs 1030. On the other hand, although Figure 16A digital signal processor 1050 is shown, but the number of digital signal processors included in the electronic device 1000c may vary depending on the embodiment.

[0263] The digital signal processor 1050 can receive multiple digital signals DS output from multiple ADCs 1030 based on multiple input data. Here, the multiple digital signals DS can be obtained based on multiple input ranges. The multiple input ranges are determined based on multiple reference voltages. In an embodiment, the multiple reference voltages can be generated based on multiple input data input at different time points and the maximum conductance value.

[0264] Furthermore, the digital signal processor 1050 can receive a digital reference signal Dref corresponding to the reference voltage Vref. For example, an ADC 1030' can be connected and configured between the second column line and the digital signal processor 1050. The ADC 1030' can receive the reference voltage Vref and convert the reference voltage Vref into a digital reference signal Dref. The ADC 1030' can then provide the digital reference signal Dref to the digital signal processor 1050.

[0265] In this embodiment, the digital signal processor 1050 can output a digital operational signal DS' based on a digital signal DS and a digital reference signal Dref. Here, the digital operational signal DS' can be a digital signal having a distribution range corresponding to a previously normal distribution range. Here, the previously normal distribution range can be the normal distribution range of multiple analog signal voltages Vsig corresponding to multiple digital signals DS. That is, the previously normal distribution range can represent the range formed by the continuous values ​​of the analog signal voltage Vsig before the analog signal voltage is converted into the Vsig digital signal DS by the ADC 1030.

[0266] In this embodiment, the digital signal processor 1050 can perform a multiplication operation on the digital signal DS and the digital reference voltage Dref, and output a digital operation signal DS' as the result of the multiplication operation.

[0267] In an embodiment, the digital signal processor 1050 can output multiple digital signals DS' at different time points based on multiple reference voltages and digital operation signals DS output from multiple ADCs 1030s that apply multiple reference voltages.

[0268] For example, the digital signal processor 1050 can perform a multiplication operation on any one of a plurality of digital signals DS and a digital reference signal Dref corresponding to a reference voltage Vref used to generate a digital signal DS. The digital signal processor 1050 can output a digital operation signal DS' as the result of the multiplication operation.

[0269] In an embodiment, the electronic device 1000c may use a plurality of digital operation signals DS' to perform digital signal processing operations. Here, the digital signal processing operation may be any one of the following operations performed on the digital signal: noise cancellation, filtering, error removal, error detection, and calculation.

[0270] Figure 17A and Figure 17B A digital signal processor according to an embodiment of the present disclosure is shown. Figure 17A The digital signal processor shown can correspond to Figure 16 The digital signal processor 1050 shown can therefore be referenced. Figure 16 To describe the digital signal processor 1050.

[0271] Reference Figure 17A The digital signal processor 1050 can perform a multiplication operation on the digital signal DS and the digital reference signal Dref output from the ADC 1030, and can output a digital operation signal DS' as the result of the multiplication operation.

[0272] In this embodiment, the output value of the ADC 1030 can be represented by the following equation (2):

[0273]

[0274] In equation (2), ADCOut can represent the output value of ADC 1030, Vsig can represent the analog signal voltage input to ADC1030, Vref can represent the reference voltage, and bit can represent the resolution.

[0275] Referring to equation (2), the output value of ADC 1030 is inversely proportional to the reference voltage Vref. Here, the reference voltage Vref can vary with the input data input to the crossbar switch array 1010. That is, whenever the input data changes, the reference voltage Vref applied to ADC 1030 can also change. Therefore, in order to perform operations between digital signals DS with different applied reference voltages, the digital signal DS needs to be corrected.

[0276] For example, refer to Figure 17BWhen the reference voltage Vref is 10mV and the analog signal voltage Vsig is 10mV, the ADC 1030, as shown in (a), can output "11" as the digital signal DS. For example, when the reference voltage Vref is 5mV and the analog signal voltage Vsig is 5mV, the ADC 1030, as shown in (b), can output "11" as the digital signal DS. As described above, since the reference voltage Vref varies with the input data, the output value of the ADC 1030 can be equal even if the analog signal voltages Vsig are different.

[0277] In this case, in order to perform digital signal processing operations using the digital signal DS output based on different reference voltages Vref, the digital signal DS needs to be corrected to have the range of the previous normal distribution.

[0278] Therefore, the digital signal processor 1050 can output a digital operation signal DS' by multiplying the digital signal DS by the digital reference voltage Dref.

[0279] For example, the digital operation signal DS' can be represented by the following equation (3):

[0280] DS'=DS×Drref (3)

[0281] In detail, the digital signal DS can be the signal output from the corresponding ADC 1030 with a gain corresponding to the reference voltage Vref. Therefore, the digital signal DS can be corrected by multiplying the digital signal DS by the reciprocal of the gain applied to the ADC 1030. This operation is expressed in equation (3), where the reciprocal of the gain is multiplied by the digital signal DS by multiplying the digital reference signal Dref by the digital signal DS. Therefore, the digital operational signal DS' can have the signal value before the gain is applied to the analog-to-digital converter 1030.

[0282] Figure 18A and Figure 18B An embodiment according to this disclosure is shown. Figure 16 The operation of the digital signal processor 1050.

[0283] Reference Figure 18AMultiple input voltages V1' to V3' corresponding to the first input data can be input through multiple row lines. A multiplication-accumulation operation can be performed on the maximum conductance value Gmax stored in each of the multiple input voltages V1' to V3' and memory cells 1101, 1102, and 1103 connected to the second column line, and the maximum output current Imax' as the result of the multiplication-accumulation operation can be output. The maximum output current Imax' can be converted into a reference voltage Vref' by IVC 1020 connected to the second column line. The reference voltage Vref' can be converted into a digital reference signal Dref_1 by ADC 1030'.

[0284] The digital signal processor 1050 can receive a digital reference signal Dref_1. Further, the digital signal processor 1050 can receive a digital signal DS_1 from one of a plurality of first column lines. Here, the digital signal DS_1 can correspond to an analog signal voltage generated by performing a multiplication-accumulation operation on a plurality of input voltages V1' to V3' and conductance values ​​stored in a memory cell connected to one of the plurality of first column lines. The digital signal processor 1050 can perform a multiplication operation on the digital signal DS_1 and the digital reference signal Dref_1, and can output a digital operation signal DS'_1.

[0285] Reference Figure 18B Multiple input voltages V1” to V3” corresponding to the second input data can be input through multiple row lines. Here, the second input data can be input to multiple row lines after the first input data has been input. A multiplication-accumulation operation can be performed on the maximum conductance value Gmax stored in each of the multiple input voltages V1” to V3” and memory cells 1101, 1102 and 1103 connected to the second column line, and the maximum output current Imax” as the result of the multiplication-accumulation operation can be output. The maximum output current Imax” can be converted into a reference voltage Vref by IVC 1020 connected to the second column line. The reference voltage Vref” can be converted into a digital reference signal Dref_2 by ADC 1030'.

[0286] The digital signal processor 1050 can receive a digital reference signal Dref_2. Further, the digital signal processor 1050 can receive a digital signal DS_2 from one of the plurality of first column lines. Here, the digital signal DS_2 can correspond to an analog signal voltage output by performing a multiplication-accumulation operation on multiple input voltages V1” to V3” and conductance values ​​stored in a memory cell included in one of the plurality of first column lines. The digital signal processor 1050 can perform a multiplication operation on the digital signal DS_2 and the digital reference signal Dref_2, and can output a digital operation signal DS'_2.

[0287] In an embodiment, Figure 16 The electronic device 1000c can perform digital signal processing operations using a digital operation signal DS'_1 output for the first input data and a digital operation signal DS'_2 output for the second input data.

[0288] Figure 19 Neural network operations using multiple electronic devices 1000-1 to 1000-n are illustrated according to embodiments of the present disclosure.

[0289] Reference Figure 19 Each of the plurality of electronic devices 1000-1 to 1000-n can correspond to Figure 10 Electronic device 1000a, Figure 13 Electronic device 1000b and Figure 16 Any one of the electronic devices 1000c.

[0290] The multiple electronic devices 1000-1 to 1000-n can be devices for implementing the various layers included in the neural network. For example, when the neural network includes n layers, the multiple electronic devices 1000-1 to 1000-n can implement the n layers respectively.

[0291] Each of the multiple electronic devices 1000-1 to 1000-n can use a crossbar switch array to perform a multiplication-accumulation operation on the input data. Each of the multiple electronic devices 1000-1 to 1000-n can use the result of the multiplication-accumulation operation output by multiple ADCs as a digital signal. The digital signal can then be input to subsequent electronic devices as input data.

[0292] In an embodiment, each of the plurality of electronic devices 1000-1 to 1000-n may further include a plurality of digital-to-analog converters (DACs). Each of the plurality of electronic devices 1000-1 to 1000-n may use the plurality of DACs to convert digital signals input from previous electronic devices into a plurality of input voltages. Hereinafter, as described above, the plurality of electronic devices 1000-1 to 1000-n may ultimately output output data corresponding to the input data by repeatedly performing multiplication-accumulation operations.

[0293] In this embodiment, digital signal processing operations can be performed on the digital signal before it is provided to a subsequent electronic device.

[0294] For example, the first electronic device 1000-1 can output digital signals via multiple ADCs. Furthermore, the first electronic device 1000-1 can perform digital signal processing operations on the digital signals. In embodiments, the above references can be used. Figure 16 , Figure 17A , Figure 17B , Figure 18A and Figure 18B The described digital signal processor 1050 performs digital signal processing operations. Hereinafter, the digital signal that has undergone digital signal processing can be provided to the second electronic device 1000-2. The second electronic device 1000-2 can use a DAC to convert the digital signal into multiple input voltages. Thereafter, the second electronic device 1000-2 can perform multiplication and accumulation operations on the multiple input voltages.

[0295] Therefore, neural network operations can be performed through the operation of multiple electronic devices 1000-1 to 1000-n.

[0296] Figure 20 This is a flowchart illustrating a method of operating an electronic device according to an embodiment of the present disclosure.

[0297] Figure 20 The method shown can be derived from Figure 10 Electronic device 1000a, Figure 13 Electronic device 1000b and Figure 16 The operation is performed by any one of the electronic devices 1000c. The operation is described below for ease of description. Figure 16 The method of electronic device 1000c, but the method can also be applied to Figure 10 Electronic device 1000a and Figure 13 Electronic device 1000b.

[0298] Reference Figure 16 and Figure 20 In step S2001, the electronic device 1000c can receive multiple input voltages V1 to V3 through multiple line lines respectively.

[0299] In step S2003, the electronic device 1000c can generate a maximum output current Imax based on the maximum conductance value Gmax and multiple input voltages V1 to V3, and output the maximum output current Imax through the second column line. The maximum conductance value Gmax can be the largest among the conductance values ​​G11 to G33 stored in multiple memory cells connected to the multiple first column lines. For example, the electronic device 1000c can generate the maximum output current Imax by performing a multiplication-accumulation operation on the maximum conductance value Gmax and the multiple input voltages V1 to V3.

[0300] In step S2005, the electronic device 1000c can convert the maximum output current Imax into a reference voltage Vref. For example, the electronic device 1000c can use a current-to-voltage converter (IVC) 1020 connected to the second column line to convert the maximum output current Imax into a reference voltage Vref.

[0301] In step S2007, the electronic device 1000c can determine the maximum value of the input range of the plurality of ADCs 1030 based on the reference voltage Vref. In one embodiment, the electronic device 1000c can determine the reference voltage Vref as the maximum value of the input range of the plurality of ADCs 1030. In another embodiment, the electronic device 1000c can determine the maximum value of the input range by applying a gain corresponding to the reference voltage Vref to the plurality of ADCs 1030.

[0302] Figure 21 This is a flowchart illustrating a method of operating an electronic device according to another embodiment of the present disclosure.

[0303] Figure 21 The method shown can be derived from Figure 10 Electronic device 1000a, Figure 13 Electronic device 1000b and Figure 16 The operation is performed by any one of the electronic devices 1000c. The operation is described below for ease of description. Figure 16 The method of electronic device 1000c, but the method can also be applied to Figure 10 Electronic device 1000a and Figure 13 Electronic device 1000b.

[0304] Reference Figure 16 and Figure 21 In step S2101, the electronic device 1000c can receive multiple input voltages V1 to V3 through multiple line lines respectively.

[0305] In step S2103, the electronic device 1000c can generate a maximum output current Imax based on the maximum conductance value Gmax and multiple input voltages V1 to V3, and output the maximum output current Imax through the second column line. The maximum conductance value Gmax can be the largest among multiple conductance values ​​G11 to G33 stored in multiple memory cells connected to multiple first column lines. For example, the electronic device 1000c can generate the maximum output current Imax by performing a multiplication-accumulation operation on the maximum conductance value Gmax and the multiple input voltages V1 to V3.

[0306] In step S2105, the electronic device 1000c can convert the maximum output current Imax into a reference voltage Vref. For example, the electronic device 1000c can use a current-to-voltage converter (IVC) 1020 connected to the second column line to convert the maximum output current Imax into a reference voltage Vref.

[0307] In step S2107, the electronic device 1000c can determine the reference voltage Vref as the maximum value of the input range of the plurality of ADCs 1030.

[0308] In step S2109, the electronic device 1000c can generate multiple output currents I1 to I3 based on multiple input voltages V1 to V3 and multiple conductance values ​​G11 to G33 stored in multiple memory cells, and output the multiple output currents I1 to I3 respectively through multiple first column lines. For example, the electronic device 1000c can generate multiple output currents I1 to I3 by performing a multiplication-accumulation operation on the multiple input voltages V1 to V3 and the multiple conductance values ​​G11 to G33.

[0309] In step S2111, the electronic device 1000c can convert multiple output currents I1 to I3 into multiple analog signal voltages Vsig. For example, the electronic device 1000c can use current-to-voltage converters 1020 respectively connected to multiple first column lines to convert the multiple output currents I1 to I3 into multiple analog signal voltages Vsig. In an embodiment, the electronic device 1000c can use multiple voltage buffers 1040 to buffer the analog signal voltages Vsig, and can provide the buffered analog signal voltages Vsig' to multiple ADCs 1030.

[0310] In step S2113, the electronic device 1000c can use multiple ADCs 1030 to convert multiple analog signal voltages Vsig or buffered analog signal voltages Vsig' into multiple digital signals DS, and the maximum value of the input range of the multiple ADCs 1030 has been determined as the reference voltage Vref.

[0311] Figure 22 This is a flowchart illustrating a method for outputting multiple output currents through multiple first column lines according to an embodiment of the present disclosure.

[0312] Figure 22 The method shown can be derived from Figure 10 Electronic device 1000a, Figure 13 Electronic device 1000b and Figure 16 The operation is performed by any one of the electronic devices 1000c. The operation is described below for ease of description. Figure 16 The method of electronic device 1000c, but the method can also be applied to Figure 10 Electronic device 1000a and Figure 13 Electronic device 1000b.

[0313] and, Figure 22 The method shown can be used to implement Figure 21 The method of step S2109.

[0314] Reference Figure 16 and Figure 22 In step S2201, the electronic device 1000c can store multiple conductance values ​​G11 to G33 in multiple memory cells connected to multiple first column lines. Here, the multiple conductance values ​​G11 to G33 can correspond to multiple weight data.

[0315] In step S2203, the electronic device 1000c can perform a multiplication-accumulation operation on multiple input voltages V1 to V3 and multiple conductance values ​​G11 to G33. For example, the electronic device 1000c can perform a multiplication operation on multiple input voltages V1 to V3 and multiple conductance values ​​G11 to G33. Afterward, the electronic device 1000c can perform an accumulation operation on the result of the multiplication operation.

[0316] In step S2205, the electronic device 1000c can generate multiple output currents I1 to I3 based on the result of the multiplication and accumulation operation.

[0317] Figure 23 This is a flowchart illustrating a method for outputting maximum output current via a second column of lines according to an embodiment of the present disclosure.

[0318] Figure 23 The method shown can be derived from Figure 10 Electronic device 1000a, Figure 13 Electronic device 1000b and Figure 16 The operation is performed by any one of the electronic devices 1000c. The operation is described below for ease of description. Figure 16 The method of electronic device 1000c, but the method can also be applied to Figure 10 Electronic device 1000a and Figure 13 Electronic device 1000b.

[0319] and, Figure 23 The method shown can be used to implement Figure 21 The method of step S2103.

[0320] Reference Figure 16 and Figure 23 In step S2301, the electronic device 1000c can store the maximum conductance value Gmax in each of the plurality of memory cells connected to the second column line.

[0321] In step S2303, the electronic device 1000c can perform a multiplication-accumulation operation on multiple input voltages V1 to V3 and the maximum conductance value Gmax. For example, the electronic device 1000c can perform a multiplication operation on multiple input voltages V1 to V3 and the maximum conductance value Gmax. Afterward, the electronic device 1000c can perform an accumulation operation on the result of the multiplication operation.

[0322] In step S2305, the electronic device 1000c can generate the maximum output current Imax based on the result of the multiplication and accumulation operation.

[0323] Figure 24 This is a flowchart illustrating a method for outputting a digital signal via an analog-to-digital converter according to an embodiment of the present disclosure.

[0324] Figure 24 The method shown can be derived from Figure 10 Electronic device 1000a, Figure 13 Electronic device 1000b and Figure 16 The operation is performed by any one of the electronic devices 1000c. The operation is described below for ease of description. Figure 16 The method of electronic device 1000c, but the method can also be applied to Figure 10 Electronic device 1000a and Figure 13 Electronic device 1000b.

[0325] and, Figure 24 The method shown can be used to implement Figure 21 The method of step S2113.

[0326] Reference Figure 16 and Figure 24 In step S2401, the electronic device 1000c can determine the maximum value of the input range of the ADC 1030 based on the reference voltage Vref. In an embodiment, the minimum value of the input range of the ADC 1030 can be 0 or a negative value of the reference voltage Vref, i.e., -Vref.

[0327] In step S2403, the electronic device 1000c can determine multiple comparison voltages based on the reference voltage Vref and the resolution of the ADC 1030. For example, when the resolution is 2 bits, the ADC 1030 can output a digital signal indicating any one of "00", "01", "10", and "11". Therefore, the electronic device 1000c can determine multiple comparison voltages for identifying four types of digital signals within the input range.

[0328] In step S2405, the electronic device 1000c can generate a digital signal DS based on the comparison results between multiple comparison voltages and the analog signal voltage Vsig.

[0329] Figure 25 This is a flowchart illustrating a method for performing digital signal processing operations according to an embodiment of the present disclosure.

[0330] Figure 25 The method shown can, for example, be derived from... Figure 16The electronic device 1000c shown is used to perform this action.

[0331] Reference Figure 16 and Figure 25 In step S2501, the electronic device 1000c can generate a digital signal DS through multiple first column lines.

[0332] In step S2503, electronic device 1000c can generate a digital reference signal Dref corresponding to the reference voltage Vref. For example, electronic device 1000c can use ADC 1030' connected to the second column line to convert the reference voltage Vref into the digital reference signal Dref.

[0333] In step S2505, the electronic device 1000c can perform a multiplication operation on the digital signal DS and the digital reference signal Dref generated through multiple first column lines.

[0334] In step S2507, the electronic device 1000c can generate a digital operation signal DS' based on the result of the multiplication operation.

[0335] In step S2509, the electronic device 1000c can use the digital arithmetic signal DS' to perform data signal processing operations.

[0336] Figure 26 A computing system 2000 according to an embodiment of the present disclosure is shown.

[0337] Reference Figure 26 The computing system 2000 can use neural networks to analyze input data in real time, extract useful information from the input data, and determine the status of electronic devices or control electronic devices installed in the computing system 2000 based on the extracted information. For example, the computing system 2000 can be applied to drones, advanced driver assistance systems (ADAS), smart TVs, smartphones, medical devices, mobile devices, image display devices, measuring devices, Internet of Things (IoT) devices, etc., and can be installed in any of a variety of electronic devices other than these examples.

[0338] The computing system 2000 may include a central processing unit (CPU) 2100, random access memory (RAM) 2200, a neural network processor 2300, input / output (I / O) devices 2400, and memory 2500. The computing system 2000 may further include one or more other general-purpose components, such as a multi-format codec (MFC), a video module (e.g., a camera interface, a Joint Photographic Experts Group (JPEG) processor, a video processor, a mixer, etc.), a 3D graphics kernel, an audio system, a display driver, a graphics processing unit (GPU), or a digital signal processor (DSP). The CPU 2100, RAM 2200, neural network processor 2300, I / O devices 2400, and memory 2500 can send / receive data via a communication bus 2600.

[0339] In one embodiment, the components of the computing system 2000, namely the CPU 2100, RAM 2200, neural network processor 2300, input / output device 2400, and memory 2500, can be integrated into a single semiconductor chip, and the computing system 2000 can be implemented as, for example, a system-on-a-chip (SoC). However, the embodiments are not limited thereto. In another embodiment, the computing system 2000 can be implemented using multiple semiconductor chips. In another embodiment, the computing system 2000 can be an application processor installed in a mobile device.

[0340] CPU 2100 can control all operations of computing system 2000. CPU 2100 can have a single-core architecture or a multi-core architecture with multiple cores. CPU 2100 can process or run programs and / or data stored in RAM 2200 and memory 2500. For example, CPU 2100 can control the functions of computing system 2000 by running programs stored in memory 2500.

[0341] RAM 2200 can temporarily store programs, data, or instructions. For example, programs and / or data stored in memory 2500 can be temporarily loaded into RAM 2200 under the control of CPU 2100 or according to boot code. RAM 2200 can be implemented using memory such as dynamic RAM (DRAM) or static RAM (SRAM).

[0342] Input / output device 2400 can receive user input or input data from an external system and can output data results processed by computing system 2000. Input / output device 2400 can be implemented as a touchscreen panel, keyboard, any type of sensor, etc. In embodiments, input / output device 2400 can collect information about computing system 2000. For example, input / output device 2400 may include at least one of various types of sensing devices, such as imaging devices, image sensors, LiDAR sensors, ultrasonic sensors, and infrared sensors, or may receive sensing signals from such devices.

[0343] Memory 2500 can be a storage device for storing data, and can store, for example, an operating system (OS), various types of programs, and various types of data. Memory 2500 can be, but is not limited to, DRAM. Memory 2500 can include at least one of volatile memory and non-volatile memory. Examples of non-volatile memory include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Examples of volatile memory include dynamic RAM (DRAM), static RAM (SRAM), and synchronous DRAM (SDRAM). Moreover, in embodiments, memory 2500 can be implemented as a storage device such as a hard disk drive (HDD), solid-state drive (SSD), compact flash memory (CF), secure digital storage (SD), micro secure digital storage (microSD), mini secure digital storage (miniSD), extreme digital storage (xD), memory stick, etc.

[0344] The neural network processor 2300 may include a neural network, train the neural network (or allow the neural network to perform learning), perform operations based on received input data, or generate information signals or retrain the neural network based on the operation results. The neural network may include, but is not limited to, any of various types of neural networks, such as convolutional neural networks (CNNs), region convolutional neural networks (R-CNNs), region proposal networks (RPNs), recurrent neural networks (RNNs), deep neural networks (DNNs), stacked deep neural networks (S-DNNs), state-space dynamic neural networks (S-SDNNs), deconvolutional networks, deep belief networks (DBNs), restricted Boltzmann machines (RBNs), fully convolutional networks, long short-term memory (LSTM) networks, and classification networks.

[0345] The neural network processor 2300 can be a dedicated hardware accelerator for neural networks itself or a device including a dedicated hardware accelerator, and can be used... Figure 10 Electronic device 1000a, Figure 13 Electronic device 1000b and Figure 16 It can be implemented by any one of the electronic devices 1000c.

[0346] Although not shown in the accompanying drawings, the computing system 2000 may further include a sensor module.

[0347] The sensor module can collect information about the electronic devices surrounding the installed computing system 2000. The sensor module can sense or receive signals from outside the electronic devices and can convert the sensed or received signals into data. Signals can include image signals, audio signals, magnetic signals, biometric signals, touch signals, etc. For this operation, the sensor module can include at least one of various types of sensing devices, such as microphones, imaging devices, image sensors, LiDAR sensors, ultrasonic sensors, infrared sensors, biosensors, touch sensors, etc.

[0348] The sensor module can provide the converted data as input data to the neural network processor 2300. For example, the sensor module may include an image sensor capable of capturing images of the external environment of the electronic device and generating a video stream, and can sequentially provide consecutive data frames from the video stream as input data to the neural network processor 2300. However, the embodiments are not limited to this. The sensor module can provide various types of data to the neural network processor 2300.

[0349] Figure 27 It shows Figure 26 The neural network processor 2300.

[0350] Reference Figure 27 The neural network processor 2300 may include a controller 2310, a buffer 2320, and a computing circuit 2330. In an embodiment, the controller 2310, the buffer 2320, and the computing circuit 2330 may communicate with each other via a communication bus.

[0351] In one embodiment, the neural network processor 2300 may be implemented as a single semiconductor chip, such as a system-on-a-chip (SoC). However, the embodiments are not limited thereto. In another embodiment, the neural network processor 2300 may be implemented using multiple semiconductor chips.

[0352] The controller 2310 can control all operations of the neural network processor 2300. The controller 2310 can control the operation of the buffer 2320 and the computing circuit 2330. For example, the controller 2310 can set and manage parameters related to neural network operations such as convolution operations to enable the computing circuit 2330 to properly run the layers of the neural network.

[0353] The controller 2310 may be implemented as hardware, software (or firmware), or a combination of hardware and software. In one embodiment, the controller 2310 may be implemented as hardware logic designed to perform the aforementioned functions. In another embodiment, the controller 2310 may be implemented as at least one processor, such as a CPU, microprocessor, etc., and may run a program including instructions constituting the aforementioned functions.

[0354] The buffer 2320 can store weight data. The weight data stored in the buffer 2320 can be provided to the calculation circuit 2330. Moreover, when the weight data is updated, the buffer 2320 can store the updated weight data and provide the updated weight data to the calculation circuit 2330.

[0355] The buffer 2320 can be implemented as random access memory (RAM), such as SRAM, DRAM, etc.

[0356] Furthermore, buffer 2320 can exchange data with external devices. Buffer 2320 can store weight data provided by external devices and provide the weight data to the calculation circuit 2330. Buffer 2320 can provide output information provided by the calculation circuit 2330 to external devices.

[0357] The computing circuit 2330 may include multiple processing elements PE. The computing circuit 2330 can perform convolution operations, such as element-wise multiply-accumulate (MAC) operations. The multiple processing elements PE can store weight data provided by the buffer 2320, receive input data, and perform multiply-accumulate operations on the input data and weight data. The computing circuit 2330 can provide the result of the multiply-accumulate operation to the buffer 2320 or the controller 2310. In an embodiment, each processing element PE can use... Figure 10 Electronic device 1000a, Figure 13 Electronic device 1000b and Figure 16 It can be implemented by any one of the electronic devices 1000c.

[0358] In an embodiment, the controller 2310 can control the buffer 2320 and the computing circuit 2330 so that multiple input voltages corresponding to the input data are input to the computing circuit 2330 through multiple row lines.

[0359] Furthermore, the controller 2310 can control the buffer 2320 and the computing circuit 2330 so that multiple conductance values ​​are stored in multiple memory cells connected to multiple first column lines of the computing circuit 2330.

[0360] Furthermore, the controller 2310 can control the computing circuit 2330 to perform a multiplication-accumulation operation on multiple input voltages and multiple conductance values. The computing circuit 2330 can perform multiplication operations on multiple input voltages and multiple conductance values ​​stored in memory cells connected to each first column line. Additionally, the computing circuit 2330 can perform an accumulation operation on the result of the multiplication operation performed for each first column line. As a result of the multiplication-accumulation operation on multiple input voltages and multiple conductance values, the computing circuit 2330 can output multiple output currents.

[0361] Furthermore, the controller 2310 can control the buffer 2320 and the computing circuit 2330 so that the maximum conductance value is stored in multiple memory cells connected to the second column line of the computing circuit 2330. Here, the maximum conductance value can be the largest among multiple conductance values ​​stored in multiple memory cells connected to multiple first column lines.

[0362] Furthermore, the controller 2310 can control the calculation circuit 2330 to perform a multiplication-accumulation operation on multiple input voltages and maximum conductance values. The calculation circuit 2330 can perform multiplication operations on multiple input voltages and maximum conductance values. Additionally, the calculation circuit 2330 can perform an accumulation operation on the result of the multiplication operation performed on the second column line. As a result of the multiplication-accumulation operation on multiple input voltages and maximum conductance values, the calculation circuit 2330 can output the maximum output current.

[0363] Additionally, the controller 2310 can control the computing circuit 2330 to convert multiple output currents into multiple analog signal voltages. The controller 2310 can also control the computing circuit 2330 to convert the maximum output current into a reference voltage.

[0364] Additionally, the controller 2310 can control the computing circuit 2330 to convert multiple analog signal voltages into multiple digital signals. The computing circuit 2330 can convert the multiple analog signal voltages into multiple digital signals based on an input range determined according to a reference voltage. In this case, the reference voltage can be determined as the maximum value of the input range. In an embodiment, the computing circuit 2330 can output multiple digital signals based on the comparison result between the reference voltage and the multiple analog signal voltages. For example, the computing circuit 2330 can determine multiple comparison voltages based on the reference signal and a preset resolution. The input range can be divided into several segments by the multiple comparison voltages, each segment corresponding to several different digital values. The computing circuit 2330 can output multiple digital signals based on the comparison result between the multiple comparison voltages and the multiple analog signal voltages, each of the multiple digital signals having one of a plurality of different digital values.

[0365] In one embodiment, the controller 2310 can control the computing circuit 2330 to convert multiple digital signals into multiple digital operation signals having a previously normal distribution range. Here, the previously normal distribution range may correspond to the normal distribution range of multiple analog signal voltages. In one embodiment, the computing circuit 2330 can perform a multiplication operation on the multiple digital signals and a digital reference signal corresponding to a reference voltage. The reference voltage is converted into a digital reference signal using an analog-to-digital converter. As a result of the multiplication operation, the computing circuit 2330 can output multiple digital operation signals having a previously normal distribution range. Furthermore, the computing circuit 2330 can use the digital operation signals having a previously normal distribution range to perform digital signal processing operations.

[0366] Figure 28 It shows Figure 27 The controller is 2310.

[0367] Reference Figure 28 The controller 2310 may include a processor 2311, an activation function circuit 2312, a layer controller 2313, a compression / decompression engine 2314, and an input / output (I / O) interface 2315.

[0368] The processor 2311 can control all operations of the controller 2310.

[0369] The activation function circuit 2312 can apply the activation function to the circuit. Figure 27 The result of the multiplication and accumulation operation provided by the computing circuit 2330.

[0370] The layer controller 2313 can control the data transmission between multiple processing elements PE in the computing circuit 2330.

[0371] Compression / decompression engine 2314 can compress / decompress... Figure 26The CPU 2100 performs decompression operations on the data provided and performs compression operations on the data to be provided to the CPU 2100.

[0372] I / O interface 2315 can perform interface operations related to data input / output between CPU 2100 and controller 2310.

[0373] In this embodiment, the activation function circuit 2312 and the I / O interface 2315 may be implemented using a field-programmable gate array (FPGA), and the processor 2311, the layer controller 2313, and the compression / decompression engine 2314 may be implemented using an application-specific integrated circuit (ASIC).

[0374] Figure 29 It shows Figure 27 The computing circuit 2330.

[0375] Reference Figure 29 The computing circuit 2330 may include multiple processing elements PE. Each of the multiple processing elements PE can perform a multiplication-accumulation operation on the input data and weight data. For example, the multiple processing elements PE can operate independently and can perform multiplication-accumulation operations simultaneously. Therefore, multiplication-accumulation operations can be performed on multiple input data in parallel. In an embodiment, a layer included in the neural network may be implemented using one processing element PE. In an embodiment, each processing element PE may use... Figure 10 Electronic device 1000a, Figure 13 Electronic device 1000b and Figure 16 It can be implemented by any one of the electronic devices 1000c.

[0376] In an embodiment, each of the plurality of processing elements PE may include a plurality of subarrays SA. The plurality of subarrays SA can perform multiply-accumulate operations on the input data and weight data. For example, the plurality of subarrays SA can operate independently and can perform multiply-accumulate operations simultaneously. Therefore, multiply-accumulate operations can be performed on multiple input data in parallel. In an embodiment, a layer included in a neural network can be implemented using a single processing element PE or a single subarray SA. In an embodiment, each subarray SA can use... Figure 10 Electronic device 1000a, Figure 13 Electronic device 1000b and Figure 16 It can be implemented by any one of the electronic devices 1000c.

[0377] Figure 30 It shows Figure 29 The subarray SA.

[0378] Reference Figure 30The subarray SA may include a crossbar switch array 2331, row drive circuitry 2332, column drive circuitry 2333, multiple current-to-voltage converters (IVCs) 2334, and multiple analog-to-digital converters (ADCs) 2335. In an embodiment, row drive circuitry 2332 may be designated as a row selector, and column drive circuitry 2333 may be designated as a column selector.

[0379] The crossbar switch array 2331 may include multiple resistive memory cells arranged in a matrix, each memory cell including a resistive element. Each of the multiple resistive memory cells may be connected to one of a plurality of row lines and one of a plurality of column lines.

[0380] The crossbar switch array 2331 can store multiple weight data, such as multiple weights. For example, multiple resistive memory cells can store multiple weights using the resistance variation of the resistive elements included in each of the multiple resistive memory cells. The crossbar switch array 2331 can receive multiple input voltages corresponding to input data and generate multiple currents based on the multiple input voltages and multiple weights. For example, multiple input voltages can be input to the crossbar switch array 2331 through multiple row lines.

[0381] The row drive circuit 2332 can be connected to multiple row lines of the crossbar switch array 2331. Although not shown in detail in the figures, the row drive circuit 2332 can drive multiple row lines based on a row selection signal for selecting at least one of the multiple row lines. Furthermore, the row drive circuit 2332 can drive multiple row lines based on a row drive voltage for driving at least one of the multiple row lines.

[0382] The column drive circuit 2333 can be connected to multiple column lines of the crossbar switch array 2331. Although not shown in detail in the accompanying drawings, the column drive circuit 2333 can drive multiple column lines based on a column selection signal for selecting at least one of the multiple column lines. Furthermore, the column drive circuit 2333 can drive multiple column lines based on a column drive voltage for driving at least one of the multiple column lines.

[0383] Multiple current-to-voltage converters 2334 can convert multiple currents output from the cross-switch array 2331 into multiple analog signal voltages. For example, each of the multiple current-to-voltage converters 2334 can be implemented to include a current mirror. The multiple current-to-voltage converters 2334 can correspond to Figure 2A and Figure 2B The current-to-voltage converter 220 is shown.

[0384] Multiple ADC 2335s can convert multiple analog signal voltages into multiple digital signals. Multiple ADC 2335s can correspond to... Figure 2A and Figure 2B The ADC 230 shown.

[0385] Figure 31 A cross switch array with a hierarchical structure according to an embodiment of the present disclosure is shown.

[0386] Reference Figure 31 The neural network processor 2300 may include a controller 2310, a buffer 2320, and multiple crossbar switch arrays 2331-1 to 2331-n. The neural network processor 2300 may be configured such that the controller 2310, buffer 2320, and multiple crossbar switch arrays 2331-1 to 2331-n are individually stacked and packaged. The controller 2310, buffer 2320, and multiple crossbar switch arrays 2331-1 to 2331-n may be electrically connected to each other, and for such connection, the neural network processor 2300 may include a conductive method for electrically connecting the controller 2310, buffer 2320, and multiple crossbar switch arrays 2331-1 to 2331-n to each other. In an embodiment, a silicon via (TSV) may be applied as a conductive method.

[0387] In an embodiment, buffer 2320 may store the results of operations performed by a plurality of crossbar switch arrays 2331-1 to 2331-n. Buffer 2320 may include volatile memory cells or non-volatile memory cells.

[0388] Controller 2310 can be with Figure 26 The CPU 2100 can communicate with the CPU 2100, receive requests and weights, and provide commands corresponding to the requests and weights to multiple crossbar switch arrays 2331-1 to 2331-n.

[0389] The controller 2310 can generate commands in response to requests provided by the CPU 2100, and can provide commands to multiple cross switch arrays 2331-1 to 2331-n via commands TSVs formed independently for each cross switch array 2331-1 to 2331-n.

[0390] The controller 2310 can store weights in multiple cross switch arrays 2331-1 to 2331-n, provide input data to multiple cross switch arrays 2331-1 to 2331-n, and receive final data from multiple cross switch arrays 2331-1 to 2331-n.

[0391] Input data and weights can be provided to at least one of the multiple cross switch arrays 2331-1 to 2331-n, and final data from at least one of the multiple cross switch arrays 2331-1 to 2331-n can be provided to another cross switch array or controller 2310.

[0392] Figure 32 A neural network processor 3200 according to an embodiment of the present disclosure is shown.

[0393] Figure 32 The neural network processor 3200 can be implemented as Figure 26 A component of the neural network processor 2300.

[0394] Reference Figure 32 The neural network processor 3200 may include a cross-switch array 3210, a plurality of first neurons 3220, and a plurality of second neurons 3230. The cross-switch array 3210 may be referred to as a "synaptic array". Each of the plurality of first neurons 3220 may be referred to as a "presynaptic neuron", and each of the plurality of second neurons 3230 may be referred to as a "postsynaptic neuron".

[0395] The cross switch array 3210 may include multiple synapses 3211, which can be connected to multiple first neurons 3220 via multiple row lines RL and to multiple second neurons 3230 via multiple column lines CL.

[0396] The cross-switch array 3210 can store the weights included in the layers constituting a neural network system and can perform operations based on the weights and input data. In the cross-switch array 3210, the weights can be stored in multiple synapses 3211.

[0397] Figure 33 The diagram illustrates the connections between a first neuron, a second neuron, and synapses connecting the first neuron and the second neuron according to embodiments of the present disclosure. Figure 33 The synapse shown can correspond to Figure 32 One of the multiple synapses 3211 included in the cross switch array 3210.

[0398] exist Figure 33 In the process, the first neuron 3220 is connected to the synapse 3211 via the row line RL, while the second neuron 3230 is connected to the synapse 3211 via the column line CL.

[0399] Synapse 3211 may include a memristor 3213 with a variable resistance value and a transistor 3212 to which at least two input signals are applied. The resistance value of memristor 3213 may vary depending on the time difference between applying at least two input signals to transistor 3212.

[0400] The resistance of memristor 3213 may vary with the voltage change caused by the time difference between when an input signal is applied to transistor 3212. For example, the resistance of memristor 3213 may vary with the voltage change caused by the time difference between a first input signal and a second input signal. The first input signal may be a signal applied to the gate terminal of transistor 3212. Further, the second input signal may be a signal based on the membrane voltage applied to the source terminal of transistor 3212. The first input signal may be transmitted from the first neuron 3220, while the second input signal may be transmitted from the second neuron 3230.

[0401] The direction of the current flowing through memristor 3213 can depend on the time difference between the first input signal and the second input signal being applied to transistor 3212. For example, when the first input signal is input to transistor 3212 earlier than the second input signal, current can flow from transistor 3212 to memristor 3213. On the other hand, when the first input signal is input to transistor 3212 later than the second input signal, current may flow from memristor 3213 to transistor 3212 in the opposite direction to the previous direction.

[0402] The direction and amount of current flowing through memristor 3213 can depend on the voltage difference caused by the time difference between the first input signal and the second input signal being applied to transistor 3212. For example, when the time difference between the first and second input signals is large and therefore the first and second input signals are unlikely to influence each other, transistor 3212 is turned on simultaneously with the first input signal, and current flows from memristor 3213 to transistor 3212 because the reference voltage Vref is greater than the idle voltage Vrest. The reference voltage Vref is applied to one end of memristor 3213, and the idle voltage Vrest is applied from the second neuron 3230 to transistor 3212. In this case, because the voltage difference (Vref-Vrest) across memristor 3213 is less than the threshold voltage that changes the characteristics of memristor 3213, memristor 3213 is in a high-resistance state (HRS), and only a small amount of current close to "0" can flow through memristor 3213.

[0403] When the difference in time between the input of the first input signal and the second input signal is within the range where the first input signal and the second input signal influence each other and thus the input of the first input signal is slightly earlier than the input of the second input signal, the transistor 3212 is turned on while the first input signal is being input. In this case, when the voltage Vb at the source terminal of the transistor 3212 satisfies the relationship Vb > Vref, current flows from the transistor 3212 to the memristor 3213. Here, when the voltage difference (Vb - Vref) between both ends of the memristor 3213 is greater than the threshold voltage for changing the characteristics of the memristor 3213, the memristor 3213 can be changed to the low resistance state (LRS). When the memristor 3213 is in the low resistance state (LRS), a large amount of current may flow through the memristor 3213; otherwise, the memristor 3213 can maintain the high resistance state (HRS).

[0404] When the difference in time between the input of the first input signal and the second input signal is within this range and thus the times of input of the first input signal and the second input signal are close or the input of the first input signal is slightly later than the input of the second input signal, the transistor 3212 is turned on while the first input signal is being input. In this case, when the voltage Vb at the source terminal of the transistor 3212 satisfies the relationship Vb < Vref, current flows from the memristor 3213 to the transistor 3212. When the voltage difference (Vref - Vb) between both ends of the memristor 3213 is greater than the threshold voltage for changing the characteristics of the memristor 3213, the memristor 3213 can be changed to the high resistance state (HRS), and thus a small amount of current can flow through the memristor 3213. Otherwise, the memristor 3213 may maintain the low resistance state (LRS).

[0405] When the input of the first input signal is much later than the input of the second input signal, that is, when there is a large time difference in time between the input of the first input signal and the second input signal and thus the first input signal and the second input signal are difficult to influence each other, since the reference voltage Vref becomes greater than the idle voltage Vrest, current flows from the memristor 3213 to the transistor 3212. Here, since the voltage difference (Vref - Vrest) between both ends of the memristor 3213 is less than the threshold voltage for changing the characteristics of the memristor 3213, the memristor 3213 can be in the high resistance state (HRS). The large time difference can be determined based on whether the first input signal and the second input terminal influence each other.

[0406] The first terminal of memristor 3213 can be connected to the drain terminal of transistor 3212, and its second terminal can be connected to a voltage source providing a reference voltage Vref. The channel of memristor 3213 can be connected in series with the channel of transistor 3212. Memristor 3213 and transistor 3212 can be subjected to different voltages, and transistor 3212 can be an NMOS transistor.

[0407] Synapse 3211 may further include a first node connected to the gate terminal of transistor 3212 to provide a first input signal to transistor 3212, and a second node connected to the source terminal of transistor 3212 to provide a second input signal to transistor 3212. Synapse 3211 can be connected to a first neuron 3220 via the first node, and can be connected to a second neuron 3230 via the second node. Here, a first voltage Va can be provided from the first neuron 3220 to synapse 3211 via the first node, and a second voltage Vb can be provided from the second neuron 3230 to synapse 3211 via the second node.

[0408] The first neuron 3220 may include an integral and trigger (I&F) spike neuron 3221 that triggers spikes or pulses. The second neuron 3230 may include an I&F spike neuron 3231. Each of the first neuron 3220 and the second neuron 3230 may trigger a spike or pulse when the amount of current received through the synapse 3211 is greater than a preset threshold.

[0409] The second neuron 3230 can generate spikes triggered by the idle voltage Vrest. The second neuron 3230 may further include a capacitor 3232.

[0410] Figure 33 The structure can perform Spike-Timing-Dependent Plasticity (STDP) operations.

[0411] Figure 34 It is shown Figure 33 The graph shows the operational characteristics of the memristor included in the synapse.

[0412] Reference Figure 34 This describes the operating characteristics of a memristor. A memristor is a passive component that can remember how much current has flowed through it and can also remember the amount of charge and change its resistance value according to the amount of charge it remembers. In other words, the resistance value of a memristor can change according to the flow of current and the amount of charge.

[0413] exist Figure 34The graph shows that when the voltage supplied to the memristor is below ±0.8V, almost no current flows through it. However, it also shows that when the supply voltage exceeds ±0.8V, a large current suddenly flows through the memristor. Here, the voltage at which the current changes abruptly can be considered the threshold voltage of the memristor, and can correspond to... Figure 34 ±0.8V.

[0414] A resistive state in which the voltage supplied to the memristor does not reach the threshold voltage and therefore current hardly flows through the memristor can be considered a high-resistance state (HRS). On the other hand, a resistive state in which the voltage supplied to the memristor exceeds the threshold voltage and therefore current suddenly flows through the memristor can be considered a low-resistance state (LRS).

[0415] Figure 35 and Figure 36 It shows in Figure 33 The relationship between the amount of current flowing between the first and second neurons and the difference between the number of spikes occurring during a typical STDP operation and the changes in synaptic weights.

[0416] Figure 35 This illustrates the relationship between the time difference between the occurrence of the postsynaptic spike and the presynaptic pulse and the amount of current flowing during that time difference. It can be seen that the relationship between the time difference and the amount of current has a similarity to... Figure 36 Its characteristics.

[0417] When the spikes triggered in the synapse are modeled as electronic waveforms, the changes in synaptic weights can be represented by subtraction between the pulse waveform triggered in the first neuron (hereinafter referred to as the "presynaptic pulse") and the spike waveform triggered in the second neuron (hereinafter referred to as the "postsynaptic spike").

[0418] Figure 37 A neural network processor 3700 according to another embodiment of the present disclosure is shown.

[0419] Figure 37 The neural network processor 3700 can be implemented as Figure 26 A component of the neural network processor 2300.

[0420] Reference Figure 37 The neural network processor 3700 may include a cross-switch array 3710, a plurality of first neurons 3720, and a plurality of second neurons 3730. The cross-switch array 3710 may be referred to as a "synaptic array". Each of the plurality of first neurons 3720 may be referred to as a "presynaptic neuron", and each of the plurality of second neurons 3730 may be referred to as a "postsynaptic neuron".

[0421] The cross switch array 3710 may include multiple synapses 3711, which can be connected to multiple first neurons 3720 via multiple row lines RL and to multiple second neurons 3730 via multiple column lines CL and multiple selection lines SL.

[0422] The cross-switch array 3710 can store the weights included in each of the layers that make up the neural network system in multiple synapses 3711, and can perform operations based on the weights and input data.

[0423] Figure 38 An embodiment according to this disclosure is shown. Figure 37 One of the multiple synapses included in the synaptic array.

[0424] Reference Figure 38 The first neuron 3720 is connected to the synapse 3711 via the row line RL, and the second neuron 3730 is connected to the synapse 3711 via the column line CL and multiple selection lines SL.

[0425] Synapse 3711 may include a switching transistor 3713 and a memristor 3715 connected in series. Switching transistor 3713 may include a 3-terminal selector such as a MOS transistor or a 2-terminal selector such as a diode. The gate electrode of switching transistor 3713 is electrically connected to a second neuron 3730 via select line SL, the drain of switching transistor 3713 is electrically connected to a first neuron 3720 via row line RL, and the source of switching transistor 3713 is electrically connected to a first terminal of memristor 3715. The second terminal of memristor 3715 is electrically connected to the second neuron 3730 via column line CL.

[0426] Reference Figure 37 and Figure 38 Row signals can be provided from the first neuron 3720 to the synapse 3711 via row line RL. When the switching transistor 3713 of the synapse 3711 is turned on, the row signals can be provided to the memristor 3715. The row signals can be used to train the memristor 3715 in various modes, allowing the resistance state of the memristor 3715 to be adjusted. Based on the resistance state of the memristor 3715 in read mode, the row signals can be converted into current values. That is, the resistance state of the memristor 3715 can change in response to the row signals, or the current value of the memristor 3715's resistance state can be output to the column line CL in response to the row signals. In other words, the weights of the synapse 3711 can be output to the column line CL.

[0427] Figure 39 An embodiment according to this disclosure is shown. Figure 37 The second neuron.

[0428] Reference Figure 39 The second neuron 3730 may include a summing circuit 3731 connected in series with each other, a variable resistive element (resistor) 3732 and a comparator 3733.

[0429] The output terminal of synapse 3711 can be connected to the input terminal of summing circuit 3731 via column line CL. The output terminal of summing circuit 3731 can be connected to the first electrode of variable resistive element 3732 via first node N1. The second electrode of variable resistive element 3732 can be connected to the input terminal of comparator 3733 via second node N2. Second neuron 3730 may further include a first feedback line 3734 and a second feedback line 3735. The first feedback line 3734 electrically connects the output terminal of comparator 3733 to variable resistive element 3732, and the second feedback line 3735 electrically connects the output terminal of comparator 3733 to synapse 3711. The first feedback line 3734 can be electrically connected to second node N2, and the second feedback line 3735 can be connected to select line SL. Optionally, the second feedback line 3735 may be part of select line SL.

[0430] The summing circuit 3731 can sum the weights of multiple synapses 3711 connected to the same column line CL and provide the summation result to the variable resistive element 3732.

[0431] The resistance or conductivity of the variable resistive element 3732 can be changed by the output of the summing circuit 3731 and / or the output of the comparator 3733. For example, the resistance of the variable resistive element 3732 can be decreased by the output of the summing circuit 3731 (setting operation) and increased by the output of the comparator 3733 (reset operation). For example, when the synaptic current obtained by summing the sums from the summing circuit 3731 is low, the variable resistive element 3732 can have a higher resistance level. Therefore, a low-level current and a low-level synaptic weight can be provided to the comparator 3733. On the other hand, when the synaptic current output from the summing circuit 3731 is high, the variable resistive element 3732 can have a lower resistance level. Therefore, a high-level current and a high-level synaptic weight can be provided to the comparator 3733.

[0432] When the output of the variable resistor element 3732 is higher than the reference voltage, the comparator 3733 can output an electrical signal. That is, the comparator 3733 can be triggered. After being triggered, the comparator 3733 can output an output signal Sout. A portion of the output signal Sout can be divided into a first feedback signal Sb1 and a second feedback signal Sb2.

[0433] The first feedback signal Sb1, derived from the output signal Sout of comparator 3733, can be provided to the variable resistor element 3732 and used to initialize it. Figure 37 The second feedback signal Sb2, derived from the output signal Sout of the comparator 3733, can be provided to the gate electrode of the switching transistor 3713. Therefore, the second feedback signal Sb2 can be provided to the gate electrode of the switching transistor 3713 and used to set / reset the memristor 3715. For example, the second feedback signal Sb2 can be used to perform spike timing-dependent plasticity (STDP) operations to change the weights of the synapse 3711.

[0434] According to embodiments of this disclosure, an electronic device and a method for operating the electronic device are provided that can reduce errors in quantization operations by adjusting the input range of an analog-to-digital converter (ADC) based on input data.

[0435] Furthermore, according to embodiments of this disclosure, by adjusting the input range of the ADC based on the input data, the accuracy of neural network operations can be improved, and the implementation cost of the analog-to-digital converter (ADC) can be reduced.

[0436] While this disclosure has been shown and described with reference to certain exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the exemplary embodiments described above, but should be determined not only by the appended claims but also by their equivalents.

Claims

1. An electronic device comprising: Cross switch array, including: Multiple first memory units, each storing multiple conductance values; A plurality of second memory units, each second memory unit storing the maximum conductance value determined among the plurality of conductance values; Multiple line lines are connected to the multiple first memory cells and the multiple second memory cells, and multiple input voltages are supplied to the multiple first memory cells and the multiple second memory cells; Multiple first column lines are connected to the multiple first memory cells, and respectively output multiple output currents generated using the multiple input voltages and the multiple conductance values; and The second column of lines is connected to the plurality of second memory cells and outputs the maximum output current generated using the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells; and Multiple analog-to-digital converters (ADCs) are respectively connected to the multiple first column lines. Each of the multiple ADCs receives a reference voltage and an analog signal voltage corresponding to each of the multiple output currents, and generates a digital signal corresponding to the analog signal voltage based on the reference voltage, which is generated according to the maximum output current. Each of the plurality of analog-to-digital converters determines the maximum allowable value of the analog signal voltage based on the reference voltage.

2. The electronic device according to claim 1, wherein: The plurality of first column lines output the plurality of output currents by performing a multiplication and accumulation operation on the plurality of input voltages and the plurality of conductance values, and The second column line outputs the maximum output current by performing a multiplication-accumulation operation on the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells.

3. The electronic device of claim 1, wherein each of the plurality of analog-to-digital converters determines a plurality of comparison voltages based on the reference voltage and a resolution set in the plurality of analog-to-digital converters, and outputs the digital signal based on the result of comparing the analog signal voltage with the plurality of comparison voltages.

4. The electronic device of claim 3, wherein when the magnitude of the analog signal voltage is greater than the magnitude of the reference voltage, each of the plurality of analog-to-digital converters changes the magnitude of the analog signal voltage to be equal to the magnitude of the reference voltage, and outputs the digital signal based on the result of comparing the magnitude-changed analog signal voltage with the plurality of comparison voltages.

5. The electronic device according to claim 1, further comprising: A plurality of first current-to-voltage converters, each receiving an output current from a corresponding line of the plurality of first column lines and converting the output current into an analog signal voltage; as well as The second current-to-voltage converter receives the maximum output current from the second column line and converts the maximum output current into the reference voltage.

6. The electronic device according to claim 5, further comprising: Multiple voltage buffers are respectively connected to and disposed between the multiple first current-to-voltage converters and the multiple analog-to-digital converters, and receive analog signal voltages from the multiple first current-to-voltage converters, buffer the analog signal voltages to eliminate noise contained in the analog signal voltages, and output the buffered analog signal voltages to the multiple analog-to-digital converters.

7. The electronic device of claim 6, wherein each of the plurality of voltage buffers receives the reference voltage and determines that the maximum value of the output voltage is limited to the reference voltage.

8. The electronic device of claim 7, wherein each of the plurality of voltage buffers outputs a buffered analog signal voltage of the same magnitude as the reference voltage to a corresponding one of the plurality of analog-to-digital converters when the magnitude of the corresponding analog signal voltage is greater than the magnitude of the reference voltage.

9. The electronic device according to claim 1, further comprising: A digital signal processor outputs a digital processing signal based on a digital signal output from one of the plurality of analog-to-digital converters and the reference voltage.

10. The electronic device of claim 9, wherein the digital signal processor outputs the digital arithmetic signal as the result of multiplying the digital signal and a digital reference signal corresponding to the reference voltage.

11. The electronic device according to claim 9, wherein: The digital signal processor outputs multiple digital operation signals based on multiple digital signals and multiple reference voltages. These multiple digital signals are respectively output from the multiple analog-to-digital converters to which the multiple reference voltages are applied. Each of the plurality of reference voltages is generated based on a multiplication-accumulation operation performed on the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory units, the plurality of input voltages corresponding to each of the plurality of input data input at different time points.

12. The electronic device of claim 11, wherein the electronic device uses the plurality of digital arithmetic signals to perform digital signal processing operations.

13. The electronic device of claim 1, wherein the maximum conductance value stored in each of the plurality of second memory cells corresponds to the largest of the plurality of conductance values.

14. The electronic device of claim 1, wherein the maximum conductance value stored in one of the plurality of second memory cells corresponds to the maximum of the conductance values ​​stored in a first memory cell connected to a row line to which the second memory cell is connected.

15. An electronic device comprising: Cross switch array, including: Multiple first memory units, each storing multiple conductance values; Multiple second memory units, each second memory unit storing the maximum conductance value among the multiple conductance values; Multiple line lines are connected to the multiple first memory cells and the multiple second memory cells, and multiple input voltages are supplied to the multiple first memory cells and the multiple second memory cells; Multiple first column lines are connected to the multiple first memory cells, and respectively output multiple output currents generated using the multiple input voltages and the multiple conductance values; and The second column of lines is connected to the plurality of second memory cells and outputs the maximum output current generated using the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells; and Multiple analog-to-digital converters are respectively connected to the multiple first column lines. Each of the multiple analog-to-digital converters receives a reference voltage and an analog signal voltage corresponding to each of the multiple output currents, and converts the analog signal voltage into a digital signal corresponding to the analog signal voltage by applying a gain corresponding to the reference voltage to the analog signal voltage. The reference voltage is generated based on the maximum output current.

16. The electronic device of claim 15, wherein each of the plurality of analog-to-digital converters determines a plurality of comparison voltages based on the reference voltage and a resolution set in the plurality of analog-to-digital converters, and outputs the digital signal based on the result of comparing the analog signal voltage to which the gain is applied with the plurality of comparison voltages.

17. The electronic device of claim 15, wherein when the magnitude of the analog signal voltage is greater than the magnitude of the reference voltage, the plurality of analog-to-digital converters control the gain such that the magnitude of the analog signal voltage to which the gain is applied is less than or equal to the magnitude of the reference voltage.

18. The electronic device of claim 15, further comprising: A plurality of first current-to-voltage converters, each receiving an output current from a corresponding line of the plurality of first column lines and converting the output current into the analog signal voltage; as well as The second current-to-voltage converter receives the maximum output current from the second column line and converts the maximum output current into the reference voltage.

19. The electronic device according to claim 15, further comprising: A digital signal processor performs a multiplication operation on a digital signal output from one of the plurality of analog-to-digital converters and a digital reference signal corresponding to the reference voltage.

20. A method of operating an electronic device, the electronic device comprising a crossbar switch array, the crossbar switch array comprising a plurality of row lines, a plurality of first column lines, a second column line, a plurality of first memory cells connected to the plurality of row lines and the plurality of first column lines, and a plurality of second memory cells connected to the plurality of row lines and the second column lines, the method comprising: Multiple input voltages are received through the multiple rows of lines; The maximum output current is generated based on the plurality of input voltages and the maximum conductance value stored in each of the plurality of second memory cells, the maximum conductance value corresponding to the maximum conductance value among the plurality of conductance values ​​stored in the plurality of first memory cells; Convert the maximum output current into a reference voltage; as well as The maximum allowable value of the analog signal voltage input to each of the plurality of analog-to-digital converters respectively connected to the plurality of first column lines is determined based on the reference voltage. The analog signal voltage corresponds to each of the plurality of output currents output from the plurality of first column lines.

21. The method of claim 20, further comprising: The analog signal voltage is buffered and the buffered analog signal voltage is provided to each of the plurality of analog-to-digital converters.

22. The method of claim 21, wherein the determination comprises: The reference voltage is determined to be the maximum value of the input range of the analog signal voltage.

23. The method of claim 20, wherein the determination further comprises: A gain corresponding to the reference voltage is applied to the analog signal voltage.

24. The method of claim 20, further comprising: Multiple output currents are generated based on the multiple input voltages and the multiple conductance values ​​of the multiple first column lines; and The plurality of analog signal voltages are converted into a plurality of digital signals by the plurality of analog-to-digital converters, the plurality of analog signal voltages being generated based on the plurality of output currents.

25. The method of claim 24, wherein converting the plurality of analog signal voltages into the plurality of digital signals comprises: Multiple comparison voltages are determined based on the reference voltage and the resolution set in the multiple analog-to-digital converters; and The plurality of analog signal voltages are converted into the plurality of digital signals based on the result of comparing each of the plurality of analog signal voltages with the plurality of comparison voltages.

26. The method of claim 24, further comprising: A multiplication operation is performed on each of the plurality of digital signals and the digital reference signal corresponding to the reference voltage.

Images