Display driving circuit, display module and display device

Abstract

The application discloses a display driving circuit, a display module and a display device. If a high-speed display data is received by a data receiving port of an interface sub-circuit of the display driving circuit, the interface sub-circuit can transmit an effective enable signal to a corresponding synchronization sub-circuit. The synchronization sub-circuit can output a first indication signal based on the effective enable signal, so that a channel statistics sub-circuit can count a first number of the received first indication signals. A processing sub-circuit can further convert the display data transmitted by the synchronization sub-circuit into a serial signal based on the first number. Since the first number can reflect the number of the data receiving ports of the display driving circuit that receive the high-speed display data, i.e. the number of effective data channels, the number of the effective data channels does not need to be configured by a developer through writing a register, so that the efficiency and flexibility of the display data transmission are effectively improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display driving circuit, a display module and a display device. BACKGROUND

[0002] The display device generally comprises a processor, a touch and display driver integrated circuit (TDDIC) and a display screen. The processor can transmit display data to the TDDIC through a display serial interface (DSI) protocol defined by a mobile industry processor interface (MIPI) alliance (referred to as MIPI-DSI protocol), and the TDDIC can further drive the display screen to display images.

[0003] In the MIPI-DSI protocol, the sending port of the processor can be connected with the receiving port of the TDDIC through four data channels. The number of data channels required to be used when transmitting display data to the TDDIC by using the MIPI-DSI protocol can be pre-configured in the register of the display device. Thus, the processor can select to use at least one data channel in the four data channels to transmit display data in parallel based on the number configured in the register. After the TDDIC receives the display data through the receiving port, the TDDIC can also serialize the display data transmitted in parallel in the at least one data channel based on the number of data channels configured in the register, and drive the display screen to display images based on the serialized display data.

[0004] However, the above method needs the developer to write the number of channels into the register, which results in low efficiency and flexibility of display data transmission. SUMMARY

[0005] The present application provides a display driving circuit, a display module and a display device, which can solve the problem of low efficiency and flexibility of display data transmission in the related art. The technical solution is as follows:

[0006] In one aspect, a display driving circuit is provided, the display driving circuit has a plurality of data receiving ports, the plurality of data receiving ports are used to connect with a plurality of data sending ports of a processor through a plurality of data channels; the display driving circuit comprises: an interface sub-circuit, a plurality of synchronization sub-circuits corresponding to the plurality of data receiving ports one by one, a channel statistics sub-circuit, and a processing sub-circuit.

[0007] The interface sub-circuit is connected with the plurality of data receiving ports and the plurality of synchronization sub-circuits respectively, and is configured to output display data received by a corresponding data receiving port and an enable signal to each of the plurality of synchronization sub-circuits; wherein if the display data is high-speed display data, the enable signal is a valid enable signal, and if the display data is low-speed display data or the data receiving port does not receive display data, the enable signal is an invalid enable signal.

[0008] Each of the plurality of synchronization sub-circuits is connected with the channel statistics sub-circuit and the processing sub-circuit respectively, and is configured to transmit the display data received thereby to the processing sub-circuit, and output a first indication signal to the channel statistics sub-circuit if the valid enable signal is received.

[0009] The channel statistics sub-circuit is connected with the processing sub-circuit, and is configured to count a first number of the first indication signals received, and send the first number to the processing sub-circuit.

[0010] The processing sub-circuit is configured to perform parallel-serial conversion on the display data received based on the first number.

[0011] Optionally, the channel statistics sub-circuit comprises an adder.

[0012] The adder is configured to sum the first indication signals received, and send the first number obtained by the summing to the processing sub-circuit.

[0013] Optionally, the display driving circuit further comprises a register, and the channel statistics sub-circuit further comprises a data selector.

[0014] The register is connected with a control terminal and a first input terminal of the data selector respectively, and is configured to transmit a selection signal to the control terminal, and transmit a second number of valid data channels to the first input terminal.

[0015] A second input terminal of the data selector is connected with an output terminal of the adder, an output terminal of the data selector is connected with the processing sub-circuit, and the data selector is configured to transmit the second number received by the first input terminal to the processing sub-circuit if the selection signal is a first selection signal, and transmit the first number received by the second input terminal to the processing sub-circuit if the selection signal is a second selection signal.

[0016] The processing sub-circuit is further configured to perform parallel-serial conversion on the display data received based on the second number.

[0017] Optionally, the display data comprises a synchronization header and valid data; the synchronization sub-circuit is configured to:

[0018] If the synchronization header in the display data is detected, the valid data in the display data is transmitted to the processing sub-circuit.

[0019] Optionally, each of the synchronization sub-circuits comprises a sampling sub-circuit and an identification sub-circuit.

[0020] The sampling sub-circuit is connected to the interface sub-circuit and the identification sub-circuit, respectively, and is configured to sample the received display data when the received enable signal is the valid enable signal, and transmit the sampling result to the identification sub-circuit.

[0021] The identification sub-circuit is connected to the channel statistics sub-circuit and the processing sub-circuit, respectively, and is configured to, if the synchronization header in the display data is detected based on the sampling result, transmit the valid data in the display data to the processing sub-circuit, and transmit a first indication signal to the channel statistics sub-circuit.

[0022] Optionally, the display driving circuit further has a clock receiving port, which is configured to be connected to a clock sending port of the processor through a clock channel.

[0023] The interface sub-circuit is further connected to the clock receiving port, and is further configured to receive a clock signal sent by the clock sending port through the clock receiving port, and transmit the clock signal to each of the sampling sub-circuits, respectively.

[0024] The plurality of sampling sub-circuits are further configured to perform data synchronization on the received display data based on the clock signal.

[0025] Optionally, the display data further comprises a packet tail.

[0026] The identification sub-circuit is further configured to, if the packet tail in the display data is detected based on the sampling result, stop transmitting display data to the processing sub-circuit, and stop transmitting the first indication signal to the channel statistics sub-circuit.

[0027] Optionally, the plurality of data receiving ports comprise one first data receiving port and three second data receiving ports.

[0028] The first data receiving port is configured to receive high-speed display data or low-speed display data sent by a corresponding one of the signal sending ports.

[0029] Each of the second data receiving ports is configured to receive high-speed display data sent by a corresponding one of the signal sending ports.

[0030] Optionally, the interface sub-circuit comprises a control sub-circuit and a high-speed transmission sub-circuit connected with the plurality of data receiving ports one by one.

[0031] The control sub-circuit is connected with the clock receiving port of the display driving circuit and each high-speed transmission sub-circuit, and is configured to transmit a control signal to each high-speed transmission sub-circuit based on a clock signal received by the clock receiving port.

[0032] Each high-speed transmission sub-circuit is further connected with a corresponding synchronization sub-circuit, and is configured to, under the control of the control signal, transmit high-speed display data received by the data receiving port to the corresponding synchronization sub-circuit, transmit an effective enable signal to the corresponding synchronization sub-circuit, and transmit an ineffective enable signal to the corresponding synchronization sub-circuit when the display data received by the data receiving port is low-speed display data or no display data is received.

[0033] In another aspect, a display module is provided, comprising the display driving circuit in the above aspect and a display screen.

[0034] The display driving circuit is configured to drive the display screen to display an image based on the received display data.

[0035] In yet another aspect, a display device is provided, comprising a processor and the display module in the above aspect.

[0036] The processor has a plurality of data sending ports connected with a plurality of data receiving ports of a display driving circuit in the display module through a plurality of data channels, and is configured to transmit display data to the display driving circuit.

[0037] Optionally, the display data is transmitted between the processor and the display driving circuit in the display module through a MIPI-DSI protocol.

[0038] Optionally, the processor is a central processing unit (CPU), and the display driving circuit is a TDDIC.

[0039] The technical scheme provided in the application has at least the following beneficial effects:

[0040] The application discloses a display driving circuit, a display module and a display device. If a high-speed display data is received by an interface sub-circuit of the display driving circuit through a data receiving port, the interface sub-circuit can transmit an effective enable signal to a corresponding synchronization sub-circuit. The synchronization sub-circuit can output a first indication signal based on the effective enable signal, so that a channel statistical sub-circuit can count a first quantity of the first indication signals received by the channel statistical sub-circuit. A processing sub-circuit can further convert display data transmitted by the synchronization sub-circuit into a serial signal based on the first quantity. Since the first quantity can reflect the quantity of data receiving ports receiving the high-speed display data in the plurality of data receiving ports of the display driving circuit, i.e., the quantity of effective data channels, the quantity of the effective data channels does not need to be configured by a developer through a register writing mode, thereby effectively improving the efficiency and flexibility of display data transmission. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0042] Figure 1 is a structural schematic diagram of a display device provided by an embodiment of the present application;

[0043] Figure 2 is a structural schematic diagram of a display driving circuit provided by an embodiment of the present application;

[0044] Figure 3 is a partial structural schematic diagram of a display driving circuit provided by an embodiment of the present application;

[0045] Figure 4 is a partial structural schematic diagram of another display driving circuit provided by an embodiment of the present application;

[0046] Figure 5 is a partial structural schematic diagram of still another display driving circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the present application more clear, the embodiments of the present application will be further described in detail with reference to the drawings.

[0048] Figure 1 is a structural schematic diagram of a display device provided by an embodiment of the present application, referring to Figure 1 , the display device comprises a processor 10 and a display module 20. The processor 10 is configured to transmit display data to the display module 20, so that the display module 20 displays an image.

[0049] As shown in Figure 1 The display module 20 can include a display driving circuit 21 and a display screen 22. The processor 10 has a plurality of data sending ports, which are used to connect with a plurality of data receiving ports of the display driving circuit 21 through a plurality of data channels, and are used to transmit display data to the display driving circuit 21. The display driving circuit 21 is used to drive the display screen 22 to display images based on the received display data.

[0050] Optionally, the display device can be a virtual reality (VR) device, a liquid crystal display device, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator or any product or component with display function.

[0051] The processor 10 in the display device can be a system on chip (SoC). Alternatively, the processor 10 can be a micro controller unit (MCU), a micro processor unit (MPU) or a CPU or other integrated circuits with signal processing function. The display driving circuit 21 can be a TDDIC.

[0052] In the display device, the processor 10 can be referred to as a host of the display device, and the display driving circuit 21 can be referred to as a slave or a peripheral device of the processor 10.

[0053] Optionally, the display data can be transmitted between the processor 10 and the display driving circuit 21 of the display module 20 through a MIPI-DSI protocol. In the MIPI-DSI protocol, when the plurality of data channels between the processor 10 and the display driving circuit 21 transmit data, two transmission modes can be included: a high-speed (HS) mode and a low-power (LP) mode.

[0054] For example, referring to Figure 1 The processor 10 and the display driving circuit 21 can include four data channels: Lane0, Lane1, Lane2 and Lane3. In the high-speed mode, the processor 10 can transmit high-speed data to the display driving circuit 21 through the four data channels, while the display driving circuit 21 cannot transmit high-speed data to the processor 10 through the four data channels. That is, the four data channels can be used for unidirectional high-speed transmission. The high-speed data can be high-speed display data.

[0055] In low-speed mode, only data channel Lane 0 among the four data channels can achieve bidirectional transmission of low-speed data. For example, in low-speed mode, processor 10 can transmit control parameters of display driver circuit 21 to display driver circuit 21 through data channel Lane 0. Alternatively, display driver circuit 21 can transmit its status information to processor 10 through data channel Lane 0. Furthermore, processor 10 can transmit screen-off data of display screen 22 to display driver circuit 21 through data channel Lane 0, so that display driver circuit 21 controls display screen 22 to turn off. This low-speed data can also be referred to as low-speed display data.

[0056] Among them, high-speed display data has a faster transmission rate (i.e., a higher signal frequency) and a lower voltage level (e.g., a voltage level of 200 millivolts), while low-speed display data has a slower transmission rate (i.e., a lower signal frequency) and a higher voltage level (e.g., a voltage level of 1.2 volts).

[0057] Figure 2 This is a schematic diagram of a display driving circuit provided in an embodiment of this application. The display driving circuit can be as follows: Figure 1 The display driver circuit 21 in the display device shown. (Reference) Figure 2 The display driving circuit 21 includes: an interface sub-circuit 210, multiple synchronization sub-circuits 220 corresponding one-to-one with multiple data receiving ports, a channel statistics sub-circuit 230, and a processing sub-circuit 240.

[0058] The display driver circuit 21 has multiple data receiving ports. These multiple data receiving ports are used to connect to multiple data transmitting ports of the processor 10 via multiple data channels. For example, refer to... Figure 2 The display driver circuit 21 may have four data receiving ports: RX0, RX1, RX2, and RX3. These four data receiving ports are connected to the four data transmitting ports of the processor 10 via four data channels: Lane0, Lane1, Lane2, and Lane3. The interface sub-circuit 210 is connected to the plurality of data receiving ports and the plurality of synchronization sub-circuits 220, respectively, and is used to output the display data received by the corresponding data receiving port and an enable signal to each of the synchronization sub-circuits 220.

[0059] If the display data received by a certain data receiving port is high-speed display data, the enable signal transmitted by the interface sub-circuit 210 to the corresponding synchronization sub-circuit 220 is a valid enable signal. If the display data received by a certain data receiving port is low-speed display data or the data receiving port does not receive display data, the enable signal transmitted by the interface sub-circuit 210 to the corresponding synchronization sub-circuit 220 is an invalid enable signal. The level of the valid enable signal can be a high level relative to the level of the invalid enable signal.

[0060] Each of the synchronization sub-circuits 220 is connected to the channel statistics sub-circuit 230 and the processing sub-circuit 240, and is configured to transmit the display data received thereby to the processing sub-circuit 240, and output a first indication signal to the channel statistics sub-circuit 230 if a valid enable signal is received. In addition, the synchronization sub-circuit 220 can output a second indication signal to the channel statistics sub-circuit 230 or output no indication signal to the channel statistics sub-circuit 230 if an invalid enable signal is received. The level of the first indication signal can be a high level relative to the level of the second indication signal.

[0061] The channel statistics sub-circuit 230 is connected to the processing sub-circuit 240, and is configured to count a first number of the first indication signals received thereby, and send the first number to the processing sub-circuit 240. The first number can be less than or equal to the total number of the plurality of data channels. For example, if the total number of data channels between the processor 10 and the display driving circuit 21 is 4, the value of the first number can be less than or equal to 4. The first number can also be referred to as the number of valid data channels.

[0062] The processing sub-circuit 240 is configured to perform parallel-serial conversion on the display data received thereby based on the first number. That is, the processing sub-circuit 240 can perform parallel-serial conversion on the first number of parallel display data. The parallel-serial converted display data can be used to drive the display screen 22 of the display module 20 to display an image.

[0063] It can be understood that when the processor 10 transmits display data to the display driving circuit 21 through the plurality of data channels, the processor 10 can only use part of the plurality of data channels to transmit display data. That is, only part of the plurality of data channels are valid data channels. Correspondingly, only part of the plurality of synchronization sub-circuits 220 in the display driving circuit 21 can receive the display data transmitted by the interface sub-circuit 210.

[0064] For example, as shown in FIG. 2, the display driving circuit 21 can include four synchronization sub-circuits 220, and the processor 10 can transmit display data to the display driving circuit 21 through four data channels. In this case, only two of the four data channels are valid data channels, and only two of the four synchronization sub-circuits 220 can receive the display data transmitted by the interface sub-circuit 210. Figure 2As shown, there can be four data lanes between the processor 10 and the display driving circuit 21, including Lane0, Lane1, Lane2, and Lane3. In the high-speed mode, all or only some of the data lanes (e.g., Lane0, Lane1, and Lane2) can receive high-speed display data transmitted by the processor 10. In the low-speed mode, only the data lane Lane0 can receive low-speed display data transmitted by the processor 10.

[0065] It can also be understood that at least one of the display data output by the processor 10 is transmitted in parallel to the display driving circuit 21, and the display screen 22 displays images based on the serial display data. Therefore, the processing sub-circuit 240 needs to perform parallel-to-serial conversion on the received at least one display data based on the number of valid data lanes, so as to convert the at least one parallel display data into serial display data. The parallel-to-serial conversion of the display data can also be referred to as fusion of the display data.

[0066] For example, if the first number predetermined by the processing sub-circuit 240 is 3, the processing sub-circuit 240 can only perform parallel-to-serial conversion on the received three parallel display data.

[0067] Optionally, the processing sub-circuit 240 can also be used to packetize and verify the serial display data after the parallel-to-serial conversion, and the packetized and verified display data can be used by the display screen 22 to display images. In addition, the processing sub-circuit 240 can also achieve timing control of the display data transmitted by the processor 10.

[0068] It can also be understood that when the processor 10 transmits display data to the display driving circuit 21 through at least one of the plurality of data lanes, the display driving circuit 21 is unaware of the number of valid data lanes selected by the processor 10. Accordingly, if the processing sub-circuit 240 in the display driving circuit 21 cannot determine the number of valid data lanes, or the number of valid data lanes predetermined by the processing sub-circuit 240 is inconsistent with the number of valid data lanes actually selected by the processor 10, the processing sub-circuit 240 may, after performing parallel-to-serial conversion on the at least one display data, obtain serial display data with data loss.

[0069] In the embodiments of the present application, the lane counting sub-circuit 230 can count the first number of valid data lanes and transmit the first number to the processing sub-circuit 240. Based on this, the processing sub-circuit 240 can perform parallel-to-serial conversion on the received display data based on the first number actually counted by the lane counting sub-circuit 230, so as to avoid the problem of data loss in the display data obtained by the processing sub-circuit 240 after the parallel-to-serial conversion.

[0070] And, since the first number is determined by the statistics sub-circuit 230 based on the number of display data with enable signals in at least one of the display data received by the interface sub-circuit 210, the first number is consistent with the number of valid data channels selected by the processor 10 in multiple data channels. Thus, the accuracy of the parallel-serial conversion of the display data by the processing sub-circuit 240 can be ensured.

[0071] In summary, the present application discloses a display driving circuit, if the interface sub-circuit of the display driving circuit receives high-speed display data through the data receiving port, it can transmit the valid enable signal to the corresponding synchronization sub-circuit. The synchronization sub-circuit can output the first indication signal based on the valid enable signal, so that the channel statistics sub-circuit can count the first number of the first indication signal received. The processing sub-circuit can further parallel-serial convert the display data transmitted by the synchronization sub-circuit based on the first number. Since the first number can reflect the number of data receiving ports receiving high-speed display data in multiple data receiving ports of the display driving circuit, i.e. the number of valid data channels, the number of valid data channels does not need to be configured by the developer through writing registers, thereby effectively improving the efficiency and flexibility of display data transmission.

[0072] Figure 3 is a partial structure schematic diagram of a display driving circuit provided by an embodiment of the present application. As shown in Figure 3 The display driving circuit 21 can also have a clock receiving port. The clock receiving port can include a high-speed clock receiving port C_HS_RX and a low-speed clock receiving port C_LP_RX. Both of the two clock receiving ports can be connected with the clock transmitting port of the processor 10 through a clock channel, and are used to receive the clock signal transmitted by the processor 10. The clock signal can be transmitted in the form of differential signal in the clock channel, Figure 3 The CP and CN in the clock channel are a pair of differential clock lines when the clock signal is transmitted in the clock channel.

[0073] Optionally, the multiple data receiving ports of the display driving circuit 21 can include one first data receiving port and three second data receiving ports. The first data receiving port can be used to receive the high-speed display data or low-speed display data transmitted by the corresponding one signal transmitting port. Each second data receiving port can be used to receive the high-speed display data transmitted by the corresponding one signal transmitting port.

[0074] Referring to Figure 2The processor 10 and the display driving circuit 21 of the display module 20 can include four data channels: Lane0, Lane1, Lane2, and Lane3. The data channel Lane0 can be connected to a first data receiving port of a plurality of data receiving ports. The data channels Lane1, Lane2, and Lane3 can be connected to a plurality of second data receiving ports, respectively.

[0075] In the embodiments of the present application, among the plurality of data channels between the processor 10 and the display driving circuit 21, only the data channel Lane0 can realize the transmission of high-speed display data and low-speed display data, and the remaining data channels can only transmit high-speed display data. Therefore, the first data receiving port can receive both high-speed display data and low-speed display data.

[0076] Correspondingly, as shown in Figure 3 the first data receiving port can include a high-speed data receiving port D_HS_RX and a low-speed data receiving port D_LP_RX. In the high-speed mode, the high-speed data receiving port D_HS_RX in the first data receiving port can receive high-speed display data transmitted by the data channel Lane0. In the low-speed mode, the low-speed data receiving port D_LP_RX in the first data receiving port can receive low-speed display data or low-power consumption signals transmitted by the data channel Lane0.

[0077] It can be understood that the high-speed data receiving port D_HS_RX in the first data receiving port can detect the data transmitted by the data channel Lane0 to determine whether the data is high-speed display data. If the data is high-speed display data, the high-speed data receiving port D_HS_RX can receive the high-speed display data and transmit the high-speed display data to the circuit connected thereto. If the data is low-speed display data or low-power consumption signals, the high-speed data receiving port D_HS_RX does not receive the low-speed display data or low-power consumption signals. Correspondingly, the low-speed display data or low-power consumption signals can be received by the low-speed data receiving port D_LP_RX in the first data receiving port.

[0078] Optionally, the high-speed data receiving port D_HS_RX can detect whether the data transmitted by the data channel Lane0 is high-speed display data based on the transmission rate of the data and the level value of the data.

[0079] The second data receiving port can also include a high-speed data receiving port D_HS_RX and a low-speed data receiving port D_LP_RX Figure 3The high-speed data receiving port D HS RX is capable of receiving high-speed display data in the high-speed mode. In the low-speed mode, the low-speed data receiving port D LP RX is only capable of receiving low-power consumption signals to make the circuit connected thereto enter a default low-power consumption state, i.e., a state of not transmitting display data.

[0080] In the embodiments of the present application, the display data is transmitted in the form of differential signals. For example, referring to Figure 3 , DP0 and DN0 can be a pair of differential signal lines for transmitting display data of a data channel Lane0. Alternatively, referring to Figure 3 , the high-speed data receiving port D HS RX and the high-speed clock receiving port C HS RX input end can also be provided with a resistor R T , which is used for realizing impedance matching of the high-speed display data and the high-speed clock signal. T

[0081] In the MIPI-DSI protocol, the plurality of data receiving ports and the clock receiving port can be referred to as an analog part in a physical layer of the MIPI-DSI protocol.

[0082] Alternatively, referring to Figure 3 , the interface sub-circuit 210 can include a control sub-circuit 211 and a plurality of high-speed transmission sub-circuits 212 connected to the plurality of data receiving ports one by one. Figure 3 Only one high-speed transmission sub-circuit corresponding to the high-speed data receiving port D HS RX in the first data receiving port is shown in the figure. The control sub-circuit 211 is connected to the clock receiving port of the display driving circuit 21 and each high-speed transmission sub-circuit 212, respectively. Each high-speed transmission sub-circuit 212 is also connected to a corresponding synchronization sub-circuit 220.

[0083] The control sub-circuit 211 is configured to transmit a control signal to each high-speed transmission sub-circuit based on the clock signal received by the clock receiving port. The high-speed transmission sub-circuit 212 is configured to, under the control of the control signal, if high-speed display data transmitted by the data receiving port is received, transmit the high-speed display data to the corresponding synchronization sub-circuit 220, transmit an active enable signal to the corresponding synchronization sub-circuit 220, and if low-speed display data is received by the data receiving port or no display data is received, transmit an inactive enable signal to the corresponding synchronization sub-circuit 220. The data received by each high-speed transmission sub-circuit 212 is high-speed display data received by the high-speed data receiving port D HS RX in the data receiving port corresponding to the high-speed transmission sub-circuit 212.

[0084] ​In the embodiment of the present application, when the processor 10 transmits the high-speed display data to the display driving circuit 21, the clock sending port of the processor 10 sends the high-speed clock signal to the clock receiving port of the display driving circuit 21 through the clock channel. The clock channel enters the high-speed mode. When the high-speed clock signal is transmitted to the display driving circuit 21, the high-speed clock receiving port C_HS_RX in the clock receiving port receives the high-speed clock signal. The control sub-circuit 211 can further receive the high-speed clock signal and transmit the control signal to the high-speed transmission sub-circuit 212.

[0085] After receiving the high-speed display data transmitted by the data receiving port, the high-speed transmission sub-circuit 212 can transmit the high-speed display data to the corresponding synchronization sub-circuit 220 and control the level of the enable signal of the display data to be the valid enable signal. If the high-speed transmission sub-circuit 212 does not receive the high-speed display data transmitted by the data receiving port, the enable signal can be controlled to be the invalid enable signal.

[0086] It can be understood that the plurality of data channels between the processor 10 and the display driving circuit 21 are in the low-power state by default when no high-speed display data is transmitted. The display data transmitted by the processor 10 to the display driving circuit 21 can include the low-power signal. The transmission rate and level of the low-power signal can be the same as those of the low-speed display data.

[0087] Reference Figure 3 The interface sub-circuit 210 can further include a channel control sub-circuit 213 and a low-power transmission sub-circuit 214. The channel control sub-circuit 213 is connected with the low-speed data receiving port D_LP_RX and the low-power transmission sub-circuit 214, respectively. The low-power transmission sub-circuit 214 is further connected with the input end of the synchronization sub-circuit 220, and the synchronization sub-circuit 220 is the synchronization sub-circuit 220 corresponding to the data channel Lane0.

[0088] The channel control sub-circuit 213 can be used to control the working state of the high-speed data receiving port D_HS_RX and the low-speed data receiving port D_HS_RX (for example, control the rate of receiving the display data by the data receiving port). In addition, the channel control sub-circuit 213 can further transmit the low-speed display data received by the low-speed data receiving port D_LP_RX to the low-power transmission sub-circuit 214. The low-power transmission sub-circuit 214 can further output the low-speed display data to the synchronization sub-circuit 220 connected therewith.

[0089] Based on the above analysis, for the data receiving port connected by the data channel Lane0, if the display data transmitted by the data channel Lane0 is high-speed display data, the high-speed display data will be transmitted to the high-speed transmission sub-circuit 212 through the high-speed data receiving port D HS RX. If the display data transmitted by the data channel Lane0 is low-speed display data, the high-speed display data will be transmitted to the low-power transmission sub-circuit 214 through the low-speed data receiving port D LP RX.

[0090] It can be understood that in the MIPI-DSI protocol, the interface sub-circuit 210 can be referred to as a digital part in the physical layer of the MIPI-DSI protocol.

[0091] Optionally, the high-speed display data can include a synchronization header and valid data. Each synchronization sub-circuit 220 can also be configured to, if the synchronization header in the display data is detected, transmit the valid data in the display data to the processing sub-circuit 240 and transmit a first indication signal to the channel statistics sub-circuit 230. The valid data in the high-speed display data is data for displaying an image by the display screen 22.

[0092] It can be understood that the plurality of data channels between the processor 10 and the display driving circuit 21 are in a low-speed state (also referred to as a low-power state) by default when transmitting low-speed display data or no display data is received. Correspondingly, the signal received by each synchronization sub-circuit 220 by default is a low-power signal. When the synchronization sub-circuit 220 receives the valid enable signal and the high-speed display data, the synchronization sub-circuit 220 can determine that the data channel corresponding to the synchronization sub-circuit 220 has entered a high-speed mode and that the data channel transmits high-speed display data. Therefore, the synchronization sub-circuit 220 can detect the display data received by the synchronization sub-circuit 220. If the synchronization sub-circuit 220 detects a synchronization header, it can be determined that the subsequent transmitted display data is valid data, and therefore the subsequent received data can be transmitted to the processing sub-circuit 240 as valid data and a first indication signal can be transmitted to the channel statistics sub-circuit 230.

[0093] In the embodiment of the present application, the synchronization header of the high-speed display data is located in the synchronization header sequence packet of the high-speed display data. The high-speed display data is transmitted in byte units, and thus the synchronization header sequence packet of the high-speed display data can include 8-bit binary numbers. In addition, the synchronization header sequence packets of the multi-channel high-speed display data transmitted by the plurality of data channels can be different, and the synchronization headers included in the plurality of synchronization header sequence packets are the same. The synchronization header included in the plurality of synchronization header sequence packets can be a 6-bit target sequence, for example, "011101". Correspondingly, during the detection of the synchronization packet of the high-speed display data, if the 6-bit sequence included in a byte is detected as the target sequence by the synchronization sub-circuit 220, it can be determined that the byte is the synchronization header sequence packet of the high-speed display data, and the target sequence is the synchronization header.

[0094] Optionally, as shown in Figure 4 each synchronization sub-circuit 220 can include a sampling sub-circuit 221 and an identification sub-circuit 222. The sampling sub-circuit 221 is connected to the interface sub-circuit 210 and the identification sub-circuit 222 respectively, and the identification sub-circuit 222 is connected to the channel statistics sub-circuit 230 and the processing sub-circuit 240 respectively.

[0095] The sampling sub-circuit 221 is configured to sample the received display data when the received enable signal is the valid enable signal, and transmit the sampling result to the identification sub-circuit 222. The identification sub-circuit 222 is configured to transmit the valid data in the display data to the processing sub-circuit 240 and transmit a first indication signal to the channel statistics sub-circuit 230 if the synchronization header in the display data is detected based on the sampling result.

[0096] In the embodiment of the present application, the sampling sub-circuit 221 in each synchronization sub-circuit 220 can determine that the data channel corresponding to the synchronization sub-circuit 220 enters the high-speed mode if the received enable signal is the valid enable signal. Based on this, the sampling sub-circuit 221 can sample the display data output by the interface sub-circuit 210 based on the clock signal received by the interface sub-circuit 210 and send the sampling result to the identification sub-circuit 222. The sampling sub-circuit 221 can sample at the rising edge and the falling edge of the clock signal.

[0097] The identification sub-circuit 222 can determine that the subsequent transmitted display data are all valid data if the synchronization header of the high-speed display data is detected based on the sampling result. Based on this, the identification sub-circuit 222 can transmit the subsequent received data to the processing sub-circuit 240 as valid data.

[0098] Optionally, the high-speed display data can further include a packet tail. The packet tail is used to indicate that the valid data in the high-speed display data has been transmitted completely. The identification sub-circuit 222 is further configured to stop transmitting the display data to the processing sub-circuit 240 and stop transmitting the first indication signal to the channel statistics sub-circuit 230 if it is detected, based on the sampling result, that the packet tail in the display data.

[0099] It can be understood that the valid data in the high-speed display data is located between the synchronization header and the packet tail during the transmission. Therefore, the identification sub-circuit 222 can determine that the valid data in the high-speed display data has been transmitted completely if it detects the packet tail. Based on this, the identification sub-circuit 222 can stop transmitting the first indication signal to the channel statistics sub-circuit 230.

[0100] In this embodiment of this application, the packet tail is the level value (for example, can be “0” or “1”) of the last bit of the valid data in the high-speed display data after being inverted. In addition, the packet tail has a certain length. Therefore, when the identification sub-circuit 222 continuously detects the data of a certain fixed level, it can be determined that the data is the packet tail of the high-speed display data.

[0101] Optionally, for each sampling sub-circuit 221 in each synchronization sub-circuit 220, the sampling sub-circuit can further perform data synchronization on the received display data based on the clock signal transmitted by the interface sub-circuit after receiving the display data. In this way, at least one piece of display data transmitted in parallel can be transmitted synchronously.

[0102] Figure 5 FIG. 18 is a partial structural schematic diagram of another display driving circuit provided by an embodiment of this application. As shown in FIG. 18, the channel statistics sub-circuit 230 can include an adder 231. The adder 231 is configured to sum the received first indication signals and send the summed first quantity to the processing sub-circuit 240. Figure 5

[0103] In this embodiment of this application, the adder 231 can have multiple input ends, and each input end can be connected with the output end of one synchronization sub-circuit 220. The adder 231 can sum the first indication signals received by at least one of the multiple input ends. The first quantity of the first indication signals received by the adder 231 is the quantity of the data channels (i.e., the quantity of the valid data channels) in which the high-speed display data is transmitted among the multiple data channels between the processor 10 and the display driving circuit 21. After obtaining the sum result, the adder 231 can transmit the sum result to the processing sub-circuit 240.

[0104] ​Based on the foregoing analysis, in the plurality of data channels between the processor 10 and the display driving circuit 21, only part of the data channels can transmit high-speed display data, and thus only part of the plurality of synchronization sub-circuits 220 outputs the first indication signal to the adder 231. The rest of the synchronization sub-circuits 220 can output the second indication signal to the adder, or stop outputting the signal to the adder 231. The level of the first indication signal can be high relative to the level of the second indication signal. Based on this, for the signals received by the plurality of input terminals of the adder 231, the adder 231 can only sum the signals with the level of the first indication signal, and send the first quantity obtained by the summation to the processing sub-circuit 240. Thus, the processing sub-circuit 240 can parallel-serial convert the valid data in the at least one high-speed display data based on the first quantity.

[0105] Optionally, as shown in FIG. 2, the display driving circuit 21 can further include a register 250. The channel statistics sub-circuit 230 can further include a data selector (multiplexer, MUX) 232. The register 250 is connected to the control terminal C and the first input terminal IN1 of the data selector 232, respectively. The second input terminal IN2 of the data selector 232 is connected to the output terminal O1 of the adder 231, and the output terminal O2 of the data selector 232 is connected to the processing sub-circuit 240. Figure 5

[0106] The register 250 is configured to transmit a selection signal to the control terminal C of the data selector 232, and transmit the second quantity of the valid data channel to the first input terminal IN1. The data selector 232 is configured to transmit the second quantity received by the first input terminal IN1 to the processing sub-circuit 240 if the selection signal is a first selection signal, and transmit the first quantity received by the second input terminal IN2 to the processing sub-circuit 240 if the selection signal is a second selection signal. The level of the first selection signal can be high relative to the level of the second selection signal.

[0107] In the embodiment of the present application, the register 250 transmits the second quantity of the valid data channel to the first input terminal IN1 of the data selector 232, which can be written by the developer in advance. The register 250 can output the first selection signal or the second selection signal to the data selector 232 based on the transmission requirement set in advance.

[0108] The first selection signal is configured to instruct the data selector 232 to transmit the second quantity received by the first input terminal IN1 to the processing sub-circuit 240. In the implementation manner, the processing sub-circuit 240 can parallel-serial convert the received valid data based on the quantity of the valid data channel configured in the register 250. The first selection signal is configured to instruct the data selector 232 to transmit the second quantity received by the first input terminal IN1 to the processing sub-circuit 240. In the implementation manner, the processing sub-circuit 240 can parallel-serial convert the received valid data based on the quantity of the valid data channel configured in the register 250.

[0109] The second selection signal is used to instruct the data selector 232 to transmit the first number received by the second input IN2 of the data selector 232 to the processing sub-circuit 240. In this implementation, the processing sub-circuit 240 can parallel-serial convert the received valid data based on the first number (i.e. the number of actually counted valid data lanes) counted by the adder 231 in the lane counting sub-circuit 230.

[0110] Based on the above analysis, the processing sub-circuit 240 can process the valid data in the received high-speed display data based on the pre-determined second number, or based on the first number actually counted by the adder 231 in the lane counting sub-circuit 230. Thus, the flexibility of the processing sub-circuit 240 in processing the high-speed display data is effectively improved.

[0111] Optionally, the display driving circuit 21 can further be provided with a pad. The pad can be connected to the processor 10 as a pin or control terminal of the display driving circuit 21. The control terminal C of the data selector 232 can also be connected to the pad. The control terminal C can transmit the second number received by the first input IN1 of the data selector 232 or the first number received by the second input IN2 of the data selector 232 based on the level of the pad.

[0112] For example, when the level of the pad is a first level, the data selector 232 can select the second number received by the first input IN1 of the data selector 232 for output. When the level of the pad is a second level, the data selector 232 can select the first number received by the second input IN2 of the data selector 232 for output. Optionally, the first level can be a high level relative to the second level.

[0113] It can be understood that when the processor 10 selects at least one valid data lane from the plurality of data lanes, the processor 10 starts from the data lane with the smallest number (e.g. Lane0) and selects in the order of the numbers of the plurality of data lanes from small to large. That is, the valid data lane selected by the processor 10 at least includes the data lane Lane0. For example, if the plurality of data lanes include four data lanes: Lane0, Lane1, Lane2 and Lane3. When the processor 10 needs to select one data lane from the four data lanes as a valid data lane, the processor 10 can select the data lane Lane0. When the processor 10 needs to select two data lanes as valid data lanes, the processor 10 can select the data lanes Lane0 and Lane1. When the processor 10 needs to select three data lanes as valid data lanes, the processor 10 can select the data lanes Lane0, Lane1 and Lane2.

[0114] And, the processor 10 also assigns the display data according to the number of the data channels when assigning the display data to the selected multiple data channels for parallel transmission.

[0115] Therefore, the processing sub-circuit 240 can directly determine the number of the valid data channels after determining the number of the valid data channels, and determine the arrangement order of the at least one valid data when performing parallel-serial conversion on the at least one valid data.

[0116] In summary, the display driving circuit provided by the embodiments of the present application can transmit the valid enable signal to the corresponding synchronization sub-circuit if the interface sub-circuit receives the high-speed display data through the data receiving port. The synchronization sub-circuit can output the first indication signal based on the valid enable signal, so that the channel counting sub-circuit counts the first number of the received first indication signals. The processing sub-circuit can further perform parallel-serial conversion on the display data transmitted by the synchronization sub-circuit based on the first number. Since the first number can reflect the number of the data receiving ports (i.e., the number of the valid data channels) of the display driving circuit that receive the high-speed display data, the number of the valid data channels does not need to be configured by the developer through writing the register, thereby effectively improving the efficiency and flexibility of the display data transmission.

[0117] It can be understood that the term "at least one" in the present application refers to one or more, and the term "multiple" refers to two or more.

[0118] In the present application, "and / or" means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. The character " / " generally represents an "or" relationship between the objects before and after it.

[0119] In the present application, the terms "first", "second", and the like are used to distinguish the same items or similar items with basically the same function and action, and it should be understood that there is no logical or time sequence relationship between "first", "second", and "nth", and the number and execution order are not limited.

[0120] The above only describes exemplary embodiments of the present application, and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A display drive circuit, characterized by comprising: The display driving circuit has a plurality of data receiving ports for connecting with a plurality of data sending ports of a processor through a plurality of data channels; the display driving circuit comprises an interface sub-circuit, a plurality of synchronization sub-circuits corresponding to the plurality of data receiving ports, a channel statistics sub-circuit and a processing sub-circuit; The interface sub-circuit is connected with the plurality of data receiving ports and the plurality of synchronization sub-circuits respectively, and is configured to output display data received by each data receiving port and an enable signal to each synchronization sub-circuit in the plurality of synchronization sub-circuits; if the display data is high-speed display data, the enable signal is a valid enable signal, and if the display data is low-speed display data or no display data is received by the data receiving port, the enable signal is an invalid enable signal; Each synchronization sub-circuit in the plurality of synchronization sub-circuits is connected with the channel statistics sub-circuit and the processing sub-circuit respectively, and is configured to transmit the display data received thereby to the processing sub-circuit, and output a first indication signal to the channel statistics sub-circuit if the valid enable signal is received; The channel statistics sub-circuit is connected with the processing sub-circuit, and is configured to count a first number of the first indication signals received, and send the first number to the processing sub-circuit; The processing sub-circuit is configured to select display data transmitted by the first number of data channels in the plurality of data channels in ascending order of the numbers of the plurality of data channels, starting from the data channel with the smallest number.

2. The display driving circuit according to claim 1, wherein The channel statistics sub-circuit comprises an adder; The adder is configured to sum the first indication signals received, and send the first number obtained by the summing to the processing sub-circuit.

3. The display driving circuit according to claim 2, wherein The display driving circuit further comprises a register, and the channel statistics sub-circuit further comprises a data selector; The register is connected with a control end and a first input end of the data selector respectively, and is configured to transmit a selection signal to the control end, and transmit a second number of valid data channels to the first input end; A second input end of the data selector is connected with an output end of the adder, an output end of the data selector is connected with the processing sub-circuit, and the data selector is configured to transmit the second number received by the first input end to the processing sub-circuit if the selection signal is a first selection signal, and transmit the first number received by the second input end to the processing sub-circuit if the selection signal is a second selection signal; The processing sub-circuit is further configured to perform parallel-serial conversion on the display data received based on the second number.

4. The display driving circuit according to any one of claims 1 to 3, wherein The display data comprises a synchronization header and valid data; the synchronization sub-circuit is configured to: If the synchronization header in the display data is detected, the valid data in the display data is transmitted to the processing sub-circuit.

5. The display driving circuit according to claim 4, wherein Each synchronization sub-circuit comprises a sampling sub-circuit and an identification sub-circuit; The sampling sub-circuit is connected with the interface sub-circuit and the identification sub-circuit respectively, and is configured to sample the received display data when the received enable signal is the valid enable signal, and transmit the sampling result to the identification sub-circuit. The identification sub-circuit is connected with the channel statistics sub-circuit and the processing sub-circuit respectively, and is configured to transmit valid data in the display data to the processing sub-circuit and transmit a first indication signal to the channel statistics sub-circuit if a synchronization header in the display data is detected based on the sampling result.

6. The display driving circuit according to claim 5, wherein The display driving circuit further has a clock receiving port, which is configured to be connected with a clock sending port of the processor through a clock channel. The interface sub-circuit is further connected with the clock receiving port, and is further configured to receive a clock signal sent by the clock sending port through the clock receiving port, and transmit the clock signal to each sampling sub-circuit respectively. The plurality of sampling sub-circuits are further configured to perform data synchronization on the received display data based on the clock signal.

7. The display driving circuit according to claim 5, wherein The display data further comprises a packet tail. The identification sub-circuit is further configured to stop transmitting display data to the processing sub-circuit and stop transmitting the first indication signal to the channel statistics sub-circuit if a packet tail in the display data is detected based on the sampling result.

8. The display driving circuit according to any one of claims 1 to 3, wherein The plurality of data receiving ports comprise one first data receiving port and three second data receiving ports. The first data receiving port is configured to receive high-speed display data or low-speed display data sent by a corresponding one signal sending port. Each second data receiving port is configured to receive high-speed display data sent by a corresponding one signal sending port.

9. The display driving circuit according to any one of claims 1 to 3, wherein The interface sub-circuit comprises a control sub-circuit and a high-speed transmission sub-circuit connected with the plurality of data receiving ports one by one. The control sub-circuit is connected with the clock receiving port of the display driving circuit and each high-speed transmission sub-circuit respectively, and is configured to transmit a control signal to each high-speed transmission sub-circuit based on a clock signal received by the clock receiving port. Each high-speed transmission sub-circuit is further connected with a corresponding one synchronization sub-circuit, and is configured to transmit high-speed display data received by the data receiving port to the corresponding one synchronization sub-circuit and transmit a valid enable signal to the corresponding one synchronization sub-circuit under the control of the control signal, and transmit an invalid enable signal to the corresponding one synchronization sub-circuit when the display data received by the data receiving port is low-speed display data or no display data is received.

10. A display module, characterized by The display module comprises the display driving circuit and a display screen. The display driving circuit is configured to drive the display screen to display an image based on the received display data.

11. A display device, characterized by comprising: The display device comprises a processor and the display module. The processor has a plurality of data transmission ports connected with a plurality of data receiving ports of a display driving circuit in the display module through a plurality of data channels, and is configured to transmit display data to the display driving circuit.

12. The display device of claim 11, wherein, The display data is transmitted between the processor and the display driving circuit in the display module through a display serial interface (DSI) protocol defined by a Mobile Industry Processor Interface (MIPI) alliance.

13. The display device according to claim 11 or 12, characterized in that, The processor is a central processing unit (CPU), and the display driving circuit is a display driving integrated circuit (TDDIC).

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