SOC chip performance test device, method and equipment and readable storage medium

Abstract

The invention relates to an SOC chip performance test device, method and equipment and a readable storage medium. In the device, an upper computer is used for sending an excitation instruction to a voltage simulator and sending a test instruction to a signal generator according to a test requirement; the voltage simulator is used for inputting a voltage excitation signal to the test board according to the excitation instruction; the signal generator is used for inputting a test signal to the test board according to the test instruction; the test board is used for conditioning the voltage excitation signal and the test signal and sending a first conditioning signal to the SOC chip to be tested so as to indicate the SOC chip to be tested to respond to the first conditioning signal; the test board is also used for acquiring a response signal returned by the SOC chip to be tested, conditioning the response signal, and returning a second conditioning signal to the upper computer; and the upper computer is also used for analyzing the second conditioning signal to obtain a performance test result. The SOC chip performance test efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of SOC chip testing, in particular to a SOC chip performance testing device, method, equipment and readable storage medium. BACKGROUND

[0002] As a core component of modern electronic devices, a system on a chip (SOC) integrates multiple functional modules such as processors, memories, input / output interfaces, etc. on a single chip, and has the advantages of high integration, low power consumption and high performance. Its application fields cover smart phones, tablet computers, smart cars, industrial control and many other industries. With the rapid development of emerging technology fields such as the Internet of Things and artificial intelligence, the functionality of SOC chips is continuously enhanced, the integration level is continuously improved, and the application field is continuously expanded. The performance reliability testing requirements for SOC chips are more stringent, and the complexity of performance testing is greatly increased.

[0003] Traditional SOC chip performance testing methods focus on evaluating single-dimensional indicators or factors. However, a SOC chip is a complex system, and its performance is affected by multiple factors. Focusing on a single performance and factor cannot comprehensively and accurately evaluate the actual performance of the chip. Therefore, multiple test items need to be performed sequentially, the test process is tedious, time-consuming, and increases the product development cycle and cost, resulting in low testing efficiency. SUMMARY

[0004] Therefore, it is necessary to provide a SOC chip performance testing device, method, equipment and readable storage medium to improve the SOC chip performance testing efficiency.

[0005] In a first aspect, the present application provides a SOC chip performance testing device, which comprises a test board, a host computer, a voltage simulator, a signal generator, a signal monitor and a to-be-tested SOC chip. The test board is connected with the host computer, the voltage simulator, the signal generator and the signal monitor. The host computer is connected with the voltage simulator and the signal generator.

[0006] The host computer is configured to send an excitation instruction to the voltage simulator and a test instruction to the signal generator according to a test requirement.

[0007] The voltage simulator is configured to input a voltage excitation signal to the test board according to the excitation instruction.

[0008] The signal generator is configured to input a test signal to the test board according to the test instruction.

[0009] The test board is configured to condition the voltage excitation signal and the test signal, and send a first conditioned signal to the SOC chip to be tested, so that the SOC chip to be tested responds to the first conditioned signal;

[0010] The test board is further configured to obtain a response signal returned by the SOC chip to be tested, condition the response signal, and return a second conditioned signal to the host computer;

[0011] The host computer is further configured to analyze the second conditioned signal to obtain a performance test result of the SOC chip to be tested.

[0012] In some embodiments, the test board comprises an interface layer, a processing layer, and a functional layer. The interface layer comprises a multi-protocol serial interface chip configured to receive the voltage excitation signal and the test signal, and perform protocol conversion on the voltage excitation signal and the test signal, respectively. The processing layer comprises a clock circuit configured to perform clock synchronization on the voltage excitation signal after protocol conversion and the test signal after protocol conversion. The functional layer comprises a gain amplifier configured to perform gain amplification on the voltage excitation signal after clock synchronization and the test signal after clock synchronization, respectively, to obtain the first conditioned signal.

[0013] In some embodiments, the functional layer is further configured to receive a response signal returned by the SOC chip to be tested, perform gain amplification on the response signal to obtain the second conditioned signal. The processing layer and the interface layer are further configured to forward the second conditioned signal to the host computer.

[0014] In some embodiments, the device further comprises a test seat. The test seat comprises a base, and the base comprises a first pin channel and a second pin channel. The test seat is connected to the test board through the first pin channel and connected to the SOC chip to be tested through the second pin channel.

[0015] In some embodiments, the test seat further comprises a cover seat, and the base and the cover seat together form a cavity in the middle. The SOC chip to be tested is exposed in the cavity.

[0016] In some embodiments, the device further comprises a temperature controller connected to the host computer. The cover seat is internally provided with a heater, a cooler, and a temperature sensor. The heater, the cooler, and the temperature sensor are connected to the temperature controller. The temperature controller is configured to control the heater, the cooler, and the temperature sensor according to an environmental temperature excitation parameter sent by the host computer.

[0017] In some embodiments, the host computer is further configured to determine a reference test result according to a test instruction, and analyze the second conditioned signal according to the reference test result to obtain the performance test result of the SOC chip to be tested.

[0018] In a second aspect, the present application further provides a SOC chip performance test method applied to the SOC chip performance test device of the first aspect. The method comprises:

[0019] According to the test requirement, the excitation instruction is sent to the voltage simulator, and the test instruction is sent to the signal generator; the excitation instruction is used to instruct the voltage simulator to input the voltage excitation signal to the test board according to the excitation instruction; the test instruction is used to instruct the signal generator to input the test signal to the test board according to the test instruction; the voltage excitation signal and the test signal are used to instruct the test board to condition the voltage excitation signal and the test signal, and send the first conditioned signal to the to-be-tested SOC chip, so as to instruct the to-be-tested SOC chip to respond to the first conditioned signal; the response signal of the to-be-tested SOC chip is used to instruct the test board to condition the response signal.

[0020] The second conditioned signal returned by the test board is analyzed to obtain the performance test result of the to-be-tested SOC chip.

[0021] In a third aspect, the present application further provides a computer device, comprising a memory and a processor, the memory stores a computer program, and the processor realizes the following steps when executing the computer program:

[0022] According to the test requirement, the excitation instruction is sent to the voltage simulator, and the test instruction is sent to the signal generator; the excitation instruction is used to instruct the voltage simulator to input the voltage excitation signal to the test board according to the excitation instruction; the test instruction is used to instruct the signal generator to input the test signal to the test board according to the test instruction; the voltage excitation signal and the test signal are used to instruct the test board to condition the voltage excitation signal and the test signal, and send the first conditioned signal to the to-be-tested SOC chip, so as to instruct the to-be-tested SOC chip to respond to the first conditioned signal; the response signal of the to-be-tested SOC chip is used to instruct the test board to condition the response signal.

[0023] The second conditioned signal returned by the test board is analyzed to obtain the performance test result of the to-be-tested SOC chip.

[0024] In a fourth aspect, the present application further provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to realize the following steps:

[0025] According to the test requirement, the excitation instruction is sent to the voltage simulator, and the test instruction is sent to the signal generator; the excitation instruction is used to instruct the voltage simulator to input the voltage excitation signal to the test board according to the excitation instruction; the test instruction is used to instruct the signal generator to input the test signal to the test board according to the test instruction; the voltage excitation signal and the test signal are used to instruct the test board to condition the voltage excitation signal and the test signal, and send the first conditioned signal to the to-be-tested SOC chip, so as to instruct the to-be-tested SOC chip to respond to the first conditioned signal; the response signal of the to-be-tested SOC chip is used to instruct the test board to condition the response signal.

[0026] The second conditioning signal returned by the test board is analyzed to obtain the performance test result of the SOC chip under test.

[0027] In a fifth aspect, the present application also provides a computer program product comprising a computer program which, when executed by a processor, implements the following steps:

[0028] According to the test requirement, the excitation instruction is sent to the voltage simulator, and the test instruction is sent to the signal generator; the excitation instruction is used to instruct the voltage simulator to input the voltage excitation signal to the test board according to the excitation instruction; the test instruction is used to instruct the signal generator to input the test signal to the test board according to the test instruction; the voltage excitation signal and the test signal are used to instruct the test board to condition the voltage excitation signal and the test signal, and send the first conditioning signal to the SOC chip under test, so as to instruct the SOC chip under test to respond to the first conditioning signal; and the response signal of the SOC chip under test is used to instruct the test board to condition the response signal.

[0029] The second conditioning signal returned by the test board is analyzed to obtain the performance test result of the SOC chip under test.

[0030] The SOC chip performance test device, method, computer device, computer readable storage medium and computer program product described above, the test board provides an input interface of the voltage excitation signal and the test signal, through the cooperation of the voltage simulator and the signal generator, the voltage excitation signal and the test signal can be input to the SOC chip under test at the same time, the voltage simulator can simulate different power supply voltage conditions, the signal generator can generate diversified test signals, which can cover the diversified power supply environment of the SOC chip under test in actual application and the interactive scene of the external test signal, adapt to the complex test requirement of the SOC chip under test; the test board can condition the input signal, ensure that the output signal is more consistent with the actual running state; the test board also provides a receiving interface of the response signal of the SOC chip under test, so that the response signal can be fed back to the host computer through the test board, and the response signal is analyzed by the host computer, which is beneficial to obtain the accurate performance test result of the SOC chip under test; such a device through centralized control of the host computer, automatic conditioning of the test board and cooperation of the voltage excitation signal and the test signal is beneficial to simplify the performance test process of the SOC chip under test and improve the performance test efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings needed to be used in the description of the embodiments of the present application or the related art. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other related drawings without creative labor based on these drawings.

[0032] Figure 1 Fig. 1 is a structural block diagram of a SOC chip performance testing device in an embodiment;

[0033] Figure 2 Fig. 2 is a structural block diagram of a test board in an embodiment;

[0034] Figure 3 Fig. 3 is a flowchart of a SOC chip performance testing method in an embodiment;

[0035] Figure 4 Fig. 4 is an internal structural diagram of a computer device in an embodiment. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not to limit the present application.

[0037] It should be noted that the terms "first", "second" and the like used in the present application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "include" and "have" and any variations thereof used in the present application are intended to cover non-exclusive inclusion. The term "multiple" used in the present application refers to two or more. The term "and / or" used in the present application refers to one of the options or any combination of multiple options.

[0038] The SOC chip performance testing device provided by the embodiments of the present application can be applied in an application environment as shown in Fig. 1. In the application environment, the SOC chip performance testing device includes a test board 101, a host computer 102, a voltage simulator 103, a signal generator 104, a signal monitor 105 and a to-be-tested SOC chip 106. The test board 101 is connected with the host computer 102, the voltage simulator 103, the signal generator 104 and the signal monitor 105 respectively. The host computer 102 is connected with the voltage simulator 103 and the signal generator 104 respectively. Figure 1

[0039] The host computer 102 is configured to send an excitation instruction to the voltage simulator 103 and a test instruction to the signal generator 104 according to a test requirement.

[0040] The voltage simulator 103 is configured to input a voltage excitation signal to the test board 101 according to the excitation instruction.

[0041] The signal generator 104 is configured to input a test signal to the test board 101 according to the test instruction.

[0042] ​The test board 101 is configured to condition the voltage excitation signal and the test signal, and send a first conditioned signal to the SOC chip 106 to be tested, so that the SOC chip 106 to be tested responds to the first conditioned signal.

[0043] The test board 101 is further configured to acquire a response signal returned by the SOC chip 106 to be tested, condition the response signal, and return a second conditioned signal to the host computer 102.

[0044] The host computer 102 is further configured to analyze the second conditioned signal, and obtain a performance test result of the SOC chip 106 to be tested.

[0045] The host computer 102 refers to a computer or a special-purpose device with control and analysis functions, as the core of the test system, can issue instructions to the voltage simulator 103 and the signal generator 104, receive the conditioned signals fed back by the test board 101, and analyze the signal data through the built-in algorithm, and finally generate the performance test result of the SOC chip 106 to be tested. The host computer 102 can be a terminal or a server. The terminal can be, but is not limited to, various personal computers, notebook computers, tablet computers. The server can be a standalone physical server, a server cluster or a distributed system composed of multiple physical servers, or a cloud server providing cloud computing services.

[0046] The SOC chip 106 to be tested refers to an SOC chip that needs to be tested for performance. In different application fields, the SOC chip 106 to be tested has different functions.

[0047] The voltage simulator 103 refers to a device that can output different voltage signals according to control instructions, and can simulate the power supply environment that the SOC chip 106 to be tested may face in actual application, such as voltage fluctuation, high and low voltage anomaly, stable voltage, etc., to provide diversified power excitation for the SOC chip 106 to be tested.

[0048] The signal generator 104 refers to a device that can generate electrical signals with specific frequency, amplitude and waveform, which is used to simulate the external input signals (such as sensor data, communication instructions, etc.) received by the SOC chip 106 to be tested in actual application. The test signal that can be generated by the signal generator 104 includes but is not limited to numerical signal, pulse signal, video signal and audio signal, etc.

[0049] In some embodiments, the voltage simulator 103 generates a voltage excitation signal according to the excitation instruction sent by the host computer 102 and sends it to the test board 101 in the case of receiving the excitation instruction sent by the host computer 102. For example, the voltage simulator 103 generates a 0.1V voltage signal every 1s and outputs it to the test board 101, simulating the battery transient. The signal generator 104 generates a test signal according to the test instruction sent by the host computer 102 and sends it to the test board 101 in the case of receiving the test instruction sent by the host computer 102. The voltage excitation signal and the test signal can be output alternately or together according to the test requirements.

[0050] The signal monitor 105 refers to a device for monitoring various electrical signals in real time during the test process, which can capture the dynamic changes of the signals and provide raw data support for evaluating the performance of the chip and troubleshooting test abnormalities. For example, the signal generator 104 generates a test pulse waveform, which is provided to the SOC chip 106 under test through the test board 101. Under normal circumstances, the signal monitor 105 displays the same waveform, and under fault conditions of the SOC chip 106 under test, the signal monitor 105 displays an error waveform.

[0051] The test board 101 is an intermediate carrier connecting various devices, responsible for conditioning the input signals (including voltage excitation signals and test signals) (such as signal pre-emphasis, signal equalization, signal distribution, etc.), transmitting the adapted signals to the SOC chip 106 under test; at the same time, collecting the response signals of the SOC chip 106 under test, and feeding back to the host computer 102 after conditioning, playing a bridge role of signal adaptation and transmission.

[0052] The first conditioned signal refers to the signal obtained by conditioning the voltage excitation signal output by the voltage simulator 103 and the test signal output by the signal generator 104 by the test board 101, which is adapted to the input requirements of the SOC chip 106 under test and directly input to the chip to trigger its response. The response signal refers to the feedback signal generated by the SOC chip 106 under test after receiving the first conditioned signal after internal processing (such as operation, data conversion, interface output, etc.), reflecting the processing result of the input signal by the SOC chip 106 under test. The second conditioned signal refers to the signal obtained by conditioning the response signal returned by the SOC chip 106 under test by the test board 101 (such as amplifying weak signals, suppressing noise, format conversion, etc.), which is convenient for the host computer 102 to collect and analyze.

[0053] The performance test result is the conclusion about the performance indicators (such as computing power, communication rate, stability, power consumption, etc.) of the SOC chip 106 under test under specific test conditions obtained by the host computer 102 after analyzing the second conditioned signal (such as calculating the response time, error rate, power consumption value, etc.).

[0054] The SOC chip performance test device, the test board provides the input interface of the voltage excitation signal and the test signal, through the cooperation of the voltage simulator and the signal generator, the voltage excitation signal and the test signal can be input to the SOC chip to be tested at the same time, the voltage simulator can simulate different power supply voltage working conditions, the signal generator can generate diversified test signals, which can cover the diversified power supply environment of the SOC chip to be tested in actual application and the interaction scene of external test signals, adapt to the complex test requirements of the SOC chip to be tested; the test board can process the input signal to ensure that the output signal is more consistent with the actual running state; the test board also provides a receiving interface for the response signal of the SOC chip to be tested, so that the response signal can be fed back to the upper computer through the test board, and the response signal is analyzed by the upper computer, which is helpful to obtain accurate performance test results of the SOC chip to be tested; such a device controlled by the upper computer, automatically processed by the test board, and cooperated by the voltage excitation signal and the test signal is helpful to simplify the performance test process of the SOC chip to be tested and improve the performance test efficiency.

[0055] In one exemplary embodiment, as shown in Figure 2 The test board 101 includes an interface layer 1011, a processing layer 1012, and a functional layer 1013. The interface layer 1011 includes a multi-protocol serial interface chip for receiving voltage excitation signals and test signals and performing protocol conversion on the voltage excitation signals and test signals respectively. The processing layer 1012 includes a clock circuit for clock synchronization of the protocol-converted voltage excitation signals and protocol-converted test signals. The functional layer 1013 includes a gain amplifier for gain amplification of the clock-synchronized voltage excitation signals and clock-synchronized test signals respectively to obtain first processed signals.

[0056] The test board 101 is an intermediate carrier connecting various devices and includes an interface layer 1011, a processing layer 1012, and a functional layer 1013. The interface layer 1011 is the signal access and protocol conversion core layer of the test board 101 and is built-in with a multi-protocol serial interface chip, which is the core component of the interface layer 1011 and has the ability to support multiple serial communication protocol conversion, such as SPI, UART, I2C, CAN, USB, etc. It can complete the protocol conversion of the signals according to the protocol type of the input signals and the interface protocol requirements of the SOC chip to be tested 106, while ensuring the data integrity and transmission stability of the signals in the conversion process. The main function of the interface layer 1011 is to receive voltage excitation signals from the voltage simulator 103 and test signals from the signal generator 104, and to perform protocol conversion on the received voltage excitation signals and test signals respectively according to the interface protocol standard of the SOC chip to be tested 106, to ensure the compatibility of the signal protocol with the chip interface and to lay the foundation for subsequent signal processing.

[0057] The processing layer 1012 is a level in the test board 101 responsible for signal timing calibration, the core component is a clock circuit, and the main function is to receive the protocol-converted voltage excitation signal and the protocol-converted test signal sent by the interface layer 1011, and to perform clock synchronization processing on the two types of signals through the clock circuit, compensate for the clock offset caused by PCB wiring, and ensure that the signal timing matches the working clock of the to-be-tested SOC chip 106. In some embodiments, the clock circuit uses a high-performance phase-locked loop and a clock generator chip, uses a differential clock line to reduce jitter, and realizes clock delay compensation through measurement feedback.

[0058] The functional layer 1013 is a level in the test board 101 responsible for signal amplitude adjustment, the core component is a gain amplifier, and the main function is to receive the clock-synchronized voltage excitation signal and the clock-synchronized test signal sent by the processing layer 1012, and to perform gain amplification (or gain attenuation if the signal amplitude is too high) on the two types of signals through the gain amplifier according to the requirements of the to-be-tested SOC chip 106 for the input signal amplitude, so that the gain-processed signal amplitude reaches the optimal input range of the to-be-tested SOC chip 106, and ensures that the to-be-tested SOC chip 106 can stably receive and respond to the signal.

[0059] In some embodiments, the interface layer 1011 also includes Ethernet PHY and MAC chips, USB 3.0 Hub and controllers, etc., for realizing standardized access and data format unification of various interface protocols. Specifically, the functions of the interface layer 1011 can be decomposed into control instruction transmission: transmission of test procedures, configuration parameters, start / stop instructions, etc.; data transmission: transmission of test results, waveform data, characteristic parameters, etc.; protocol conversion: conversion of protocols of different external devices into a unified internal data format; error detection: CRC check on the interface to ensure accurate instructions. The specific implementation methods include: using TCP protocol to ensure reliable transmission of control instructions; using UDP protocol for high-speed transmission of real-time waveform data; using USB 3.0 Hub chip to expand multiple downstream ports; each port has independent overcurrent protection; using a multi-protocol serial interface chip to realize baud rate adaptation; built-in first-in-first-out buffer area to reduce data loss.

[0060] In some embodiments, the processing layer 1012 further includes an FPGA chip, a DDR4 cache, etc., for implementing scheduling of test procedures, decision of signal routing, real-time conditioning and acquisition of data, etc. Among them, the functions of the FPGA chip include dynamic signal routing: realizing one-to-one, one-to-many, many-to-one, etc. mode of test signals and detection signals; module working timing coordination: analyzing and executing complex test sequences; clock management and synchronization: providing a unified time reference for the whole board to ensure strict synchronization of multi-channel acquisition. The specific implementation methods include: embedding Grossbar Switch architecture in FPGA to realize signal routing; using hardware description language to realize protocol state machine to realize working timing coordination; using global clock network and delay-locked loop of FPGA to realize clock management.

[0061] Among them, the functions of the DDR4 cache include large data buffering: temporarily storing acquired data to solve the instantaneous congestion of data transmission; waveform playback: storing standard test waveforms for comparative analysis or excitation playback; test sequence storage: storing complex test procedure configurations and expected result templates. The specific implementation methods include: high-speed interconnection with FPGA through AXI bus; parallel acquisition and transmission; using DMA controller to reduce intervention.

[0062] In some embodiments, the functional layer 1013 includes a power and signal conditioning module and an active monitoring and routing module, wherein the core components of the power and signal conditioning module include a programmable gain amplifier, an active filter and an equalization circuit, a digital isolator, etc., for being responsible for the conditioning of voltage excitation signals, signal integrity enhancement and power driving; the core components of the active monitoring and routing module include a multi-channel synchronous ADC, a high-speed analog multiplexer, a monitoring signal conditioning PGA, etc., for being responsible for synchronous detection and acquisition of multi-parameters, signal routing and multiplexing.

[0063] Among them, the main function of the programmable gain amplifier is gain control, which can automatically adjust the amplification multiple according to the signal amplitude. The main functions of the active filter and the equalization circuit include anti-aliasing filtering: filtering out high-frequency noise to prevent signal aliasing; bandwidth limitation: selecting appropriate bandwidth according to test requirements to optimize signal-to-noise ratio; power supply noise isolation: preventing digital noise from crosstalk to the analog signal path. The specific implementation methods include: through a multi-stage active filter, the cut-off frequency is adjustable; using a fully differential signal path to suppress common-mode noise; the analog and digital parts are independent in power supply, and physical isolation is used. The main functions of the digital isolator include impedance matching: matching the transmission line impedance through a programmable resistance network to reduce reflection; bias adjustment: eliminating signal DC bias to avoid amplifier saturation; level conversion: realizing conversion between different logic levels. The specific implementation methods include: switching the matching resistance network through an analog switch; setting an accurate bias voltage through a DAC; using a bidirectional level converter chip. The main functions of the multi-channel synchronous ADC include voltage / current monitoring: synchronously measuring the voltage and current of each power domain of SOC; timing parameter measurement: capturing the setup / hold time, rise / fall time of the signal. The specific implementation methods include: using a multi-channel synchronous sampling ADC; using high-precision sampling resistors and current detection amplifiers. The main functions of the high-speed analog multiplexer include: channel selection: dynamically allocating limited ADC resources to hundreds of test points; signal distribution: sending key monitoring signals to multiple processing units simultaneously; test point expansion: expanding the number of monitoring channels through multi-stage multiplexing. The specific implementation methods include: using a high-speed analog switch matrix; tree-like multiplexing structure; automatic scanning through hardware channels. The main functions of the monitoring signal conditioning PGA include: digital filtering: implementing low-pass, high-pass, and band-pass filtering in the digital domain; anomaly detection: automatically identifying abnormal signals based on preset thresholds. The specific implementation methods include: using CORDIC algorithm to calculate trigonometric functions to complete filtering; setting multiple comparators for threshold judgment.

[0064] In this embodiment, the interface layer 1011 solves the problem of incompatible output signals of different test devices and the interface protocol of the SOC chip 106 to be tested. Through the multi-protocol conversion capability, the test board can be adapted to the SOC chip 106 with various interface protocols without changing the hardware, greatly improving the versatility and adaptability of the test board and reducing the hardware cost for testing different chips. The processing layer 1012 eliminates the timing deviation of the signal in the transmission and protocol conversion process, so that the signal timing of the SOC chip 106 to be tested is accurately synchronized with the chip working clock, avoiding the problem that the chip cannot respond or the response is delayed due to timing mismatch, significantly improving the reliability of the test signal, and further ensuring the accuracy of the performance test result of the SOC chip 106 to be tested. The functional layer 1013 adjusts the signal amplitude after clock synchronization to the optimal input range of the SOC chip 106 to be tested, which avoids the problem that the chip cannot recognize due to low signal amplitude, and prevents the chip interface from being damaged due to high signal amplitude. At the same time, the low-noise amplification process can ensure the signal quality and reduce the interference of signal distortion on the test result. The modular design of the test board 101 facilitates subsequent maintenance and functional upgrade, and reduces the long-term investment cost of the test equipment.

[0065] In one exemplary embodiment, the functional layer 1013 is also configured to receive a response signal returned by the SOC chip 106 to be tested, and perform gain amplification on the response signal to obtain a second conditioning signal; the processing layer 1012 and the interface layer 1011 are also configured to forward the second conditioning signal to the host computer 102.

[0066] The response signal output by the SOC chip 106 to be tested is returned to the host computer 102 through the test board 101. Specifically, the response signal is first sent to the functional layer 1013, and the functional layer 1013 performs gain amplification on the response signal to obtain a second conditioning signal, so that the weak or low-amplitude response signal can be accurately recognized and transmitted by the subsequent link.

[0067] The processing layer 1012 and the interface layer 1011 sequentially forward the second conditioning signal and send it to the host computer 102. The processing layer 1012 uses its own clock circuit to ensure that the signal transmission timing is synchronized with the receiving clock of the host computer 102 when forwarding the second conditioning signal, avoiding signal transmission errors due to timing deviation and ensuring stable transmission of the signal from the functional layer 1013 to the interface layer 1011. The interface layer 1011 converts the second conditioning signal after clock synchronization into a communication protocol supported by the host computer 102, realizing protocol-compatible transmission of the signal from the test board 101 to the host computer 102.

[0068] In this embodiment, the amplification processing of the response signal by the function layer 1013 solves the problem of weak response signal amplitude returned by the SOC chip 106 under test, which is easy to be disturbed by noise, maximizes the retention of effective information in the response signal, and guarantees the reliability of the test results; the clock synchronization of the processing layer 1012 guarantees the timing stability of the second conditioning signal in transmission, avoiding data misplacement due to timing deviation; the protocol conversion of the interface layer 1011 realizes the communication compatibility between the test board 101 and the host computer 102, without the need to customize the test board for different host computer 102 interfaces, improving the system versatility. The response signal is automatically processed through the whole process of the test board 101, forming a feedback link, and improving the test efficiency.

[0069] In one exemplary embodiment, referring to Figure 1 The device further includes a test seat 107; the test seat 107 includes a base, and the base includes a first pin channel and a second plug channel; the test seat 107 is connected with the test board 101 through the first pin channel, and is connected with the SOC chip 106 under test through the second plug channel.

[0070] In some embodiments, the base is usually made of insulating material, and is internally provided with channels for accommodating pins or plugs, which play a role in fixing the connection position and insulating and isolating different pin signals, guaranteeing the safety and stability of signal transmission.

[0071] For example, the output interface of the test board 101 is a 40-pin female header, and the first pin channel of the test seat 107 is correspondingly provided with 40 metal pins. After the pins are inserted into the female header, the first conditioning signal processed by the test board 101 can be transmitted to the test seat 107 through the pins. For example, the SOC chip 106 under test is a 100-pin QFP package, and the second plug channel of the test seat 107 is provided with 100 elastic probes, which are one-to-one corresponding to the chip pins. After the SOC chip 106 under test is inserted, the probes are in close contact with the pins, ensuring that the first conditioning signal can be accurately transmitted into the SOC chip 106 under test, and at the same time, the response signal of the chip can be transmitted back to the test seat 107 through the probes.

[0072] In this embodiment, the test seat 107 realizes the quick plug-in connection between the test board 101 and the SOC chip 106 under test through the standardized first pin channel and the second plug channel, without the need for manual soldering or complex wiring, which is especially suitable for batch testing scenarios.

[0073] In an exemplary embodiment, the test seat 107 further comprises a cover seat, and the bottom seat and the cover seat form a cavity when combined together; the SOC chip 106 to be tested is exposed in the cavity.

[0074] Wherein, the cover seat and the bottom seat in the test seat 107 are buckled together to form a closed or semi-closed control, which can accommodate the SOC chip 106 to be tested, and provide physical protection and environmental isolation (such as dustproof and external interference) for the SOC chip 106 to be tested through the space structure, while reserving space for signal transmission, heat dissipation or special environment simulation during the test process.

[0075] In this embodiment, the bottom seat and the cover seat form a cavity when combined together, and the SOC chip 106 to be tested is exposed in the cavity, which improves the stability of chip testing and adapts to complex test environment.

[0076] In an exemplary embodiment, the device further comprises a temperature controller 108 connected with the upper computer 102; the cover seat is provided with a heater, a cooler and a temperature sensor; the heater, the cooler and the temperature sensor are connected with the temperature controller 108; and the temperature controller 108 is used to control the heater, the cooler and the temperature sensor according to the environmental temperature excitation parameters sent by the upper computer 102.

[0077] Wherein, the environmental temperature excitation parameters refer to the target parameters set by the upper computer 102 according to the test requirements for controlling the temperature of the cavity, which can include target temperature value, temperature stabilization time, temperature change rate, cycle mode, etc., and are the core instruction basis for the temperature controller 108 to perform temperature control operation.

[0078] The temperature controller 108 is connected with the upper computer 102, used to receive the environmental temperature excitation parameters sent by the upper computer 102, and read the cavity temperature data of the temperature sensor in real time according to the environmental temperature excitation parameters, automatically control the heater to heat up or the cooler to cool down, and stabilize the cavity temperature in the target range, so as to build a controllable temperature test environment for the SOC chip 106 to be tested.

[0079] For example, the real-time temperature data of the temperature sensor is received and compared with the environmental temperature excitation parameters; if the real-time temperature data is lower than the target temperature range in the environmental temperature excitation parameters, the output signal starts the heater and adjusts the power; if the real-time temperature data is higher than the target temperature range in the environmental temperature excitation parameters, the cooler is started; and if the real-time temperature data is in the target temperature range, the current state is maintained or the power is fine-tuned to ensure that the real-time temperature data is stable in the target temperature range.

[0080] Since the to-be-tested SOC chip 106 is placed in the cavity of the base, the environmental temperature excitation parameter is applied through the test seat 107, and the provided environmental temperature is the working temperature of the chip, which only acts on the working temperature environment of the to-be-tested SOC chip 106 and does not act on other devices of the test device, so that the interference of temperature changes of other devices on the test result is avoided. Compared with the traditional test device, the authenticity of the test data can be effectively improved.

[0081] In addition, in the traditional test device, most of them can only simulate tests under a single excitation condition, such as a single voltage fluctuation excitation or an environmental temperature change excitation. A multi-simulation excitation test device is extremely complex, because a complete test board needs to be installed in a temperature box, and a large number of switching devices are needed to connect the test board in the temperature box with all external devices, and meanwhile, the problem of data distortion caused by temperature changes of other devices on the test board cannot be avoided. The test device and method provided in the application can simultaneously simulate the reliability test of the to-be-tested SOC chip 106 under voltage fluctuation excitation and environmental temperature excitation. When the test device is used for testing, the voltage excitation signal and the environmental temperature excitation can be applied simultaneously to simulate the performance of the to-be-tested SOC chip 106 under the condition that the voltage fluctuation and the environmental temperature change simultaneously during the working process of the to-be-tested SOC chip 106; or the voltage excitation signal or the environmental temperature excitation can be applied singly to simulate the influence of the voltage fluctuation or the environmental temperature change during the working process of the to-be-tested SOC chip 106 on the performance of the to-be-tested SOC chip 106.

[0082] In the embodiment, the temperature controller 108 can simulate the temperature conditions of different working environments in response to the environmental temperature excitation parameter sent by the upper computer 102, so that the accurate shell temperature of the chip is provided, and the influence caused by the temperature changes of other devices in the traditional temperature box test is avoided; the automatic detection and temperature regulation of the cavity temperature are realized, the temperature conditions of the test environment are simulated, the multi-dimensional test requirements are met, and the test efficiency is improved.

[0083] In an exemplary embodiment, the upper computer 102 is further configured to determine a reference test result according to the test instruction; analyze the second conditioning signal according to the reference test result to obtain a performance test result of the to-be-tested SOC chip 106.

[0084] The test instruction refers to an instruction input by a user or preset by the upper computer 102 according to the test requirement, and contains information such as a test target, a parameter range, and a standard index. For example, the test instruction can be that each executes 100,000 times of random addition operation under different environmental temperature excitation.

[0085] The reference test result is an expected standard result generated by the upper computer 102 according to the test instruction, which is reference data for evaluating the performance of the to-be-tested SOC chip 106. It can be a theoretical calculation value, historical test data of a same type of qualified chip, or an index range specified by an industry standard.

[0086] The host computer 102 compares and calculates the actual data in the second conditioned signal with the reference test result, which can include deviation analysis, compliance judgment, and abnormal positioning, and finally converts into a quantifiable performance conclusion, i.e., a performance test result. For example, the host computer 102 counts the number of calculation errors of the SOC chip 106 under each environmental temperature excitation, i.e., the number of times that the actual data in the second conditioned signal is inconsistent with the reference test result, by using a mathematical statistical analysis method, analyzes the influence of the environmental temperature on the performance of the SOC chip 106, and obtains the performance test result. The performance test result can include performance test pass and performance test fail, and can also include accuracy and average processing time.

[0087] In this embodiment, by determining the reference test result matched with the test instruction, a quantifiable reference index is provided for analyzing the second conditioned signal, which is conducive to obtaining an accurate performance test result; without manual judgment, a unified algorithm ensures the consistency of the analysis logic of each SOC chip 106, and improves the reliability of the performance test result and the performance test efficiency.

[0088] In one exemplary embodiment, as shown in Figure 3 a SOC chip performance test method is provided. Taking the host computer 102 in Figure 1 as an example, the method includes the following steps 202 to 206. Among them:

[0089] Step 202, according to the test requirement, send the excitation instruction to the voltage simulator 103, and send the test instruction to the signal generator 104; the excitation instruction is used to instruct the voltage simulator 103 to input the voltage excitation signal to the test board 101 according to the excitation instruction; the test instruction is used to instruct the signal generator 104 to input the test signal to the test board 101 according to the test instruction; the voltage excitation signal and the test signal are used to instruct the test board 101 to condition the voltage excitation signal and the test signal, and send the first conditioned signal to the SOC chip 106 to be tested, so as to instruct the SOC chip 106 to be tested to respond to the first conditioned signal; the response signal of the SOC chip 106 to be tested is used to instruct the test board 101 to condition the response signal.

[0090] Step 204, analyze the second conditioned signal returned by the test board 101 to obtain the performance test result of the SOC chip 106 to be tested.

[0091] In the SOC chip performance test method, the test board 101 provides an input interface of the voltage excitation signal and the test signal, and through the cooperation of the voltage simulator 103 and the signal generator 104, the voltage excitation signal and the test signal can be input to the to-be-tested SOC chip 106 at the same time. The voltage simulator 103 can simulate different power supply voltage conditions, and the signal generator 104 can generate diversified test signals, which can cover the diversified power supply environment of the to-be-tested SOC chip 106 in actual application and the interactive scene of the external test signal, and adapt to the complex test requirements of the to-be-tested SOC chip 106. The test board 101 can process the input signal to ensure that the output signal is more consistent with the actual running state. The test board 101 also provides a receiving interface of the response signal of the to-be-tested SOC chip 106, so that the response signal can be fed back to the host computer 102 through the test board 101, and the response signal is analyzed by the host computer 102, which is beneficial to obtain accurate performance test results of the to-be-tested SOC chip 106. The device that the host computer 102 controls, the test board 101 automatically processes, and the voltage excitation signal and the test signal cooperate is beneficial to simplify the performance test process of the to-be-tested SOC chip 106 and improve the performance test efficiency.

[0092] In one exemplary embodiment, the second processed signal returned by the test board 101 is analyzed to obtain the performance test result of the to-be-tested SOC chip 106, including: determining a reference test result according to the test instruction; and analyzing the second processed signal according to the reference test result to obtain the performance test result of the to-be-tested SOC chip 106.

[0093] In this embodiment, by determining the reference test result matched with the test instruction, a quantifiable reference index is provided for analyzing the second processed signal, which is beneficial to obtain accurate performance test results. Without manual judgment, the unified algorithm ensures the consistency of the analysis logic of each to-be-tested SOC chip 106, and improves the reliability of the performance test result and the performance test efficiency.

[0094] To describe the SOC chip performance test device and method in this scheme in detail, a most detailed embodiment is described as follows:

[0095] Reference Figure 1The SOC chip performance testing device comprises a test board 101, a host computer 102, a voltage simulator 103, a signal generator 104, a signal monitor 105 and a to-be-tested SOC chip 106; the test board 101 is connected with the host computer 102, the voltage simulator 103, the signal generator 104 and the signal monitor 105 respectively; the host computer 102 is connected with the voltage simulator 103 and the signal generator 104 respectively; the host computer 102 is used for sending an excitation instruction to the voltage simulator 103 and sending a test instruction to the signal generator 104 according to a test requirement; the voltage simulator 103 is used for inputting a voltage excitation signal to the test board 101 according to the excitation instruction; the signal generator 104 is used for inputting a test signal to the test board 101 according to the test instruction; the test board 101 is used for conditioning the voltage excitation signal and the test signal and sending a first conditioned signal to the to-be-tested SOC chip 106 to instruct the to-be-tested SOC chip 106 to respond to the first conditioned signal; the test board 101 is also used for acquiring a response signal returned by the to-be-tested SOC chip 106, conditioning the response signal and returning a second conditioned signal to the host computer 102; the host computer 102 is also used for analyzing the second conditioned signal to obtain a performance test result of the to-be-tested SOC chip 106.

[0096] In an exemplary embodiment, the device further comprises a test seat 107; the test seat 107 comprises a base, and the base comprises a first pin channel and a second plug channel; the test seat 107 is connected with the test board 101 through the first pin channel and is connected with the to-be-tested SOC chip 106 through the second plug channel.

[0097] In an exemplary embodiment, the test seat 107 further comprises a cover seat, and the base and the cover seat form a cavity when combined; the to-be-tested SOC chip 106 is exposed in the cavity.

[0098] In an exemplary embodiment, the device further comprises a temperature controller 108, and the temperature controller 108 is connected with the host computer 102; a heater, a cooler and a temperature sensor are arranged in the cover seat; the heater, the cooler and the temperature sensor are connected with the temperature controller 108; the temperature controller 108 is used for controlling the heater, the cooler and the temperature sensor according to an environmental temperature excitation parameter sent by the host computer 102.

[0099] In an exemplary embodiment, the device further comprises a power supply 109, and the power supply 109 is used for supplying power to the voltage simulator 103 and the test board 101.

[0100] In an exemplary embodiment, the host computer 102 is also used for determining a reference test result according to the test instruction; the second conditioned signal is analyzed according to the reference test result to obtain the performance test result of the to-be-tested SOC chip 106.

[0101] In one exemplary embodiment, with reference to Figure 2 The test board 101 comprises an interface layer 1011, a processing layer 1012, and a functional layer 1013. The interface layer 1011 comprises a multi-protocol serial interface chip for receiving a voltage excitation signal and a test signal, and performing protocol conversion on the voltage excitation signal and the test signal, respectively. The processing layer 1012 comprises a clock circuit for clock synchronization of the protocol-converted voltage excitation signal and the protocol-converted voltage test signal. The functional layer 1013 comprises a gain amplifier for gain amplification of the clock-synchronized voltage excitation signal and the clock-synchronized test signal, respectively, to obtain a first conditioning signal.

[0102] In one exemplary embodiment, the functional layer 1013 is further configured to receive a response signal returned by the SOC chip under test 106, and perform gain amplification on the response signal to obtain a second conditioning signal. The processing layer 1012 and the interface layer 1011 are further configured to forward the second conditioning signal to the host computer 102.

[0103] In one exemplary embodiment, the SOC chip performance test method comprises the following steps:

[0104] The temperature of the cavity of the test seat 107 is controlled by the temperature controller 108 to provide environmental temperature excitation parameters for the SOC chip under test 106. The test board 101 is provided with a time sequence voltage signal by the voltage simulator 103 to provide time sequence voltage excitation for the SOC chip under test 106. The test board 101 is provided with a test signal by the signal generator 104 to provide performance test parameter excitation for the SOC chip under test 106. The detection signal of the SOC chip under test 106 is monitored by the signal monitor 105, and the test data is acquired and analyzed by the host computer 102 to complete the performance test of the SOC chip under test 106.

[0105] In some embodiments, the voltage excitation signal and the environmental temperature excitation can be applied simultaneously to simulate the performance of the SOC chip under test 106 when the voltage fluctuation and the environmental temperature change simultaneously. Alternatively, only the voltage excitation signal or the environmental temperature excitation can be applied to simulate the influence of the voltage fluctuation or the environmental temperature change on the performance of the SOC chip under test 106 during operation.

[0106] The SOC chip performance testing device and method, the test board 101 provides the input interface of the voltage excitation signal and the test signal, through the cooperation of the voltage simulator 103 and the signal generator 104, the voltage excitation signal and the test signal can be input to the SOC chip 106 to be tested at the same time, the voltage simulator 103 can simulate different power supply voltage working conditions, the signal generator 104 can generate diversified test signals, which can cover the diversified power supply environment of the SOC chip 106 to be tested in actual application and the interactive scene of the external test signal, adapt to the complex test requirements of the SOC chip 106 to be tested; the test board 101 can process the input signal, to ensure that the output signal is more consistent with the actual running state; the test board 101 also provides a receiving interface of the response signal of the SOC chip 106 to be tested, so that the response signal can be fed back to the host computer 102 through the test board 101, and the response signal is analyzed by the host computer 102, which is beneficial to obtain accurate performance test results of the SOC chip 106 to be tested; such a device through centralized control of the host computer 102, automatic processing of the test board 101, and cooperation of the voltage excitation signal and the test signal is beneficial to simplify the performance test process of the SOC chip 106 to be tested and improve the performance test efficiency.

[0107] It should be understood that, although each step in the flowchart involved in each embodiment as described above is displayed in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart involved in each embodiment as described above can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be alternately executed with at least part of other steps or steps or stages in other steps. It can be understood that the steps in different embodiments can be freely combined as needed, and various non-contradictory schemes formed by the combination are within the scope of protection of the present application.

[0108] Based on the same inventive concept, the embodiments of the present application also provide a SOC chip performance testing device for implementing the above-mentioned SOC chip performance testing method. The problem-solving implementation scheme provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more SOC chip performance testing device embodiments provided below can refer to the limitations of the SOC chip performance testing method in the foregoing, which will not be described here.

[0109] In an exemplary embodiment, a computer device, which can be a terminal, is provided, and an internal structure diagram of the computer device can be as shown inFigure 4 The computer device shown in the figure includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capability. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be realized through WIFI, mobile cellular network, Near Field Communication (NFC) or other technologies. The computer program is executed by the processor to realize a SOC chip performance testing method. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0110] Those skilled in the art can understand that, Figure 4 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0111] In one exemplary embodiment, a computer device is provided, including a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps in each of the above method embodiments.

[0112] In one embodiment, a computer readable storage medium is provided, having a computer program stored thereon, the computer program being executed by a processor to implement the steps in each of the above method embodiments.

[0113] In one embodiment, a computer program product is provided, including a computer program, the computer program being executed by a processor to implement the steps in each of the above method embodiments.

[0114] It should be noted that the user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of related data need to comply with relevant regulations.

[0115] It can be understood by those skilled in the art that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing related hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments of each method. In the embodiments provided in the present application, any reference to memory, database or other medium can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0116] Any technical features in the above embodiments can be combined, and for the sake of brevity, not all possible combinations are described above, however, any combination of these technical features is deemed to be within the scope of the present application.

[0117] The above embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the present application. It should be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A SOC chip performance test device, characterized in that, The device comprises a test board, a host computer, a voltage simulator, a signal generator, a signal monitor and a to-be-tested SOC chip; the test board is connected with the host computer, the voltage simulator, the signal generator and the signal monitor respectively; the host computer is connected with the voltage simulator and the signal generator respectively; The host computer is used to send an excitation instruction to the voltage simulator and a test instruction to the signal generator according to test requirements; The voltage simulator is used to input a voltage excitation signal to the test board according to the excitation instruction; The signal generator is used to input a test signal to the test board according to the test instruction; The test board is used to condition the voltage excitation signal and the test signal, and send a first conditioned signal to the to-be-tested SOC chip to instruct the to-be-tested SOC chip to respond to the first conditioned signal; The test board is also used to acquire a response signal returned by the to-be-tested SOC chip, condition the response signal, and return a second conditioned signal to the host computer; The host computer is also used to analyze the second conditioned signal to obtain a performance test result of the to-be-tested SOC chip.

2. The apparatus of claim 1, wherein, The test board comprises an interface layer, a processing layer and a functional layer; the interface layer comprises a multi-protocol serial interface chip, which is used to receive the voltage excitation signal and the test signal, and perform protocol conversion on the voltage excitation signal and the test signal respectively; the processing layer comprises a clock circuit, which is used to perform clock synchronization on the voltage excitation signal after protocol conversion and the test signal after protocol conversion; the functional layer comprises a gain amplifier, which is used to perform gain amplification on the voltage excitation signal after clock synchronization and the test signal after clock synchronization respectively to obtain the first conditioned signal.

3. The apparatus of claim 2, wherein, The functional layer is also used to receive the response signal returned by the to-be-tested SOC chip, perform gain amplification on the response signal to obtain the second conditioned signal; the processing layer and the interface layer are also used to forward the second conditioned signal to the host computer.

4. The apparatus of claim 1, wherein, The device further comprises a test seat; the test seat comprises a base, and the base comprises a first pin channel and a second pin channel; the test seat is connected with the test board through the first pin channel and connected with the to-be-tested SOC chip through the second pin channel.

5. The apparatus of claim 4, wherein, The test seat further comprises a cover, and a cavity is formed between the base and the cover when they are combined; the to-be-tested SOC chip is exposed in the cavity.

6. The apparatus of claim 5, wherein, The device further comprises a temperature controller, which is connected with the host computer; the cover is internally provided with a heater, a cooler and a temperature sensor; the heater, the cooler and the temperature sensor are connected with the temperature controller; the temperature controller is used to control the heater, the cooler and the temperature sensor according to environmental temperature excitation parameters sent by the host computer.

7. The apparatus of claim 1, wherein, The host computer is also used to determine a reference test result according to the test instruction; and to analyze the second conditioning signal according to the reference test result to obtain the performance test result of the SOC chip under test.

8. A method for testing performance of an SOC chip, characterized by, The method, applied to the SOC chip performance testing apparatus according to any one of claims 1 to 7, comprises: According to the test requirements, an excitation command is sent to the voltage simulator, and a test command is sent to the signal generator. The excitation command instructs the voltage simulator to input a voltage excitation signal to the test board according to the excitation command. The test command instructs the signal generator to input a test signal to the test board according to the test command. The voltage excitation signal and the test signal instruct the test board to condition the voltage excitation signal and the test signal, and send a first conditioned signal to the SOC chip under test to instruct the SOC chip under test to respond to the first conditioned signal. The response signal of the SOC chip under test instructs the test board to condition the response signal. The second conditioning signal returned by the test board is analyzed to obtain the performance test results of the SOC chip under test. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-8 when the computer program is executed by the processor. When the processor executes the computer program, it implements the steps of the method of claim 8.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the method of claim 8.

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