Data acceleration processing method and apparatus, chip, device, and readable storage medium

Abstract

The present application relates to a data acceleration processing method and apparatus, a chip, a device, and a readable storage medium. The method comprises: receiving a trigger message for a data processing task, the trigger message comprising pointer information of a queue, the pointer information of the queue being address information of the queue in a memory, and the queue being used for storing a task descriptor of the data processing task; updating the pointer information of the queue to a queue manager for scheduling by a queue scheduler; when the queue is selected by the queue scheduler, transmitting the pointer information of the queue to a descriptor cache acquisition unit, so as to notify the descriptor cache acquisition unit to acquire the task descriptor of the data processing task from the memory; and selecting an idle engine from among a plurality of identical data acceleration processing engines as a target engine, and executing the data processing task on the basis of the task descriptor by means of the target engine.

Description

Data acceleration processing method, device, chip, equipment and readable storage medium

[0001] Related applications

[0002] The present application claims priority to the Chinese patent application No. 2024110136181, filed on July 25, 2024, entitled "Data acceleration processing method, device, chip, equipment and readable storage medium", the contents of which are hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the chip technical field, in particular, to a data acceleration processing method, device, chip, equipment and readable storage medium. BACKGROUND

[0004] With the development of chip technology, the amount of data processed by processor chips is increasing, and accordingly, the movement of data between different devices through processor chips is becoming more and more important.

[0005] In related technologies, processor chips process data movement between different devices, which usually requires a central processing unit (CPU) to first move data from the memory of the device to the general register, and then move the data from the general register to the memory of the device.

[0006] However, this data movement method requires moving data into the general register first and then moving data out of the general register, which occupies a large amount of CPU resources, and may cause the CPU to interrupt the current data movement task to execute a higher priority task, resulting in a large data movement delay. Therefore, the data movement method in related technologies has large CPU resource overhead and low efficiency. SUMMARY

[0007] According to various embodiments of the present application, a data acceleration processing method, device, chip, equipment and readable storage medium are provided.

[0008] In a first aspect, the present application provides a data acceleration processing method, comprising:

[0009] receiving a trigger message of a data processing task, the trigger message including pointer information of a queue, the pointer information of the queue being address information of the queue in memory, and the queue being used to store a task descriptor of the data processing task;

[0010] updating the pointer information of the queue into a queue manager for scheduling by a queue scheduler;

[0011] When the queue is selected by the queue scheduler, pointer information of the queue is passed to a descriptor cache acquisition unit to inform the descriptor cache acquisition unit to acquire a task descriptor of the data processing task from the memory;

[0012] An idle engine is selected as a target engine from a plurality of same data acceleration processing engines, and the data processing task is executed by the target engine according to the task descriptor.

[0013] In one embodiment, the data acceleration processing engine includes a descriptor parsing unit, a state machine unit, a read data payload unit and a data calculation processing unit, and the execution of the data processing task by the target engine according to the task descriptor includes:

[0014] The data structure of the task descriptor is determined by parsing the task descriptor through the descriptor parsing unit;

[0015] A target field is acquired from the data structure of the task descriptor by the descriptor parsing unit, and the target field is encapsulated into a state machine instruction and sent to the state machine unit;

[0016] According to the instruction type of the state machine instruction, the state machine is switched between different states to inform the read data payload unit or the data calculation processing unit to execute the data processing task.

[0017] In one embodiment, the states of the state machine include an idle state, a read-write control state and a write-back state; the idle state is a state in which the data processing task is not executed;

[0018] The informing of the read data payload unit or the data calculation processing unit to execute the data processing task includes:

[0019] When the state machine is in the read-write control state, the read data payload unit or the data calculation processing unit is informed by the state machine unit to execute the data processing task;

[0020] When the state machine is in the write-back state, a task completion unit or an interrupt message corresponding to the data processing task is sent to the queue manager by the state machine unit according to write-back control information.

[0021] In one embodiment, the switching of the state machine between different states includes:

[0022] When the state machine instruction is received by the state machine unit, the state machine is switched from the idle state to the read-write control state by the state machine unit;

[0023] In the case that the read data load unit or the data computing processing unit completes the data processing task, the state machine is switched from the read-write control state to the write-back state by the state machine unit;

[0024] In the case that the target engine receives a feedback message corresponding to the task completion unit or the interrupt message, the state machine is switched from the write-back state to the idle state by the state machine unit.

[0025] In one embodiment, the read data load unit is configured to, when the state machine is in the read-write control state, notify a direct memory access unit to perform data transfer according to the read data request information, so as to execute the data processing task.

[0026] The data computing processing unit is configured to, when the state machine is in the read-write control state, execute a data computing operation in the data processing task by an arithmetic logic component according to the computing request information, and notify the direct memory access unit to perform data transfer by a write data processing component according to the write data request information, so as to execute the data processing task.

[0027] In one embodiment, the task descriptor includes an operation domain segment, and the operation domain segment is configured to indicate at least one data processing operation in the data processing task.

[0028] In one embodiment, the queue manager and the data acceleration processing engine maintain an inversion indication information respectively, and the method further includes:

[0029] The queue manager marks the task descriptor by the inversion indication information, and sends the task descriptor marked by the inversion indication information to the target engine.

[0030] In the case that the inversion indication information marked by the received task descriptor is the same as the inversion indication information maintained by the data acceleration processing engine, the target engine executes the data processing task according to the task descriptor; after the data processing task is executed, the target engine generates a task completion unit and sends the task completion unit back to the queue manager; and the queue manager updates the task completion unit to a task completion queue.

[0031] In the case that the inversion indication information marked by the received task descriptor is different from the inversion indication information maintained by the data acceleration processing engine, the target engine gives up to execute the data processing task, generates a task completion unit and sends the task completion unit back to the queue manager; and the queue manager does not update the task completion unit to the task completion queue.

[0032] In one of the embodiments, in the case that the received task descriptor carries the same reverse indication information as the reverse indication information maintained by the data acceleration processing engine, the method further comprises:

[0033] In the case that the received task descriptor carries the barrier identification, and the current queue has other in-transit task descriptors which are not processed by the data acceleration processing engine, the target engine reverses the reverse indication information maintained by the data acceleration processing engine; the target engine generates a rollback request, and sends the rollback request to the queue manager, the rollback request being used to instruct the queue manager to stop scheduling the current queue, the rollback request comprising address information of the task descriptor carrying the barrier identification; the queue manager waits until the data acceleration processing engine processes the other in-transit task descriptors, and then resumes scheduling the current queue from the task descriptor carrying the barrier identification;

[0034] In the case that the received task descriptor carries the barrier identification, and the current queue has no other in-transit task descriptors which are not processed by the data acceleration processing engine, the target engine executes the data processing task according to the received task descriptor; after executing the task, the target engine generates a task completion unit, and sends the task completion unit back to the queue manager; the queue manager updates the task completion unit into the task completion queue.

[0035] In one of the embodiments, the data processing task comprises a batch processing task, the batch processing task comprises a plurality of sub-tasks, and the batch processing task comprises message tail indication information, the message tail indication information being used to indicate the last sub-task in the batch processing task.

[0036] The task completion unit corresponding to the batch processing task is triggered after the last sub-task is executed.

[0037] In one of the embodiments, the task descriptor comprises at least one of the following information:

[0038] Source address of task data, destination address of task data, operator of task data, and data volume of task data.

[0039] In a second aspect, the application provides a data acceleration processing device, comprising:

[0040] A queue management module is configured to receive a trigger message of a data processing task, wherein the trigger message comprises pointer information of a queue, and the pointer information of the queue is address information of the queue in a memory, and the queue is configured to store a task descriptor of the data processing task; the pointer information of the queue is updated to a queue manager for scheduling by a queue scheduler; when the queue is selected by the queue scheduler, the pointer information of the queue is transmitted to a descriptor cache acquisition unit to notify the descriptor cache acquisition unit to acquire the task descriptor of the data processing task from the memory.

[0041] A data processing acceleration module is configured to select an idle engine as a target engine from a plurality of same data processing acceleration engines, and execute the data processing task according to the task descriptor by the target engine.

[0042] In a third aspect, the present application further provides a chip comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the data processing method of the first aspect when executing the computer program.

[0043] In a fourth aspect, the present application further provides a network interface card comprising the chip of the third aspect and a plurality of interfaces, and the chip communicates with the outside through the interfaces.

[0044] In a fifth aspect, the present application further provides a computer device comprising a processor and the network interface card of the fourth aspect, wherein the network interface card is configured to schedule a packet to the processor or the network interface card itself for processing, and the processor is configured to process the packet scheduled by the network interface card.

[0045] In a sixth aspect, the present application further provides a computer readable storage medium, which stores a computer program, and the computer program implements the data processing method of the first aspect when executed by a processor.

[0046] In a seventh aspect, the present application further provides a computer program product comprising a computer program, and the computer program implements the data processing method of the first aspect when executed by a processor.

[0047] Details of one or more embodiments of the present application are presented in the accompanying drawings and description below. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description only represent some embodiments of the present application, and other drawings can be obtained by those of ordinary skill in the art without any creative effort based on the disclosed drawings.

[0049] FIG. 1 is a structural schematic diagram of an SDAE provided by an embodiment of the present application;

[0050] FIG. 2 is a flow schematic diagram of a data acceleration processing method provided by an embodiment of the present application;

[0051] FIG. 3 is a state transition diagram of an acceleration engine provided by an embodiment of the present application;

[0052] FIG. 4 is a flow schematic diagram of another data acceleration processing method provided by an embodiment of the present application;

[0053] FIG. 5 is a flow schematic diagram of still another data acceleration processing method provided by an embodiment of the present application;

[0054] FIG. 6 is a structural block diagram of a data acceleration processing apparatus provided by an embodiment of the present application;

[0055] FIG. 7 is an internal structural diagram of a computer device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative effort fall within the scope of the present application.

[0057] In order to make the purposes, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0058] The related art will be described first below.

[0059] With the development of chip technology, the amount of data processed by a processor chip is increasing, and accordingly, it is more and more important to move data between different devices through a processor chip.

[0060] In the related art, a processor chip processes data migration between different devices, which usually needs to be performed by a central processing unit (CPU) to first migrate data from the memory of the device that moves out to a general register, and then migrate the data from the general register to the memory of the device that moves in. For example, to migrate data from memory A to memory B, the CPU is needed to first migrate the data from memory A to a general register, and then migrate the data from the general register to memory B.

[0061] However, this data migration method needs to first move data into a general register and then move data out of the general register, which occupies a large amount of CPU resources, and may cause the CPU to interrupt the current data migration task to execute a higher priority task, resulting in a large data migration delay. Therefore, the data migration method in the related art has a large CPU resource overhead and low efficiency.

[0062] In addition, the processor chip can also process data migration between different devices through direct memory access (DMA). DMA is usually used to migrate memory. DMA operation can operate a bus to directly migrate data from memory A to memory B without occupying CPU resources. Moreover, once the DMA starts to perform a data migration task, it will not be interrupted. Therefore, compared with the CPU data migration method, the DMA data migration method has a lower CPU resource overhead and higher efficiency.

[0063] However, the current DMA operation generally only completes the data migration work, and is usually provided based on a certain device or a certain service, that is, each device needs independent DMA operation logic, and the DMA operation is single-function, for example, single-channel large data uploading and issuing in a certain device or a certain service, which is not universal.

[0064] To solve the above problems, the embodiments of the present application provide a data acceleration processing method, device, chip, equipment and readable storage medium. Since a free target engine can be directly selected from a plurality of same data acceleration processing engines to process a task descriptor of a data processing task issued by system software, the data processing can be completed by relying on the hardware of the data acceleration processing engine itself, without CPU instruction processing, so that the data acceleration processing method provided by the present application has a lower CPU resource overhead, higher efficiency, and universality.

[0065] The data acceleration processing method provided by the embodiments of the present application can be applied to a chip or a smart data acceleration engine (SDAE) on the chip.

[0066] The SDAE can be a new generation of input / output local bus standard (Peripheral Component Interconnect Express, PCIe) device for a central processing unit (CPU) in a server. The SDAE can be an application specific integrated circuit (ASIC)-based hardware module. The SDAE can be a stateless accelerator, that is, there is no correlation between tasks processed by the SDAE. The stateless accelerator can provide a throughput much greater than the actual demand of the CPU, ensuring the efficiency and timeliness of the tasks. In addition, the SDAE can also provide flexible data migration and operation services for the system, including cyclic redundancy check (CRC), checksum calculation, AI allreduce operation, T10 generation, deletion, update, and other operations, as well as data backup, duplicate checking, deletion, and other operations. It should be noted that the system in the embodiments of the present application can be an operating system on a server or a chip. The operating system can run on the server, and the operating system can also run on the chip.

[0067] In the present application, the SDAE provides a programmable data migration and processing mode for the CPU: through the system software, the Doorbell carries programmable data processing information such as data migration and calculation commands, and the hardware SDAE completes priority scheduling, data migration, simple data processing and calculation, and other data processing tasks, thereby providing a common or universal programmable data acceleration channel for various system applications on the system upper layer, releasing the workload of the CPU and providing sufficient flexibility for the CPU. It should be noted that in the present application, software can refer to an operating system or a computer program running on the operating system.

[0068] The system application can include a single root I / O virtualization (SRIOV) application, a scalable I / O virtualization (SIOV) application, a network processing application, a storage application, a memory initialization application, a security management application, and the like.

[0069] FIG. 1 is a structural schematic diagram of an SDAE provided by an embodiment of the present application. As shown in FIG. 1, the SDAE can include a queue manager (QM) module, a HOST DMA (HDMA) module, and a data processing state machine (DPF) module.

[0070] The QM module can complete queue management, priority-based COS scheduling, and reading of a task descriptor. The HDMA module can complete DMA read and write requests from different sources. The DPF module can include a plurality of identical data acceleration processing engines. The data acceleration processing engines obtain a task descriptor from the QM module, obtain data information through a DMA operation according to an operation type in the task descriptor, and execute related instructions by the corresponding data acceleration processing engines.

[0071] In the present application, only one general DMA channel of the SDAE is needed to implement DMA moving work between the remaining devices. Compared with the related art in which each device needs independent DMA operation logic and is a single-function DMA, the SDAE is equivalent to a general DMA device, which saves CPU resource overhead, improves efficiency, and has general applicability.

[0072] In an exemplary embodiment, as shown in FIG. 2, a data acceleration processing method is provided by an embodiment of the present application. The method is taken as an example for description in the SDAE in FIG. 1, and includes the following steps S201 to S204.

[0073] S201, receiving a trigger message of a data processing task.

[0074] It should be understood that the embodiments of the present application do not limit the above trigger message. In some embodiments, the above trigger message can include a doorbell message. When a data processing task needs to be executed, software can issue a doorbell message to the SDAE through a CPU.

[0075] The trigger message includes pointer information of a queue. The pointer information of the queue is address information of the queue in a memory. The queue is used to store a task descriptor of the data processing task. The queue can be a send queue (SQ) or a submit queue (SQ), which is not limited in the embodiments of the present application.

[0076] Exemplarily, the above task descriptor can be stored in the memory in the form of a submission queue, so that the subsequent SDAE can obtain it from the memory. Correspondingly, the address information of the submission queue in the memory can be indicated by the queue pointer information.

[0077] In some embodiments, when generating a data processing task, a software (e.g., an application) can fill a task descriptor by a CPU and save the task descriptor into a memory, which can be a Double Data Rate (DDR) memory. The memory can be disposed in a server or a chip.

[0078] It should be noted that the above queue pointer information can be updated in real time, and correspondingly, the queue pointer information included in the trigger message can be the current latest queue pointer information.

[0079] It should be understood that the embodiments of the present application do not limit the above task descriptor, and in some embodiments, the task descriptor includes at least one of the following information: a source address of the task data, a destination address of the task data, an operator of the task data, and a data volume of the task data.

[0080] The operator can be an operation domain segment. The operator is used to indicate at least one data processing operation in the data processing task.

[0081] Exemplarily, the DPF module in the SDAE can determine at least one data processing operation in the data processing task according to the operation domain segment in the task descriptor. Exemplarily, the data processing operation can include data migration, Cyclic Redundancy Check (CRC), CheckSum calculation, AI allreduce operation, T10 generation, T10 deletion, T10 update, and the like, as well as backup, duplication checking, deletion, and the like of data.

[0082] S202, update the pointer information of the queue into the queue manager for scheduling by the queue scheduler.

[0083] In this step, when the SDAE receives the trigger message of the data processing task issued by the software, the pointer information of the queue can be updated into the queue manager for scheduling by the queue scheduler.

[0084] In some embodiments, before scheduling the queue, the queue scheduler can compare the queue pointer in the trigger message with the queue pointer in the queue manager to determine whether the queue pointer is offset.

[0085] Further, in the case that the queue pointer in the trigger message and the queue pointer in the queue manager have no offset, it can be determined that the queue corresponding to the queue pointer in the trigger message is an empty queue. In the case that the queue pointer in the trigger message and the queue pointer in the queue manager have an offset, it can be determined that the queue corresponding to the queue pointer in the trigger message is a non-empty queue.

[0086] It should be noted that in the present application, in the case that the queue is an empty queue, the queue scheduler cannot schedule the empty queue. In the case that the queue is a non-empty queue, the queue scheduler can schedule the non-empty queue.

[0087] S203, when the queue is selected by the queue scheduler, the pointer information of the queue is transmitted to the descriptor buffer acquisition unit to inform the descriptor buffer acquisition unit to acquire the task descriptor of the data processing task from the memory.

[0088] In this step, after the pointer information of the queue is updated in the queue manager, the queue can be selected by the queue scheduler. The queue manager can manage a plurality of queues, and when the queue is selected by the queue scheduler, the pointer information of the queue is transmitted to the descriptor buffer acquisition unit to inform the descriptor buffer acquisition unit to acquire the task descriptor of the data processing task from the memory.

[0089] For example, the QM module of the SDAE can include a queue scheduler (QSCH) and a buffer descriptor fetch (BDF) unit. The QSCH can select a submission queue from the non-empty queues based on a scheduling rule. The QSCH can send the information of the selected submission queue to the BDF unit. Subsequently, the BDF unit locates the submission queue in which the task descriptor is located in the memory based on the information of the submission queue, and extracts the task descriptor of the data processing task therefrom.

[0090] It should be understood that the embodiments of the present application do not limit the scheduling rule of the QSCH, and in some embodiments, the scheduling rule of the QSCH can be a scheduling rule corresponding to scheduling based on the class of service (CoS) of the data processing task.

[0091] S204, an idle engine is selected as a target engine from a plurality of identical data acceleration processing engines, and the target engine executes the data processing task according to the task descriptor.

[0092] In this step, after the descriptor cache obtaining unit obtains the task descriptor of the data processing task from the memory, the SDAE can select an idle engine as the target engine from the plurality of same data acceleration processing engines, and the target engine executes the data processing task according to the task descriptor.

[0093] It should be understood that the embodiments of the present application do not limit how to select the target engine from the plurality of same data acceleration processing engines. In some embodiments, an idle engine can be determined from the plurality of same data acceleration processing engines according to the state information of the data acceleration processing engines.

[0094] The state information of the data acceleration processing engine is used to indicate that the data acceleration processing engine is in an engine idle state or an engine busy state. The same data acceleration processing engines can be components that are homogeneous, i.e., at least including the same components. The target engine can be a data acceleration processing engine that processes the task descriptor.

[0095] For example, the DPF module can determine the data acceleration processing engines in the engine idle state from the plurality of data acceleration processing engines according to the engine state information. Then, the DPF module performs polling scheduling among all the data acceleration processing engines in the engine idle state, selects one of the data acceleration processing engines in the engine idle state as the target engine, and assigns the task descriptor in the task submission unit (Submitted queue entry, SQE) of the submission queue to the target engine.

[0096] For example, each data acceleration processing engine includes engine state information (engine busy bitmap). The engine busy bitmap can be marked as 1 or 0 by the corresponding bit to represent different engine states. In the case that the engine busy bitmap corresponding bit is marked as 1, it indicates that the data acceleration processing engine is in the engine busy state. In the case that the engine busy bitmap corresponding bit is marked as 0, it indicates that the data acceleration processing engine is in the engine idle state.

[0097] For example, after the task descriptor is assigned to the target engine, the engine busy bitmap corresponding to the target engine can be marked as 1, indicating that it is occupied. After the task descriptor of the target engine is processed, the engine busy bitmap corresponding bit can be marked as 0, indicating that it is idle and can be scheduled.

[0098] In some embodiments, after selecting the target engine, the DPF module can send a resource application request to the two storage resource pools, and the resource application request is used to request storage entries from the two storage resource pools respectively.

[0099] For example, two static random access memories (SRAMs) can be used as the two storage resource pools for caching, so that the dynamic management and scheduling of storage entries can be performed through the two storage resource pools and the corresponding storage entry allocator. Before performing DMA transfer, any data acceleration processing engine can apply for a storage entry from the storage entry allocator, and the storage entry allocator can interleave the allocation of entries of the two storage resource pools to the maximum extent when allocating entries. For example, half of the entries of the two storage resource pools are allocated each time an application is made.

[0100] It should be noted that the storage entry allocator needs to handle the odd number of entry requests and the instantaneous asymmetry of the resources of the two storage resource pools when allocating storage entries. When the SQE processing in the engine is completed and the entry is not needed or is temporarily not needed, the storage entry allocator can also release the entry back to the two storage resource pools.

[0101] It should be understood that the embodiments of the present application do not limit how the target engine performs the data processing task according to the task descriptor. In some embodiments, each data acceleration processing engine can include a descriptor decoding (DSD) unit, a finite state machine (FSM) unit, a read data payload (RDP) unit, and a data compute process unit.

[0102] In some embodiments, the task descriptor can be parsed by the descriptor decoding unit, the data structure of the task descriptor can be determined, the target field can be obtained from the data structure of the task descriptor, and the target field can be encapsulated into a state machine instruction and sent to the state machine unit. According to the instruction type of the state machine instruction, the state machine unit can control the state machine to switch between different states to notify the read data payload unit or the data compute process unit to perform the data processing task.

[0103] For example, the DSD unit can perform parsing of a task descriptor, parsing a data structure of the task descriptor, pre-processing of the task descriptor, extracting a valid target field of the task descriptor to encapsulate into a VLIW instruction word for FSM running, and sending the VLIW instruction word to the FSM. For example, the FSM unit can determine a VLIW instruction type based on the VLIW instruction word, and then control the state machine to switch between different states according to the VLIW instruction type.

[0104] In some embodiments, the states of the state machine include an IDLE state, a read-write control (RWC) state, and a copy-back (CMW) state.

[0105] The IDLE state is a state in which no data processing task is performed. When the state machine is in the RWC state, the state machine unit can notify the read data load unit or the data computation processing unit to perform a data processing task. When the state machine is in the CMW state, the state machine unit can send a completion queue entry (CQE) or an interrupt message corresponding to the data processing task to the queue manager according to copy-back control information.

[0106] For example, after the DPF module performs a data processing task, completes the moving and computation, and receives responses of all copy-back data, the state machine unit can also copy back the CQE to the QM module. After receiving the CQE, the QM module can determine whether to send an interrupt message according to information of the CQE, and if so, send the interrupt message to the application to notify the application to read the CQE.

[0107] FIG. 3 is a state transition diagram of a data acceleration processing engine provided in an embodiment of the present application. As shown in FIG. 3, when the state machine unit receives a state machine instruction, the state machine unit switches the state machine from the IDLE state to the RWC state. When the read data load unit or the data computation processing unit completes a data processing task, the state machine unit switches the state machine from the RWC state to the CMW state. When the target engine receives a feedback message corresponding to the CQE or the interrupt message, the state machine unit switches the state machine from the CMW state to the IDLE state.

[0108] For example, the IDLE state is the initial state of the state machine, and is a state in which no data processing task is performed. After receiving a VLIW, the state machine first jumps from the IDLE state to the RWC state. In the RWC state, the state machine unit invokes the RDP unit and the DCP unit according to the read-write request information and the calculation request information, to complete the functions of responding to data reading, calculation, and write-back. In addition, the state machine unit can control the state machine to jump from the RWC state to the CMW state after the data processing task is completed. In the CMW state, the state machine unit can send a write-back CQE and a Message Signaled Interrupts (MSI) request to the QM module, and control the state machine to jump from the CMW state to the IDLE state after the QM module updates the CQE to a completion queue manager (CQM) and generates a feedback message.

[0109] In some embodiments, the read data load unit is configured to, when the state machine is in the read-write control state, notify the DMA unit to perform data transfer according to the read data request information, to perform the data processing task. The data calculation processing unit is configured to, when the state machine is in the read-write control state, perform a data calculation operation in the data processing task by using an arithmetic and logic unit (ALU) component according to the calculation request information, and the data calculation processing unit is further configured to, according to the write data request information, notify the DMA unit to perform data transfer by using a write data process (WDP) component, to perform the data processing task.

[0110] It should be noted that, from the perspective of hardware implementation, different data processing operations can be normalized into the target engine allocated to perform the operations, and different operations call ALU components or WDP components in different DCP units to implement corresponding functions, so that the data acceleration processing engine has versatility.

[0111] In some embodiments, the queue manager and the data acceleration processing engine each maintain an inversion indication information. The queue manager marks the task descriptor by using the inversion indication information, and sends the task descriptor marked by the inversion indication information to the target engine.

[0112] In some embodiments, the inversion indication information marked by the task descriptor received by the target engine can be the same as the inversion indication information maintained by the data acceleration processing engine, or can be different from the inversion indication information maintained by the data acceleration processing engine.

[0113] In case that the received task descriptor marked reverse indication information is same as the reverse indication information maintained by the data acceleration processing engine, the target engine executes the data processing task according to the task descriptor. After the data processing task is executed, the target engine generates a task completion unit CQE and sends the task completion unit CQE back to the queue manager. The queue manager updates the task completion unit CQE into a task completion queue (CQ).

[0114] In case that the received task descriptor marked reverse indication information is different from the reverse indication information maintained by the data acceleration processing engine, the target engine gives up executing the data processing task, generates a task completion unit CQE and sends the task completion unit CQE back to the queue manager; the queue manager does not update the task completion unit CQE into the task completion queue CQ.

[0115] The reverse indication information can be a preset signal (for example, rb_toggle_flg). For example, the QM module needs to mark the task descriptor with the reverse indication information when sending the task descriptor to the DPF module. For example, the initial value of the reverse indication information marked can be 0, and the value of the reverse indication information marked can be changed from 0 to 1 when flipping, or the value of the reverse indication information marked can be changed from 1 to 0 when flipping. It should be noted that the initial values of the reverse indication information marked by the queue manager and the data acceleration processing engine are the same at the initial time.

[0116] The following describes how to process the data processing task and schedule the current queue based on the fence identifier in case that the received task descriptor marked reverse indication information is same as the reverse indication information maintained by the data acceleration processing engine.

[0117] In some embodiments, in case that the received task descriptor carries the fence identifier, and the current queue has other in-transit task descriptors that have not been processed by the data acceleration processing engine, the target engine inverts the reverse indication information maintained by the data acceleration processing engine. Then, the target engine generates a rollback request and sends the rollback request to the queue manager. Finally, the queue manager waits for the data acceleration processing engine to process the other in-transit task descriptors, and then starts scheduling the current queue from the task descriptor carrying the fence identifier.

[0118] The rollback request is used to instruct the queue manager to stop scheduling the current queue, and the rollback request includes address information of the task descriptor carrying the fence identifier.

[0119] In some embodiments, when it is identified that the received task descriptor carries a fence identifier, and there is no other inflight task descriptor in the current queue that has not been processed by the data acceleration processing engine, the target engine executes the data processing task according to the received task descriptor. Subsequently, after the execution of the task, the target engine generates a task completion unit and sends the task completion unit back to the queue manager. Finally, the queue manager updates the task completion unit into the task completion queue.

[0120] wherein the other inflight task descriptor refers to the task descriptor that has not been processed by the data acceleration processing engine, among the task descriptors that have been dispatched out of the current queue and sent to the data acceleration processing engine for processing, except for the task descriptor carrying the fence identifier.

[0121] wherein the fence identifier is used to restrict the execution order of the task descriptors issued by the software, and separate the task descriptors or data processing tasks that are executed first from those that are executed later. The task descriptor executed first cannot be executed after the task descriptor executed later is executed, and the task descriptor executed later cannot be executed before the task descriptor executed first.

[0122] For example, when it is identified that the received task descriptor carries a fence identifier, and there is other inflight task descriptor in the current queue that has not been processed by the data acceleration processing engine (i.e., there is inflight SQE), the target engine inverts the reverse indication information maintained by the data acceleration processing engine, generates a rollback request and sends the rollback request to the queue manager. After the data acceleration processing engine processes the other inflight task descriptor, the queue manager starts to dispatch the current queue from the task descriptor carrying the fence identifier in a pointer rollback manner.

[0123] For example, when it is identified that the received task descriptor carries a fence identifier, and there is no other inflight task descriptor in the current queue that has not been processed by the data acceleration processing engine (i.e., there is no inflight SQE), the target engine processes according to the normal process, i.e., the target engine executes the data processing task according to the received task descriptor. After the execution of the data processing task, the target engine generates a task completion unit CQE and sends the task completion unit CQE back to the queue manager. The queue manager updates the task completion unit CQE into the task completion queue.

[0124] In the present application, the target engine can determine the order of data processing tasks and determine whether to back off according to whether the fence identifier is carried in the task descriptor and whether there is another in-transit task descriptor that has not been processed by the data acceleration processing engine. Thus, the out-of-order situation of multiple channels in the data moving process can be solved within a certain range. When the software does not have a data preservation requirement, the fence identifier can not be used for preservation, so as to support more concurrency and improve performance.

[0125] In some embodiments, the data processing task includes a batch processing task, the batch processing task includes a plurality of subtasks, and the batch processing task includes packet tail indication information, which is used to indicate the last subtask in the batch processing task. The task completion unit corresponding to the batch processing task can be triggered after the last subtask is executed.

[0126] For example, the data processing task includes a batch task, which is continuously stored in the SQ, and the batch task further includes End Of Packet (EOP) indication information, which is used to mark the last subtask of the batch task. Accordingly, the QM can write the CQE of the batch task after all the subtasks are processed.

[0127] For example, the different subtasks of the batch task have no sequence relationship and can be distributed to different data acceleration processing engines for processing in parallel.

[0128] In some embodiments, similar to the non-batch task, the QM module in the present application embodiment does not continuously read all the subtasks of the batch task. In the case where the task descriptor corresponding to each subtask of the batch task further carries a fence identifier, the order of the subtasks can also be determined according to the fence identifier carried by the task descriptor corresponding to the subtask of the batch task when the subtask of the batch task is read.

[0129] In some embodiments, in order to enable the data acceleration processing engine to support the batch task without additional logical algorithms, the last subtask of the batch task can be set as a no operation (NOP) instruction, and a corresponding CQE can be generated. Meanwhile, a fence identifier can be set as valid, and the task descriptors corresponding to each subtask of the batch task can carry the fence identifier, so that each subtask is executed in sequence. In this application, since the data acceleration processing engine of the SDAE can support the batch task, centralized data collection within a specific range can be supported, and the centralized collected data can be divided into multiple subtasks for reporting through the batch task, so that the CPU load can be reduced.

[0130] In addition, the data acceleration processing method provided by the embodiments of the present application greatly improves the performance of data migration (for example, only 16 cycles are required to complete a data migration), which exceeds the performance requirement of the CPU, thereby meeting the requirement of the CPU for data migration.

[0131] The data acceleration processing method provided by the embodiments of the present application first receives a trigger message of a data processing task, the trigger message including pointer information of a queue, the pointer information of the queue being address information of the queue in a memory, and the queue being used to store a task descriptor of the data processing task. Secondly, the pointer information of the queue is updated to a queue manager for scheduling by a queue scheduler. Thirdly, when the queue is selected by the queue scheduler, the pointer information of the queue is transmitted to a descriptor cache acquisition unit to notify the descriptor cache acquisition unit to acquire the task descriptor of the data processing task from the memory. Finally, an idle engine is selected from a plurality of same data acceleration processing engines as a target engine, and the target engine executes the data processing task according to the task descriptor. Since an idle target engine can be directly selected from a plurality of same data acceleration processing engines to process the task descriptor of the data processing task issued by the system software, the data processing can be completed by relying on the hardware of the data acceleration processing engine itself, without CPU instruction processing, so that the data acceleration processing method provided by the present application has low CPU resource consumption, high efficiency, and general applicability.

[0132] The following describes how to execute the data processing task. FIG. 4 is a flowchart of another data acceleration processing method provided by the embodiments of the present application. As shown in FIG. 4, the data acceleration processing method includes steps S301 to S307.

[0133] S301, receiving a trigger message of a data processing task, the trigger message including pointer information of a queue, the pointer information of the queue being address information of the queue in a memory, and the queue being used to store a task descriptor of the data processing task.

[0134] S302, update the pointer information of the queue to the queue manager for scheduling by the queue scheduler.

[0135] S303, when the queue is selected by the queue scheduler, pass the pointer information of the queue to the descriptor cache obtaining unit to notify the descriptor cache obtaining unit to obtain the task descriptor of the data processing task from the memory.

[0136] S304, select an idle engine as a target engine from a plurality of same data acceleration processing engines.

[0137] S305, parse the task descriptor by the descriptor parsing unit to determine the data structure of the task descriptor.

[0138] S306, obtain the target field from the data structure of the task descriptor by the descriptor parsing unit, and encapsulate the target field into a state machine instruction and send it to the state machine unit.

[0139] S307, control the state machine to switch between different states according to the instruction type of the state machine instruction by the state machine unit, to notify the read data payload unit or the data calculation processing unit to execute the data processing task.

[0140] The following describes how to process the task descriptor carrying the fence information. FIG. 5 is a flowchart of another data acceleration processing method provided by an embodiment of the present application. As shown in FIG. 5, the data acceleration processing method includes steps S401 to S411.

[0141] S401, receive a trigger message of a data processing task, the trigger message including pointer information of a queue, the pointer information of the queue being address information of the queue in the memory, and the queue being used to store a task descriptor of the data processing task.

[0142] S402, update the pointer information of the queue to the queue manager for scheduling by the queue scheduler.

[0143] S403, when the queue is selected by the queue scheduler, pass the pointer information of the queue to the descriptor cache obtaining unit to notify the descriptor cache obtaining unit to obtain the task descriptor of the data processing task from the memory.

[0144] S404, determine whether the inversion indication information of the task descriptor flag is same as the inversion indication information maintained by the data acceleration processing engine.

[0145] If yes, execute S405, and if no, execute S409.

[0146] S405, the target engine executes the data processing task according to the task descriptor.

[0147] S406, after the data processing task is executed, the target engine generates a task completion unit.

[0148] S407, the task completion unit is sent back to the queue manager.

[0149] S408, the queue manager updates the task completion unit to the task completion queue.

[0150] S409, the target engine abandons the execution of the data processing task and generates a task completion unit.

[0151] S410, the target engine sends the task completion unit back to the queue manager.

[0152] S411, the queue manager does not update the task completion unit in the task completion queue.

[0153] In some embodiments, when the received task descriptor is marked with the reverse indication information and the reverse indication information maintained by the data acceleration processing engine is the same, in the case of identifying that the received task descriptor carries the barrier identifier, and the current queue exists other in-transit task descriptors which are not processed by the data acceleration processing engine, the target engine inverts the reverse indication information maintained by the data acceleration processing engine; the target engine generates a rollback request and sends the rollback request to the queue manager, the rollback request is used to instruct the queue manager to stop scheduling the current queue, and the rollback request includes address information of the task descriptor carrying the barrier identifier; the queue manager waits for the data acceleration processing engine to process the other in-transit task descriptors, and then starts to schedule the current queue from the task descriptor carrying the barrier identifier.

[0154] In the case of identifying that the received task descriptor carries the barrier identifier, and the current queue does not exist other in-transit task descriptors which are not processed by the data acceleration processing engine, the target engine executes the data processing task according to the received task descriptor; after executing the task, the target engine generates a task completion unit and sends the task completion unit back to the queue manager; the queue manager updates the task completion unit to the task completion queue.

[0155] The data acceleration processing method provided in the embodiments of the present application first receives a trigger message of a data processing task, the trigger message comprising pointer information of a queue, the pointer information of the queue being address information of the queue in a memory, and the queue being used to store a task descriptor of the data processing task. Secondly, the pointer information of the queue is updated to a queue manager, for scheduling by a queue scheduler. Thirdly, when the queue is selected by the queue scheduler, the pointer information of the queue is transmitted to a descriptor cache acquisition unit, to notify the descriptor cache acquisition unit to acquire the task descriptor of the data processing task from the memory. Finally, an idle engine is selected from a plurality of same data acceleration processing engines as a target engine, and the target engine executes the data processing task according to the task descriptor. Since an idle target engine can be directly selected from the plurality of same data acceleration processing engines to process the task descriptor of the data processing task issued by system software, the data processing can be completed by relying on the hardware of the data acceleration processing engine itself, without the need of CPU instruction processing, so that the data acceleration processing method provided in the present application has low CPU resource consumption, high efficiency, and general applicability.

[0156] It should be understood that, although each step in the flowchart involved in the above embodiments is shown in sequence according to the arrow, these steps are not necessarily executed in sequence according to the arrow. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least part of the steps in the flowchart involved in the above embodiments can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or steps or stages in other steps.

[0157] Based on the same concept, the embodiments of the present application also provide a data acceleration processing device for implementing the above-mentioned data acceleration processing method. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme described in the above method, so the specific limitations in one or more data acceleration processing device embodiments provided below can refer to the limitations of the data acceleration processing method in the foregoing, which will not be repeated here.

[0158] In an exemplary embodiment, as shown in FIG. 6, a data acceleration processing device 500 is provided, comprising a queue management module 501 and a data acceleration processing module 502, wherein:

[0159] The queue management module 501 is configured to receive a trigger message of a data processing task, the trigger message comprising pointer information of a queue, the pointer information of the queue being address information of the queue in the memory, the queue being configured to store a task descriptor of the data processing task; update the pointer information of the queue to a queue manager, so as to be scheduled by a queue scheduler; and when the queue is selected by the queue scheduler, deliver the pointer information of the queue to a descriptor cache acquisition unit, so as to notify the descriptor cache acquisition unit to acquire the task descriptor of the data processing task from the memory.

[0160] The data acceleration processing module 502 is configured to select an idle engine from a plurality of same data acceleration processing engines as a target engine, and execute the data processing task by the target engine according to the task descriptor.

[0161] In one embodiment, the data acceleration processing engine comprises a descriptor parsing unit, a state machine unit, a read data payload unit, or a data calculation processing unit.

[0162] The data acceleration processing module 502 is further configured to parse the task descriptor by the descriptor parsing unit, determine a data structure of the task descriptor, acquire a target field from the data structure of the task descriptor by the descriptor parsing unit, encapsulate the target field into a state machine instruction, and send the state machine instruction to the state machine unit; and control the state machine to switch between different states according to an instruction type of the state machine instruction by the state machine unit, so as to notify the read data payload unit or the data calculation processing unit to execute the data processing task.

[0163] In one embodiment, the states of the state machine comprise an idle state, a read-write control state, and a write-back state; and the idle state is a state in which the data processing task is not executed.

[0164] The data acceleration processing module 502 is further configured to, when the state machine is in the read-write control state, notify the read data payload unit or the data calculation processing unit to execute the data processing task by the state machine unit; and when the state machine is in the write-back state, send a task completion unit or an interrupt message corresponding to the data processing task to the queue manager according to write-back control information by the state machine unit.

[0165] In one embodiment, the data acceleration processing module 502 is further configured to, when the state machine unit receives the state machine instruction, switch the state machine from the idle state to the read-write control state by the state machine unit; when the read data payload unit or the data calculation processing unit completes the data processing task, switch the state machine from the read-write control state to the write-back state by the state machine unit; and when the target engine receives a feedback message corresponding to the task completion unit or the interrupt message, switch the state machine from the write-back state to the idle state by the state machine unit.

[0166] In one of the embodiments, the read data payload unit is configured to, when the state machine is in the read-write control state, notify the DMA unit to perform data transfer according to the read data request information, so as to execute the data processing task.

[0167] The data computation processing unit is configured to, when the state machine is in the read-write control state, execute data computation operation in the data processing task by the ALU according to the computation request information, and notify the DMA unit to perform data transfer by the write data processing unit according to the write data request information, so as to execute the data processing task.

[0168] In one of the embodiments, the operation domain segment is included in the task descriptor, and the operation domain segment is configured to indicate at least one data processing operation in the data processing task.

[0169] In one of the embodiments, the queue manager and the data acceleration processing engine maintain a reverse indication information respectively.

[0170] The queue management module 501 is further configured to mark the task descriptor by the reverse indication information, and send the task descriptor marked by the reverse indication information to the target engine.

[0171] The data acceleration processing module 502 is further configured to, when the reverse indication information marked by the received task descriptor is same as the reverse indication information maintained by the data acceleration processing engine, execute the data processing task according to the task descriptor by the target engine; after the data processing task is executed, generate a task completion unit by the target engine, and send the task completion unit back to the queue manager; and update the task completion unit to the task completion queue by the queue manager.

[0172] The data acceleration processing module 502 is further configured to, when the reverse indication information marked by the received task descriptor is different from the reverse indication information maintained by the data acceleration processing engine, abandon to execute the data processing task, generate a task completion unit, and send the task completion unit back to the queue manager; and the queue manager does not update the task completion unit to the task completion queue.

[0173] In one of the embodiments, in the case that the received task descriptor carries the barrier identifier, and the current queue does not have other in-transit task descriptors that are not processed by the data acceleration processing engine, the target engine executes the data processing task according to the received task descriptor; after the execution of the task, the target engine generates a task completion unit and sends the task completion unit back to the queue manager; and the queue manager updates the task completion unit into the task completion queue.

[0174] In the case that the received task descriptor carries the barrier identifier, and the current queue does not have other in-transit task descriptors that are not processed by the data acceleration processing engine, the target engine executes the data processing task according to the received task descriptor; after the execution of the task, the target engine generates a task completion unit and sends the task completion unit back to the queue manager; and the queue manager updates the task completion unit into the task completion queue.

[0175] In one of the embodiments, the data processing task includes a batch processing task, the batch processing task includes a plurality of subtasks, the batch processing task includes message tail indication information, the message tail indication information is used to indicate the last subtask in the batch processing task, and the task completion unit corresponding to the batch processing task is triggered after the execution of the last subtask is completed.

[0176] In one of the embodiments, the task descriptor includes at least one of the following information: a source address of task data, a destination address of the task data, an operator of the task data, and a data volume of the task data.

[0177] The above data acceleration processing apparatus can be implemented by software, hardware, or a combination thereof. The above modules can be embedded in or independent of a processor in a computer device in a hardware form, or stored in a memory in a computer device in a software form, so as to be called and executed by a processor to perform the operations of the above modules.

[0178] In an embodiment, a computer device is provided, which can be a server, the server configures a network interface card, the network interface card includes a chip, the chip can implement the data acceleration processing method described above. The internal structure diagram of the server can be as shown in FIG. 7. The computer device includes a processor, a memory, an input / output interface (I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The input / output interface of the computer device is used to exchange information between the processor and external devices. The communication interface of the computer device is used to communicate with the terminal outside through the network connection.

[0179] Those skilled in the art can understand that the structure shown in FIG. 7 is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or less components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0180] In an exemplary embodiment, the present application also provides a chip including a memory and a processor, the memory stores a computer program, and the processor implements the data acceleration processing method described above when executing the computer program.

[0181] In an exemplary embodiment, the present application also provides a network interface card, the network interface card includes the chip described above and a plurality of interfaces, such as PCI / PCIE interface, network interface, etc., and the chip communicates with the outside through the interface.

[0182] In an exemplary embodiment, the present application also provides a computer device, the computer device includes a processor and the network interface card described above, the network interface card is used to schedule messages to the processor or the network interface card itself for processing, and the processor is used to process the messages scheduled by the network interface card.

[0183] In an exemplary embodiment, a computer readable storage medium is provided, which stores a computer program, and the computer program is executed by the processor to implement the data acceleration processing method described above.

[0184] In one example embodiment, a computer program product is provided, comprising a computer program which, when executed by a processor, implements the above-mentioned data acceleration processing method.

[0185] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, the computer program can include the processes of the above-mentioned embodiment methods. Any reference to a memory, a database or other medium used in the embodiments provided in the present application can include at least one of a non-volatile memory and a volatile memory. The non-volatile memory can include a read-only memory (ROM), a magnetic tape, a floppy disk, a flash memory, an optical storage, a high-density embedded non-volatile memory, a resistive random access memory (ReRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a graphene memory, etc. The volatile memory can include a random access memory (RAM) or an external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., without being limited thereto.

[0186] Any combination of the technical features of the above-mentioned embodiments can be made. In order to make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as the combination of the technical features does not exist, it should be considered as the scope of the present application.

[0187] The above embodiments only express several implementation ways of the present application, and the description is specific and detailed, but it should not be understood as a limitation to the patent scope of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method of data acceleration processing, the method comprising: The method comprises: receiving a trigger message of a data processing task, wherein the trigger message comprises pointer information of a queue, the pointer information of the queue being address information of the queue in memory, and the queue being used for storing a task descriptor of the data processing task; updating the pointer information of the queue into a queue manager for scheduling by a queue scheduler; when the queue is selected by the queue scheduler, passing the pointer information of the queue to a descriptor cache acquisition unit to inform the descriptor cache acquisition unit to acquire the task descriptor of the data processing task from the memory; selecting an idle engine as a target engine from a plurality of same data acceleration processing engines, and executing the data processing task by the target engine according to the task descriptor.

2. The method of claim 1, wherein, The data acceleration processing engine comprises a descriptor parsing unit, a state machine unit, a read data load unit and a data calculation processing unit, and the execution of the data processing task by the target engine according to the task descriptor comprises: parsing the task descriptor by the descriptor parsing unit to determine the data structure of the task descriptor; acquiring a target field from the data structure of the task descriptor by the descriptor parsing unit, and encapsulating the target field into a state machine instruction and sending the state machine instruction to the state machine unit; controlling the state machine to switch between different states according to the instruction type of the state machine instruction, so as to inform the read data load unit or the data calculation processing unit to execute the data processing task.

3. The method of claim 2, wherein, The states of the state machine comprise an idle state, a read-write control state and a write-back state; the idle state is a state in which the data processing task is not executed; the informing the read data load unit or the data calculation processing unit to execute the data processing task comprises: when the state machine is in the read-write control state, informing the read data load unit or the data calculation processing unit to execute the data processing task by the state machine unit; when the state machine is in the write-back state, sending a task completion unit or an interrupt message corresponding to the data processing task to the queue manager according to write-back control information by the state machine unit.

4. The method of claim 3, wherein, The controlling the state machine to switch between different states comprises: when the state machine unit receives the state machine instruction, switching the state machine from the idle state to the read-write control state by the state machine unit; when the read data load unit or the data calculation processing unit completes the data processing task, switching the state machine from the read-write control state to the write-back state by the state machine unit; when the target engine receives a feedback message corresponding to the task completion unit or the interrupt message, switching the state machine from the write-back state to the idle state by the state machine unit.

5. The method of claim 3, wherein, The read data load unit is configured to, when the state machine is in the read-write control state, inform a direct memory access unit to perform data transfer according to read data request information of the state machine unit, so as to execute the data processing task. The data computing processing unit is configured to, when the state machine is in the read-write control state, perform a data computing operation in the data processing task according to computing request information of the state machine unit through an arithmetic logic component; and perform data carrying according to write data request information of the state machine unit through a write data processing component to notify the direct memory access unit to perform the data processing task.

6. The method of claim 1, wherein, The task descriptor comprises an operation domain segment, which is used to indicate at least one data processing operation in the data processing task.

7. The method of claim 1, wherein, The queue manager and the data acceleration processing engine maintain an inversion indication information respectively, and the method further comprises: The queue manager marks the task descriptor with the inversion indication information and sends the task descriptor marked with the inversion indication information to the target engine; When the inversion indication information marked by the received task descriptor is the same as the inversion indication information maintained by the data acceleration processing engine, the target engine executes the data processing task according to the task descriptor; after the execution of the data processing task is completed, the target engine generates a task completion unit and sends the task completion unit back to the queue manager; and the queue manager updates the task completion unit to the task completion queue; When the inversion indication information marked by the received task descriptor is different from the inversion indication information maintained by the data acceleration processing engine, the target engine gives up to execute the data processing task, generates a task completion unit and sends the task completion unit back to the queue manager; and the queue manager does not update the task completion unit to the task completion queue.

8. The method of claim 7, wherein, When the inversion indication information marked by the received task descriptor is the same as the inversion indication information maintained by the data acceleration processing engine, the method further comprises: When it is identified that the received task descriptor carries a barrier identifier and the current queue has other in-transit task descriptors that have not been processed by the data acceleration processing engine, the target engine inverts the inversion indication information maintained by the data acceleration processing engine; the target engine generates a rollback request and sends the rollback request to the queue manager, the rollback request being used to instruct the queue manager to stop scheduling the current queue, the rollback request comprising address information of the task descriptor carrying the barrier identifier; and the queue manager waits until the data acceleration processing engine processes the other in-transit task descriptors, and then resumes scheduling the current queue from the task descriptor carrying the barrier identifier; When it is identified that the received task descriptor carries a barrier identifier and the current queue has no other in-transit task descriptors that have not been processed by the data acceleration processing engine, the target engine executes the data processing task according to the received task descriptor; after the execution of the task is completed, the target engine generates a task completion unit and sends the task completion unit back to the queue manager; and the queue manager updates the task completion unit to the task completion queue.

9. The method of claim 1, wherein, The data processing task includes a batch processing task, the batch processing task includes a plurality of subtasks, the batch processing task includes message tail indication information, and the message tail indication information is used to indicate a last subtask in the batch processing task. The task completion unit corresponding to the batch processing task is triggered after the last subtask is executed.

10. The method according to any one of claims 1 to 9, characterized in that, The task descriptor includes at least one of the following information: A source address of task data, a destination address of the task data, an operator of the task data, and a data volume of the task data.

11. A data processing acceleration device, comprising: The device includes: A queue management module, configured to receive a trigger message of a data processing task, the trigger message including pointer information of a queue, the pointer information of the queue being address information of the queue in a memory, the queue being used to store a task descriptor of the data processing task; update the pointer information of the queue to a queue manager for scheduling by a queue scheduler; and when the queue is selected by the queue scheduler, pass the pointer information of the queue to a descriptor cache acquisition unit to notify the descriptor cache acquisition unit to acquire the task descriptor of the data processing task from the memory. A data processing acceleration module, configured to select an idle engine as a target engine from a plurality of same data acceleration processing engines, and execute the data processing task according to the task descriptor by the target engine.

12. A chip, characterized by A computer device includes a memory and a processor, and the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any one of claims 1 to 10.

13. A network interface card, comprising: The network interface card includes the chip and a plurality of interfaces, and the chip communicates with the outside through the interfaces.

14. A computer device, comprising: The computer device includes a processor and the network interface card in claim 13, the network interface card is used to schedule a message to the processor or the network interface card itself to process, and the processor is used to process the message scheduled by the network interface card.

15. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 10.

16. A computer program product comprising a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 10.

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