Amplifier, amplification control method, and storage circuit

Abstract

The application provides an amplifier, an amplification control method and a storage circuit. The amplifier comprises a first node, a second node, a first control circuit, a second control circuit, a third control circuit and a fourth control circuit; the third control circuit controls the communication or disconnection between the third node and the first voltage end under the control of a first control signal provided by the first control end; the fourth control circuit controls the communication or disconnection between the fourth node and the second voltage end under the control of a second control signal provided by the second control end; the transistor included in the third control circuit and the transistor included in the fourth control circuit are oxide transistors. By setting the transistor included in the third control circuit and the transistor included in the fourth control circuit as oxide transistors, the leakage current of the amplifier can be reduced, and the power consumption can be reduced.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to an amplifier, an amplification control method, and a storage circuit. Background Technology

[0002] In related technologies, flexible sensing, near-memory computing, and in-memory computing all require storage circuits. The sensitive amplifiers included in the storage circuits suffer from problems such as large leakage current and high power consumption. Summary of the Invention

[0003] The main objective of this invention is to provide an amplifier, an amplification control method, and a storage circuit to solve the problems of high leakage current and high power consumption in existing storage circuits, including sensitive amplifiers.

[0004] This invention provides an amplifier, including a first node, a second node, a first control circuit, a second control circuit, a third control circuit, and a fourth control circuit;

[0005] The first control circuit is electrically connected to the first node, the second node, the third node and the fourth node respectively, and is used to control the connection or disconnection between the second node and the third node, and to control the connection or disconnection between the second node and the fourth node under the control of the potential of the first node;

[0006] The second control circuit is electrically connected to the first node, the second node, the third node and the fourth node respectively, and is used to control the connection or disconnection between the first node and the third node, and the connection or disconnection between the first node and the fourth node under the control of the potential of the second node;

[0007] The third control circuit is electrically connected to the first control terminal, the first voltage terminal and the third node respectively, and is used to control the connection or disconnection between the third node and the first voltage terminal under the control of the first control signal provided by the first control terminal.

[0008] The fourth control circuit is electrically connected to the second control terminal, the second voltage terminal and the fourth node respectively, and is used to control the connection or disconnection between the fourth node and the second voltage terminal under the control of the second control signal provided by the second control terminal;

[0009] The transistors included in the third control circuit and the transistors included in the fourth control circuit are oxide transistors.

[0010] Optionally, the third control circuit includes a first transistor, and the fourth control circuit includes a second transistor;

[0011] The gate of the first transistor is electrically connected to the first control terminal, the first terminal of the first transistor is electrically connected to the first voltage terminal, and the second terminal of the first transistor is electrically connected to the third node.

[0012] The gate of the second transistor is electrically connected to the second control terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the second voltage terminal.

[0013] Both the first transistor and the second transistor are oxide transistors.

[0014] Optionally, the amplifier described in at least one embodiment of the present invention further includes a fifth control circuit and a sixth control circuit;

[0015] The fifth control circuit is electrically connected to the first node, the second node, and the fourth node respectively, and is used to control the connection or disconnection between the second node and the fourth node under the control of the potential of the first node;

[0016] The sixth control circuit is electrically connected to the first node, the second node, and the fourth node respectively, and is used to control the connection or disconnection between the first node and the fourth node under the control of the potential of the second node.

[0017] Optionally, the fifth control circuit includes a third transistor, and the sixth control circuit includes a fourth transistor;

[0018] The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the fourth node.

[0019] The gate of the fourth transistor is electrically connected to the second node, the first terminal of the fourth transistor is electrically connected to the first node, and the second terminal of the fourth transistor is electrically connected to the fourth node.

[0020] Optionally, both the third transistor and the fourth transistor are oxide transistors.

[0021] Optionally, the amplifier described in at least one embodiment of the present invention further includes a first switch control circuit and a second switch control circuit;

[0022] The first switch control circuit is electrically connected to the first switch control terminal, the first input terminal, and the first node, respectively, and is used to control the connection or disconnection between the first input terminal and the first node under the control of the first switch control signal provided by the first switch control terminal;

[0023] The second switch control circuit is electrically connected to the second switch control terminal, the second input terminal, and the second node, respectively, and is used to control the connection or disconnection between the second input terminal and the second node under the control of the second switch control signal provided by the second switch control terminal.

[0024] Optionally, the first switch control circuit includes a fifth transistor, and the second switch control circuit includes a sixth transistor;

[0025] The gate of the fifth transistor is electrically connected to the first switch control terminal, the first electrode of the fifth transistor is electrically connected to the first input terminal, and the second electrode of the fifth transistor is electrically connected to the first node.

[0026] The gate of the sixth transistor is electrically connected to the second switch control terminal, the first terminal of the sixth transistor is electrically connected to the second input terminal, and the second terminal of the sixth transistor is electrically connected to the second node.

[0027] Optionally, the first control circuit includes a seventh transistor and an eighth transistor, and the second control circuit includes a ninth transistor and a tenth transistor.

[0028] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the third node, and the second electrode of the seventh transistor is electrically connected to the second node.

[0029] The gate of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0030] The gate of the ninth transistor is electrically connected to the second node, the first terminal of the ninth transistor is electrically connected to the third node, and the second terminal of the ninth transistor is electrically connected to the first node.

[0031] The gate of the tenth transistor is electrically connected to the second node, the first terminal of the tenth transistor is electrically connected to the first node, and the second terminal of the tenth transistor is electrically connected to the fourth node.

[0032] Optionally, the seventh transistor and the ninth transistor are both p-type transistors, and the eighth transistor and the tenth transistor are both n-type transistors.

[0033] Optionally, the amplifier further includes a fifth control circuit and a sixth control circuit, the fifth control circuit including a third transistor and the sixth control circuit including a fourth transistor;

[0034] The threshold voltage of the eighth transistor is less than the threshold voltage of the third transistor, and the threshold voltage of the tenth transistor is less than the threshold voltage of the fourth transistor.

[0035] Optionally, the third control circuit includes a first transistor, and the fourth control circuit includes a second transistor;

[0036] The aspect ratio of the first transistor is greater than that of the seventh transistor, the aspect ratio of the first transistor is greater than that of the eighth transistor, the aspect ratio of the first transistor is greater than that of the ninth transistor, and the aspect ratio of the first transistor is greater than that of the tenth transistor.

[0037] The aspect ratio of the second transistor is greater than that of the seventh transistor, the aspect ratio of the second transistor is greater than that of the eighth transistor, the aspect ratio of the second transistor is greater than that of the ninth transistor, and the aspect ratio of the second transistor is greater than that of the tenth transistor.

[0038] The aspect ratio of the eighth transistor is smaller than that of the seventh transistor, and the aspect ratio of the tenth transistor is smaller than that of the ninth transistor.

[0039] This invention also provides an amplification control method applied to the aforementioned amplifier, the amplification control method comprising:

[0040] The first control circuit, under the control of the potential of the first node, controls the connection or disconnection between the second node and the third node, and controls the connection or disconnection between the second node and the fourth node.

[0041] The second control circuit, under the control of the potential of the second node, controls the connection or disconnection between the first node and the third node, and controls the connection or disconnection between the first node and the fourth node.

[0042] The third control circuit, under the control of the first control signal, controls the connection or disconnection between the third node and the first voltage terminal;

[0043] The fourth control circuit, under the control of the second control signal, controls the connection or disconnection between the fourth node and the second voltage terminal.

[0044] Optionally, the amplifier further includes a first switch control circuit and a second switch control circuit; the amplification period includes an input stage and an amplification stage set sequentially.

[0045] The amplification control method further includes:

[0046] During the input phase, the first switch control circuit, under the control of the first switch control signal, controls the connection between the first input terminal and the first node; the second switch control circuit, under the control of the second switch control signal, controls the connection between the second input terminal and the second node.

[0047] During the amplification stage, the first switch control circuit, under the control of the first switch control signal, controls the first input terminal to disconnect from the first node; the second switch control circuit, under the control of the second switch control signal, controls the second input terminal to disconnect from the second node.

[0048] Optionally, the amplification control method described in at least one embodiment of the present invention further includes: during the amplification stage, a third control circuit controls the connection between the third node and the first voltage terminal under the control of the first control signal, and a fourth control circuit controls the connection between the fourth node and the second voltage terminal under the control of the second control signal;

[0049] During the scaling-up stage,

[0050] When the potential of the first node is the third voltage and the potential of the second node is the fourth voltage, the first control circuit controls the connection between the second node and the third node under the control of the potential of the first node, and the second control circuit controls the connection between the first node and the fourth node under the control of the potential of the second node.

[0051] When the potential of the first node is the fourth voltage and the potential of the second node is the third voltage, the first control circuit controls the connection between the second node and the fourth node under the control of the potential of the first node, and the second control circuit controls the connection between the first node and the third node under the control of the potential of the second node.

[0052] This invention also provides a storage circuit, including the amplifier described above.

[0053] The amplifier, amplification control method, and storage circuit described in this embodiment of the invention can reduce the leakage current of the amplifier and lower power consumption by setting the transistors included in the third control circuit and the fourth control circuit as oxide transistors. Attached Figure Description

[0054] Figure 1 This is a structural diagram of the amplifier according to at least one embodiment of the present invention;

[0055] Figure 2 This is a structural diagram of the amplifier according to at least one embodiment of the present invention;

[0056] Figure 3 This is a structural diagram of the amplifier according to at least one embodiment of the present invention;

[0057] Figure 4 This is a circuit diagram of the amplifier according to at least one embodiment of the present invention;

[0058] Figure 5 This is a circuit diagram of the amplifier according to at least one embodiment of the present invention;

[0059] Figure 6 This is a structural diagram of the storage circuit according to at least one embodiment of the present invention. Detailed Implementation

[0060] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal, and the other as the second terminal.

[0062] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0063] like Figure 1 As shown, the amplifier described in this embodiment of the invention includes a first node BIT, a second node BIT#, a first control circuit 11, a second control circuit 12, a third control circuit 13, and a fourth control circuit 14.

[0064] The first control circuit 11 is electrically connected to the first node BIT, the second node BIT#, the third node N3 and the fourth node N4 respectively, and is used to control the connection or disconnection between the second node BIT# and the third node N3, and to control the connection or disconnection between the second node BIT# and the fourth node N4 under the control of the potential of the first node BIT.

[0065] The second control circuit 12 is electrically connected to the first node BIT, the second node BIT#, the third node N3 and the fourth node N4 respectively, and is used to control the connection or disconnection between the first node BIT and the third node N3, and to control the connection or disconnection between the first node BIT and the fourth node N4 under the control of the potential of the second node BIT#.

[0066] The third control circuit 13 is electrically connected to the first control terminal SE#, the first voltage terminal V1 and the third node N3 respectively, and is used to control the connection or disconnection between the third node N3 and the first voltage terminal V1 under the control of the first control signal provided by the first control terminal SE#.

[0067] The fourth control circuit 14 is electrically connected to the second control terminal SE, the second voltage terminal V2 and the fourth node N4 respectively, and is used to control the connection or disconnection between the fourth node N4 and the second voltage terminal V2 under the control of the second control signal provided by the second control terminal SE.

[0068] The amplifier described in this embodiment of the invention reduces leakage current and power consumption by setting the transistors included in the third control circuit 13 and the fourth control circuit 14 as oxide transistors.

[0069] In at least one embodiment of the present invention, the amplifier may be a sensitive amplifier, and the amplifier may be applied to SRAM (Static Random-Access Memory), but is not limited thereto.

[0070] When the amplifier described in this embodiment of the invention is working, during the amplification stage, the third control circuit 13 controls the connection between the third node N3 and the first voltage terminal V1 under the control of the first control signal, and the fourth control circuit 14 controls the connection between the fourth node N4 and the second voltage terminal V2 under the control of the second control signal.

[0071] During the scaling-up stage,

[0072] When the potential of the first node BIT is a third voltage (for example, the third voltage can be a low voltage) and the potential of the second node BIT# is a fourth voltage (for example, the fourth voltage can be a high voltage), the first control circuit 11 controls the second node BIT# to connect with the third node N3 under the control of the potential of the first node BIT, and the second control circuit 12 controls the first node BIT to connect with the fourth node N4 under the control of the potential of the second node BIT#.

[0073] When the potential of the first node BIT is the fourth voltage (the fourth voltage can be, for example, a high voltage) and the potential of the second node BIT# is the third voltage (the third voltage can be, for example, a low voltage), the first control circuit 11 controls the connection between the second node BIT# and the fourth node N4 under the control of the potential of the first node BIT, and the second control circuit 12 controls the connection between the first node BIT and the third node N3 under the control of the potential of the second node N2.

[0074] exist Figure 1 In at least one embodiment of the amplifier shown, the first node BIT is used for both input and output, and the second node BIT# is used for both input and output.

[0075] In at least one embodiment of the present invention, the first voltage terminal may be a power supply voltage terminal, and the second voltage terminal may be a ground terminal or a low voltage terminal, but is not limited thereto.

[0076] Optionally, the third control circuit includes a first transistor, and the fourth control circuit includes a second transistor;

[0077] The gate of the first transistor is electrically connected to the first control terminal, the first terminal of the first transistor is electrically connected to the first voltage terminal, and the second terminal of the first transistor is electrically connected to the third node.

[0078] The gate of the second transistor is electrically connected to the second control terminal, the first terminal of the second transistor is electrically connected to the fourth node, and the second terminal of the second transistor is electrically connected to the second voltage terminal.

[0079] In at least one embodiment of the present invention, both the first transistor and the second transistor are oxide transistors.

[0080] In a practical implementation, both the first transistor and the second transistor can be oxide transistors. Oxide transistors have smaller leakage current, which reduces the leakage current and crosstalk of the amplifier.

[0081] like Figure 2 As shown, in Figure 1 Based on at least one embodiment of the amplifier shown, the amplifier of at least one embodiment of the present invention further includes a fifth control circuit 15 and a sixth control circuit 16;

[0082] The fifth control circuit 15 is electrically connected to the first node BIT, the second node BIT#, and the fourth node N4 respectively, and is used to control the connection or disconnection between the second node BIT# and the fourth node N4 under the control of the potential of the first node BIT.

[0083] The sixth control circuit 16 is electrically connected to the first node BIT, the second node BIT#, and the fourth node N4 respectively, and is used to control the connection or disconnection between the first node BIT and the fourth node N4 under the control of the potential of the second node BIT#.

[0084] exist Figure 2 In at least one embodiment of the amplifier shown, the leakage current of the amplifier can be reduced by setting the transistors included in the fifth control circuit 15 and the sixth control circuit 16 as oxide transistors, which have lower leakage current.

[0085] Optionally, the fifth control circuit includes a third transistor, and the sixth control circuit includes a fourth transistor;

[0086] The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the second node, and the second electrode of the third transistor is electrically connected to the fourth node.

[0087] The gate of the fourth transistor is electrically connected to the second node, the first terminal of the fourth transistor is electrically connected to the first node, and the second terminal of the fourth transistor is electrically connected to the fourth node.

[0088] In at least one embodiment of the present invention, both the third transistor and the fourth transistor are oxide transistors.

[0089] like Figure 3 As shown, in Figure 2 Based on at least one embodiment of the amplifier shown, the amplifier described in at least one embodiment of the present invention may further include a first switch control circuit 31 and a second switch control circuit 32;

[0090] The first switch control circuit 31 is electrically connected to the first switch control terminal K1, the first input terminal I1 and the first node BIT respectively, and is used to control the connection or disconnection between the first input terminal I1 and the first node BIT under the control of the first switch control signal provided by the first switch control terminal K1.

[0091] The second switch control circuit 32 is electrically connected to the second switch control terminal K2, the second input terminal I2, and the second node BIT#, respectively, and is used to control the connection or disconnection between the second input terminal I2 and the second node BIT# under the control of the second switch control signal provided by the second switch control terminal K2.

[0092] The present invention is as follows Figure 3 In at least one embodiment of the amplifier shown, the amplification cycle may include an input phase and an amplification phase that are set sequentially during operation;

[0093] During the input phase, the first switch control circuit 31, under the control of the first switch control signal, controls the connection between the first input terminal I1 and the first node BIT; the second switch control circuit 32, under the control of the second switch control signal, controls the connection between the second input terminal I2 and the second node BIT#; the first input terminal I1 provides a first input signal to the first node BIT, and the second input terminal I2 provides a second input signal to the second node BIT#;

[0094] During the amplification stage, the first switch control circuit 31, under the control of the first switch control signal, controls the first input terminal I1 to disconnect from the first node BIT; the second switch control circuit, under the control of the second switch control signal, controls the second input terminal I2 to disconnect from the second node BIT#.

[0095] Optionally, the first switch control circuit includes a fifth transistor, and the second switch control circuit includes a sixth transistor;

[0096] The gate of the fifth transistor is electrically connected to the first switch control terminal, the first electrode of the fifth transistor is electrically connected to the first input terminal, and the second electrode of the fifth transistor is electrically connected to the first node.

[0097] The gate of the sixth transistor is electrically connected to the second switch control terminal, the first terminal of the sixth transistor is electrically connected to the second input terminal, and the second terminal of the sixth transistor is electrically connected to the second node.

[0098] Optionally, the first control circuit includes a seventh transistor and an eighth transistor, and the second control circuit includes a ninth transistor and a tenth transistor.

[0099] The gate of the seventh transistor is electrically connected to the first node, the first electrode of the seventh transistor is electrically connected to the third node, and the second electrode of the seventh transistor is electrically connected to the second node.

[0100] The gate of the eighth transistor is electrically connected to the first node, the first electrode of the eighth transistor is electrically connected to the second node, and the second electrode of the eighth transistor is electrically connected to the fourth node.

[0101] The gate of the ninth transistor is electrically connected to the second node, the first terminal of the ninth transistor is electrically connected to the third node, and the second terminal of the ninth transistor is electrically connected to the first node.

[0102] The gate of the tenth transistor is electrically connected to the second node, the first terminal of the tenth transistor is electrically connected to the first node, and the second terminal of the tenth transistor is electrically connected to the fourth node.

[0103] In at least one embodiment of the present invention, the seventh transistor and the ninth transistor are both p-type transistors, and the eighth transistor and the tenth transistor are both n-type transistors.

[0104] Optionally, the amplifier further includes a fifth control circuit and a sixth control circuit, the fifth control circuit including a third transistor and the sixth control circuit including a fourth transistor;

[0105] The threshold voltage of the eighth transistor is lower than that of the third transistor, and the threshold voltage of the tenth transistor is lower than that of the fourth transistor, so that only the eighth and tenth transistors are turned on when the voltage is low, and the third and fourth transistors are turned on when a large current is required.

[0106] Optionally, the third control circuit includes a first transistor, and the fourth control circuit includes a second transistor;

[0107] The aspect ratio of the first transistor is greater than that of the seventh transistor, the aspect ratio of the first transistor is greater than that of the eighth transistor, the aspect ratio of the first transistor is greater than that of the ninth transistor, and the aspect ratio of the first transistor is greater than that of the tenth transistor.

[0108] The aspect ratio of the second transistor is greater than that of the seventh transistor, the aspect ratio of the second transistor is greater than that of the eighth transistor, the aspect ratio of the second transistor is greater than that of the ninth transistor, and the aspect ratio of the second transistor is greater than that of the tenth transistor.

[0109] The aspect ratio of the eighth transistor is smaller than that of the seventh transistor, and the aspect ratio of the tenth transistor is smaller than that of the ninth transistor.

[0110] like Figure 4 As shown, in Figure 2 Based on at least one embodiment of the amplifier shown, the third control circuit includes a first transistor M1, and the fourth control circuit includes a second transistor M2;

[0111] The gate of the first transistor M1 is electrically connected to the first control terminal SE#, the source of the first transistor M1 is electrically connected to the power supply voltage terminal VDD, and the drain of the first transistor M1 is electrically connected to the third node N3.

[0112] The gate of the second transistor M2 is electrically connected to the second control terminal SE, the source of the second transistor M2 is electrically connected to the fourth node N4, and the drain of the second transistor M2 is electrically connected to the ground terminal GND.

[0113] The fifth control circuit includes a third transistor M3, and the sixth control circuit includes a fourth transistor M4;

[0114] The gate of the third transistor M3 is electrically connected to the first node BIT, the source of the third transistor M3 is electrically connected to the second node BIT#, and the drain of the third transistor M3 is electrically connected to the fourth node N4.

[0115] The gate of the fourth transistor M4 is electrically connected to the second node BIT#, the source of the fourth transistor M4 is electrically connected to the first node BIT, and the drain of the fourth transistor M4 is electrically connected to the fourth node N4.

[0116] The first control circuit includes a seventh transistor M7 and an eighth transistor M8, and the second control circuit includes a ninth transistor M9 and a tenth transistor M10.

[0117] The gate of the seventh transistor M7 is electrically connected to the first node BIT, the source of the seventh transistor M7 is electrically connected to the third node N3, and the drain of the seventh transistor M7 is electrically connected to the second node BIT#.

[0118] The gate of the eighth transistor M8 is electrically connected to the first node BIT, the source of the eighth transistor M8 is electrically connected to the second node BIT#, and the drain of the eighth transistor M8 is electrically connected to the fourth node N4.

[0119] The gate of the ninth transistor M9 is electrically connected to the second node BIT#, the source of the ninth transistor M9 is electrically connected to the third node N3, and the drain of the ninth transistor M9 is electrically connected to the first node BIT.

[0120] The gate of the tenth transistor M10 is electrically connected to the second node BIT#, the source of the tenth transistor M10 is electrically connected to the first node BIT, and the drain of the tenth transistor M10 is electrically connected to the fourth node N4.

[0121] exist Figure 4 In at least one embodiment of the amplifier shown, M1 and M2 are oxide transistors, M3 and M4 are oxide transistors, M7 and M9 are both LTPS (low-temperature polysilicon) transistors, and M8 and M10 are both oxide transistors.

[0122] This invention Figure 4 In at least one embodiment of the amplifier shown, when operating, both SE# and SE provide high voltage signals, and M1 and M2 are turned on;

[0123] When a high voltage signal is input to BIT and a low voltage signal is input to BIT#, M8 and M3 are turned on, and M9 is turned on to control the connection between BIT# and ground GND, and to control the electrical connection between BIT and power supply voltage VDD for differential amplification. That is, the difference between the voltage value of the high voltage signal input to BIT and the voltage value of the low voltage signal input to BIT# is amplified, so that the difference between the voltage value of the signal output by BIT and the voltage value of the signal output by BIT# is larger.

[0124] When BIT inputs a low voltage signal and BIT# inputs a high voltage signal, M7, M4, and M10 are turned on to control the connection between BIT and GND, and to control the connection between BIT# and the power supply voltage terminal VDD, in order to perform differential amplification. That is, the difference between the voltage value of the high voltage signal input to BIT and the voltage value of the low voltage signal input to BIT# is amplified, so that the difference between the voltage value of the signal output by BIT and the voltage value of the signal output by BIT# is larger.

[0125] In this invention Figure 4 In at least one embodiment of the amplifier shown, M1 and M2 are both oxide transistors. The leakage current of oxide transistors is much smaller than that of LTPS transistors, thereby reducing the leakage current of the amplifier and lowering power consumption. However, the mobility of oxide transistors is lower than that of LTPS transistors. When M7, M8, M9, and M10 are all LTPS transistors, the aspect ratio of M1 and M2 needs to be increased to achieve current matching and improve amplification speed. For example, if the mobility of oxide transistors is 1 / 4 of that of LTPS transistors, then the aspect ratio of oxide transistors needs to be four times that of LTPS transistors.

[0126] In this invention Figure 4 In at least one embodiment of the amplifier shown, M3 and M4 are oxide transistors to reduce the leakage current of the amplifier.

[0127] In this invention Figure 4 In at least one embodiment of the amplifier shown, M3 and M8 are connected in parallel, and M4 and M10 are connected in parallel. By designing the aspect ratios of M3, M8, M4, and M10, leakage current can be reduced and read speed can be improved (because the subthreshold slope of the oxide transistor is small, the turn-on and turn-off speeds of the oxide transistor are faster, thus improving the read speed).

[0128] In at least one embodiment of the present invention, the aspect ratios of M7, M9, M1, and M2 are matched to determine the magnitude of the amplifier's operating current. The product of the mobility of M7 and its aspect ratio is equal to the product of the mobility of M8 and its aspect ratio and the product of the mobility of M3 and its aspect ratio. The product of the mobility of M9 and its aspect ratio is equal to the product of the mobility of M10 and its aspect ratio and the product of the mobility of M4 and its aspect ratio.

[0129] In this invention Figure 4 In at least one embodiment of the amplifier shown, the aspect ratio of M8 is less than that of M7, and the aspect ratio of M10 is less than that of M9, so that the leakage current of M8 is less than that of M7, and the leakage current of M10 is less than that of M9.

[0130] In this invention Figure 4 In at least one embodiment of the amplifier shown, the threshold voltage of the eighth transistor M8 is less than the threshold voltage of the third transistor M3, and the threshold voltage of the tenth transistor M10 is less than the threshold voltage of the fourth transistor M4. This is so that when the absolute values ​​of the voltage signals provided by BIT and BIT# are smaller, only the eighth transistor M8 and the tenth transistor M10 are turned on to improve the amplification speed. Conversely, when the absolute values ​​of the voltage signals provided by BIT and BIT# are larger, i.e. when a large current is required, the eighth transistor M8, the third transistor M3, the tenth transistor M10, and the fourth transistor M4 are turned on simultaneously to improve the driving capability.

[0131] At least one embodiment of the present invention provides a sensitive amplifier applied to TFT (thin-film transistor) SRAM. By using LTPS CMOS (Complementary Metal Oxide Semiconductor) technology and oxide TFT technology, it compensates for the amplification speed problem caused by the lower mobility of TFT compared to silicon-based MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), and also compensates for the power consumption problem caused by the large leakage current of LTPS transistor.

[0132] In at least one embodiment of the present invention, the amplifier may be disposed on a flexible substrate or a glass substrate, but is not limited thereto. The amplifier described in at least one embodiment of the present invention has advantages such as simple structure, low static power consumption, and fast amplification speed.

[0133] In practical implementation, the sensitive amplifier is one of the core peripheral circuits of SRAM. Because the voltage difference between "0" and "1" in SRAM is primarily determined by the supply voltage of the logic circuit, given a fixed design structure, a higher supply voltage results in a larger voltage difference, making it easier to detect and increasing read speed, but also increasing power consumption. Using a sensitive amplifier can reduce the supply voltage while increasing the voltage difference between "0" and "1"; additionally, from an area perspective, it is also advantageous for flexible sensing applications.

[0134] This invention Figure 5 At least one embodiment of the amplifier shown is related to Figure 4 The difference in at least one embodiment of the amplifier shown is that:

[0135] like Figure 5As shown, the amplifier described in at least one embodiment of the present invention further includes a first switch control circuit and a second switch control circuit;

[0136] The first switch control circuit includes a fifth transistor M5, and the second switch control circuit includes a sixth transistor M6;

[0137] The gate of the fifth transistor M5 is electrically connected to the first switch control terminal K1, the source of the fifth transistor M5 is electrically connected to the first input terminal I1, and the drain of the fifth transistor M5 is electrically connected to the first node BIT.

[0138] The gate of the sixth transistor M6 is electrically connected to the second switch control terminal K2, the source of the sixth transistor M6 is electrically connected to the second input terminal I2, and the drain of the sixth transistor M6 is electrically connected to the second node BIT#.

[0139] exist Figure 5 In at least one embodiment of the amplifier shown, M5 and M6 can both be n-type transistors, but are not limited thereto. In actual operation, M5 and M6 can also be p-type transistors.

[0140] This invention Figure 5 In at least one embodiment of the amplifier shown, the amplification cycle may include an input phase and an amplification phase that are set sequentially during operation;

[0141] During the input phase, K1 and K2 provide high voltage signals, and M5 and M6 are both turned on to control the connection between I1 and BIT, and to control the connection between I2 and BIT#.

[0142] During the amplification stage, K1 and K2 provide low voltage signals, and M5 and M6 are disconnected; SE# and SE both provide high voltage signals, and M1 and M2 are turned on.

[0143] During the scaling-up stage,

[0144] When a high voltage signal is input to BIT and a low voltage signal is input to BIT#, M8 and M3 are turned on, and M9 is turned on to control the connection between BIT# and ground GND, and to control the electrical connection between BIT and power supply voltage VDD for differential amplification. That is, the difference between the voltage value of the high voltage signal input to BIT and the voltage value of the low voltage signal input to BIT# is amplified, so that the difference between the voltage value of the signal output by BIT and the voltage value of the signal output by BIT# is larger.

[0145] When BIT inputs a low voltage signal and BIT# inputs a high voltage signal, M7, M4, and M10 are turned on to control the connection between BIT and GND, and to control the connection between BIT# and the power supply voltage terminal VDD, in order to perform differential amplification. That is, the difference between the voltage value of the high voltage signal input to BIT and the voltage value of the low voltage signal input to BIT# is amplified, so that the difference between the voltage value of the signal output by BIT and the voltage value of the signal output by BIT# is larger.

[0146] The amplification control method described in this embodiment of the invention is applied to the aforementioned amplifier, and the amplification control method includes:

[0147] The first control circuit, under the control of the potential of the first node, controls the connection or disconnection between the second node and the third node, and controls the connection or disconnection between the second node and the fourth node.

[0148] The second control circuit, under the control of the potential of the second node, controls the connection or disconnection between the first node and the third node, and controls the connection or disconnection between the first node and the fourth node.

[0149] The third control circuit, under the control of the first control signal, controls the connection or disconnection between the third node and the first voltage terminal;

[0150] The fourth control circuit, under the control of the second control signal, controls the connection or disconnection between the fourth node and the second voltage terminal.

[0151] Optionally, the amplifier further includes a first switch control circuit and a second switch control circuit; the amplification period includes an input stage and an amplification stage set sequentially.

[0152] The amplification control method further includes:

[0153] During the input phase, the first switch control circuit, under the control of the first switch control signal, controls the connection between the first input terminal and the first node; the second switch control circuit, under the control of the second switch control signal, controls the connection between the second input terminal and the second node.

[0154] During the amplification stage, the first switch control circuit, under the control of the first switch control signal, controls the first input terminal to disconnect from the first node; the second switch control circuit, under the control of the second switch control signal, controls the second input terminal to disconnect from the second node.

[0155] The amplification control method described in at least one embodiment of the present invention further includes: during the amplification stage, a third control circuit controls the connection between the third node and the first voltage terminal under the control of the first control signal, and a fourth control circuit controls the connection between the fourth node and the second voltage terminal under the control of the second control signal;

[0156] During the scaling-up stage,

[0157] When the potential of the first node is the third voltage and the potential of the second node is the fourth voltage, the first control circuit controls the connection between the second node and the third node under the control of the potential of the first node, and the second control circuit controls the connection between the first node and the fourth node under the control of the potential of the second node.

[0158] When the potential of the first node is the fourth voltage and the potential of the second node is the third voltage, the first control circuit controls the connection between the second node and the fourth node under the control of the potential of the first node, and the second control circuit controls the connection between the first node and the third node under the control of the potential of the second node.

[0159] The storage circuit described in this embodiment of the invention includes the amplifier described above.

[0160] like Figure 6 As shown, the storage circuit described in at least one embodiment of the present invention includes a storage array 61, a row decoder 621, a column decoder 622, an input buffer 63, control logic 64, and a sensitive amplifier 60;

[0161] A typical repeating unit of the storage array 61 is a 6-T structure with two inverters interlocked.

[0162] The row decoder 621 and the column decoder 622 serve as addressing functions, decoding the received address signals to read information from a specific location in the storage array 61.

[0163] The input buffer 63 is used to enhance the write drive capability;

[0164] The control logic 64 controls the commands for the entire storage circuit;

[0165] After the information at a specific location in the storage array 6 is read out, the sensitive amplifier 60 performs differential amplification, thereby enabling subsequent data processing and improving the reading speed.

[0166] exist Figure 6 In the diagram, OP1 is the first operational amplifier, OP2 is the second operational amplifier, OP3 is the third operational amplifier, and OP4 is the fourth operational amplifier.

[0167] In at least one embodiment of the present invention, memory circuits are required in various TFT-based electronic product applications, such as display integration, flexible sensing, near-memory computing, and in-memory computing. Among many transistor-based memory circuit implementations, SRAM has a simple structure, low margin requirements for the manufacturing process, and fast read / write speeds.

[0168] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An amplifier characterized by, The first node, the second node, the first control circuit, the second control circuit, the third control circuit and the fourth control circuit are included; The first control circuit is electrically connected with the first node, the second node, the third node and the fourth node respectively, and is used for controlling the second node and the third node to be connected or disconnected under the control of the potential of the first node, and controlling the second node and the fourth node to be connected or disconnected; The second control circuit is electrically connected with the first node, the second node, the third node and the fourth node respectively, and is used for controlling the first node and the third node to be connected or disconnected under the control of the potential of the second node, and controlling the first node and the fourth node to be connected or disconnected; The third control circuit is electrically connected with the first control end, the first voltage end and the third node respectively, and is used for controlling the third node and the first voltage end to be connected or disconnected under the control of the first control signal provided by the first control end; The fourth control circuit is electrically connected with the second control end, the second voltage end and the fourth node respectively, and is used for controlling the fourth node and the second voltage end to be connected or disconnected under the control of the second control signal provided by the second control end; The transistors included in the third control circuit and the transistors included in the fourth control circuit are oxide transistors; The amplifier further includes a fifth control circuit and a sixth control circuit; the fifth control circuit includes a third transistor, and the sixth control circuit includes a fourth transistor; The gate of the third transistor is electrically connected with the first node, the first pole of the third transistor is electrically connected with the second node, and the second pole of the third transistor is electrically connected with the fourth node; The gate of the fourth transistor is electrically connected with the second node, the first pole of the fourth transistor is electrically connected with the first node, and the second pole of the fourth transistor is electrically connected with the fourth node; The first control circuit includes a seventh transistor and an eighth transistor, and the second control circuit includes a ninth transistor and a tenth transistor; The gate of the seventh transistor is electrically connected with the first node, the first pole of the seventh transistor is electrically connected with the third node, and the second pole of the seventh transistor is electrically connected with the second node; The gate of the eighth transistor is electrically connected with the first node, the first pole of the eighth transistor is electrically connected with the second node, and the second pole of the eighth transistor is electrically connected with the fourth node; The gate of the ninth transistor is electrically connected with the second node, the first pole of the ninth transistor is electrically connected with the third node, and the second pole of the ninth transistor is electrically connected with the first node; The gate of the tenth transistor is electrically connected with the second node, the first pole of the tenth transistor is electrically connected with the first node, and the second pole of the tenth transistor is electrically connected with the fourth node; The threshold voltage of the eighth transistor is less than the threshold voltage of the third transistor, and the threshold voltage of the tenth transistor is less than the threshold voltage of the fourth transistor.

2. The amplifier of claim 1, wherein, The third control circuit includes a first transistor, and the fourth control circuit includes a second transistor; The gate of the first transistor is electrically connected with the first control end, the first pole of the first transistor is electrically connected with the first voltage end, and the second pole of the first transistor is electrically connected with the third node. The gate of the second transistor is electrically connected with the second control end, the first pole of the second transistor is electrically connected with the fourth node, and the second pole of the second transistor is electrically connected with the second voltage end. The first transistor and the second transistor are both oxide transistors.

3. The amplifier of claim 1, wherein, The fifth control circuit is electrically connected with the first node, the second node and the fourth node respectively, and is used for controlling the communication or disconnection between the second node and the fourth node under the control of the potential of the first node. The sixth control circuit is electrically connected with the first node, the second node and the fourth node respectively, and is used for controlling the communication or disconnection between the first node and the fourth node under the control of the potential of the second node.

4. The amplifier of claim 1, wherein, The third transistor and the fourth transistor are both oxide transistors.

5. The amplifier of any one of claims 1 to 4, wherein, Further comprising a first switch control circuit and a second switch control circuit; The first switch control circuit is electrically connected with the first switch control end, the first input end and the first node respectively, and is used for controlling the communication or disconnection between the first input end and the first node under the control of the first switch control signal provided by the first switch control end. The second switch control circuit is electrically connected with the second switch control end, the second input end and the second node respectively, and is used for controlling the communication or disconnection between the second input end and the second node under the control of the second switch control signal provided by the second switch control end.

6. The amplifier of claim 5, wherein, The first switch control circuit comprises a fifth transistor, and the second switch control circuit comprises a sixth transistor; The gate of the fifth transistor is electrically connected with the first switch control end, the first pole of the fifth transistor is electrically connected with the first input end, and the second pole of the fifth transistor is electrically connected with the first node. The gate of the sixth transistor is electrically connected with the second switch control end, the first pole of the sixth transistor is electrically connected with the second input end, and the second pole of the sixth transistor is electrically connected with the second node.

7. The amplifier of claim 1, wherein, The seventh transistor and the ninth transistor are both p-type transistors, and the eighth transistor and the tenth transistor are both n-type transistors.

8. The amplifier of claim 7, wherein, The third control circuit comprises a first transistor, and the fourth control circuit comprises a second transistor; The width-length ratio of the first transistor is greater than the width-length ratio of the seventh transistor, the width-length ratio of the first transistor is greater than the width-length ratio of the eighth transistor, the width-length ratio of the first transistor is greater than the width-length ratio of the ninth transistor, and the width-length ratio of the first transistor is greater than the width-length ratio of the tenth transistor. The width-length ratio of the second transistor is greater than the width-length ratio of the seventh transistor, the width-length ratio of the second transistor is greater than the width-length ratio of the eighth transistor, the width-length ratio of the second transistor is greater than the width-length ratio of the ninth transistor, and the width-length ratio of the second transistor is greater than the width-length ratio of the tenth transistor. The eighth transistor has a width-length ratio smaller than that of the seventh transistor, and the tenth transistor has a width-length ratio smaller than that of the ninth transistor.

9. An amplification control method applied to the amplifier according to any one of claims 1 to 8, characterized by, The amplification control method comprises: The first control circuit controls the second node and the third node to be connected or disconnected under the control of the potential of the first node, and controls the second node and the fourth node to be connected or disconnected; The second control circuit controls the first node and the third node to be connected or disconnected under the control of the potential of the second node, and controls the first node and the fourth node to be connected or disconnected; The third control circuit controls the third node and the first voltage terminal to be connected or disconnected under the control of the first control signal; The fourth control circuit controls the fourth node and the second voltage terminal to be connected or disconnected under the control of the second control signal.

10. The amplification control method according to claim 9, wherein The amplifier further comprises a first switch control circuit and a second switch control circuit; and the amplification period comprises an input stage and an amplification stage arranged in sequence. The amplification control method further comprises: In the input stage, the first switch control circuit controls the first input terminal and the first node to be connected under the control of the first switch control signal; and the second switch control circuit controls the second input terminal and the second node to be connected under the control of the second switch control signal; In the amplification stage, the first switch control circuit controls the first input terminal and the first node to be disconnected under the control of the first switch control signal; and the second switch control circuit controls the second input terminal and the second node to be disconnected under the control of the second switch control signal.

11. The amplification control method according to claim 9 or 10, wherein Further comprising: In the amplification stage, the third control circuit controls the third node and the first voltage terminal to be connected under the control of the first control signal, and the fourth control circuit controls the fourth node and the second voltage terminal to be connected under the control of the second control signal; In the amplification stage, When the potential of the first node is the third voltage and the potential of the second node is the fourth voltage, the first control circuit controls the second node and the third node to be connected under the control of the potential of the first node, and the second control circuit controls the first node and the fourth node to be connected under the control of the potential of the second node; When the potential of the first node is the fourth voltage and the potential of the second node is the third voltage, the first control circuit controls the second node and the fourth node to be connected under the control of the potential of the first node, and the second control circuit controls the first node and the third node to be connected under the control of the potential of the second node.

12. A storage circuit, characterized by comprising: The amplifier comprises any one of claims 1 to 8.

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