Array substrate, display panel and display device

Abstract

The present invention discloses an array substrate, a display panel, and a display device. Each pixel unit of the array substrate includes a first thin-film transistor and a second thin-film transistor. The first thin-film transistor includes a first gate, a first active layer disposed on one side of the first gate, and a first source and a first drain disposed on a side of the first active layer facing away from the first gate. The second thin-film transistor includes a second gate, a second active layer disposed on one side of the second gate, and a second source and a second drain disposed on a side of the second active layer facing away from the second gate. The first source and the second source are both connected to a pixel electrode. The ratio of the width dimension of the first active layer to the spacing between the first source and the first drain is greater than the ratio of the width dimension of the second active layer to the spacing between the second source and the second drain. The technical solution of the present invention can adapt to different scenarios and reduce energy consumption.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel using the array substrate, and a display device using the display panel. Background Art

[0002] As display devices become more and more popular, users have higher and higher requirements for display devices. High refresh rate display devices are produced under market demand. However, traditional display devices usually only have high refresh rates or low refresh rates, so it is difficult to choose the appropriate refresh rate according to different scenarios. For example, in some cases where high refresh is not required, such as reading news or novels, we need to choose a low refresh rate mode to reduce energy consumption. If the display device only has a high refresh rate mode, the power consumption may increase in this case. Summary of the Invention

[0003] The main purpose of the present invention is to provide an array substrate, aiming to improve the problem that traditional display devices cannot select a suitable refresh rate mode according to different scenarios.

[0004] To achieve the above-mentioned object, the array substrate proposed in the present invention includes a substrate, on which a plurality of pixel units arranged in an array are provided, each of the pixel units includes a pixel electrode, a first thin film transistor and a second thin film transistor, the first thin film transistor includes a first gate, a first active layer, a first drain and a first source, the first gate is provided on one side of the substrate, the first active layer is provided on a side of the first gate away from the substrate, the first source and the first drain are provided on a side of the first active layer away from the first gate; the spacing between the first source and the first drain is L1; the direction perpendicular to the line connecting the first source to the first drain and parallel to the substrate is defined as the width direction, the The dimension of the first active layer in the width direction is W1; the second thin film transistor includes a second gate, a second active layer, a second drain and a second source, the second gate is arranged on one side of the substrate, the second active layer is arranged on the side of the second gate away from the substrate, the second source and the second drain are spaced apart and arranged on the side of the second active layer away from the second gate; and the first source and the second source are connected in parallel to the pixel electrode; the spacing between the second source and the second drain is L2, and the direction perpendicular to the line between the second source and the second drain and parallel to the substrate is defined as the width direction, and the dimension of the second active layer in the width direction is W2; W1 / L1﹥W2 / L2.

[0005] In one embodiment, the array substrate further includes a data line, a first scan line, and a second scan line, wherein the first scan line and the second scan line are both perpendicular to the data line; the first drain and the second drain in the same pixel unit are both connected to the same data line; the first gate and the second gate in the same pixel unit are arranged at intervals and are respectively connected to the first scan line and the second scan line.

[0006] In one embodiment, the first gate and the second gate are both disposed on the same side of the pixel electrode.

[0007] In one embodiment, the first gate and the second gate are spaced apart from each other along the extending direction of the data line.

[0008] In one embodiment, the first active layer and the second active layer are staggered, and the first source electrode and the second source electrode are respectively disposed on both sides of the pixel electrode.

[0009] In one embodiment, a direction from the first drain to the first source is the same as a direction from the second drain to the second source.

[0010] In one embodiment, the first active layer and the second active layer are made of the same material.

[0011] In one embodiment, a first insulating layer is provided between the first gate and the first active layer; and a second insulating layer is provided between the second gate and the second active layer.

[0012] The present invention further provides a display panel, comprising an opposing substrate, liquid crystal, and the above-mentioned array substrate. The opposing substrate and the array substrate are arranged opposite to each other, and the liquid crystal is arranged between the opposing substrate and the array substrate.

[0013] The present invention further provides a display device, characterized in that it comprises a backlight module and the above-mentioned display panel, wherein the backlight module is arranged on a side of the array substrate facing away from the opposing substrate.

[0014] The technical solution of the present invention is to set a first thin film transistor and a second thin film transistor in each pixel unit, the spacing between the first source and the first drain in the first thin film transistor is L1, the spacing between the second source and the second drain in the second thin film transistor is L2, the size of the first active layer of the first thin film transistor in the width direction is W1, the size of the second active layer in the second thin film transistor in the width direction is W2, and W1 / L1>W2 / L2, so that the size of the first thin film transistor is larger than the size of the second thin film transistor, so that the first thin film transistor can carry a larger driving current and adapt to high refresh rate scenarios; the second thin film transistor can be used in low refresh rate scenarios, thereby reducing electric energy and improving the endurance of the display device. The array substrate in the present invention can select a suitable refresh rate mode according to different scenarios to improve the flexibility and service life of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0016] Figure 1 A top view of a pixel unit in an array substrate according to an embodiment of the present invention;

[0017] Figure 2 is a partial cross-sectional view of an array substrate according to a first embodiment of the present invention;

[0018] Figure 3 This is a schematic structural diagram of a display panel according to a second embodiment of the present invention;

[0019] Figure 4 FIG. 4 is a structural diagram of a display device according to a third embodiment of the present invention.

[0020] Description of Figure Numbers:

[0021]

[0022] 1262 Fourth connecting segment 1263 Fifth connecting section 127 First insulating layer 128 First light shielding layer 129 Second light shielding layer 200 Counter substrate 300 liquid crystal 400 Backlight module

[0023] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0025] It should be noted that if the embodiments of the present invention involve directional indications (such as up, down, left, right, front, back, etc.), the directional indications are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly.

[0026] In addition, if there are descriptions involving "first", "second", etc. in the embodiments of the present invention, the descriptions of "first", "second", etc. are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features specified as "first" and "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that ordinary technicians in this field can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0027] Example 1:

[0028] The present invention provides an array substrate 100 .

[0029] In the embodiments of the present invention, please refer to Figure 1 and Figure 2The array substrate 100 includes a substrate 110, on which a plurality of pixel units 120 arranged in an array are provided. Each pixel unit 120 includes a pixel electrode 121 and a thin film transistor. The thin film transistor includes a gate, an active layer, a drain, and a source. The gate is provided on one side of the substrate 110, the active layer is provided on the side of the gate facing away from the substrate 110, and the source and drain are provided at intervals on the side of the active layer facing away from the gate. Each pixel unit 120 has at least two thin film transistors, wherein the two thin film transistors are defined as a first thin film transistor 122 and a second thin film transistor 123; the source, drain, and active layer of the first thin film transistor 122 are defined as a first source electrode 1224, a first drain electrode 1223, and a first active layer 1222, respectively. The first source electrode 1224 and the first drain electrode 1223 are connected to each other. The spacing between the first source electrode 1224 and the first drain electrode 1223 is L1, and the direction perpendicular to the line connecting the first source electrode 1224 to the first drain electrode 1223 and parallel to the substrate 110 is defined as the width direction, and the size of the first active layer 1222 in the width direction is W1; the source, drain and active layer in the second thin film transistor 123 are defined as the second source electrode 1234, the second drain electrode 1233 and the second active layer 1232, respectively, and the first source electrode 1224 and the second source electrode 1234 are connected in parallel to the pixel electrode 121; the spacing between the second source electrode 1234 and the second drain electrode 1233 is L2, and the direction perpendicular to the line connecting the second source electrode 1234 to the second drain electrode 1233 and parallel to the substrate 110 is defined as the width direction, and the size of the second active layer 1232 in the width direction is W2; and W1 / L1>W2 / L2.

[0030] Specifically, in the present invention, the first thin film transistor 122 includes a first gate 1221, a first active layer 1222, a first drain 1223 and a first source 1224. The first gate 1221 is provided on one side of the substrate 110, the first active layer 1222 is provided on the side of the first gate 1221 away from the substrate 110, and the first source 1224 and the first drain 1223 are spaced apart and provided on the side of the first active layer 1222 away from the first gate 1221; the spacing between the first source 1224 and the first drain 1223 is L1, and the direction perpendicular to the line between the first source 1224 and the first drain 1223 and parallel to the substrate 110 is defined as the width direction, and the size of the first active layer 1222 in the width direction is W1; the second thin film transistor 123 includes a second gate 123 1. A second active layer 1232, a second drain 1233, and a second source 1234. The second gate 1231 is disposed on one side of the substrate 110. The second active layer 1232 is disposed on a side of the second gate 1231 facing away from the substrate 110. The second source 1234 and the second drain 1233 are spaced apart and disposed on a side of the second active layer 1232 facing away from the second gate 1231. The first source 1224 and the second source 1234 are connected in parallel to the pixel electrode 121. The spacing between the second source 1234 and the second drain 1233 is L2. The direction perpendicular to the line connecting the second source 1234 to the second drain 1233 and parallel to the substrate 110 is defined as the width direction. The dimension of the second active layer 1232 in the width direction is W2. Wherein W1 / L1 is greater than W2 / L2.

[0031] In order to achieve the effect of separately controlling the opening of the first thin film transistor 122 and the second thin film transistor 123, in one example, each pixel unit 120 also corresponds to at least two scanning lines and at least two data lines 124, and the first gate 1221 of the first thin film transistor 122 and the second gate 1231 of the second thin film transistor 123 are respectively arranged at intervals, and the first gate 1221 and the second gate 1231 are respectively connected to different scanning lines, and the first drain 1223 in the first thin film transistor 122 and the second drain 1233 in the second thin film transistor 123 are respectively connected to different data lines 124. Alternatively, each pixel unit 120 may be provided with one scan line and at least two data lines 124, wherein the two data lines 124 are connected to the first drain electrode 1223 and the second drain electrode 1233, respectively. The first gate electrode 1221 of the first thin-film transistor 122 and the second gate electrode 1231 of the second thin-film transistor 123 may be on the same layer, i.e., the first gate electrode 1221 of the first thin-film transistor 122 is also the second gate electrode 1231 of the second thin-film transistor 123. In this case, the first gate electrode 1221 and the second gate electrode 1231 may be connected to the same scan line. Alternatively, each pixel unit 120 may also be provided with at least two scan lines and one data line 124, wherein the first drain electrode 1223 of the first thin-film transistor 122 and the second drain electrode 1233 of the second thin-film transistor 123 are both connected to the same data line 124, and the first gate electrode 1221 of the first thin-film transistor 122 and the second gate electrode 1231 of the second thin-film transistor 123 are respectively connected to different scan lines. By providing the first thin film transistor 122 and the second thin film transistor 123 , both the first thin film transistor 122 and the second thin film transistor 123 can control the pixel unit 120 .

[0032] A first active layer 1222 is provided between the first gate 1221 and the first drain 1223, and a second active layer 1232 is provided between the second gate 1231 and the second drain 1233. The first drain 1223 and the first source 1224 are both provided on the side of the first active layer 1222 away from the first gate 1221. The first drain 1223 and the first source 1224 are spaced apart. The distance between the first drain 1223 and the first source 1224 is defined as L1. The size of the projection of the first active layer 1222 on the substrate 110 in the direction perpendicular to the line connecting the first drain 1223 and the first source 1224 is W1. Similarly, the distance between the second drain 1233 and the second source 1224 is defined as W1. The electrodes 1234 are both located on the side of the second active layer 1232 facing away from the second gate electrode 1231. The second drain electrode 1233 and the second source electrode 1234 are spaced apart, and the spacing between the second drain electrode 1233 and the second source electrode 1234 is defined as L2. The projection of the second active layer 1232 on the substrate 110 in a direction perpendicular to the line connecting the second drain electrode 1233 and the second source electrode 1234 is defined as W2. By setting W1 / L1>W2 / L2, the size of the first thin film transistor 122 is larger than that of the second thin film transistor 123, so that the first thin film transistor 122 can withstand a larger drive current when turned on, thereby adapting to the high refresh rate mode. When it is necessary to switch to the low refresh rate mode, the first thin film transistor 122 can be turned off and the second thin film transistor 123 can be turned on, thereby reducing leakage current and thus reducing energy consumption. Since the ratio of the size of the active layer's projection on the substrate 110 in a direction perpendicular to the line connecting the drain and source (i.e., the size of the active layer in the width direction) to the distance between the drain and source determines the size of the thin film transistor, the size of the first thin film transistor 122 can be increased by setting the spacing between the first drain electrode 1223 and the first source electrode 1224 in the first thin film transistor 122 to be smaller than the spacing between the second drain electrode 1233 and the second source electrode 1234 in the second thin film transistor 123. Alternatively, this can be achieved by setting the width dimension of the first active layer 1222 to be larger than the width dimension of the second active layer 1232. In conjunction with the aforementioned scheme in which each pixel unit 120 corresponds to at least two scan lines, the two scan lines are respectively connected to the first gate electrode 1221 and the second gate electrode 1231. Therefore, different scan lines can be used to control the conduction of the first gate electrode 1221 or the second gate electrode 1231, i.e., to control the turn-on of the first thin film transistor 122 or the turn-on of the second thin film transistor 123. Combined with the above-mentioned solution in which each pixel unit 120 corresponds to at least two data lines 124, the two data lines 124 are respectively connected to the first drain 1223 and the second drain 1233, so that each data line 124 can control the first drain 1223 or the second drain 1233 to be turned on, that is, the first thin film transistor 122 can be controlled to be turned on or the second thin film transistor 123 can be controlled to be turned on.

[0033] The technical solution of the present invention is to set a first thin film transistor 122 and a second thin film transistor 123 in each pixel unit 120, the distance between the first source 1224 and the first drain 1223 in the first thin film transistor 122 is L1, the distance between the second source 1234 and the second drain 1233 in the second thin film transistor 123 is L2, the size of the first active layer 1222 of the first thin film transistor 122 in the width direction is W1, the size of the second active layer 1232 of the second thin film transistor 123 in the width direction is W2, and W1 / L1>W2 / L2, so that the size of the first thin film transistor 122 is larger than that of the second thin film transistor 123, so that the first thin film transistor 122 can carry a larger driving current and adapt to high refresh rate scenarios; the second thin film transistor 123 can be used in low refresh rate scenarios, thereby reducing power and improving the endurance of the display device. The array substrate 100 of the present invention can select a suitable refresh rate mode according to different scenarios to improve the flexibility and service life of the display device.

[0034] As an example, Figure 1 As shown, the array substrate 100 also includes a data line 124, a first scan line and a second scan line, the data line 124 is perpendicular to the first scan line and the second scan line; the first drain 1223 and the second drain 1233 in the same pixel unit 120 are connected to the same data line 124; the first gate 1221 and the second gate 1231 in the same pixel unit 120 are respectively connected to the first scan line and the second scan line.

[0035] By connecting the first drain electrode 1223 and the second drain electrode 1233 in the same pixel unit 120 to the same data line 124, and connecting the first gate electrode 1221 and the second gate electrode 1231 in the same pixel unit 120 to the first scan line and the second scan line respectively, the first thin film transistor 122 and the second thin film transistor 123 can be independently turned on under the control of the first scan line and the second scan line, respectively, to meet two different usage scenarios of high refresh rate and low refresh rate; and the first thin film transistor 122 and the second thin film transistor 123 can also share a data line 124, reducing the number of data lines 124 to improve the aperture ratio, reducing the number of integrated circuit chips, and saving costs.

[0036] Further, if Figure 1 As shown, the first gate 1221 and the second gate 1231 are both disposed on the same side of the pixel electrode 121 .

[0037] By arranging the first gate 1221 and the second gate 1231 on the same side of the pixel electrode 121, the first thin film transistor 122 and the second thin film transistor 123 are arranged close to each other, thereby reducing the length of the connection line when the first source 1224 and the second source 1234 in the first thin film transistor 122 are connected, thereby reducing the area of ​​the pixel unit 120 occupied by the connection line, and further improving the aperture ratio.

[0038] Further, if Figure 1 As shown, the first gate 1221 and the second gate 1231 are spaced apart from each other along the extending direction of the data line 124 .

[0039] By arranging the first gate electrode 1221 and the second gate electrode 1231 at intervals along the extension direction of the data line 124, the arrangement of the first thin film transistor 122 and the second thin film transistor 123 is made more regular, thereby avoiding wasting more areas of the pixel units 120, thereby reducing the area of ​​each pixel unit 120, increasing the number of pixel units 120 set in the entire array panel, and improving the resolution of the display device using the array substrate 100.

[0040] Further, if Figure 1 As shown, the first active layer 1222 and the second active layer 1232 are staggered, and the first source electrode 1224 and the second source electrode 1234 are respectively disposed on both sides of the pixel electrode 121 .

[0041] By staggering the first active layer 1222 and the second active layer 1232, and arranging the first source electrode 1224 and the second source electrode 1234 on both sides of the pixel electrode 121, respectively, the first source electrode 1224 and the second source electrode 1234 are made closer to the pixel electrode 121, thereby shortening the total length of the connecting line when the first source electrode 1224 and the second source electrode 1234 are connected to the pixel electrode 121, and the shape of the connecting line is simple, which is conducive to increasing the aperture ratio and saving costs.

[0042] Further, if Figure 1 As shown, the direction from the first drain 1223 to the first source 1224 is the same as the direction from the second drain 1233 to the second source 1234 .

[0043] By making the direction from the first drain 1223 to the first source 1224 the same as the direction from the second drain 1233 to the second source 1234, the risk of the drain connection line 125 and the source connection line 126 being cross-connected to each other is avoided when the first drain 1223 and the second drain 1233 are connected through the drain connection line 125 and the first source 1224 and the second source 1234 are connected through the source connection line 126.

[0044] Specifically, when the first drain 1223 is located on the left side of the first source 1224 and the second drain 1233 is located on the left side of the second source 1234, the drain connection line 125 between the first drain 1223 and the second drain 1233 may include a first connection segment 1251 and a second connection segment 1252, the first connection segment 1251 is perpendicular to the second connection segment 1252, the first connection segment 1251 is collinear with the first data line 124, and one end of the first connection segment 1251 is connected to the first drain 1223, and the other end extends to above the second gate 1231; one end of the second connection segment 1252 is located above the second gate 1231, and one end is connected to the first connection segment 1251, and the other end is connected to the second drain 1233. The connection line between the first source 1224 and the second source 1234 may include a third connection segment 1261, a fourth connection segment 1262 and a fifth connection segment 1263. It is defined that the first gate 1221 is closer to the pixel electrode 121 than the second gate 1231. Then, one end of the third connection segment 1261 is connected to the second source 1234, and the other end extends above the first gate 1221. The fourth connection segment 1262 is located above the first gate 1221, and the two ends of the fourth connection segment 1262 are respectively connected to the first source 1224 and the third connection segment 1261. The fifth connection segment 1263 has one end connected to the pixel electrode 121, and the other end is connected to the fourth connection segment 1262.

[0045] In one example, the first active layer 1222 and the second active layer 1232 are made of the same material.

[0046] By using the same material for the first active layer 1222 and the second active layer 1232, the first active layer 1222 and the second active layer 1232 can be formed simultaneously using the same photomask in the same process step, thereby reducing the number of photomasks and, in turn, reducing process costs and efficiency. Specifically, the first active layer 1222 and the second active layer 1232 can both be made of metal oxide, or both be made of amorphous silicon layers or polycrystalline silicon layers.

[0047] Of course, in other embodiments, the materials of the first active layer 1222 and the second active layer 1232 may also be different. Furthermore, to ensure that the first thin-film transistor 122 can more stably adapt to the high refresh rate mode and the first thin-film transistor 122 is adapted to the low refresh rate mode, the first active layer 1222 may be an amorphous silicon layer or a polycrystalline silicon layer, and the second active layer 1232 may be a metal oxide layer. It is understood that the ion mobility of crystalline silicon is higher than that of metal oxide, and therefore is more suitable for high refresh rate mode. Based on the above-mentioned ratio of the width dimension W1 of the first active layer 1222 of the first thin film transistor 122 to the distance L1 from the first drain electrode 1223 to the first source electrode 1224 being greater than the ratio of the width dimension W2 of the second active layer 1232 of the second thin film transistor 123 to the distance L2 from the second drain electrode 1233 to the second source electrode 1234, so as to adapt the first thin film transistor 122 to the high refresh rate mode, in this embodiment, the first active layer 1222 is further made of crystalline silicon material, which further ensures that the first thin film transistor 122 can better adapt to the high refresh rate mode. Of course, by setting the second active layer 1232 to be a metal oxide, due to its low ion mobility, the leakage current of the second thin film transistor 123 can be reduced, thereby achieving its adaptation to the low refresh rate mode, and having the effect of reducing energy consumption, increasing the battery life of the display device, and improving the service life.

[0048] Further, if Figure 2 As shown, a first insulating layer 127 is provided between the first gate 1221 and the first active layer 1222 ; and a second insulating layer is provided between the second gate 1231 and the second active layer 1232 .

[0049] In this example, the first insulating layer 127 is provided to isolate the first gate 1221 and the first active layer 1222 in the first thin-film transistor 122 from each other, thereby preventing the risk of a short circuit between the first gate 1221 and the first active layer 1222. The second insulating layer is provided to isolate the second gate 1231 and the second active layer 1232 in the second thin-film transistor 123 from each other, thereby preventing the risk of a short circuit between the second gate 1231 and the second active layer 1232. The first insulating layer 127 and the second insulating layer can be the same layer.

[0050] Further, if Figure 2 As shown, the array substrate 100 also includes a first light-shielding layer 128 and a second light-shielding layer 129. The first light-shielding layer 128 is arranged between the first active layer 1222 and the first gate 1221; the second light-shielding layer 129 is connected to the first light-shielding layer 128 and together wraps the first active layer 1222, the first drain 1223 and the first source 1224.

[0051] By disposing the first light-shielding layer 128 between the first active layer 1222 and the first gate electrode 1221, the first light-shielding layer 128 can block the backlight from the backlight module 400, thereby preventing the first active layer 1222 from being affected by the backlight and causing the resistance of the first thin-film transistor 122 to decrease. The second light-shielding layer 129 is connected to the first light-shielding layer 128 and together wraps the first active layer 1222, the first source electrode 1224, and the first drain electrode 1223. The second light-shielding layer 129 can block external light, thereby preventing external light from affecting the first active layer 1222. Furthermore, by having the second light-shielding layer 129 and the first light-shielding layer 128 jointly envelop the first active layer 1222, the first active layer 1222 is completely enclosed within the space enclosed by the first light-shielding layer 128 and the second light-shielding layer 129. This prevents diffraction of light from the backlight module 400 when it passes through the edge of the first gate electrode 1221, which would cause the diffracted light to irradiate the first active layer 1222. This further reduces the risk of the first active layer 1222 being affected by light and causing the resistance of the first thin-film transistor 122 to decrease, further reducing the risk of an increase in the off-state current. Furthermore, with this configuration, the projected areas of the first light-shielding layer 128 and the second light-shielding layer 129 on the substrate 110 do not need to be significantly larger than the projected area of ​​the first active layer 1222 in order to minimize the impact of light diffraction on the first active layer 1222.

[0052] Similarly, the array substrate 100 may further include a third light-shielding layer and a fourth light-shielding layer. The third light-shielding layer is disposed between the second active layer 1232 and the second gate electrode 1231. The fourth light-shielding layer is connected to the third light-shielding layer and together encloses the second active layer 1232, the second drain electrode 1233, and the second source electrode 1234. The third light-shielding layer and the fourth light-shielding layer may be co-layered with the first light-shielding layer 128 and the second light-shielding layer 129, respectively.

[0053] Example 2:

[0054] The present invention also provides a display panel, such as Figure 3 As shown, the display panel includes an opposing substrate 200, a liquid crystal 300, and an array substrate 100. The specific structure of the array substrate 100 is similar to that of the above-mentioned embodiments. Since this display panel adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above-mentioned embodiments, and will not be described in detail here. Specifically, the opposing substrate 200 is arranged opposite to the array substrate 100, and the liquid crystal 300 is arranged between the opposing substrate 200 and the array substrate 100.

[0055] The array substrate 100 includes a display area and a non-display area surrounding the display area. To enable the display panel to display images, the display area of ​​the array substrate 100 is provided with a plurality of pixel units 120 distributed in a matrix, each pixel unit 120 having a pixel display area and a pixel non-display area. A first thin-film transistor 122 and a second thin-film transistor 123 are provided in the pixel non-display area. A liquid crystal 300 is provided between the position of the array substrate 100 corresponding to the pixel display area and the opposing substrate 200, so that the first thin-film transistor 122 or the second thin-film transistor 123 controls the direction of the liquid crystal 300 to achieve the effect of whether the display panel can display an image or not.

[0056] Example 3:

[0057] The present invention also provides a display device, such as Figure 4 As shown, the display device includes a backlight module 400 and a display panel. The specific structure of the display panel is similar to the above embodiments. Since the present display device adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here. Among them, the backlight module 400 is provided on the side of the array substrate 100 away from the opposite substrate 200.

[0058] The backlight module 400 is used to provide light. By arranging the backlight module 400 on the side of the substrate 110 away from the opposing substrate 200, the light emitted by the backlight module 400 can irradiate the array substrate 100 and pass through the array substrate 100 toward the opposing substrate 200, thereby achieving the effect of emitting light from the light-emitting surface of the opposing substrate 200 and displaying the picture.

[0059] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made by using the contents of the present invention description and drawings under the inventive concept of the present invention, or direct / indirect application in other related technical fields are included in the patent protection scope of the present invention.

Claims

1. An array substrate, comprising a substrate on which a plurality of pixel units arranged in an array are provided, characterized in that: Each of the pixel units comprises: pixel electrode; a first thin film transistor, the first thin film transistor comprising a first gate, a first active layer, a first drain, and a first source, wherein the first gate is disposed on one side of the substrate, the first active layer is disposed on a side of the first gate facing away from the substrate, the first source and the first drain are spaced apart and disposed on a side of the first active layer facing away from the first gate; a distance between the first source and the first drain is L1; a direction perpendicular to a line connecting the first source and the first drain and parallel to the substrate is defined as a width direction, and a dimension of the first active layer in the width direction is W1; and A second thin film transistor, the second thin film transistor includes a second gate, a second active layer, a second drain and a second source, the second gate is arranged on one side of the substrate, the second active layer is arranged on the side of the second gate away from the substrate, the second source and the second drain are spaced apart and arranged on the side of the second active layer away from the second gate; and the first source and the second source are connected to the pixel electrode in parallel; the spacing between the second source and the second drain is L2, the direction perpendicular to the line between the second source and the second drain and parallel to the substrate is defined as the width direction, the size of the second active layer in the width direction is W2; W1 / L1﹥W2 / L2.

2. The array substrate according to claim 1, wherein: The array substrate also includes a data line, a first scan line and a second scan line, wherein the first scan line and the second scan line are both perpendicular to the data line; the first drain and the second drain in the same pixel unit are both connected to the same data line; the first gate and the second gate in the same pixel unit are arranged at intervals and are respectively connected to the first scan line and the second scan line.

3. The array substrate according to claim 2, wherein: The first gate and the second gate are both arranged on the same side of the pixel electrode.

4. The array substrate according to claim 3, wherein: The first gate and the second gate are spaced apart from each other along an extending direction of the data line.

5. The array substrate according to claim 2, wherein: The first active layer and the second active layer are staggered, and the first source electrode and the second source electrode are respectively arranged on both sides of the pixel electrode.

6. The array substrate according to claim 2, wherein: A direction from the first drain to the first source is the same as a direction from the second drain to the second source.

7. The array substrate according to claim 1, wherein: The first active layer and the second active layer are made of the same material.

8. The array substrate according to any one of claims 1 to 7, wherein: A first insulating layer is provided between the first gate and the first active layer; and a second insulating layer is provided between the second gate and the second active layer.

9. A display panel, characterized in that: The invention comprises an opposing substrate, liquid crystal, and the array substrate according to any one of claims 1 to 8, wherein the opposing substrate and the array substrate are arranged opposite to each other, and the liquid crystal is arranged between the opposing substrate and the array substrate.

10. A display device, characterized in that: The display device comprises a backlight module and the display panel as claimed in claim 9, wherein the backlight module is arranged on a side of the array substrate facing away from the counter substrate.

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