A vcc control method and device for a multiphase interleaved parallel buck converter

Abstract

The present application belongs to the field of power electronics, and particularly relates to a VCC control method and device for a multi-phase interleaved Buck converter. Based on voltage ripple and inductance current ripple information, the present application realizes current sharing control based on ripple. Compared with a traditional peak current control method, the control device of the present application calculates an adaptive adjustment peak modulation wave signal according to load current, can effectively realize n-phase current sharing, can effectively reduce the current sharing adjustment time after load jump, and quickly reaches a steady state. Compared with the traditional peak current control method, the carrier signal in the present application simultaneously contains input voltage and inductance current information, and the control loop is simple, without a lead or lag element, so that a faster transient response speed to input voltage and load current changes can be realized.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a VCC control method and device for a multiphase interleaved parallel Buck converter. Background Technology

[0002] High-performance microprocessors require power supplies that are low-voltage, high-current, and highly efficient, while also possessing the ability to rapidly handle large current surges. To meet these requirements, existing technologies typically employ multiphase interleaved parallel Buck converters as the main circuit topology. Multiphase interleaved parallel Buck converters exhibit ripple cancellation effects, helping to minimize output capacitance and improve load transient performance. However, in practical applications, current-sharing control of the load current in multiphase interleaved parallel Buck converters is necessary to reduce current stress on switching devices and improve the converter's efficiency, transient performance, and reliability.

[0003] Currently, control techniques for improving the transient performance of multiphase interleaved parallel Buck converters mainly include high-bandwidth linear control methods, nonlinear control methods, and optimal control methods. However, the transient performance of linear control methods is always limited by the voltage loop bandwidth, and the effect of optimizing its compensation circuit to improve transient performance is limited. Voltage hysteresis control in nonlinear control methods is unaffected by the lead or lag of the compensation network and has a very fast response speed, but frequency conversion control increases the difficulty of filter circuit design, and because it relies on parasitic parameters, its practical application in multiphase interleaved parallel converter design is difficult. Some scholars have proposed using optimal control, i.e., using classical linear control in steady state and utilizing charge balance theory to achieve optimal control of the load transient trajectory in transient state. However, this method, when applied to multiphase interleaved parallel Buck converters, is prone to the problem of unbalanced currents in each phase after the transient state is completed, resulting in poor dynamic current sharing. Multiphase current sharing control is usually implemented using peak current control, average current control, etc. These control methods include event-sampling-based peak current control, DC bus current reconstruction phase current method, and average inductor current estimation method. However, it suffers from issues such as high hardware costs, high sensor accuracy requirements, and low accuracy of estimation results at high frequencies, and it is difficult to simultaneously guarantee fast transient response and good current sharing effect. Summary of the Invention

[0004] To address the problems existing in the prior art, this invention provides a control method and apparatus for a multiphase interleaved parallel Buck converter, which enables it to simultaneously achieve fast transient response, low output voltage ripple, and effectively achieve n-phase current sharing.

[0005] The technical solution of this invention is as follows:

[0006] A VCC control method for a multiphase interleaved parallel Buck converter includes the following steps:

[0007] S1. Obtain the inductor current signal, voltage signal and load current signal of each branch in the multiphase interleaved parallel Buck converter by sampling;

[0008] S2. Calculate the carrier signal and peak modulation wave signal of each phase using the acquired inductor current signal, voltage signal and load current signal;

[0009] S3. Generate PWM control signals based on the obtained phase carrier signals and peak modulation wave signals, and realize the control of the multi-phase interleaved parallel Buck converter through the drive circuit.

[0010] Furthermore, in step S2, when calculating the carrier signal and peak modulation wave signal of each phase, in addition to using the inductor current signal, voltage signal and load current signal, it is also necessary to use the voltage peak factor and current peak factor, which are calculated by known circuit parameters.

[0011] Furthermore, defining a multiphase interleaved parallel Buck converter as having n phases, then the carrier signal of each phase is calculated. The formula is:

[0012]

[0013] Where, k v and k i It is the current weighting factor. The voltage signal obtained by sampling. The sampled branch inductor current signal is given, where the subscript k indicates a branch in an n-phase interleaved parallel Buck converter. ;

[0014] Calculate peak modulation signal The formula is:

[0015]

[0016] in, For voltage peak factor, This is the peak factor of the inductor current. For reference voltage, For reference current, The load current signal is obtained from the sampling circuit;

[0017] The formulas for calculating the voltage peak factor and the inductor current peak factor are as follows:

[0018]

[0019]

[0020] in This is the inductor current ripple factor. For switching frequency, This is the output capacitor.

[0021] Furthermore, in step S3, the method for generating the PWM control signal is to input each phase carrier signal and the peak modulation wave signal into a comparator, wherein each phase carrier signal is the input to the non-inverting input of the comparator, and the peak modulation wave signal is the input to the inverting input of the comparator. The output signal of the comparator is used as the input to the R terminal of the RS flip-flop, and the RS flip-flop outputs the PWM control signal, which is then passed through the drive circuit to control the switching transistors in the multi-phase interleaved parallel Buck converter.

[0022] A VCC control device for a multiphase interleaved parallel Buck converter includes an interconnected main power topology, a sampling circuit, a digital control system, and a drive circuit. The main power topology is an n-phase interleaved parallel Buck converter. The gates of the switching devices of the n-phase interleaved parallel Buck converter are connected to the output of the drive circuit, and the output of the n-phase interleaved parallel Buck converter is connected to the sampling circuit. The output of the sampling circuit is connected to the digital control system, and the output of the digital control system is connected to the input of the drive circuit. The digital control system includes an n-channel carrier signal generation module, a peak modulation wave signal generation module, a comparator, and an RS flip-flop. The sampling circuit is used to acquire the branch inductor current signal and voltage signal in the n-phase interleaved parallel Buck converter. The signal and load current signal are input to an n-channel carrier signal generation module, where the branch inductor current signal and voltage signal are input to an n-channel carrier signal generation module, and the load current signal is input to a peak modulation wave signal generation module. The output of the n-channel carrier signal generation module is connected to the positive input of a comparator, the output of the peak modulation wave signal generation module is connected to the negative input of a comparator, the output of the comparator is connected to the reset terminal of an RS flip-flop, the set terminal of the RS flip-flop is connected to a clock signal, and the output of the RS flip-flop is the output of a digital control system. The n-channel carrier signal generation module calculates and generates each phase carrier signal based on the obtained branch inductor current signal and voltage signal, and the peak modulation wave signal generation module calculates and generates the peak modulation wave signal based on the obtained load current signal.

[0023] Furthermore, the n-channel carrier signal generation module calculates the carrier signal of each phase. The formula is:

[0024]

[0025] Where, k v and k i It is the current weighting factor. The voltage signal output by the sampling circuit. The subscript represents the branch inductor current signal output by the sampling circuit. This represents a branch in an n-phase interleaved parallel Buck converter. .

[0026] Furthermore, the peak modulation wave signal generation module calculates the peak modulation wave signal. The formula is:

[0027]

[0028] in, For voltage peak factor, This is the peak factor of the inductor current. For reference voltage, For reference current, This is the load current signal output by the sampling circuit.

[0029] Furthermore, the voltage peak factor and inductor current peak factor are calculated based on preset values ​​of circuit parameters, and the formulas are as follows:

[0030]

[0031]

[0032] in This is the inductor current ripple factor. For switching frequency, This is the output capacitor.

[0033] Furthermore, the comparator is used to reset the RS flip-flop when the carrier signal is greater than the peak modulation wave signal, and correspondingly, after the RS flip-flop is reset, the main switch is turned off and the synchronous switch is turned on through the driving circuit.

[0034] In the above control method and device:

[0035] At the beginning of each switching cycle, sample the inductor current i from n channels. L1~n Output voltage V o Load current I o Each phase carrier signal V ck Based on the n-way inductor current i L1~n Output voltage V o The calculation yielded:

[0036]

[0037] Weighting factor k v and k i The proportions of output voltage and inductor current in the carrier wave are determined, and k must satisfy... v +k i=1, under the premise of achieving current equalization, in order to achieve faster response speed and smaller overshoot and drop, k v It should be as large as possible;

[0038] Adaptive peak modulation wave signal V p Based on the load current I o The calculated peak factor V op and I Lp produce:

[0039]

[0040] The phase difference of each phase clock signal of the n-phase interleaved parallel Buck converter is... ; The PWM drive signals of the main switch and synchronous switch of each phase of the interleaved parallel Buck converter are phase-shifted. .

[0041] The specific control measures are as follows:

[0042] 1. Start the main power topology of the converter. The drive circuit provides a fixed frequency clock signal to the switching transistors of the n-phase interleaved parallel Buck converter.

[0043] 2. The sampling circuit samples the output voltage V at the beginning of each switching cycle. o Inductor current i in each phase Lk (k=1,2, ..., n) and output current i o And send it into the digital control system;

[0044] 3. The digital control system receives the sampled signal, and the carrier signal generation module outputs voltage V. o Inductor current i in each phase Lk After standardization and weighting, each phase carrier signal is generated. The peak modulation wave signal generation module outputs current i o Pre-calculated output voltage peak factor and inductor current peak factor Generates adaptive peak modulation wave signal and each phase carrier signal V ck With peak modulation wave signal V p In comparison, the PWM control signal of each phase Buck converter switching transistor is obtained by sending the RS flip-flop reset terminal, thereby achieving fast transient response, low output voltage ripple and multi-phase current sharing control.

[0045] The control process requirements are as follows: Taking the first phase as an example, at the beginning of each switching cycle, the clock signal sets the RS flip-flop, and the main switch transistor drive signal v... s1When the signal is high, the main switch is on and the synchronous switch is off. When the first phase carrier signal V... ck1 Peak modulation signal V p When the RS flip-flop is reset, v s1 When the clock signal goes low, the main switch turns off and the synchronous switch turns on, until the next clock signal arrives. The clock signals of each subsequent phase differ from the clock signal of the first phase sequentially by a phase difference. .

[0046] The beneficial effects of this invention are as follows:

[0047] 1. This invention provides a VCC control device for an n-phase interleaved parallel Buck converter. Based on voltage ripple and inductor current ripple information, it realizes ripple-based current sharing control. Compared with the traditional peak current control method, the control device of this invention calculates the adaptively adjusted peak modulation wave signal based on the load current, which can effectively realize n-phase current sharing. When the load changes, the peak modulation wave signal is adjusted in real time, which can effectively reduce the current sharing adjustment time after the load trip and quickly reach steady state.

[0048] 2. Compared with traditional peak current control methods, the carrier signal in this invention contains both input voltage and inductor current information, and the control loop is simple, without the need for lead or lag elements. Therefore, it can achieve a faster transient response speed to changes in input voltage and load current. Attached Figure Description

[0049] Figure 1 This is a structural block diagram of a VCC control method and device for a multiphase interleaved parallel Buck converter proposed in this invention.

[0050] Figure 2 This is a circuit topology diagram for implementing the multiphase interleaved parallel Buck converter of this invention.

[0051] Figure 3 This is a flowchart illustrating the VCC control calculation method for an n-phase interleaved parallel Buck converter operating in continuous conduction mode, as proposed in this invention, taking the first phase as an example.

[0052] Figure 4 This is a waveform diagram illustrating the operation of the first phase as an example in an embodiment of the present invention.

[0053] Figure 5 This is a specific circuit connection diagram for implementing the embodiments of the present invention in a six-phase interleaved parallel Buck converter.

[0054] Figure 6 This is a time-domain simulation waveform diagram of an embodiment of the present invention, taking the first phase as an example.

[0055] Figure 7This is a simulation waveform diagram of the six-phase current sharing effect in an embodiment of the present invention.

[0056] Figure 8 Time-domain simulation waveforms of load current and output voltage of a conventional peak current controlled six-phase interleaved parallel Buck converter when the load current changes (the load current jumps from 300A to 200A in 2.5ms).

[0057] Figure 9 This is a time-domain simulation waveform of the load current and output voltage of a six-phase interleaved parallel Buck converter when the load current changes (the load current jumps from 300A to 200A in 2.5ms).

[0058] Figure 10 This is a time-domain simulation waveform of the load current and output voltage of a traditional peak current controlled six-phase interleaved parallel Buck converter when the load current changes (the load current jumps from 200A to 300A in 2.5ms).

[0059] Figure 11 This is a time-domain simulation waveform of the load current and output voltage of a six-phase interleaved parallel Buck converter when the load current changes (the load current jumps from 200A to 300A in 2.5ms).

[0060] Figure 12 This is a time-domain simulation waveform of the input voltage, load current, and output voltage of a traditional peak current controlled six-phase interleaved parallel Buck converter when the input voltage changes (the input voltage jumps from 6V to 4V in 2.5ms).

[0061] Figure 13 This is a time-domain simulation waveform diagram of the input voltage, load current and output voltage of a six-phase interleaved parallel Buck converter when the input voltage changes (the input voltage jumps from 6V to 4V in 2.5ms).

[0062] Figure 14 This is a time-domain simulation waveform of the input voltage, load current, and output voltage of a traditional peak current controlled six-phase interleaved parallel Buck converter when the input voltage changes (the input voltage jumps from 4V to 6V in 2.5ms).

[0063] Figure 15 This is a time-domain simulation waveform of the input voltage, load current, and output voltage of a six-phase interleaved parallel Buck converter when the input voltage changes (the input voltage jumps from 4V to 6V in 2.5ms).

[0064] Figure 16The waveform of the six-phase inductor current is shown when a load switch occurs every 1.25ms. Detailed Implementation

[0065] The technical solution of the present invention will now be clearly and completely described in conjunction with the accompanying drawings, so that those skilled in the art can better understand the present invention.

[0066] like Figure 1 The diagram shows a structural block diagram of a VCC control device for a multiphase interleaved parallel Buck converter proposed in this invention, including a main power topology, a sampling circuit, a digital control system, and a drive circuit.

[0067] like Figure 2 The diagram shows the main power circuit topology of a multi-phase interleaved parallel Buck converter proposed in this invention, including an input voltage source, an n-phase interleaved parallel Buck converter, and an output load connected in series. The n-phase interleaved parallel Buck converter of this invention is designed with a duty cycle of D=1 / n based on the relationship between output current ripple and duty cycle, in order to minimize output current ripple and avoid low-frequency oscillations.

[0068] Figure 3 This is a flowchart illustrating the VCC controller calculation process for the first phase of the proposed VCC control method for an n-phase interleaved parallel Buck converter operating in continuous conduction mode. The flowchart shows the specific calculation formulas for the carrier signal generation module and the peak modulation wave signal generation module for each phase. The carrier signals for each phase are... The peak modulated wave signal is .

[0069] Figure 4 It is based on V ck V p The waveform diagram of the first phase of the n-phase interleaved parallel Buck converter of this invention designed according to the expression is shown. At the beginning of each switching cycle, taking the first phase as an example, CLK1 sets the RS flip-flop, v s1 When the voltage level is high, the main switch is on, the synchronous switch is off, and the inductor current i L1 and output voltage v o Rise, when the first phase carrier signal v c1 Rise to peak modulation signal v p When the comparator flips, it resets the RS flip-flop, v s1 When the signal is low, the main switch is off and the synchronous switch is on. L1 and v o The clock signal decreases until the next clock cycle arrives. The operation of the other phase branches is similar, except that the clock signal is 90° out of phase with the previous phase branch.

[0070] Figure 5The following is based on V ck V p The embodiment of the invention designed with the expression shows the specific circuit connection diagram of VCC control applied to a six-phase interleaved parallel Buck converter. At the beginning of each switching cycle, the voltage sampling module VS of the sampling circuit detects the output voltage V of the six-phase interleaved parallel Buck converter. o The current sampling modules CS1~6 detect the inductor current i. L1~6 CS7 detects load current i o The digital control system receives the outputs of VS and CSK (k=1,2,...,6) and combines them with a preset reference voltage V. ref Reference current I ref =i o / 6 and weighting factor k v and k i The inductor current i of each phase Lk With k i / I ref By multiplying by MULk, the output voltage V o With k v / V ref After multiplying by MUL7, the outputs of MULk and MUL7 are added together by adder ADDk to generate the carrier signal V. ck The output is then sent to comparator CMPk; in addition, the control circuit uses the output current i sampled by CS7 as a reference. o The calculated peak output voltage factor V op and inductor current peak factor I Lp The output current i o The input sent to MUL8, along with k i / 6I ref Multiply and output to the input of ADD7, then multiply with k. v V ref The summation output is fed to the input of MUL9, and then compared with (1+V). op +I Lp Multiplication outputs peak modulated wave signal V p The signal is sent to comparator CMPk. Finally, the carrier signals V of each phase are... ck With peak modulation wave signal V p The comparison result output by CMPk is sent to the reset terminal of RS flip-flop RSk (k=1,2,...,6), and the clock signal CLKk is sent to the set terminal of RS flip-flop RSk (k=1,2,...,6), thereby obtaining the PWM control signals of the main switching transistors and synchronous switching transistors of each phase Buck converter, which are then sent to the drive circuit and output as drive signals to control the on / off state of each phase switching transistor in the main power topology.

[0071] The following is a time-domain simulation of the scheme in this embodiment, taking a six-phase interleaved parallel Buck converter as an example. Simulation conditions are set as follows: input voltage V in =4~6V, switching frequency fs=500kHz, output voltage reference value V ref =1V, load current 200A, inductance of each phase L=0.13μH, equivalent inductance resistance R L =0.58Ω, output filter capacitor C=1000μF, equivalent capacitance resistance is R C =1Ω, output voltage weighting factor k v =0.9, inductor current weighting factor k i =0.1, and time-domain simulation was performed using Matlab / Simulink software. The results are as follows:

[0072] like Figure 6 The waveform shown is the first phase operating waveform in steady state. Figure 6 In the image (a), the waveform of the RS1 clock signal CLK1 is shown. Figure 6 (b) in the diagram represents the first phase carrier signal V. c1 and peak modulation wave signal V p Waveform, Figure 6 (c) in the image represents the drive pulse waveform of the first phase main switch transistor. Figure 6 (d) in the figure represents the waveform of the first phase inductor current. It can be seen that the waveform of the simulation result is consistent with the theoretical analysis.

[0073] Figure 7 The simulation waveform diagram of the six-phase current sharing effect in this embodiment of the invention shows that VCC control can effectively achieve inter-phase current sharing.

[0074] Figure 8 This is a time-domain simulation waveform of the load current and output voltage of a traditional peak current controlled six-phase interleaved parallel Buck converter when the load current changes (the load current jumps from 300A to 200A in 2.5ms). It can be seen that its transient adjustment process requires 390μs, there is a voltage overshoot of 0.18V, and the output voltage ripple is relatively large.

[0075] Figure 9 This is a time-domain simulation waveform of the load current and output voltage of the six-phase interleaved parallel Buck converter in this embodiment of the invention when the load current changes (the load current jumps from 300A to 200A in 2.5ms). It can be seen that its transient adjustment process requires 20μs, there is a voltage overshoot of 0.09V, and the output voltage ripple is small.

[0076] Figure 10This is a time-domain simulation waveform of the load current and output voltage of a traditional peak current controlled six-phase interleaved parallel Buck converter when the load current changes (the load current jumps from 200A to 300A in 2.5ms). It can be seen that its transient adjustment process takes 610μs, and there is a voltage drop of 0.13V and a large output voltage ripple.

[0077] Figure 11 This is a time-domain simulation waveform of the load current and output voltage of the six-phase interleaved parallel Buck converter in this embodiment of the invention when the load current changes (the load current jumps from 200A to 300A in 2.5ms). It can be seen that its transient adjustment process requires 23μs, there is a voltage drop of 0.08V, and the output voltage ripple is small.

[0078] Therefore, compared with the traditional peak current controlled six-phase interleaved parallel Buck converter, the output voltage ripple of the converter controlled by the present invention is significantly smaller in steady state than the traditional peak current control method. It also has a faster transient response speed and smaller voltage overshoot and drop when the load current changes.

[0079] Figure 12 This is a time-domain simulation waveform of the input voltage, load current, and output voltage of a traditional peak current controlled six-phase interleaved parallel Buck converter when the input voltage changes (the input voltage jumps from 6V to 4V in 2.5ms). It can be seen that its transient adjustment process requires 140μs, and the output voltage ripple is relatively large.

[0080] Figure 13 This is a time-domain simulation waveform of the input voltage, load current, and output voltage of the six-phase interleaved parallel Buck converter in this embodiment of the invention when the input voltage changes (the input voltage jumps from 6V to 4V in 2.5ms). It can be seen that its transient adjustment process requires 100μs, and the output voltage ripple is relatively small.

[0081] Figure 14 This is a time-domain simulation waveform of the input voltage, load current, and output voltage of a traditional peak current controlled six-phase interleaved parallel Buck converter when the input voltage changes (the input voltage jumps from 4V to 6V in 2.5ms). It can be seen that its transient adjustment process requires 235μs, and the output voltage ripple is relatively large.

[0082] Figure 15 This is a time-domain simulation waveform of the input voltage, load current, and output voltage of the six-phase interleaved parallel Buck converter in this embodiment of the invention when the input voltage changes (the input voltage jumps from 4V to 6V in 2.5ms). It can be seen that its transient adjustment process requires 100μs, and the output voltage ripple is relatively small.

[0083] Therefore, compared with the traditional peak current controlled six-phase interleaved parallel Buck converter, the converter controlled by the present invention has a significantly smaller output voltage ripple than the traditional peak current controlled six-phase interleaved parallel Buck converter, and has a faster transient response speed and smaller output voltage ripple when the input voltage changes.

[0084] Figure 16 The waveforms of the six-phase inductor currents when a load switch occurs every 1.25ms show that the six-phase inductor currents can quickly reach a steady state after the transient switching process, maintaining a good six-phase current sharing effect.

Claims

1. A VCC control method for a multiphase interleaved parallel Buck converter, characterized in that, Includes the following steps: S1. Obtain the inductor current signal, voltage signal and load current signal of each branch in the multiphase interleaved parallel Buck converter by sampling; S2. Calculate the carrier signal and peak modulation wave signal of each phase using the acquired inductor current signal, voltage signal and load current signal; S3. Generate PWM control signals based on the obtained phase carrier signals and peak modulation wave signals, and realize the control of the multi-phase interleaved parallel Buck converter through the drive circuit. In step S2, when calculating the carrier signal and peak modulation wave signal of each phase, in addition to using the inductor current signal, voltage signal and load current signal, it is also necessary to use the voltage peak factor and current peak factor, which are calculated by known circuit parameters. If a multiphase interleaved parallel Buck converter is defined to have n phases, then the carrier signal of each phase is calculated. The formula is: ， Where, k v and k i It is the current weighting factor. The voltage signal obtained by sampling. The sampled branch inductor current signal is given, where the subscript k indicates a branch in an n-phase interleaved parallel Buck converter. ; Calculate peak modulation signal The formula is: ， in, For voltage peak factor, This is the peak factor of the inductor current. For reference voltage, For reference current, The load current signal is obtained from the sampling circuit; The formulas for calculating the voltage peak factor and the inductor current peak factor are as follows: ， ， in This is the inductor current ripple factor. For switching frequency, This is the output capacitor.

2. The VCC control method for a multiphase interleaved parallel Buck converter according to claim 1, characterized in that, In step S3, the method for generating the PWM control signal is to input the carrier signal of each phase and the peak modulation wave signal into a comparator, wherein the carrier signal of each phase is the input of the non-inverting terminal of the comparator, and the peak modulation wave signal is the input of the inverting terminal of the comparator. The output signal of the comparator is used as the input of the R terminal of the RS flip-flop. The RS flip-flop outputs the PWM control signal, which is then passed through the drive circuit to control the switching transistors in the multi-phase interleaved parallel Buck converter.

3. A VCC control device for a multiphase interleaved parallel Buck converter, characterized in that, The system includes an interconnected main power topology, sampling circuit, digital control system, and drive circuit. The main power topology is an n-phase interleaved parallel Buck converter. The gates of the switching devices of the n-phase interleaved parallel Buck converter are connected to the output of the drive circuit, and the output of the n-phase interleaved parallel Buck converter is connected to the sampling circuit. The output of the sampling circuit is connected to the digital control system, and the output of the digital control system is connected to the input of the drive circuit. The digital control system includes an n-channel carrier signal generation module, a peak modulation wave signal generation module, a comparator, and an RS flip-flop. The sampling circuit is used to acquire the branch inductor current signal, voltage signal, and load current signal in the n-phase interleaved parallel Buck converter. The branch inductor current and voltage signals are input to the n-channel carrier signal generation module, and the load current signal is input to the peak modulation wave signal generation module. The output of the n-channel carrier signal generation module is connected to the positive input of a comparator, the output of the peak modulation wave signal generation module is connected to the negative input of a comparator, the output of the comparator is connected to the reset terminal of an RS flip-flop, the set terminal of the RS flip-flop is connected to a clock signal, and the output of the RS flip-flop is the output of the digital control system. The n-channel carrier signal generation module calculates and generates each phase carrier signal based on the obtained branch inductor current and voltage signals, and the peak modulation wave signal generation module calculates and generates the peak modulation wave signal based on the obtained load current signal. The n-channel carrier signal generation module calculates the carrier signal of each phase. The formula is: ， Where, k v and k i It is the current weighting factor. The voltage signal output by the sampling circuit. The subscript represents the branch inductor current signal output by the sampling circuit. This represents a branch in an n-phase interleaved parallel Buck converter. ; The peak modulation wave signal generation module calculates the peak modulation wave signal. The formula is: ， in, For voltage peak factor, This is the peak factor of the inductor current. For reference voltage, For reference current, The load current signal output by the sampling circuit; The voltage peak factor and inductor current peak factor are calculated based on preset values ​​of circuit parameters, and the formulas are as follows: ， ， in This is the inductor current ripple factor. For switching frequency, This is the output capacitor.

4. The VCC control device for a multiphase interleaved parallel Buck converter according to claim 3, characterized in that, The comparator is used to reset the RS flip-flop when the carrier signal is greater than the peak modulation wave signal. Correspondingly, after the RS flip-flop is reset, the main switch is turned off and the synchronous switch is turned on through the driving circuit.

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