Pitch reduced memory subsystem for memory devices

Abstract

A memory device includes an array of memory cells and a plurality of bit lines, where each bit line is connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit line connection and each second memory circuit includes a second bit line connection, the first and second bit line connections can be connected to a respective bit line. Each first bit line connection is disposed on a first bit line connection line of the memory subsystem and each second bit line connection is disposed on a second bit line connection line of the memory subsystem, and the second bit line connection line can be offset from the first bit line connection line by a predetermined distance greater than zero.

Description

Technical Field

[0001] This disclosure generally relates to memory devices, and in particular, to memory subsystems for reducing the pitch of memory devices. Background Technology

[0002] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. Many different types of memory exist, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), static random access memory (SRAM), and flash memory. As memory devices evolve, there is a need to make memory devices (including memory subsystems) as small and / or as compact as possible.

[0003] For the reasons stated above, and for other reasons set forth below that will become obvious to those skilled in the art upon reading and understanding this specification, there is a need in the art for memory subsystems that allow for smaller pitch. Attached Figure Description

[0004] Figure 1 A block diagram illustrating an embodiment of the memory system according to the present disclosure.

[0005] Figure 2A and 2B A top plan view illustrating a simplified layout of the protection circuit according to this disclosure.

[0006] Figures 3A to 3C A top view illustrating a simplified block diagram of a portion of the protection circuit according to this disclosure.

[0007] Figure 3D This describes the alternative configurations of the bitline node and source node according to this disclosure.

[0008] Figure 4A and 4B The side and top views of the integrated planar NMOS-vertical PMOS inverter according to this disclosure are shown.

[0009] Figure 5A and 5B The side and top views of the integrated vertical CMOS inverter according to this disclosure are shown.

[0010] Figures 6A to 6D A top view illustrating the inverter interconnection according to this disclosure.

[0011] Figure 7A and 7B illustrate Figure 6D Alternative embodiments of interconnection.

[0012] Figures 8A to 8C This describes the intermediate components formed during the exemplary manufacturing process of an integrated inverter according to this disclosure.

[0013] Figures 9A to 9G This describes the intermediate components formed during the exemplary manufacturing process of an integrated inverter according to this disclosure. Detailed Implementation

[0014] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and specific embodiments are illustrated in the drawings by way of illustration. Throughout the drawings, the same reference numerals describe generally similar components. Other embodiments may be utilized without departing from the scope of this disclosure, and structural, logical, and electrical changes may be made. Therefore, the following detailed description should not be considered limiting.

[0015] For example, as used herein, the term "semiconductor" may refer to a layer of material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referenced to a semiconductor in the following description, regions / junctions may have been formed in the substrate semiconductor structure using prior processing steps, and the term semiconductor may include an underlying layer containing such regions / junctions.

[0016] Some exemplary embodiments of this disclosure may relate to memory devices such as flash memory devices. Flash memory devices (e.g., NAND, NOR, etc.) have been developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its data value for a long time without the application of power. Flash memory devices typically use single-transistor memory cells that allow for high memory density, high reliability, and low power consumption. The data value of each memory cell is determined by a change in the threshold voltage of the memory cell through programming (sometimes referred to as writing) of the charge storage structure (e.g., a floating gate or charge trap) or other physical phenomena (e.g., phase change or polarization). Common uses for flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, electrical appliances, vehicles, wireless devices, mobile phones, and removable memory modules, and the uses of non-volatile memory continue to expand.

[0017] In NOR flash architecture, memory cells arranged in columns are coupled in parallel, with each memory cell coupled to a data line, such as a bit line. A "column" refers to a group of memory cells that are commonly coupled to a local data line (e.g., a local bit line). A column does not require any specific orientation or linear relationship, but rather refers to the logical relationship between the memory cell and the data line. Typically, memory cell arrays for NAND flash memory devices are arranged such that the control gates of each memory cell in a row are connected together to form an access line, such as a word line. A column of the array contains a string of memory cells (often called a NAND string) connected in series (e.g., source-to-drain) between a pair of select lines (e.g., source select line and drain select line). A source select line contains a source select gate at each intersection of the NAND string and the source select line, and a drain select line contains a drain select gate at each intersection of the NAND string and the drain select line. Each source select gate is connected to a source line, and each drain select gate is connected to a data line, such as a column bit line.

[0018] This disclosure relates to a memory device having a memory cell array. The memory device includes a plurality of bit lines, wherein each bit line is connected to a corresponding set of memory cells in the memory cell array. The memory device may include a memory subsystem having a set of first memory circuits and a set of second memory circuits. Each first memory circuit may be laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit line connection and each second memory circuit includes a second bit line connection, the first and second bit line connections being adaptable to connect to corresponding bit lines of the plurality of bit lines. In some embodiments, each of the first bit line connections is disposed on a first bit line connection line of the memory subsystem and each of the second bit line connections is disposed on a second bit line connection line of the memory subsystem, and the second bit line connection line may be offset from the first bit line connection line by a predetermined distance greater than zero.

[0019] In another embodiment, the memory device includes a memory cell array and a plurality of bit lines, wherein each bit line is connected to a corresponding set of memory cells in the memory cell array. The memory device includes memory circuitry with a memory latch. The memory latch includes a first integrated inverter having at least one vertical transistor and a second integrated inverter having at least one vertical transistor. In some embodiments, each integrated inverter includes a common input gate configured around a gate.

[0020] Figure 1This is a simplified block diagram of a NAND flash memory device 100 communicating with a processor 130, which is part of an electronic system, according to an embodiment. The processor 130 may be a memory controller or other external host device. The memory device 100 includes a memory cell array 104. A row decoder 108 and a column decoder 110 are provided to decode address signals. Address signals are received and decoded to access the memory array 104.

[0021] The memory device 100 also includes an input / output (I / O) control circuitry 112 to manage inputs of commands, addresses, and data to the memory device 100, as well as outputs of data and status information from the memory device 100. An address register 114 communicates with the I / O control circuitry 112 and row decoders 108 and column decoders 110 to latch address signals before decoding. A command register 124 communicates with the I / O control circuitry 112 and control logic 116 to latch incoming commands. Control logic 116 controls access to the memory array 104 in response to commands and generates status information for the external processor 130. Control logic 116 communicates with row decoders 108 and column decoders 110 to control row decoders 108 and column decoders 110 in response to addresses.

[0022] Control logic 116 also communicates with memory subsystem circuitry, which may include cache register 118, data register 120, and / or circuit protection subsystem 150. Cache register 118 latches incoming or outgoing data, as directed by control logic 116, to temporarily store data while memory array 104 is busy writing or reading other data. During a write operation, data is transferred from cache register 118 to data register 120 for transfer to memory array 104; subsequently, new data is latched from I / O control circuitry system 112 into cache register 118. During a read operation, data is transferred from cache register 118 to I / O control circuitry system 112 for output to external processor 130; subsequently, new data is transferred from data register 120 back to cache register 118. Status register 122 communicates with I / O control circuitry system 112 and control logic 116 to latch status information for output to processor 130.

[0023] According to various embodiments, the circuit protection subsystem 150 may be arranged between the data register 120 (and / or cache register 118) and the memory array 104. For example, the low-voltage circuitry of the data register 120 and / or cache register 118 may be coupled to one side of the circuit protection subsystem 150 (e.g., the low-voltage side), and the data lines or bit lines of the memory array 104 may be coupled to the other side of the circuit protection subsystem 150 (e.g., the high-voltage side).

[0024] The memory device 100 receives control signals from the processor 130 at the control logic 116 via the control link 132. The control signals may include at least chip enable (CE#), command latch enable (CLE), address latch enable (ALE), and write enable (WE#). The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via a multiplexed input / output (I / O) bus 134 and outputs data to the processor 130 via the I / O bus 134.

[0025] For example, commands are received via the input / output (I / O) pins [7:0] of the I / O bus 134 at I / O control circuitry system 112, and written to the command register 124. Addresses are received via the input / output (I / O) pins [7:0] of the bus 134 at I / O control circuitry system 112, and written to the address register 114. Data is received via the input / output (I / O) pins [7:0] for 8-bit devices or the input / output (I / O) pins [15:0] for 16-bit devices at I / O control circuitry system 112, and written to the cache register 118. The data is then written to the data register 120 for programming the memory array 104. In another embodiment, the cache register 118 may be omitted, and data may be written directly to the data register 120. Data can also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices.

[0026] Those skilled in the art should understand that additional circuitry and signals can be provided. Figure 1 The memory device has been simplified. It should be recognized that the reference... Figure 1 The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0027] Furthermore, although specific I / O pins are described according to general conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins may be used in various embodiments. The configuration of memory array 104 is known to those skilled in the art and will therefore not be discussed further unless required to describe exemplary embodiments of this disclosure. Additionally, although exemplary embodiments may be discussed in conjunction with NAND flash architectures, the embodiments described herein are not limited to NAND flash, and exemplary embodiments may include other flash architectures, such as NOR flash, etc.

[0028] Data lines are sometimes coupled to circuitry that can be configured to handle relatively low voltages (e.g., referred to as low-voltage circuitry), such as data cache circuitry. Low-voltage circuitry can provide relatively low voltages (e.g., 0V up to about 4V) to the data lines during read or write operations. However, during erase operations (e.g., involving NAND memory arrays), a memory cell can be erased at a certain point by grounding all access lines in the block, for example, allowing each data line to float simultaneously. A relatively high erase voltage (e.g., about 20V to 30V) is then applied to the semiconductor on which the memory cell forms, and thus to the channels of the memory cell, to remove charge from the charge storage structure. This can cause the data lines to float near the erase voltage and can damage the low-voltage circuitry coupled to the data lines.

[0029] Protection devices (e.g., field-effect transistors (FETs)) may be coupled between the bit line and a low-voltage circuitry (e.g., the low-voltage circuitry of data cache 118 and / or data register 120) to protect the low-voltage circuitry from relatively high voltages that may be present on the bit line during an erase operation. For example, the FET may be turned off during an erase operation to protect the low-voltage circuitry from relatively high voltages that may be present on the bit line, and the FET may be turned on during a read or write operation to pass a relatively low voltage between the low-voltage circuitry and the bit line. Each circuit protection device may be formed on an active region separated and electrically isolated from an adjacent active region by an isolation region (e.g., a shallow trench isolation (STI) region), and adjacent circuit protection devices may be formed on said adjacent active region. The bit line may be coupled to the high-voltage side of the circuit protection device, and the low-voltage circuitry may be coupled to the low-voltage side of the circuit protection device. For example, in a FET, contacts (e.g., referred to as high-side contacts) couple bit lines to the source / drain regions on the high-side, and contacts (e.g., also referred to as low-side contacts) couple low-voltage circuitry to the source / drain regions on the low-side. Circuit protection devices can be coupled to bit lines on a one-to-one basis, or a circuit protection device can be coupled to two or more data lines via a multiplexer. However, the spacing between circuit protection devices can be relatively large (e.g., 38 nm or more) to prevent circuit protection device failure. This relatively large spacing occupies a considerable area and thus increases the size of the memory device.

[0030] Figure 2A and 2B This is a top plan view of an exemplary embodiment of a circuit protection subsystem 150 that may include multiple protection circuits 210 to provide high-voltage isolation (e.g., isolation of 20V to 30V signals). Similar protection circuits are discussed in detail in the applicant's U.S. Patents Nos. 8,766,365 and 10,163,893, which are incorporated herein by reference in their entirety as background. Therefore, for the sake of brevity, the description of the protection circuits herein focuses on the features of the present invention. Furthermore, while the exemplary embodiments of this disclosure are provided using circuit protection devices associated with caches and / or data registers, those skilled in the art will understand that this disclosure is applicable to other types of memory circuits, such as circuits connected to other types of data lines.

[0031] In an exemplary embodiment of this disclosure, the circuit protection subsystem 150 may include a circuit arranged in line 212 (e.g., as shown in the example). Figure 2AThis includes a collection of one or more protection circuits 210 arranged vertically (as shown in the diagram) and another collection of one or more protection circuits 210 arranged in line 214 of the protection circuits 210. Representative protection circuits 210 are identified by dashed rectangles. Each protection circuit 210 may include a source / drain node 220, a polysilicon gate 215 (also referred to herein as data gate 215), and a source / drain node 222. Node 220 (also referred to herein as low-voltage (LV) node 220) may be coupled via, for example, contact 225 (“LV contact 225”) to a low-voltage circuit system such as data cache 118 and / or data register 120. Depending on the memory operation (e.g., erase, read, program, etc.), node 222 may be coupled to a circuit system that may have a relatively high voltage (e.g., about 20V to about 30V during, for example, an erase operation) and / or a relatively low voltage (e.g., about 0V to about 4V during, for example, a read or program operation). In some embodiments, each node 222 (also referred to herein as bit line (BL) node 222) may be connected to a corresponding bit line of memory array 104 via, for example, contact 227 (“BL contact 227”). In operation, when a low-voltage memory operation (e.g., a read / program operation) occurs, the data gate 215 may be turned on to connect LV node 220 to BL node 222. When a high-voltage memory operation (e.g., an erase operation) occurs, the data gate 215 may be turned off to isolate the LV node from the high voltage on BL node 222. As used herein, BL nodes and corresponding BL contacts may also be referred to herein as BL connections.

[0032] Each portion of the protection circuit 210 may be formed in an individual active region 228 defined by an isolation region 230 (e.g., an STI region) formed in the semiconductor. Each active region 228 may include a corresponding LV node 220, a data gate 215, and may extend to a corresponding BL node 222 surrounding the BL contact 227 (see, for example...). Figure 2A (See arrow 228 in the diagram). Isolation regions 230 may be formed on either side of one or more active regions 228. Each isolation region 230 electrically isolates and / or physically separates adjacent active regions 228 from each other. The semiconductor may be made of silicon (e.g., single-crystal silicon) and may be conductively doped to have a conductivity type (e.g., p-type conductivity) for example to form a p-well.

[0033] In some embodiments, the circuit protection subsystem 150 may include an active region 232 configured to form one or more transistors (e.g., FETs). The active region 232 may be covered by a polysilicon layer forming a common gate 235 for one or more transistors, which in some embodiments may extend beyond the active region 232. In some embodiments, the polysilicon layer may be segmented such that more than one gate (e.g., a gate similar to the common gate 235) is formed. In some embodiments, the active region 232 may include one or more source (SRC) nodes 237 that may be formed in openings in the polysilicon layer. The SRC node 237 may include contacts 239 that can be connected to a voltage source. As used herein, the SRC node and the corresponding SRC contact may also be referred to herein as an SRC connection. In some embodiments, the active region 232 may include at least a portion of a BL node 222. One or more transistors defined by a common gate 235 may be configured such that when the common gate 235 is turned on, the BL node 222 and one or more SRC nodes 237 are connected, and when the common gate 235 is turned off, the BL node 222 and one or more source nodes 237 are isolated from each other. In some embodiments, unlike the LV node 220, the BL node 222 and / or SRC node 237 are not separated from each other by an isolation region (e.g., STI) formed in the semiconductor. Alternatively, the BL node 222 is selectively electrically coupled to each other and electrically coupled to one or more SRC nodes 237 via the common gate 235. In some embodiments, the active region 228 may be adjacent to the active region 232. That is, the active region 228 may extend from the active region 232, such as Figure 2A As shown in the diagram. When BL node 222 is connected to a low voltage (e.g., about 0V to about 4V), sufficient isolation exists between BL nodes 222 when the common gate 235 is disconnected (e.g., by grounding the common gate contact 237). Therefore, the need to form isolation regions to create separate active regions for BL node 222 and / or SRC node 237 can be avoided.

[0034] In some embodiments, similar to the common gate 235, the polysilicon for the data gate 215 may extend beyond the active region 228. During a read / program operation, the data gate 215 may be turned on to selectively couple the corresponding low-voltage circuitry (e.g., data cache 118 and / or data register 120) to the corresponding bit line via BL node 222 and BL contact 227. During this time, the common gate 235 is turned off to isolate the BL node 222 from one or more SRC nodes 237, which may be connected to a voltage source via corresponding SRC contacts 239. During an erase operation, the data gate 215 may be turned off to isolate the low-voltage circuitry (e.g., data cache 118 and / or data register 120) from the corresponding bit line. During this time, the common gate 235 is turned on to connect the BL node 222 to a voltage source (e.g., a high-voltage source) via the SRC contacts 239 of one or more SRC nodes 237. Figure 2B As shown, the n+ mask layer 270 (mostly shaded inside) can be used to deposit n+ implantation regions around the BL contact 227 and SRC contact 239. The n+ implantation regions provide a low resistivity area around the contacts to ensure better and more reliable connections.

[0035] As memory devices become smaller and / or more compact (e.g., in 3D NAND devices), it may be necessary to reduce the distance or spacing between bit lines in a memory array (e.g., memory array 104). For example, in some memory circuits, BL contacts are arranged laterally adjacent to each other in a straight line (also referred to herein as “non-offset BL lines”). In such systems, the BL spacing is the distance between the BL contacts, and reducing the BL spacing means reducing the distance between the BL contacts. However, the BL contacts may already be at an effective distance corresponding to a minimum effective distance. As used herein, “effective distance” means the shortest distance between adjacent BL contacts or the shortest distance between n+ implants placed around adjacent BL contacts, whichever is shorter. That is, the effective distance may not necessarily be the shortest distance between the BL contacts themselves. This is because the n+ implants have low resistivity, so the shortest distance between the n+ implants around the BL contacts can be a limiting factor when the BL spacing is reduced. As used herein, “minimum effective distance” means that further reduction of the effective distance between BL contacts would adversely affect BL-BL leakage (isolation) and / or breakdown voltage (BV) until BL-BL leakage and / or BV fall outside the predetermined design values ​​of the memory device. Bit-to-bit leakage affects the ability to properly read data from the bit line, while BV affects the maximum erase voltage of the gate and / or gate oxide reliability. For example, in some memory systems, a 38 nm BL pitch may correspond to an effective distance of 5.76 nm. However, due to variations in mass production, further reduction of the effective distance may be impossible while keeping BV or BL-BL leakage within the predetermined design values ​​of the memory device. Therefore, in conventional configurations where adjacent BL contacts are arranged in a straight line, once the BL pitch of adjacent BL contacts corresponds to the minimum effective distance and / or falls within the variations in mass production, there are few or no BL pitch limits that can be sacrificed without exceeding the design guidelines regarding BL-BL leakage and / or BV, and further reduction of the protection circuit pitch may not be achievable. For example, it is believed that a BL pitch of less than 37nm (corresponding to an effective distance of 5.44nm) cannot be achieved in traditional systems.

[0036] In some exemplary embodiments of this disclosure, the BL contacts 227 (and / or corresponding n+ implants) in the circuit protection subsystem 150 may be located on a non-offset BL line, while laterally adjacent BL contacts 227 (and / or corresponding n+ implants) may be positioned at a predetermined distance (e.g., a greater than zero offset) from the non-offset BL line. The predetermined distance or offset may be in a direction perpendicular to the non-offset BL line. The direction parallel to the non-offset BL line is referred to herein as the “width direction,” and the direction perpendicular to the non-offset BL line may be referred to herein as the “length direction.” For clarity, reference to the n+ implant may be omitted in the following description when discussing the BL contacts; however, those skilled in the art will understand that in some embodiments, the BL contacts of the circuit protection subsystem 150 may have surrounding n+ implants (or p+ implants, depending on the type of transistor, or another type of doping). By offsetting some BL contacts 227 in the length direction, the BL spacing (“offset BL spacing”) in the width direction between the offset BL contacts and the non-offset BL contacts can be smaller than the BL spacing (“non-offset BL spacing”) of a circuit protection device having adjacent non-offset BL contacts. Figure 2A The arrow marked "P" indicates the BL spacing, which in this case corresponds to the offset BL spacing because the "B" BL contact 227 is offset. By offsetting the "B" BL contact 227 (discussed further below), the offset BL spacing (e.g., spacing P) can be smaller than the non-offset BL spacing, and the effective distance can remain the same between the offset and non-offset BL spacings. In some embodiments, the offset BL spacing can be smaller than the minimum effective distance, while maintaining the actual effective distance between the BL contacts at or above the minimum effective distance.

[0037] In some embodiments, more than one “B” BL contact 227 is offset from an adjacent “A” BL contact 227 and arranged on an offset bit line connection line OBL (also referred to herein as “offset BL line OBL”), while the adjacent “A” BL contact is not offset and arranged on a non-offset bit line connection line NOBL (also referred to herein as “non-offset BL NOBL”). The BL contacts 227 are arranged on the offset BL line OBL and the non-offset BL line NOBL to form an offset staggered (or Z-shaped) pattern along the width direction of the circuit protection subsystem 150. Therefore, a set of BL contacts can be formed along the non-offset BL line NOBL, and another set of BL contacts can be formed along the offset BL line OBL. In some embodiments, the non-offset BL contacts and laterally adjacent offset BL contacts can form a repeating alternating pattern. For example, such as Figure 2A and 2BAs seen herein, the "B" BL contact 227 (and corresponding BL node 222) of protection circuit 210 may be offset in the longitudinal direction by a predetermined distance L1 (also referred to herein as "offset distance L1") relative to the "A" BL contact 227 (and corresponding BL node 222) of the laterally adjacent protection circuit 210. In some exemplary embodiments, the BL contact 227 of each other protection circuit 210 may be positioned at the offset distance L1. However, in other embodiments, other offset distance patterns may be used, such as every other protection circuit 210, every two protection circuits 210, etc. Additionally, in Figure 2A In exemplary embodiments, only a single offset distance (e.g., offset distance L1) is used in the offset interlaced pattern. However, in other embodiments, the BL contacts of the corresponding protection circuits can be arranged in any number of predetermined offset distance patterns. For example, protection circuits 210 can be arranged in an interlaced pattern (e.g., a repeating interlaced pattern), wherein a first BL contact has zero offset (e.g., on a non-offset BL line NOBL), a next BL contact has a first predetermined offset distance (e.g., offset distance L1), a next BL contact has a second predetermined offset distance (not shown) that is different from offset distance L1 and is non-zero, and so on. In some embodiments, the length of the circuit protection subsystem 150 can be increased by offsetting the BL contacts 227 of one or more protection circuits 210. However, since the spacing of one or more protection circuits 210 can be reduced by offsetting the BL contacts, the total area of ​​the circuit protection subsystem 150 can be reduced regardless of the potential increase in length. Furthermore, because the offset pitch is reduced compared to the non-offset BL pitch, the memory array 104 can be made more compact and / or more memory cells can be added while shrinking its physical size (or shrinking it to a minimum without increasing its physical size). By arranging the BL contacts 227 with an offset staggered pattern, the offset BL pitch of the protection circuit 210 can be reduced compared to the non-offset BL pitch, while maintaining the same effective distance between adjacent BL contacts 227. In some embodiments, while the effective distance between adjacent BL contacts 227 is maintained at or greater than the minimum effective distance, the BL pitch can be reduced to a value less than 37 nm, less than 36 nm, between 35 nm and 37 nm, or between 35 nm and 36 nm. In some embodiments, while the effective distance between adjacent BL contacts 227 is maintained at or greater than the minimum effective distance, the BL pitch can be reduced to a value less than the minimum effective distance.

[0038] In some embodiments, the offset distance L1 is set such that the effective distance D1 between one or more adjacent BL contacts 227 (e.g., between an offset BL contact and a non-offset BL contact) (see [reference]). Figure 2BThis is equal to the minimum effective distance. In some embodiments, the offset distance L1 is set such that the effective distance D1 is in the range of 5nm to 7nm. Figure 2B As seen, the BL contact 227 is formed in a region with a rectangular cutout in the polysilicon of the common gate 235. Figure 2B In an exemplary embodiment, the effective distance D1 is measured from the corner of the n+ implant of the non-offset BL contact 227 to the nearest corner of the n+ implant of the offset BL contact 227. Of course, the polysilicon notch shape is not limited to a rectangular shape and may include other shapes, such as circular, elliptical, triangular, etc. In some embodiments, the offset distance L1 is set such that the effective distance D2 between the SRC contact 239 and one or more adjacent offset BL contacts 227 is equal to or greater than a minimum effective distance. In some embodiments, the offset distance L1 is set such that the effective distance D2 is in the range of 5 nm to 7 nm. The effective distance D2 may be the distance from the outer portion (e.g., a corner or another portion of the periphery) of the n+ implant of the SRC contact 239 to the nearest outer portion (e.g., a corner or another portion of the periphery) of the adjacent n+ implant of the offset BL contact 227.

[0039] In some embodiments, an offset distance L1 is set such that the effective distance D1 is equal to or greater than the minimum effective distance, and the length AA1 of the active region 232 is set such that the effective distance D2 is equal to or greater than the minimum effective distance. However, in some embodiments, in order to maintain the effective distance D2 at or greater than the minimum effective distance, the SRC node 237 may be selectively formed in a region of the common gate 235 that allows the effective distance to be equal to or greater than the minimum effective distance. For example, such as Figure 2A and 2B As seen, the SRC node 237 can be positioned in a location that is not offset from the opposing BL contact 227 (and corresponding BL node 222) (e.g., “A” BL contact 227). The number of SRC nodes 237 and corresponding SRC contacts 239 can depend on factors such as, for example, the number of individual polysilicon gates forming a continuous common gate 235, the number of offset BL nodes 222, the resistivity of the connection to the SRC contacts 239 of the common gate 235, and / or the reliability of the connection to the SRC contacts 239 of the common gate 235. The number of SRC nodes 237 can be equal to or greater than the number of BL nodes 222. However, in other embodiments, the number of source nodes 237 can be less than the number of BL nodes 222. For example, in Figure 2A and 2B In this embodiment, the number of SRC nodes 237 will be approximately 25% of the number of BL nodes 222.

[0040] Figure 2BAn exemplary embodiment is described for forming an n+ mask around the BL contact 227 and SRC contact 239. The n+ mask layer 270 is overlapped by a polysilicon gate 235. In some exemplary embodiments, the n+ mask layer 270 may have an interleaved configuration corresponding to an offset interleaved pattern of the BL contact 227. For example, as... Figure 2B As seen, the n+ mask layer 270 has an edge profile 272 (e.g., a stepped edge profile) that matches the offset staggered pattern on the BL contact 227 of node 222. Based on the n+ mask layer 270, the area surrounding the location of one or more BL contacts 227 and / or one or more SRC contacts 239 will contain the n+ implant. By configuring the edges of the n+ mask layer 270 to match the offset staggered pattern of the BL contacts 227, the distance D3 from the BL contacts 227 to the exposed silicon portion of node 222 remains constant between the offset and non-offset BL node 222 of the protection circuit 210.

[0041] As in Figure 2B As most clearly seen, in some embodiments, the edge 229 of the active region 228 adjacent to the active region 232 may be formed to match the staggered (e.g., offset) pattern of the active regions 232 and / or the BL contacts 227. For example, the edge 229 may be formed between the fingers 236 of the common gate 235 under the polysilicon of the common gate 235, such that the distance D4 from the BL contact 227 to the edge 229 of the active region 228 is the same for each of the protection circuits 210. In some embodiments, similar to the edge 229 of the active region 228, the polysilicon edge 237 of the common gate 235 may also have a pattern corresponding to the offset staggered pattern of the BL nodes 222 and / or the BL contacts 227. Thus, in such embodiments, similar to the distance D4, the distance from the BL contact 227 to the polysilicon edge 236 of the corresponding common gate 235 may be the same for each protection circuit 210.

[0042] In some embodiments, the distance D5 from the BL contact 227 to the data gate 215 may be equal across the protection circuits 210 in order to keep the total resistance of the BL node 222 (e.g., the resistance from the data gate 215 to the corresponding BL contact 227) equal across the protection circuits 210. Therefore, in some embodiments, the positions of one or more data gates 215 may also be staggered by an offset distance (e.g., offset distance L1) matching the offset staggered pattern of the corresponding BL contacts 227.

[0043] In some embodiments, if the data gates 215 are interleaved, the LV nodes 220 and / or LV contacts 225 may also be interleaved (not shown) such that the lengths and / or resistances of the LV nodes 220 can be set to be equal. That is, in some embodiments, the lengths of the LV nodes 220 and the data gates 215 may be equal. In some embodiments (e.g., as shown) Figure 2A As shown in the diagram, LV nodes 220 and contacts 225 are arranged in a straight line (e.g., not intersecting), but data gates 215 are intersected. Therefore, to the extent that equal resistance is required between low-voltage nodes 220, LV nodes 220 can be configured (e.g., by composition or physical dimensions such as length, width, etc.) such that the resistance values ​​are equal in the protection circuit 210.

[0044] Figure 3A A simplified block diagram illustrating a portion of the circuit protection subsystem 150, which includes a block representing the data gate 215 and a simplified section illustrating the common gate 235. Figure 2A and 3A As seen, the protection circuit 210 is mirrored along the centerline of the circuit protection subsystem 150 containing the common gate 235. In this embodiment, due to the stepped (or staggered) n+ mask edges 330, the n+ implants in the BL node 222 are equal. Therefore, the active regions 228 can also be staggered to maintain equal resistance as discussed above. Figure 3A As seen, the common gate segment 235 includes one or more p-well implant layers 310. The p-well implant layers 310 may be disposed between BL nodes 222 and / or SRC nodes 237, and serve to define the boundaries between BL nodes 222 and / or between BL nodes 222 and SRC nodes 237. In some embodiments, the p-well implant layers 310 are disposed perpendicular to a line (e.g., line 320) corresponding to the effective distance between n+ implants adjacent to BL nodes 222, and / or a line (e.g., line 322) corresponding to the shortest distance between n+ implants of SRC node 237 and adjacent BL nodes 222. In other embodiments (not shown), the p-well implants are disposed in a straight line between BL nodes 222 and / or between BL nodes 222 and SRC nodes 237, such that the p-well implants intersect each other at 90 degrees. A portion of the p-well implantation layer 310 may be doped (e.g., lightly doped) to have p-type conductivity, wherein the doped portion has a desired threshold voltage (Vt) for the channel of the field-effect transistor formed between BL nodes 222 and / or the channel of the field-effect transistor formed between BL node 222 and SRC node 237.

[0045] Figure 3BA simplified block diagram illustrating a portion of another embodiment of the circuit protection subsystem. The circuit protection subsystem 150' includes a block illustrating the data gate 215 and a simplified section illustrating the common gate 235. In this embodiment, the n+ mask layer 340 is configured to have straight edges (see dashed lines). Therefore, unlike... Figure 3A In some embodiments, the edges of the n+ mask layer 340 do not contain staggering that matches the offset of the “B” BL node 222. Due to the straight edges, the n+ implant distribution 342 (see shaded area) in each of the BL nodes 222 is not the same, and the distance from the BL contact 227 to the edge of the n+ mask layer 340 will be different. However, because the BL node 222 contains highly doped n+ implant regions 342, any difference in resistance between the BL contact 227 and the edge of the n+ mask layer 340 between the BL contact 227 and the protection circuit 210 is negligible. That is, when configuring the protection circuit, only the resistance of the non-n+ doped region of the active region 228 can be considered. Therefore, in some embodiments, the protection circuit 210 may be configured such that the data gate 215 is not staggered, and the distance D6 between the data gate 215 and the edge of the n+ mask layer 340 is set to be the same for each of the protection circuits 210. The exposed portions of the BL contact 227 and active region 228 and / or the lengths to the data gate 215 are not set to be equal, but this is not a problem because the n+ implanted regions have negligible differences in resistance. Of course, the resistance of the active region 228 can be made equal by changing the geometry (e.g., width, length, and / or shape) and / or composition (e.g., n / p doping) of each active region 228 to achieve equal resistance, to the extent that the resistance of the active region 228 will benefit from further equalization between the protection circuits 210.

[0046] As discussed above, in some embodiments, the edges of the n+ implanted layer 340 are not staggered to match the staggered arrangement of the BL contacts 227. However, in such embodiments, the effective distance between adjacent BL contacts 227 may no longer be a limiting dimension relative to the spacing of the protection circuitry 210. Instead, in some embodiments, the distance X1 between the BL nodes 222 in the fingers 345 may be configured to be at or greater than the minimum effective distance to ensure bit-to-bit line isolation and / or breakdown voltage falls within predetermined design values ​​for the memory device. Therefore, to ensure that the distance X1 is at or greater than the minimum effective distance, the polysilicon of the common gate 235 may extend into the active region 228 offset from the BL nodes 222. For example, as Figure 3B As seen, the polysilicon tab 360 extends into the active region 228 of the “B” or non-offset protection circuit 210 to ensure that the distance X1 is at or greater than the minimum effective distance.

[0047] Figure 3CAnother embodiment of this disclosure is described. Relative to an n+ mask layer having a straight edge 340, Figure 3C The embodiments in the example are similar to Figure 3B The embodiments are as follows. However, instead of a single polysilicon gate (e.g., a common gate 235), the circuit protection subsystem 150″ includes a common gate 235a″ for the protection circuit 210 in line 212 and a common gate 235b″ for the protection circuit 210 in line 214. The common gates 235a″ and 235b″ may be disposed on either side of a continuous source region 335 disposed between the protection circuit 210 of line 212 and the protection circuit 210 of line 214. In some embodiments, the continuous source region 335 may be doped with an n+ implanted layer. In some... In some embodiments, the protection circuit 210 on one side of the continuous source region 335 is offset compared to the protection circuit 210 on the other side of the continuous source region 335. In some embodiments, the offset of the protection circuit is such that the non-offset BL node 222 of the shared gate 235a″ is aligned with the offset BL node 222 of the shared gate 235b″, and vice versa. That is, the protection circuit 210 in the circuit protection subsystem 150″ is not mirrored along the centerline extending through the SRC node 237, as in the circuit protection subsystem 150 discussed above. In some embodiments, each of the shared gates 235a″ and 235b″ may include one or more SRC nodes 237″, wherein each SRC node 237″ has a contact 239″. In some embodiments, one or more SRC nodes 237″ having corresponding SRC contacts 239″ may be disposed in the continuous source region 335 between the opposite offset / non-offset pairs of BL nodes 222″. For example, as Figure 3C As seen, SRC node 237″ can be positioned between the non-offset BL node 222″ and the offset BL node 222″ on the opposed shared gate. In some embodiments, the continuous source region 335 and / or SRC node 237″ contains n+ implants. By using an offset configuration for the opposed protection circuit 210, SRC node 237 with corresponding SRC contact 239 can be positioned between each pair of opposed protection circuits 210. Therefore, although circuit protection subsystem 150″ may be larger than circuit protection subsystems 150 and 150′, a greater number of source contacts in circuit protection subsystem 150″ provides greater reliability. Figure 3CThe illustration shows a configuration in which a continuous source region 335 is added to the circuit protection subsystem 150″, which is similar to the configuration of the circuit protection subsystem 150′. However, those skilled in the art will understand that a continuous source region 335 can also be added to the circuit protection device, and the configuration of the circuit protection device is similar to that of the circuit protection subsystem 150. Furthermore, those skilled in the art will understand that other features of the circuit protection devices 150 and / or 150′ discussed above (such as those included in the circuit protection subsystem 150″) will therefore not be repeated where appropriate for the sake of brevity.

[0048] In the embodiments discussed above, the openings in the polysilicon layer for the BL and SRC contacts are shown to have a shape with right angles (e.g., a rectangle or a portion thereof). However, the openings can have other types of shapes, such as polygonal, circular, elliptical, or portions thereof. For example, as... Figure 3D As seen in some embodiments, the openings in the polysilicon for the BL contact 227 and / or SRC contact 239 may include a surface 370. The surface 370 may be positioned to interact with, for example... Figure 2A and 2B Compared to the right-angled opening shown, this increases the effective distance between adjacent BL contacts 227 (not shown) and / or the effective distance D2 between BL contacts 227 and SRC contacts 239.

[0049] In some 3D memory devices, a memory subsystem containing control logic (e.g., control logic 116) and / or page buffers (e.g., cache register 118) can be positioned below the memory array (e.g., memory array 104). This arrangement, known as under-array CMOS (CUA), allows the memory subsystem to be smaller than a system where the control logic and page buffers are located adjacent to the memory array. However, even when configured as a CUA, limitations may exist regarding how much smaller the memory device can be, due to how some cache memory latches are fabricated. In some cache memory latches, the NMOS and PMOS components (e.g., p-channel low voltage PLV and n-channel low voltage NLV) constituting the CMOS inverter of the latch are formed in separate wells. Although the wells can be closely spaced, the spacing requirements of the components will mean that the area of ​​the CMOS inverter is larger than if the components were formed in the same well. Separate far-end wells also mean that the metal routing between the components can become crowded and complicate the ability to shrink the CUA.

[0050] To reduce latch spacing and thus page buffer size, exemplary embodiments of this disclosure include integrated CMOS inverters that can be incorporated into NAND latches to create memory cells (e.g., SRAM cells). The integrated CMOS inverter may include PMOS and NMOS transistors sharing a common active region. Because the NMOS and / or PMOS transistors are floating bodies, n-well implants are not required. Therefore, the integrated CMOS inverter uses less space compared to conventional CMOS inverters. In some embodiments, the PMOS and / or NMOS transistors may be formed as vertical transistors. In some embodiments, the integrated CMOS inverter may include a common gate, which eliminates the need for separate gates connecting each component. When one or two transistors are vertical, the integrated CMOS inverter of this disclosure allows adjacent CMOS inverters to be extremely close without regard to the polysilicon-polysilicon spacing of the gate caps. Therefore, the need for gaps between gate caps (half-bytes) that may exist in conventional page buffer latch layouts is eliminated.

[0051] Figure 4A This illustration shows a cross-sectional view of an integrated inverter 400 comprising a planar NMOS transistor 410 and a vertical PMOS transistor 440 having a common output contact 430. The integrated inverter 400 may be disposed on a silicon substrate 402. The active region of the integrated inverter 400 is shared by both the NMOS and PMOS transistors and may be defined by shallow trench isolation 460 on each side of the integrated inverter 400. Figure 4AAs seen, the NMOS transistor 410 includes an NMOS source 412 and an NMOS drain 422, which may be n+ diffusion layers disposed in the silicon substrate 402. One or more metal layers (e.g., tungsten layers) may be disposed on the NMOS source 412 to form an NMOS source contact 414. One or more metal layers (e.g., tungsten layers) may be disposed on the NMOS drain 422, and the metal layers may also be connected to the PMOS drain 444 to form a common output contact 430. A channel 413 may be disposed between the NMOS source 412 and the NMOS drain 422. A portion of the channel 413 may be doped with a conductivity different from (e.g., higher) than that of the p-type substrate 402, such that the doped portion has a desired threshold voltage (Vt). The NMOS source 412 may be connected to ground potential GND via the NMOS source contact 414. The NMOS transistor 410 may also include a silicon oxide layer 416 disposed above the source 412 and the drain 422. Between the source 412 and drain 422, a silicon oxide layer 416 serves as the gate oxide for the planar NMOS transistor. The silicon oxide layer 416 may be deposited on a silicon substrate 402 to surround the metal layer 414. Furthermore, one or more silicon oxide layers may be disposed on the silicon oxide layer 416 to isolate the metal layer 414 from surrounding components. A gate 418, consisting of one or more layers of polysilicon and / or WSix (tungsten silicide), may be disposed on top of the silicon oxide layer 416. In some embodiments, the gate 418 may have a gate-all-around (GAA) design shared by both the planar NMOS transistor 410 and the vertical PMOS transistor 440. One or more metal layers (e.g., tungsten layers) may be disposed on the common gate 418 to serve as input contacts 420 (Vin) to the inverter 400.

[0052] The vertical PMOS transistor 440 includes a PMOS source 448 disposed on a channel 450, which may be a p+ implantation layer. The channel 450 may consist of one or more polysilicon layers, which may be n-type polysilicon. The channel 450 may be disposed on a PMOS drain 444, which may be a p+ diffusion layer. The PMOS drain 444 may be formed on an n-type diffusion layer 404 that may be formed on a substrate 402. The PMOS drain 444 may be connected to a common output contact 430 that may be made of one or more metal layers (e.g., tungsten layers). Thus, the common output contact 430 is connected to both the NMOS drain 422 and the PMOS drain 444. A silicon oxide layer 416 may be deposited on the silicon substrate 402 to surround the metal of the common output contact 430. In addition, one or more silicon oxide layers 424 may be disposed on the silicon oxide layer 416 to surround the common output 430 and isolate the common output 430 from the common gate 418. In some embodiments, the composition of silicon oxide layer 424 and silicon oxide layer 416 may be the same. One or more metal layers (e.g., tungsten layers) may be disposed on PMOS source 448 to serve as PMOS source contact 452. PMOS source 448 may be connected to a Vcc potential (e.g., 3.5 volts) via PMOS source contact 452. Silicon oxide layer 416 may be disposed on silicon substrate 402 to surround channel 450. One or more lateral gate oxide layers 446 may be disposed on silicon oxide layer 416 to surround channel 450 (see also...). Figure 4B In some embodiments, the composition of the lateral gate oxide layer 446 and the silicon oxide layer 416 may be the same.

[0053] Figure 4B This is a top view of inverter 400. (Example:) Figure 4B As seen, the GAA-type gate 418 covers almost all of the inverter 400. The inverter 400 may be configured with one or more NMOS source contacts 414, which may be isolated from the gate 418 by one or more silicon oxide layers 416. Figure 4B In the embodiment, there are two contacts 414, but any number of contacts can be used based on design resistivity, connection reliability, and connection complexity. For example, if only one contact is used and it is defective, the inverter 400 and therefore the memory cell will be unusable. However, forming a large number of contacts may be uneconomical or technically infeasible. Similarly, although shown as having two contacts each, one or more contacts can be formed for the input contact 420 and / or the common output contact 430. The input contact 420 is connected to the gate 418, while the common output contact 430 is isolated from the gate 418 by one or more silicon oxide layers 424. Figure 4B As shown, a single PMOS source contact 452 is formed on the vertical PMOS transistor 440. However, in some embodiments, more than one PMOS source contact may be formed. Figure 4A and 4B In this diagram, the PMOS source 448 is shown as having a rectangular pillar (e.g., a square pillar) shape. The concealed channel 450 may also have a rectangular pillar (e.g., a square pillar) shape. However, the PMOS source 448 and / or channel 450 may have other shapes, such as a cylindrical pillar shape. One or more gate oxide layers 446 may surround the channel 450 to isolate the channel 450 from the common gate 418 (see also...). Figure 4A The gate oxide layer 446 may have a geometry corresponding to the geometry of the channel 450. For example, if the channel 450 is a rectangular pillar, the gate oxide layer 446 may be a rectangular tube; if the channel 450 is a cylindrical pillar, the gate oxide layer 446 may be a cylindrical tube, and so on.

[0054] In operation, when input contact 420 (Vin) has a high signal (e.g., a high potential), the GAA-type common gate 418 is also at a high potential. With gate 418 high, the planar NMOS transistor 410 is turned on and the vertical PMOS transistor 440 is turned off. With NMOS transistor 410 turned on, the NMOS source 412 (which is at ground potential GND via NMOS source contact 414) is connected to the common output contact 430 (Vout) via channel 413 and NMOS drain 422. Therefore, when input contact 420 (Vin) has a high signal, the common output contact 430 (Vout) has a low signal. When input contact 420 (Vin) has a low signal (e.g., a low potential), gate 418 is also at a low potential. With gate 418 low, the planar NMOS transistor 410 is turned off and the vertical PMOS transistor 440 is turned on. When PMOS transistor 410 is turned on, the PMOS source 448 at the Vcc potential via PMOS source contact 452 is connected to the common output contact 430 (Vout) via channel 450 and PMOS drain 444. Therefore, when input contact 420 (Vin) has a low signal, the common output contact 430 (Vout) has a high signal. Thus, the planar NMOS-vertical PMOS inverter 400 will behave similarly to a conventional planar NMOS-planar PMOS inverter, but will occupy less space because, unlike a fully planar CMOS inverter, it does not require a separate well. Although planar NMOS and vertical PMOS have been described above, those skilled in the art will understand that planar PMOS and vertical NMOS will have similar configurations, but with the p-type and n-type implants reversed. Therefore, for simplicity, a discussion of inverters with planar PMOS and vertical NMOS is omitted.

[0055] Figure 5AThis illustration shows a cross-sectional view of an integrated inverter 500 comprising a vertical PMOS transistor 510 and a vertical NMOS transistor 540. The integrated inverter 500 may be disposed on a silicon substrate 502. The active region of the integrated inverter 500 is shared for both the PMOS and MMOS transistors and may be defined by shallow trench isolation 560 on each side of the integrated inverter 500. The vertical PMOS transistor 510 and the vertical NMOS transistor 540 include a common output contact 530 and a common gate 518. The vertical PMOS transistor 510 includes a PMOS source 512 disposed on a channel 555, which may be a p+ implanted layer. The channel 555 may consist of one or more polysilicon layers, which may be n-type polysilicon. The channel 555 may be disposed on a PMOS drain 522, which may be a p+ diffusion layer disposed in the silicon substrate 502, which may be an n-type well. A silicon oxide layer 516 may be disposed on a silicon substrate 502 to surround a channel 555. A PMOS drain 522 and an NMOS drain 544 may be connected to a common output contact 530, which may be made of one or more metal layers (e.g., tungsten layers). Therefore, the common output contact 530 is connected to both the PMOS drain 522 and the NMOS drain 544. The silicon oxide layer 516 may be deposited on the silicon substrate 502 to surround the metal of the common output contact 530. Additionally, one or more silicon oxide layers 524 may be disposed on the silicon oxide layer 516 to surround the common output 530 and isolate the common output 530 from the common gate 518. In some embodiments, the composition of the silicon oxide layers 516 and 524 may be identical. One or more metal layers (e.g., tungsten layers) may be disposed on the PMOS source 512 to serve as a PMOS source contact 514. The PMOS source 512 can be connected to a Vcc potential (e.g., 3.5 volts) via a PMOS source contact 514. One or more lateral gate oxide layers 513 can be disposed on the silicon oxide layer 516 to surround the channel 555. The common gate 518 can consist of one or more layers of polysilicon and / or WSix (tungsten silicide). The common gate 518 can be disposed on top of the silicon oxide layer 516. The common gate 518 can be a gate-all-around design. One or more metal layers (e.g., tungsten layers) can be disposed on the GAA-type gate 518 to serve as input contacts 520 (Vin) to the inverter 500.

[0056] The vertical NMOS transistor 540 of the integrated inverter 500 includes an NMOS source 548 disposed on a channel 550, the NMOS source being an n+ implanted layer. The channel 550 may consist of one or more polysilicon layers, the polysilicon being p-type polysilicon. The channel 550 may be disposed on an NMOS drain 544, the NMOS drain being an n+ diffusion layer disposed in a p-type diffusion layer 504. The p-type diffusion layer 504 may be disposed in a silicon substrate 502. The NMOS drain 544 may be connected to a common output contact 530. One or more metal layers (e.g., tungsten layers) may be disposed on the NMOS source 548 to act as NMOS source contacts 552. The NMOS source 548 may be connected to ground potential (GND) via the NMOS source contacts 552. A silicon oxide layer 516 may be disposed on the silicon substrate 502 to surround the channel 550. One or more lateral gate oxide layers 546 may be disposed on silicon oxide layer 516 to surround channel 550.

[0057] Figure 5B This is a top view of inverter 500. (Example:) Figure 5B As seen, the GAA-type gate 518 covers almost all of the inverter 500. The inverter 500 may be configured with a single PMOS source contact 514 formed on the vertical PMOS transistor 510. However, in some embodiments, more than one PMOS source contact may be formed. That is, although... Figure 5B A single contact is shown, but any number of contacts can be used based on design resistivity, connection reliability, and connection complexity. Similarly, although two contacts are shown for each, one or more contacts can be formed for the input contact 520 and / or the common output contact 530. The input contact 520 is connected to the gate 518, while the common output contact 530 is isolated from the gate 518 by one or more silicon oxide layers 524. Figure 5B As shown, a single NMOS source contact 552 is formed on a vertical NMOS transistor 540. However, similar to PMOS source contacts, in some embodiments, more than one NMOS source contact may be formed. Figure 5A and 5BIn this configuration, the PMOS source 512 and NMOS source 548 are shown to have a rectangular pillar (e.g., square pillar) shape. One or both of the corresponding channels 555 and 550 hidden beneath the sources 512 and 548 may also have a rectangular pillar (e.g., square pillar) shape. However, one or both of the PMOS source 512 and NMOS source 548 and / or one or both of the channels 555 and 550 may have other shapes, such as cylindrical pillar shapes. One or more gate oxide layers 513 and 546 may surround the corresponding channels 555 and 550. Of course, the gate oxide layers 513 and 546 may have geometries corresponding to the corresponding channels 555 and 550. For example, if one or both of the channels 555 and 550 have a rectangular pillar configuration, then the corresponding gate oxide layers 513 and 546 can be rectangular tubes; if one or both of the channels 555 and 550 have a cylindrical pillar configuration, then the corresponding gate oxide layers 513 and 546 can be cylindrical tubes, and so on.

[0058] In operation, when input contact 520 (Vin) has a high signal (e.g., a high potential), the GAA-type common gate 518 also has a high potential. When the common gate 518 is high, NMOS transistor 540 is turned on and PMOS transistor 510 is turned off. When NMOS transistor 540 is turned on, the NMOS source 458 (which is at ground potential GND via PMOS source contact 552) is connected to the common output contact 530 (Vout) via channel 550 and PMOS drain 544. Therefore, when input contact 520 (Vin) has a high signal, the common output contact 530 (Vout) has a low signal. When input contact 520 (Vin) has a low signal (e.g., a low potential), gate 518 also has a low potential. When the common gate 518 is low, NMOS transistor 540 is turned off and PMOS transistor 510 is turned on. When PMOS transistor 510 is turned on, the PMOS source 512 at the Vcc potential via PMOS source contact 514 is connected to the common output contact 530 (Vout) via channel 555 and PMOS drain 522. Therefore, when input contact 520 (Vin) has a low signal, common output contact 530 (Vout) has a high signal. The vertical NMOS-vertical PMOS inverter 500, as disclosed above, will behave similarly to a conventional planar NMOS-planar PMOS inverter, but will occupy less space because it does not require a separate well. While vertical-vertical inverters (e.g., inverter 500) can be more compact than planar-vertical inverters (e.g., inverter 400), inverter 400 can be more economical in some cases. Because one of the inverters is planar, portions of conventional manufacturing processes can be used when manufacturing a planar-vertical inverter.

[0059] Figure 6AThe memory cell 600 (e.g., an SRAM cell) has two integrated inverters 610a and b, which may be identical, for example, to an inverter 500 having PMOS and NMOS transistors, as discussed above. Figure 6A As seen, integrated inverters 610a and 610b are oriented such that the input contact 620a of inverter 610a is aligned (e.g., linearly aligned) with the output contact 630b of inverter 610b, and the input contact 620b of inverter 610b is aligned (e.g., linearly aligned) with the output contact 630a of inverter 610a. In some embodiments, conductive contact strips 640a and 640b (e.g., metal layers) may be disposed such that input contacts 620a and 620b are connected to output contacts 630b and 630a, respectively. By using an integrated inverter configuration, the routing of contact strips between the inverter connections is direct (e.g., linear) and less congested, allowing for a more compact cache configuration.

[0060] Figure 6B This describes a memory cell 600', such as an SRAM cell, with two integrated inverters 610a' and 610b'. Integrated inverter 610a' may be the same as integrated inverter 500 discussed above. Inverter 610b' may be similar to inverter 500, except that the orientation of input contacts 620b' and output contacts 630b' is reversed compared to the input contacts 620a' and output contacts 630a' of integrated inverter 610a'. By reversing the input and output contacts, one of the integrated inverters does not need to be rotated 180 degrees (as in...). Figure 6A In the case of [the situation], input contacts 620a' and 620b' can be aligned with the opposite output contacts 630b' and 630a' (e.g., linear alignment) for easy bundling. In memory cell 600', PMOS transistors are aligned between two inverters (e.g., linear alignment), and NMOS transistors are aligned between two inverters (e.g., linear alignment). Therefore, because similar transistors are aligned, the manufacture of memory cell 600' is less complex and easier than in the case of similar transistors not aligned, while still retaining the advantages of simplification and less congested routing.

[0061] Figure 6C and 6D Describe alternative layouts and interconnect arrangements for memory cells (e.g., SRAM cells) with integrated inverters. Figure 6C In some embodiments, memory cell 650 includes integrated inverters 660a and 660b. Integrated inverter 660a may be similar to integrated inverter 500, but a silicon layer 665a around the output contact 663a extends to the edge of the active region of integrated inverter 660a. In some embodiments, integrated inverter 660b may also be identical to integrated inverter 660a. However, in… Figure 6C In the embodiment, the arrangement of the integrated inverter 660b with respect to the PMOS and NMOS inverters is similar to that of the integrated inverter 500', but in the integrated inverter 660b, the silicon layer 665b surrounding the output contact 663b extends to the edge of the active region of the integrated inverter 660b. Figure 6C As seen, polysilicon interconnects, rather than metal interconnects, can be used to complete the connection between integrated inverters. For example, a polysilicon interconnect strip 664a can extend from the polysilicon gate layer 668a corresponding to the input contact 662a to the extended silicon layer 665b corresponding to the output contact 663b. Similarly, a polysilicon interconnect strip 664b can extend from the polysilicon gate layer 668b corresponding to the input contact 662b to the extended silicon layer 665a corresponding to the output contact 663a. For example, polysilicon interconnect strips 664a and 664b can be stitched to the corresponding output contacts 663b and 663a. That is, the polysilicon interconnect strip is formed on the corresponding extended silicon layer, and the corresponding output contact (e.g., an extended output contact) is formed to partially overlap with the polysilicon interconnect strip. For example, the overlapping portion 667a represents the overlap from contact 663a to polysilicon connecting strip 664b, and the overlapping portion 667b represents the overlap from contact 663b to polysilicon connecting strip 664a.

[0062] Figure 6D An embodiment of a memory cell (e.g., an SRAM cell) is described. Memory cell 680 includes integrated inverters 690a and 690b. The arrangement of the PMOS and NMOS transistors is similar to that of the integrated inverter 500. However, the inputs and outputs for the integrated inverters are formed on the same side of the PMOS and NMOS transistors, rather than between the transistors. For example, as... Figure 6D As seen, the polysilicon gate segment 692a corresponding to the input contact and the silicon oxide segment 693a corresponding to the output contact are formed on the same side of the PMOS and NMOS transistors of the integrated inverter 690a. Similarly, the polysilicon gate segment 692b corresponding to the input contact and the silicon oxide segment 693b corresponding to the output contact are formed on the same side of the PMOS and NMOS transistors of the integrated inverter 690b. Figure 6D In one embodiment, the arrangement of the PMOS and NMOS transistors is identical for both integrated transistors 690a and 690b, thus one of the inverters is rotated 180 degrees. However, in other embodiments, the arrangement of the PMOS and NMOS transistors can be reversed in integrated transistor 690b, making transistors of the same type similar to... Figure 6BThe embodiments are linearly aligned. In some embodiments, the input polysilicon gate segments 692a and 692b may be stitched to the corresponding output silicon oxide segments 693b and 693a using corresponding contact strips 695a and 695b (e.g., extended output contacts). The contact strips may be, for example, polysilicon, metal, and / or another suitable material. Although Figures 6A to 6D The diagram shows integrated inverters with vertical PMOS and vertical NMOS configurations; however, those skilled in the art will recognize that integrated inverters 400 can be similarly arranged to form compact memory cells. Therefore, for the sake of brevity, a discussion of the connections in the planar / vertical memory cells is omitted.

[0063] See above. Figure 6D As discussed, the input and output connections can be located on the same side of the integrated inverter, allowing for convenient and compact connection of corresponding inverters using, for example, extended contacts. However, instead of extended contacts, in some embodiments, a modified pillar channel can be used to directly connect the input polysilicon gate layer of one integrated inverter to the output silicon layer of another integrated inverter. For example, Figure 7A and 7B The explanation can be used as a substitute Figure 6D Two embodiments of the extended contact configuration of the support channel contact. Figure 7A In one embodiment, the input pillar connection of integrated inverter 710 is deposited on the output silicon oxide connection 742 of another integrated inverter 740. To form the pillar channel connection 720, the opening in the protective mask for forming the pillar channel 720 is larger than the diameter of the pillar channel 720, such that when the polysilicon for the pillar channel 720 is deposited, the channel polysilicon overlaps with the WSix layer 722 and / or the polysilicon layer 724 corresponding to the input connection. In some embodiments, only one of the WSix layer 722 or the polysilicon layer 724 may be formed on top of the silicon oxide layer 726. Once the pillar channel 720 is formed, an electrical connection with a current path 730 is formed between the input WSix / polysilicon layers 722 / 724 of inverter 710 and the output silicon 742 of inverter 740. Figure 7A In one embodiment, a layer of sidewall silicon oxide 728 is formed such that the current path 730 is the full length of the pillar channel 720. Figure 8B In some embodiments, the pillar channel 752 of the integrated inverter 750 is formed without sidewall silicon oxide, such that the input WSix / polysilicon layers 722 / 724 of the inverter 750 are in direct electrical contact with the polysilicon of the pillar channel 752, and a short current path 732 is formed between the inverter 750 and the output silicon 742 of the inverter 740. In some embodiments, the diameter of the pillar channels 720 and / or 752 is made as small as possible to keep the capacitance as small as possible while maintaining a reliable electrical connection.

[0064] Figures 8A to 8C This paper describes a simplified advanced manufacturing process for an integrated inverter with planar NMOS and vertical PMOS transistors. Those skilled in the art will understand the details of the CMOS inverter manufacturing process, and therefore, for brevity, details related to photoresist layers, masks, chemical and / or plasma etching, and other known details are omitted. A shallow n-type implantation layer 804 is deposited onto a p-type substrate 802 prior to the deposition of a silicon oxide layer 808. The deposition of the n-type implantation layer 804 provides isolation for the vertical PMOS transistor. A p+ implantation layer 806 may subsequently be added on top of the n-type implantation layer 804 to act as the drain for the vertical PMOS transistor. The arrangement of the n-type implantation layer 804 and the p+ implantation layer 806 results in a larger n-type implantation layer region that extends beyond the region of the p+ implantation layer 806. For example, in some embodiments, the n-type implantation layer 804 is angled and / or a resist trimming etching is performed after the p+ implantation layer 806, such that the n-type implantation region extends further than the p+ implantation layer region. In the case of a vertical NMOS transistor, the n+ implantation layer, which acts only as the drain, can be deposited on a p-type substrate. For a vertical CMOS inverter, the steps for vertical PMOS transistors and vertical NMOS transistors discussed above can be performed. After depositing the p+ implantation layer 806, one or more silicon oxide layers 808, one or more polysilicon gate layers 810, and / or one or more WSix (e.g., tungsten silicide) gate layers 812 can be deposited. Layers are added in appropriate order and at least the gate layers 810 / 812 are etched to produce an intermediate assembly, wherein the silicon oxide layer 808 deposited on the active region is covered by the polysilicon gate layer 810, and the WSix gate layer 812 and the silicon oxide layer 808 in the STI region 830 are covered by the WSix gate layer 812.

[0065] like Figure 8B As seen, a protective layer 814 with openings for a channel 818 for a vertical PMOS transistor is deposited on the WSix gate layer 814. The thickness of the protective layer 814 may be based on the desired amount of polysilicon for the vertical channel that should extend above the WSix gate layer 812. After depositing the protective layer 814, etching is performed on the WSix and polysilicon gate layers 812 / 814 to create holes for the channel 818 for the vertical PMOS transistor. One or more silicon oxide layers are deposited, and gate sidewall etching is performed to create holes and expose the bottom to the p+ implant layer 806. One or more polysilicon layers are deposited to create the channel 818 by forming a lateral gate 816. The intermediate assembly then undergoes chemical mechanical polishing (CMP) on top of the protective layer 814. The protective layer 814 is then etched away. Figure 8B (Not shown in the image).

[0066] After etching away the protective layer 814, as Figure 8CAs seen, a gate etching is performed to define a common gate configuration including an opening for the output contact region (Vout). n+ implantation layers 822 and 824, corresponding to the source and drain, respectively, can be deposited after the gate etching process. Additionally, a p+ implantation layer 820, corresponding to the source of a vertical PMOS transistor, can be deposited on the channel 818. After silicon oxide accumulation and subsequent etching of the openings for the ground (GND) and Vout contacts, one or more metal (e.g., tungsten) layers can be deposited to form the source (Vcc), ground (GND), Vin, and Vout contacts.

[0067] In some embodiments where the integrated CMOS inverter comprises planar NMOS and vertical PMOS, the vertical PMOS is fabricated by etching a silicon substrate into a groove to create a PMOS channel (e.g., a silicon mesa) rather than by forming the channel through silicon deposition as discussed above. Figure 9A As seen, the n-type silicon layer 908 is formed on the p-type silicon substrate 902. For example... Figure 9B As seen, a hard mask 912 is deposited on the region corresponding to the n-type channel for the PMOS transistor, and then the n-type silicon layer 908 is etched until the p-type substrate 902 is reached. Due to the hard mask 912, a mesa 910 corresponding to the n-type channel for the PMOS transistor is formed. After the etching process, an n-type trench is formed beneath the p-type implant layer. That is, one or more n-type dopant layers are deposited into the p-type substrate beneath the mesa 910 to produce an n-type implant 904. The n-type dopant layers of the n-type implant 904 may be angled such that the n-type implant 904 covers the p-type implant 906 already deposited beneath the mesa 910.

[0068] like Figure 9C As seen, after the etching process, a photoresist layer 922 is added, with openings in the photoresist layer 922 corresponding to the drain of the PMOS transistor. The fabrication process then includes adding a p+ implantation layer 914 to the p-type implant 906 (see [link to documentation]). Figure 9B ).like Figure 9D As seen, the formation process includes depositing one or more silicon oxide layers 916, followed by depositing one or more polysilicon layers 918 and one or more additional silicon oxide layers 920. Additionally, each STI is masked and etched. The silicon oxide layer 920 may contain a sacrificial oxide with stripes to repair any etch-induced damage. Figure 9E As seen, the silicon oxide 921 at the STI is recessed below the top of the polysilicon layer 918. One or more WSix layers 924 may be deposited on top of the polysilicon layer 918. In some embodiments, an additional thin layer of polysilicon may be deposited before the WSix layer 924 based on the topology of the active region-STI interface.

[0069] After depositing WSix layer 924, as Figure 9F As seen, etching is performed to expose the hard mask 912 on the mesa 910, and to expose the drain region 930 and source region 928 of the NMOS transistor on top of the silicon substrate 902. Further wet etching can be performed to remove the hard mask 912 from the top of the mesa 910. Additionally, using a suitable mask, p+ implant deposition can be performed to create the source 926 of the PMOS transistor, and n+ implant deposition can be performed to create the source 928 and drain 930 of the NMOS transistor. Figure 9G After the back-end oxide filling and CMP as seen, source contacts (e.g., ground GND) for the NNMOS source 928, input contacts (e.g., Vin) for the common gate 924, output contacts (e.g., Vout) bridging the n+ / p+ interface between the NMOS drain 930 and the PMOS drain 914, and source contacts (e.g., Vcc) for the PMOS source 926 can be deposited.

[0070] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement calculated to achieve a similar (e.g., identical) purpose may replace the specific embodiments shown. For example, in other embodiments, an enhancement-mode field-effect transistor may replace the depletion-mode field-effect transistor described above. For example, a metal-gate enhancement-mode field-effect transistor may replace a metal-gate depletion-mode field-effect transistor, and a lateral-gate enhancement-mode field-effect transistor may replace a lateral-gate depletion-mode field-effect transistor. Therefore, this application is intended to cover any adaptations or variations of the embodiments.

[0071] The above detailed description of embodiments of the technology is not intended to be exhaustive or to limit the technology to the precise forms disclosed above. As those skilled in the art will recognize, although specific embodiments and examples of the technology have been described above for illustrative purposes, various equivalent modifications can be made within the scope of the skill of those skilled in the art. For example, although the steps are presented in a given order, alternative embodiments may perform the steps in a different order. The various embodiments described herein may also be combined to provide other embodiments.

[0072] Based on the foregoing, it should be understood that specific embodiments of the technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of embodiments of the technology. Where the context permits, singular or plural terms may also include plural or singular terms respectively. Furthermore, unless the word “or” is explicitly limited to referring only to a single item exclusive to another item in a list referring to two or more items, its use in this list should be understood to include: (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. For example, as used herein (included in the claims), “or” as used in a list of items (e.g., a list of items beginning with phrases such as “at least one of…” or “one or more of…”) indicates an inclusive list, such that a list of at least one of A, B, or C refers to A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase “based on” should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on". Furthermore, the terms "comprising," "including," "having," and "with" are used throughout to mean at least one or more of the described features, such that no larger number of identical features and / or other features of additional types are excluded.

[0073] A processing device (e.g., processor 130 and / or another controller) represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, a processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor that implements other instruction sets, or a combination of instruction sets. A processing device (e.g., processor 130 and / or another controller) may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc.

[0074] A machine-readable storage medium (also known as a computer-readable medium) stores software that contains one or more instruction sets or embodies any one or more of the methods or functions described herein. A machine-readable storage medium may be, for example, memory system 100 or another memory device. The term "machine-readable storage medium" should be understood to include a single medium or multiple media storing one or more instruction sets. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding a set of instructions executable by a machine and causing a machine to perform any one or more of the methods disclosed herein. The term "machine-readable storage medium" should therefore be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0075] It should also be understood that various modifications can be made without departing from this disclosure. For example, those skilled in the art will understand that the various components of this technology can be further divided into sub-components, or that the various components and functions of this technology can be combined and integrated. Furthermore, certain aspects of this technology described in the context of particular embodiments may be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments are required to exhibit such advantages to fall within the scope of this technology. Therefore, this disclosure and associated technologies may cover other embodiments not explicitly shown or described.

Claims

1. An apparatus comprising: Memory cell array; Multiple bit lines, each bit line being connected to a corresponding set of memory cells in the memory cell array; and A memory subsystem having a set of first memory circuits and a set of second memory circuits, each first memory circuit being laterally adjacent to a second memory circuit, each first memory circuit including a first bit line contact and each second memory circuit including a second bit line contact, the first bit line contact and the second bit line contact being adapted to connect to a corresponding bit line among the plurality of bit lines. Each of the first bit line contacts is disposed along a first connection line of the memory subsystem, and each of the second bit line contacts is disposed along a second connection line of the memory subsystem, wherein the first connection line and the second connection line are in a first direction perpendicular to a second direction in which the bit line extends. The second connecting line is offset from the first connecting line by a predetermined distance greater than zero in the second direction. When the second connecting line is offset from the first connecting line by the predetermined distance, the spacing between the first first lines is defined by the distance between the first first line and the adjacent second second line. Where it is assumed that the first connecting line and the second connecting line are the same line, the spacing between the second bit lines is defined by the distance between the first bit line and the adjacent second bit line; and Wherein, for the same effective distance between adjacent first bit line contacts and second bit line contacts, the first bit line spacing is less than the second bit line spacing.

2. The device of claim 1, wherein the memory subsystem is a voltage isolation device, and the first and second memory circuits isolate the high voltage on the first and second bit lines from the low voltage circuit connected to the memory subsystem.

3. The device of claim 2, wherein each first memory circuit includes a first low-voltage connection configured to be connected to the low-voltage circuit, a first bit line contact, and a first data gate configured to selectively connect the first bit line contact to the first low-voltage connection, and each second memory circuit includes a second low-voltage connection configured to be connected to the low-voltage circuit, a second bit line contact, and a second data gate configured to selectively connect the second bit line contact to the second low-voltage connection.

4. The device of claim 1, wherein the memory subsystem is configured such that the first and second memory circuits are mirrored along the centerline of the memory subsystem to form an opposing first memory circuit pair and an opposing second memory circuit pair across the centerline.

5. The device of claim 4, wherein the memory subsystem is configured to have a common gate along the center line to connect the first bit line contact and the second bit line contact. The common gate includes at least one opening for the source contact, and The at least one opening for the source contact is disposed between the opposing first memory circuit pairs.

6. The device of claim 5, wherein the common gate includes a well implantation layer disposed perpendicular to at least one of a line corresponding to an effective distance between adjacent first bit line contacts and second bit line contacts or a line corresponding to a second effective distance between the source contact and the second bit line contact.

7. The device of claim 6, wherein the at least one of the source contacts and the adjacent opening for the second bit line contact comprise a surface along the line corresponding to the second effective distance.

8. The device of claim 1, wherein the memory subsystem is configured to have at least two shared gates along the centerline of the memory subsystem, the at least two gates being separated by consecutive source implantation regions, each shared gate being configured to connect a corresponding first bit line contact and a second bit line contact, and The continuous source implantation region includes at least one source contact.

9. The device of claim 8, wherein the at least two gates comprise a first gate and a second gate, and The memory subsystem is configured such that the first and second memory circuits on one side of the first gate are offset from the first and second memory circuits on one side of the second gate, and The circuit offset aligns the first memory circuit on the first gate side with the second memory circuit on the second gate side, and the second memory circuit on the first gate side with the first memory circuit on the second gate side. The source contact of the at least one source contact is disposed in the continuous source implantation region between each pair of opposing first and second memory circuits.

10. The device of claim 1, wherein the first bit spacing is less than the minimum effective distance of the memory subsystem.

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