Semiconductor memory devices

Abstract

This invention provides a semiconductor memory device, including a memory cell array, a switching circuit, and a sensing circuit. The memory cell array includes a plurality of memory cells. The switching circuit includes at least one switch. Each switch receives a control signal and is controlled to be turned on or off by the control signal. During erase verification, the sensing circuit sequentially receives the erase verification current generated by each memory cell via the switching circuit to verify the erase state of each memory cell.

Description

Technical Field

[0001] This invention relates to a memory device, and more particularly to a semiconductor memory device for an option bit or status bit required for powering up a memory chip. Background Technology

[0002] In memory products, there are mini-arrays outside the main memory used to store option bits or status bits. These option bits or status bits contain information necessary for memory operation, such as parameters that determine its function. This necessary information is read during the power-up of the memory product. Typically, the read voltage applied to the bit lines in the mini-array needs to be controlled to correctly read the option bits or status bits from the memory cell.

[0003] To provide a stable voltage source, bandgap reference (BGR) circuits are widely used in memory products. A BGR circuit is a voltage reference circuit that produces a substantially constant voltage regardless of power supply variations, temperature changes, or changes in circuit load from on-chip or off-chip components. When the memory product is powered on, the BGR circuit generates a reference voltage. At this time, the charge pump circuit generates a read voltage applied to the bit lines based on the reference voltage to read option bits or status bits from the memory cell.

[0004] However, during power-up, the BGR circuit cannot accurately provide a reference voltage because the supply voltage (VCC) may be unstable. Therefore, there is no guarantee that the charge pump circuit can generate the predetermined read voltage based on the reference voltage. The read voltage may not reach the target value, causing errors in the reads of option bits or status bits. Summary of the Invention

[0005] This invention relates to a semiconductor memory device that can correctly read information from option bits or status bits during power-on.

[0006] The semiconductor memory device of the present invention includes a memory cell array, a switching circuit, and a sensing circuit. The memory cell array includes a plurality of memory cells. The switching circuit is coupled to the memory cell array and includes at least one switch. Each switch receives a control signal and is controlled to turn on or off by the control signal. The sensing circuit is coupled to the switching circuit. During erase verification, the sensing circuit sequentially receives the erase verification current generated by each memory cell via the switching circuit to verify the erase state of each memory cell.

[0007] Based on the above, when a read operation is performed on the option bit or status bit during power-up, the sensing circuit can simultaneously receive at least two read currents generated from the memory cell. Therefore, the problem of reduced read current due to insufficient read voltage can be solved, increasing the read operation margin and thus ensuring accurate reading of the option bit or status bit. Attached Figure Description

[0008] Figure 1 This is a block diagram of a semiconductor memory device according to an embodiment of the present invention;

[0009] Figure 2 This is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention;

[0010] Figure 3A This is a schematic diagram of the erase operation of a semiconductor memory device according to an embodiment of the present invention;

[0011] Figure 3B This is a schematic diagram illustrating the operation of erasure verification of a semiconductor memory device according to an embodiment of the present invention;

[0012] Figure 3C This is a signal timing diagram for erasure verification of a semiconductor memory device according to an embodiment of the present invention;

[0013] Figure 3D This is an operational schematic diagram of a read operation of a semiconductor memory device according to an embodiment of the present invention;

[0014] Figure 3E This is a signal timing diagram of a read operation of a semiconductor memory device according to an embodiment of the present invention;

[0015] Figure 4 This is a circuit diagram of a semiconductor memory device according to another embodiment of the present invention;

[0016] Figure 5A This is a schematic diagram of the erase operation of a semiconductor memory device according to an embodiment of the present invention;

[0017] Figure 5B This is a schematic diagram illustrating the operation of erasure verification of a semiconductor memory device according to an embodiment of the present invention;

[0018] Figure 5C This is a schematic diagram of the read operation of a semiconductor memory device according to an embodiment of the present invention. Detailed Implementation

[0019] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0020] Figure 1 This is a block diagram of a semiconductor memory device according to an embodiment of the present invention. Figure 2 This is a circuit diagram of a semiconductor memory device according to an embodiment of the present invention. Please also refer to... Figure 1 and Figure 2 The semiconductor memory device 100 includes a memory cell array 110, a switching circuit 120, and a sensing circuit 130. The memory cell array 110 includes memory cells C0 and C1. In this embodiment, the memory cell array 110 is, for example, a mini-array in NOR flash memory, and memory cells C0 and C1 are used, for example, to store option bits or status bits.

[0021] like Figure 2 As shown, memory cells C0 and C1 are jointly coupled to word line WL0, and respectively coupled to switching circuit 120 and sensing circuit 130 via different bit lines BL0 and BL1. For ease of understanding, two memory cells are used in this embodiment, but the present invention is not limited thereto. As long as the circuit structure of memory cells being jointly coupled to a word line and respectively coupled to sensing circuit via different bit lines is met, those skilled in the art can extrapolate the number of memory cells used to more than one according to their actual needs, based on the teachings of the present invention.

[0022] Switching circuit 120 is coupled to memory cell array 110. Switching circuit 120 includes switches SW0 and SW1. Switch SW0 is disposed on bit line BL0 and coupled between memory cell C0 and sensing circuit 130. Switch SW1 is disposed on bit line BL1 and coupled between memory cell C1 and sensing circuit 130.

[0023] Switches SW0 and SW1 receive control signals Y0 and Y1, respectively. Switch SW0 can be turned on or off by control signal Y0. Switch SW1 can be turned on or off by control signal Y1. Switches SW0 and SW1 can be electronic components such as transistors. For example, when the control signal is a high logic level (ONL), the switch it controls will be turned on. When the control signal is a low logic level (OFFL), the switch it controls will be turned off. The ONL level is, for example, approximately 3 volts, and the OFFL level is, for example, approximately 0 volts. It should be noted that in other embodiments, the control signal can also control the state of the switch according to the logic level in the opposite manner to that described above, and the present invention is not limited thereto.

[0024] The sensing circuit 130 is coupled to the switching circuit 120. The sensing circuit 130 includes, for example, a circuit composed of a sensing amplifier, the internal structure, circuit operation and implementation of which can be adequately taught, advised and explained by ordinary knowledge in the art.

[0025] In this embodiment, when performing erase verification, the sensing circuit 130 can sequentially receive the erase verification current IEV0 generated by memory cell C0 and the erase verification current IEV1 generated by memory cell C1 via the switching circuit 120, so as to verify the erase status of each memory cell C0 and C1.

[0026] To explain in more detail the actions of the erase operation, erase verification, and read operation in this embodiment, please refer to the following. Figures 3A to 3E Please provide an explanation.

[0027] Figure 3A This is a schematic diagram illustrating the erase operation of a semiconductor memory device according to an embodiment of the present invention. Please refer to... Figure 3A During an erase operation, switches SW0 and SW1 are turned off based on control signals Y0 and Y1 at the off-level OFFL. Memory cells C0 and C1 are simultaneously erased based on the erase voltage VES applied to word line WL0. The erase voltage VES is, for example, approximately -9 volts. As a result, the data stored in memory cells C0 and C1 will, for example, become bits "1" after erasure, thus completing the erase operation.

[0028] Figure 3B This is a schematic diagram illustrating the operation of erasure verification of a semiconductor memory device according to an embodiment of the present invention. Figure 3C This is a signal timing diagram for erasure verification of a semiconductor memory device according to an embodiment of the present invention. Please also refer to... Figure 3B and Figure 3C ,like Figure 3B As shown, during erase verification, by applying the erase verification voltage VEV to the word line WL0 and sequentially applying the control signals Y0 and Y1 of the conduction level ONL to the switches SW0 and SW1, the sensing circuit 130 sequentially receives the erase verification currents IEV0 and IEV1 generated by the memory cells C0 and C1 (e.g., ...). Figure 3B (As shown from left to right). The erase verification voltage VEV is, for example, approximately 6 volts. In other words, memory cells C0 and C1 will generate verification currents IEV0 and IEV1 respectively based on the erase verification voltage VEV applied to word line WL0. And as... Figure 3CAs shown, control signal Y0 changes from an off level (OFFL) to an on level (ONL) at time t1, causing switch SW0 to conduct and allowing sensing circuit 130 to receive the erase verification current IEV0 generated by memory cell C0. Then, control signal Y1 changes from an off level (OFFL) to an on level (ONL) at time t2, causing switch SW1 to conduct and allowing sensing circuit 130 to receive the erase verification current IEV1 generated by memory cell C1.

[0029] In this way, the sensing circuit 130 can sequentially receive the erase verification current IEV0 generated by memory cell C0 and the erase verification current IEV1 generated by memory cell C1, and compare the erase verification currents IEV0 and IEV1 with a reference current respectively to complete the erase verification for memory cells C0 and C1. The reference current is, for example, 5 microamps. For example, taking the erase verification current IEV0 as an example, when the erase verification current IEV0 is greater than the reference current, it means that the erase verification for memory cell C0 has passed. When the erase verification current IEV0 is not greater than the reference current, it means that the erase verification for memory cell C0 has failed.

[0030] Figure 3D This is a schematic diagram of the read operation of a semiconductor memory device according to an embodiment of the present invention. Figure 3E This is a signal timing diagram of a read operation of a semiconductor memory device according to an embodiment of the present invention. The read operation in this embodiment is, for example, a read operation performed during the power-on period of the semiconductor memory device 100. Please also refer to... Figure 3D and Figure 3E ,like Figure 3D As shown, during a read operation, by applying a read voltage VR to the word line WL0 and simultaneously applying control signals Y0 and Y1 to switches SW0 and SW1 to enable the ONL, the sensing circuit 130 can simultaneously receive the read currents IR0 and IR1 generated by memory cells C0 and C1 via switches SW0 and SW1. In other words, memory cells C0 and C1 generate read currents IR0 and IR1 respectively based on the read voltage VR applied to the word line WL0. And as... Figure 3E As shown, control signals Y0 and Y1 will simultaneously change from the off level OFFL to the on level ONL at time t3, causing switches SW0 and SW1 to turn on at the same time. The target value of the voltage VR is, for example, approximately 6 volts, but it is usually less than the target value during power-up.

[0031] In this way, the sensing circuit 130 can simultaneously receive the read currents IR0 and IR1 generated by memory cells C0 and C1, and compare the sum of the read currents IR0 and IR1 (IR0+IR1) with a reference current (e.g., 5 microamps) to complete the read operation. For example, when the sum of the read currents IR0 and IR1 is greater than the reference current, it indicates that erased data (e.g., bit "1") stored in memory cells C0 and C1 has been read. When the sum of the read currents IR0 and IR1 is not greater than the reference current, it indicates that unerased data (e.g., bit "0") stored in memory cells C0 and C1 has been read.

[0032] Figure 4 This is a circuit diagram of a semiconductor memory device according to another embodiment of the present invention. Please refer to... Figure 4 The semiconductor memory device 200 includes a memory cell array 210, a switching circuit 220, and a sensing circuit 230. The memory cell array 210 includes memory cells C2 and C3. In this embodiment, the memory cell array 210 is, for example, a mini-array in NOR flash memory, and memory cells C2 and C3 are used, for example, to store option bits or status bits, but the present invention is not limited thereto.

[0033] like Figure 4 As shown, memory cells C2 and C3 are coupled to different word lines WL2 and WL3, respectively, and are coupled to the switching circuit 220 and the sensing circuit 230 via a common bit line BL2. For ease of understanding, two memory cells are used in this embodiment, but the present invention is not limited thereto. As long as the circuit structure of memory cells being coupled to different word lines and coupled to the sensing circuit via a common bit line is met, those skilled in the art can extrapolate the number of memory cells used to more than one according to their actual needs, based on the teachings of the present invention.

[0034] Switching circuit 220 is coupled to memory cell array 210. Switching circuit 220 includes switch SW2. Switch SW2 is disposed on bit line BL2 and coupled between memory cells C2 and C3 and sensing circuit 230.

[0035] Switch SW2 receives control signal Y2. Switch SW2 can be turned on or off by control signal Y2. Switch SW2 can be an electronic component such as a transistor. For example, when the control signal is a high logic level (ONL), the switch it controls will be on. When the control signal is a low logic level (OFFL), the switch it controls will be off. It should be noted that in other embodiments, the control signal can also control the state of the switch according to the logic level in the opposite manner to that described above. This invention is not limited thereto.

[0036] The sensing circuit 230 is coupled to the switching circuit 220. The sensing circuit 230 is, for example, a circuit composed of a sensing amplifier, and its internal structure, circuit operation and implementation may be the same as those of the sensing circuit 130 in the aforementioned embodiment.

[0037] In this embodiment, when performing erase verification, the sensing circuit 230 can sequentially receive the erase verification current IEV2 generated by memory cell C2 and the erase verification current IEV3 generated by memory cell C3 via the switching circuit 220, so as to verify the erase status of each memory cell C2 and C3.

[0038] To explain in more detail the actions of the erase operation, erase verification, and read operation in this embodiment, please refer to the following. Figures 5A to 5C Please provide an explanation.

[0039] Figure 5A This is a schematic diagram illustrating the erase operation of a semiconductor memory device according to an embodiment of the present invention. Please refer to... Figure 5A During an erase operation, switch SW2 is turned off based on the control signal Y2 at the off level OFFL, and memory cells C2 and C3 are simultaneously erased based on the erase voltage VES applied to word lines WL2 and WL3. As a result, the data stored in memory cells C2 and C3 will, for example, become a bit "1" after erasure, thus completing the erase operation.

[0040] Figure 5B This is a schematic diagram illustrating the erase verification operation of a semiconductor memory device according to an embodiment of the present invention. Please refer to... Figure 5B During erase verification, by sequentially applying the erase verification voltage VEV to word lines WL2 and WL3 and applying the control signal Y2 of the on-level ONL to switch SW2, the sensing circuit 230 sequentially receives the erase verification currents IEV2 and IEV3 generated by memory cells C2 and C3 (e.g., ...). Figure 5B (As shown from left to right). In other words, during the period when the control signal Y2 changes from the off level OFFL to the on level ONL, turning on the switch SW2, the erase verification voltage VEV is first applied to word line WL2 (while voltage V0 is applied to word line WL3), so that the sensing circuit 230 receives the erase verification current IEV2 generated by memory cell C2. Then, the erase verification voltage VEV is applied to word line WL3 (while voltage V0 is applied to word line WL2), so that the sensing circuit 230 receives the erase verification current IEV3 generated by memory cell C3. Voltage V0 is, for example, approximately 0 volts.

[0041] In this way, the sensing circuit 230 can sequentially receive the erase verification current IEV2 generated by memory cell C2 and the erase verification current IEV3 generated by memory cell C3, and compare the erase verification currents IEV2 and IEV3 with the reference current respectively to complete the erase verification for memory cells C2 and C3 respectively. For example, taking the erase verification current IEV2 as an example, when the erase verification current IEV2 is greater than the reference current, it means that the erase verification for memory cell C2 has passed. When the erase verification current IEV2 is not greater than the reference current, it means that the erase verification for memory cell C2 has failed.

[0042] Figure 5C This is a schematic diagram illustrating the read operation of a semiconductor memory device according to an embodiment of the present invention. The read operation in this embodiment is, for example, a read operation performed during the power-on period of the semiconductor memory device 100. Please refer to... Figure 5C During a read operation, by simultaneously applying a read voltage VR to word lines WL2 and WL3 and applying a control signal Y2 (ONL) to switch SW2, the sensing circuit 230 can simultaneously receive the read currents IR2 and IR3 generated by memory cells C2 and C3 via switch SW2. In other words, memory cells C2 and C3 generate read currents IR2 and IR3 respectively based on the read voltage VR applied to word lines WL2 and WL3. Furthermore, the control signal Y2 changes from an off level (OFFL) to an on level (ONL) to turn on switch SW2.

[0043] In this way, the sensing circuit 130 can simultaneously receive the read currents IR2 and IR3 generated by memory cells C2 and C3, and compare the sum of the read currents IR2 and IR3 (IR2+IR3) with a reference current to complete the read operation. For example, when the sum of the read currents IR2 and IR3 is greater than the reference current, it indicates that erased data (e.g., bit "1") stored in memory cells C2 and C3 has been read. When the sum of the read currents IR2 and IR3 is not greater than the reference current, it indicates that unerased data (e.g., bit "0") stored in memory cells C2 and C3 has been read.

[0044] Through the above operations, when a read operation is performed on the option bit or status bit during power-up, the sensing circuit can receive at least two read currents. Even if the read voltage applied to the word line does not reach the target value, resulting in a decrease in read current, the decrease can be compensated by summing the at least two read currents, increasing the read operation margin and thus correctly reading the option bit or status bit.

[0045] In summary, the semiconductor memory device of the present invention can solve the problem of reduced read current caused by insufficient read voltage, thereby correctly reading option bits or status bits during power-on.

[0046] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor memory device, characterized in that, include: A memory cell array, comprising multiple memory cells; A switching circuit, coupled to the memory cell array, includes at least one switch, each of the at least one switch receiving a control signal and being controlled by the control signal to turn on or off; as well as A sensing circuit, coupled to the switching circuit, receives erase verification currents sequentially from each of the plurality of memory cells via the switching circuit during erase verification, in order to verify the erase status of each of the plurality of memory cells. During power-up, when a read operation is performed by applying a read voltage to the memory cell array, the sensing circuit simultaneously receives the read current generated by each of the plurality of memory cells via the switching circuit, and compares the summed current obtained by summing the read currents with a reference current. The read voltage during power-on is less than the erase verification voltage used to verify the erase state.

2. The semiconductor memory device according to claim 1, characterized in that, The plurality of memory cells are coupled to at least one word line, and when an erase operation is performed, the plurality of memory cells are erased simultaneously based on the erase voltage applied to the at least one word line.

3. The semiconductor memory device according to claim 1, characterized in that, The plurality of memory cells are coupled to a word line and are respectively coupled to the switching circuit and the sensing circuit via different bit lines. Each of the at least one switch is disposed on the corresponding bit line and coupled between the corresponding memory cell and the sensing circuit.

4. The semiconductor memory device according to claim 3, characterized in that, During the erase verification, the sensing circuit sequentially receives the erase verification current generated by each of the plurality of memory cells by applying the erase verification voltage to the word line and sequentially applying the control signal of the conduction level to the at least one switch.

5. The semiconductor memory device according to claim 4, characterized in that, The at least one switch includes a first switch and a second switch, and the plurality of bit lines include a first bit line and a second bit line. The first switch is disposed on the first bit line, and the second switch is disposed on the second bit line. When the erase verification is performed, the semiconductor memory device sequentially applies the control signal of the conduction level to the first switch and the second switch, so that the sensing circuit sequentially receives the erase verification current generated by each of the plurality of memory cells.

6. The semiconductor memory device according to claim 1, characterized in that, The plurality of memory cells are respectively coupled to different word lines and coupled to the switching circuit and the sensing circuit via a common bit line. The at least one switch is disposed on the bit line and coupled between the plurality of memory cells and the sensing circuit.

7. The semiconductor memory device according to claim 6, characterized in that, During the erase verification, the sense circuit sequentially receives the erase verification current generated by each of the plurality of memory cells by sequentially applying the erase verification voltage to the plurality of word lines and applying the control signal of the conduction level to the at least one switch.

8. The semiconductor memory device according to claim 7, characterized in that, The plurality of word lines include a first word line and a second word line. When the erase verification is performed, the erase verification voltage is first applied to the first word line so that the sensing circuit receives the erase verification current generated by the memory cell coupled to the first word line. Then the erase verification voltage is applied to the second word line so that the sensing circuit receives the erase verification current generated by the memory cell coupled to the second word line.

9. The semiconductor memory device according to claim 1, characterized in that, The memory cell array is a miniature array in NOR flash memory, and the plurality of memory cells are used to store option bits or status bits.

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