Static random access memory cell and method of forming the same

Abstract

Embodiments of the present application provide a static random access memory cell and a forming method thereof, wherein the forming method comprises: providing a substrate; wherein the substrate comprises at least a substrate and an active region formed in the substrate; forming a trench extending along a first direction and arranged along a second direction in the active region; forming a second gate structure extending along the first direction in the trench; trimming the second gate structure along the second direction to form the first gate structure; wherein in a memory comprising static random access memory cells, every two rows and two rows apart of the first gate structure have the same opening position; forming a recessed channel array transistor based on the first gate structure; and forming a static random access memory cell with six transistors based on the recessed channel array transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a static random access memory cell and a method for forming the same. Background Technology

[0002] Static Random Access Memory (SRAM), as a type of memory, has advantages such as high speed, low power consumption, and compatibility with standard processes. It is widely used in personal computers, personal communications, and consumer electronics products, such as smart cards, digital cameras, and multimedia players.

[0003] In related technologies, the source and drain channels in N-channel metal-oxide-semiconductor (NMOS) and P-channel metal-oxide-semiconductor (PMOS) cells in SRAM cells are difficult to shrink, making it difficult to reduce the signal noise margin (SNM) and affecting circuit performance. Summary of the Invention

[0004] This application provides a static random access memory cell and a method for forming the same.

[0005] In a first aspect, embodiments of this application provide a method for forming a static random access memory cell, comprising:

[0006] A substrate is provided; wherein the substrate includes at least a substrate and an active region formed therein; trenches extending in a first direction and arranged in a second direction are formed in the active region; a second gate structure extending in the first direction is formed in the trenches; the second gate structure is trimmed along the second direction to form a first gate structure; wherein, in a memory including static random access memory cells, the first gate structures in every two rows and every two rows have the same opening position; a recessed channel array transistor is formed based on the first gate structure; and a static random access memory cell having six transistors is formed based on the recessed channel array transistor.

[0007] Secondly, embodiments of this application provide a static random access memory (SRAM) cell, each of which includes six transistors, including a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first access transistor, and a second access transistor. Each transistor is a recessed channel array transistor, comprising: a substrate, the substrate including at least a base and an active region formed therein; and a first gate structure located within the substrate, extending along a first direction and arranged along a second direction; wherein, in the memory including the SRAM cells, every two rows of the first gate structures spaced two rows apart have the same opening position.

[0008] In this embodiment, a recessed channel array transistor with a first gate structure is formed in the substrate. The first gate structure is a buried gate structure formed in the recess after the recess is formed in the substrate, which is different from the planar gate structure formed on the substrate surface in related technologies. That is, the gate in the SRAM of this embodiment is improved from a planar shape to a recess, so that the device can obtain a longer channel length and a better SNM under the same layout. Attached Figure Description

[0009] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0010] Figure 1a A schematic diagram illustrating the implementation flow of a static random access memory cell formation method provided in this application embodiment;

[0011] Figures 1b to 1h A schematic diagram of the formation process of a static random access memory cell provided in an embodiment of this application;

[0012] Figure 1i This is a schematic diagram of a planar gate structure in related technologies;

[0013] Figure 1j The circuit structure diagram of a 6T SRAM in related technologies is shown.

[0014] Figure 1k To and Figure 1j The corresponding layout diagram of the 6T SRAM circuit structure;

[0015] Figure 2a A schematic diagram illustrating the implementation flow of a static random access memory cell formation method provided in this application embodiment;

[0016] Figures 2b to 2i A schematic diagram illustrating the formation process of a static random access memory cell provided in an embodiment of this application;

[0017] Figure 3a A schematic diagram illustrating the implementation flow of a static random access memory cell formation method provided in this application embodiment;

[0018] Figures 3b to 3f This is a schematic diagram illustrating the formation process of a static random access memory cell, as provided in an embodiment of this application. Detailed Implementation

[0019] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the disclosure of the present application to those skilled in the art.

[0020] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0021] This application provides a method for forming a static random access memory cell, such as... Figure 1a As shown, the method includes steps S101 to S106. Wherein:

[0022] Step S101: Provide a substrate; wherein the substrate includes at least a substrate and an active region formed in the substrate.

[0023] Here, the substrate can be a silicon (Si) substrate, a germanium (Ge) substrate, a germanium-silicon (SiGe) substrate, a gallium arsenide substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display. It can also include multiple layers, such as silicon on insulator (SOI) substrates or germanium on insulator (GOI) substrates.

[0024] Step S102: Forming trenches extending in a first direction and arranged in a second direction within the active region.

[0025] Here, the substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side. Ignoring the flatness of the top and bottom surfaces, a direction perpendicular to the top and bottom surfaces of the substrate is defined as a third direction. In the direction of the top and bottom surfaces of the substrate (i.e., the plane in which the substrate lies), two intersecting (e.g., perpendicular) directions are defined. For example, the extension direction of the grooves can be defined as the first direction, and the arrangement direction of the grooves as the second direction. The planar orientation of the substrate can be determined based on the first and second directions. The first direction, the second direction, and the third direction are mutually perpendicular. In this embodiment, the first direction is defined as the X-axis direction, the second direction as the Y-axis direction, and the third direction as the Z-axis direction.

[0026] Here, the grooves can be formed using either self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP).

[0027] Step S103: A second gate structure extending along the first direction is formed in the trench.

[0028] Here, the trench extends in the same direction as the second gate structure. The material of the second gate structure can be a metal, polysilicon, conductive metal oxide, or conductive metal nitride, for example, it can be a metal such as tungsten, copper, aluminum, silver, or titanium.

[0029] Step S104: Trim the second gate structure along the second direction to form the first gate structure; wherein, in the memory including static random access memory cells, every two rows of the first gate structure with a two-row interval have the same opening position.

[0030] This can be understood as cutting the long second gate structure to form a short first gate structure. The second gate structure can be etched using either dry or wet etching to form the first gate structure. The first gate structure is used to connect to the word line, and the voltage signal on the word line can control the transistor to turn on or off.

[0031] Step S105: Based on the first gate structure, a recessed channel array transistor is formed.

[0032] Here, the recessed array transistor has a buried gate structure, which can increase the process integration of semiconductor manufacturing and reduce the device size.

[0033] Step S106: Form a static random access memory cell with six transistors based on the recessed channel array transistors.

[0034] Here, the static random access memory cell includes multiple recessed channel array transistors, such as 10, 8, 6, or other numbers of recessed channel array transistors. Generally, static random access memory (6T SRAM) with 6 transistors is more widely used, and the following embodiments of this application will use 6T SRAM as an example for illustration.

[0035] In this embodiment, a trench is formed in the active region of the substrate, followed by the formation of a buried first gate structure within the trench. A recessed channel array transistor (SNM) is then formed based on the first gate structure, ultimately forming a static random access memory (SRAM) cell. The buried first gate structure differs from the planar gate structure formed on the substrate surface in related technologies. Specifically, in this embodiment, the gate in the SRAM is modified from a planar structure to a recess, allowing the device to achieve a longer channel length and better SNM within the same layout, while maintaining sufficient channel length to reduce leakage issues.

[0036] Figures 1b to 1h This is a schematic diagram of the static random access memory cell formation process provided in the embodiments of this application. Next, in conjunction with... Figures 1b to 1h The steps S101 to S106 described above will be further explained.

[0037] like Figure 1b As shown in the left and right figures, a shallow trench isolation (STI) 102 is formed in the substrate 101. The shallow trench isolation 102 isolates several active regions 103 in the substrate 101, thus forming the substrate 100.

[0038] STI can be formed by forming isolation trenches in the substrate and then filling the isolation trenches with an isolation material layer. The filling material in the STI can include silicon nitride or silicon oxide, and silicon oxide can be formed by thermally oxidizing a silicon substrate. The STI can isolate several active regions that are distributed in an array or other types of distribution in the substrate.

[0039] Here, the substrate can be partially doped to form an n-type doped active region, and the doping element can be phosphorus, arsenic, boron or other suitable elements.

[0040] See Figure 1c A self-aligned double patterning technique is used to form grooves 106 extending along the X-axis and arranged along the Y-axis within the active region 103.

[0041] In some embodiments, the active region may include source and drain regions, wherein the source and drain regions include a source region and a drain region, which are located on opposite sides of the trench. Alternatively, a lightly doped drain region may be formed near the drain region, which can withstand a portion of the voltage.

[0042] See Figure 1c Within the groove 106, a groove extending along the X-axis direction is formed as shown in the figure. Figure 1d The second gate structure 107 is shown.

[0043] In some embodiments, see continue to see Figure 1d The second gate structure 107 includes an isolation layer 107a and a conductive layer 107b. The isolation layer 107a is located on the inner surface of the trench 106, that is, the sidewalls and bottom of the trench 106 are covered by the isolation layer 107a; the top surface of the conductive layer 107b is lower than the surface of the substrate 101.

[0044] The insulating layer can be made of silicon dioxide, which can be formed by thermal oxidation or by any of the following: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and any other suitable deposition process.

[0045] The conductive layer can be made of one or more of the following: polycrystalline silicon, metal silicide compounds, conductive metal nitrides (e.g., titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc.), and metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), etc.). The conductive layer can be formed by any of the following methods: chemical vapor deposition, physical vapor deposition, plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition, and any other suitable deposition process.

[0046] In some embodiments, see continue to see Figure 1d The second gate structure 107 further includes an insulating layer 107c located on the conductive layer 107b. The top surface of the insulating layer 107c is flush with the top surface of the substrate 101. The insulating layer 107c may be made of a high dielectric constant material such as silicon nitride.

[0047] See Figure 1e , Figure 1e for Figure 1d The top view of the second gate structure in the figure shows the second gate structure 107 etched along the Y-axis direction to form the... Figure 1fThe first gate structure 108 shown has the same opening position 108a in every two rows and every two rows of the first gate structure.

[0048] See Figure 1g Based on the first gate structure 108, a recessed channel array transistor 104 is formed; wherein, the recessed channel array transistor 104 adopts a buried first gate structure 108; based on the recessed channel array transistor 104, a recessed channel array transistor 104 is formed as follows: Figure 1h The static random access memory cell 105 shown has six transistors.

[0049] The SRAM cells provided in this application embodiment employ a buried gate structure, meaning that the upper surface of the gate structure in this application embodiment is lower than the upper surface of the substrate, unlike the planar gate structures formed on the substrate or substrate in related technologies. Therefore, SRAM can achieve a longer channel length under the same layout, resulting in better SNM. Figure 1i See the schematic diagram of the planar gate structure provided in the related art. Figure 1i Source / drain regions 202 and lightly doped drain regions 203 are formed on substrate 201. A gate structure 204 and a dielectric layer 206 are formed on substrate 201, with sidewalls 205 located on both sides of the gate structure 204 and the dielectric layer 206. Figure 1i As can be seen, in the related technologies, the bottom surface of the gate structure 204 is on the upper surface of the substrate. In other related technologies, the planar gate structure may also include a case where the upper surface of the gate structure 204 is higher than the upper surface of the substrate.

[0050] The embodiments provided in this application Figure 1h The SRAM layout shown can adopt the SRAM circuit layout provided in related technologies. The difference is that the transistors in the SRAM are trench array transistors and the gate structure is buried.

[0051] The 6T SRAM in the related technology consists of two pass-through (PG) N-channel metal-oxide-semiconductor (NMOS), two pull-up (PU) P-channel metal-oxide-semiconductor (PMOS), and two pull-down (PD) N-channel metal-oxide-semiconductor (NMOS).

[0052] Figure 1j For a circuit diagram of a 6T SRAM in related technologies, please refer to [link / reference]. Figure 1jLet the two PGs be denoted as PG1 and PG2, the two PUs as PU1 and PU2, and the two PDs as PD1 and PD2. PU1 and PD1 form the first inverter, and PU2 and PD2 form the second inverter. The first and second inverters are cross-coupled, meaning that the input of the first inverter is electrically connected to the output of the second inverter, and the output of the first inverter is electrically connected to the input of the second inverter, forming a latch circuit used to latch data logic values. The drains of PU1, PD1, and PG1, the gate of PU2, and the gate of PD2 are electrically connected to form the first memory node S; the gates of PU1 and PD1, the drains of PU2, PD2, and PG2 are electrically connected to form the second memory node SB.

[0053] See also Figure 1j and Figure 1k , Figure 1k For the corresponding Figure 1j The circuit layout shown has PG1 and PD1 located in the same active region with a common drain, and PG2 and PD2 located in the same active region with a common drain. When the first memory node S is pulled down to a low potential, the second memory node SB is pulled up to a high potential, or when the first memory node S is pulled down to a high potential, the second memory node SB is pulled up to a low potential. The first memory node S and the second memory node SB form a complementary pair. The gates of PG1 and PG2 are electrically connected to the word line (WL); the source of PG1 is electrically connected to the first bit line BL1; the source of PG2 is electrically connected to the second bit line BL2. The first bit line BL1 and the second bit line BL2 are complementary bit lines. The sources of PU1 and PU2 are electrically connected to the power line Vdd; the sources of PD1 and PD2 are electrically connected to the ground line. When the word line WL voltage is switched to the system high voltage, PG1 and PG2 are turned on, allowing the first storage node S and the second storage node SB to read and write data logic values ​​through the first bit line BL1 and the second bit line BL2. When the word line WL voltage is switched to the system low voltage, PG1 and PG2 are turned off, and the first storage node S and the second storage node SB are isolated from the first bit line BL1 and the second bit line BL2. The power supply line Vdd ensures that the state of the first storage node S and the second storage node SB is maintained.

[0054] based on Figure 1a The present application provides a method for forming a static random access memory cell, as shown in the embodiments. Figure 1h The SRAM cell 105 shown is also referred to. Figure 1g and Figure 1hEach static random access memory cell 105 includes six transistors, namely a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first access transistor PG1, and a second access transistor PG2. Each transistor employs a recessed channel array transistor 104, including:

[0055] The substrate includes at least a substrate 101 and an active region 103 formed in the substrate 101;

[0056] A first gate structure 108 is located within the substrate, extending along a first direction (X-axis direction) and arranged along a second direction (Y-axis direction); wherein, in a memory including static random access memory cells, every two rows of the first gate structures 108 with a two-row interval have the same opening 108a position.

[0057] In some embodiments, see Figure 1d The first gate structure includes: an isolation layer 107a and a conductive layer 107b formed on the isolation layer 107a; wherein the surface of the conductive layer 107b is lower than the surface of the substrate 101.

[0058] This application provides a method for forming a static random access memory cell, such as... Figure 2a As shown, the method includes steps S201 to S207. Wherein:

[0059] Step S201: Provide a substrate; wherein the substrate includes at least a substrate and an active region formed in the substrate.

[0060] Step S201 is the same as step S101, and you can refer to step S101 for understanding.

[0061] Step S202: A first mask pattern is formed in the active region using a self-aligned multi-patterning process; wherein the first mask pattern includes a first window extending along the first direction and arranged along the second direction.

[0062] Here, the first mask pattern can be obtained by exposing the photoresist layer using a preset mask; the first window corresponds to the position of the trench, and the first window can expose part of the active area.

[0063] Step S203: Etch the active region based on the first window to form a trench in the active region.

[0064] Here, the active region can be etched using dry or wet etching methods to form trenches. For example, reactive ion etching or high-density plasma etching processes can be used; alternatively, sulfuric acid, hydrofluoric acid, nitric acid, or other etchants can be used to etch the active region.

[0065] Step S204: A second gate structure extending along the first direction is formed in the trench.

[0066] Step S205: Trim the second gate structure along the second direction to form a first gate structure; wherein, in the memory including static random access memory cells, every two rows of the first gate structure have the same opening position.

[0067] Here, a split gate structure in SRAM is formed by trimming the second gate structure.

[0068] Step S206: Based on the first gate structure, form a recessed channel array transistor;

[0069] Step S207: Form a static random access memory cell with six transistors based on the recessed channel array transistor.

[0070] Steps S204 to S207 are the same as steps S103 to S106, and can be understood by referring to steps S103 to S106.

[0071] In this embodiment, a self-aligned multi-patterning process is used to form trenches on the substrate, thereby doubling the number of trenches and obtaining better dimensional resolution. A second gate structure is formed in the trench, and the second gate structure is trimmed to form a first gate structure. Then, a static random access memory cell with six transistors is formed. Since a recessed channel array transistor is used, sufficient channel length can be maintained to reduce leakage problems.

[0072] In some embodiments, step S202 may include steps S202a to S202e. Wherein:

[0073] Step S202a, see Figure 1b On the substrate 100, as shown in the figure Figure 2b The diagram shows a nitrided layer 109, a first mask layer 110, a second mask layer 111, a first anti-reflective coating 112, and a first photoresist layer 113. Figure 2b Not shown in the middle Figure 1b The shallow trench isolation 102 is shown. In some embodiments, a nitriding layer may not be formed on the substrate.

[0074] The first anti-reflective layer can be one or a stack of two of the following: a bottom anti-reflective coating (BARC) and a dielectric anti-reflective coating (DARC). The bottom anti-reflective coating is generally made of organic materials, while the dielectric anti-reflective coating is generally made of inorganic materials. Relatively speaking, the dielectric anti-reflective coating is less expensive, but its anti-reflective effect is not as good as that of the bottom anti-reflective coating, and its processing window is smaller. To ensure the anti-reflective effect, the thickness and uniformity of the underlying film need to be strictly controlled. In this embodiment, the material used for the first anti-reflective layer can be silicon oxynitride (SiON).

[0075] The first mask layer can be a double-layer structure or a single-layer structure. The material used for the first mask layer can be one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, amorphous carbon, polycrystalline silicon, hafnium oxide, titanium oxide, zirconium oxide, titanium nitride, tantalum nitride, and titanium. The first mask layer can be formed by deposition using any of the following methods: chemical vapor deposition, physical vapor deposition, atomic layer deposition, and any other suitable deposition process.

[0076] The nitride layer serves two purposes: firstly, as a passivation layer to protect the active region during the deposition of the isolation layer and conductive material in the trench; and secondly, as a polishing barrier layer in the subsequent chemical mechanical polishing (CMP) process for the isolation layer. The nitride layer is fabricated using low-pressure chemical vapor deposition (LPCVD), and its material can be silicon nitride, which can be formed by the reaction of ammonia and dichlorosilane.

[0077] The second mask layer can be silicon nitride, silicon carbide, or silicon oxynitride, and can be formed using the same deposition process as the first mask layer.

[0078] Step S202b, see Figure 2b Through processes such as exposure and development, a photoresist layer 113 is formed in the first photoresist layer 113. Figure 2c The first initial mask 113a is shown.

[0079] Step S202c, see Figure 2c The first initial mask 113a is used to etch the second mask layer 111 to transfer the pattern on the first initial mask 113a to the second mask layer 111, leaving a pattern such as... Figure 2d The second mask layer 111a after etching is shown.

[0080] Step S202d, see Figure 2dOn the surface of the etched second mask layer 111a, a deposition is made as follows: Figure 2e The insulating material 111b shown is used to remove the etched second mask layer 111a to form the following: Figure 2f The isolation sidewall 111c shown.

[0081] Step S202e, see Figure 2f The first mask layer 110 is etched through the isolation sidewall 111c to transfer the pattern of the first isolation sidewall 111c into the first mask layer 110, forming a pattern as shown in the figure. Figure 2g The first mask pattern 114 shown includes a first window 114a extending along the X-axis and arranged along the Y-axis, the first window 114a defining the position of the groove 106.

[0082] See Figure 2g In step S203, based on the first window 114a, the active region 103 is dry-etched to form a structure in the active region 103 as shown in the image. Figure 2h The groove 106 shown.

[0083] See Figure 2h Step S204 is executed, forming a groove 106 as shown in the figure. Figure 2i The second gate structure 107 shown extends along the X-axis direction.

[0084] Continuing to execute steps S205 through S207 will result in the formation of... Figure 1h The static random access memory cell 105 shown has six transistors.

[0085] This application provides a method for forming a static random access memory cell, such as... Figure 3a As shown, the method includes steps S301 to S308. Wherein:

[0086] Step S301: Provide a substrate; wherein the substrate includes at least a substrate and an active region formed in the substrate.

[0087] Step S301 is the same as step S101, and you can refer to step S101 for understanding.

[0088] Step S302: A first mask pattern is formed in the active region using a self-aligned multi-patterning process; wherein the first mask pattern includes a first window extending along the first direction and arranged along the second direction.

[0089] Step S303: Etch the active region based on the first window to form trenches extending along a first direction and arranged along a second direction in the active region.

[0090] Steps S302 to S303 are the same as steps S202 to S203, and can be understood by referring to steps S202 to S203.

[0091] Step S304: A second gate structure extending along the first direction is formed in the trench.

[0092] In some embodiments, the second gate structure includes an isolation layer and a conductive layer, and step S304 can be implemented through steps S304a and S304b. Wherein:

[0093] Step S304a, see Figure 3b An isolation layer 107a is formed on the inner surface of the trench 106.

[0094] Here, the isolation layer can be a silicon dioxide (SiO2) layer. The isolation layer can be formed by any of the following methods: chemical vapor deposition, physical vapor deposition, atomic layer deposition, and any other suitable deposition process.

[0095] In some embodiments, the thickness of the isolation layer and the size of the recessed channel array transistor satisfy a preset proportional relationship.

[0096] In some embodiments, the thickness of the insulating layer is 15 to The thickness of the isolation layer in dynamic random access memory is 30 to SRAM uses thin oxide layers, with a thickness of 15 to... It can achieve better device performance.

[0097] Step S304b, see Figure 3b Formed on the isolation layer 107a as follows Figure 1d The conductive layer 107b shown is located in the trench 106 to form a second gate structure 107 extending along the X-axis direction within the trench 106; wherein the surface of the conductive layer 107b is lower than the surface of the substrate 101.

[0098] In some embodiments, step S304b can be implemented by the following step A0: See Figure 3c A metal layer 107b1 and a polysilicon layer 107b2 are sequentially formed in the trench on the isolation layer 107a. The polysilicon layer can be replaced with a material with a low work function. The second gate structure using a tungsten metal layer and a polysilicon layer can achieve better performance; using only a tungsten metal layer to form the second gate structure requires adjusting the channel injection to obtain a larger SNM.

[0099] In some embodiments, step A0 is followed by step A1: see below. Figure 3cAn insulating layer 107c is formed on the polysilicon layer 107b2; wherein the surface of the insulating layer 107c is flush with the surface of the substrate 101. The insulating layer is isolated from the source / drain regions by an isolation layer. The insulating layer may be made of a high-dielectric-constant material such as silicon nitride.

[0100] Step S305: Form a second mask pattern on the surface of the substrate; wherein the second mask pattern includes a second window extending along the second direction and arranged along the first direction.

[0101] Here, the second window defines the location of the opening.

[0102] In some embodiments, step S305 includes steps S305a to S305c. Wherein:

[0103] Step S305a, see Figure 3d A third mask layer 115, a second anti-reflection layer 116, and a second photoresist layer 117 are sequentially formed on the substrate on which the second gate structure is formed.

[0104] Here, the material of the third mask layer can be the same as that of the first mask layer or the second mask layer, and the forming process can also be the same; the material of the second anti-reflection layer can be the same as that of the first anti-reflection layer, and the forming process can also be the same.

[0105] Step S305b, see below Figure 3d Through processes such as exposure and development, a photoresist layer 117 is formed in the second photoresist layer 117. Figure 3e Second initial mask 117a.

[0106] Step S305c, see Figure 3e The second initial mask 117a is used to etch the third mask layer 115 to transfer the pattern on the second initial mask 117a to the third mask layer 115, forming a pattern as shown in the image. Figure 3f The second mask pattern 118 shown includes a second window 118a extending along the Y-axis and arranged along the X-axis.

[0107] Step S306: Etch the second gate structure based on the second window to form a first gate structure; wherein, in the memory including static random access memory cells, every two rows of the first gate structure with a two-row interval have the same opening position.

[0108] Here, after executing step S306, the following is formed: Figure 1f The first gate structure is shown.

[0109] Step S307: Based on the first gate structure, a recessed channel array transistor is formed.

[0110] Step S308: Form a static random access memory cell with six transistors based on the recessed channel array transistor.

[0111] Steps S307 to S308 are the same as steps S105 to S106, and can be understood by referring to steps S105 to S106.

[0112] In this embodiment, a self-aligned multi-patterning process is used to form trenches in the substrate, and a second gate structure is formed in the trenches. The second gate structure is etched based on a second window to form a recessed channel array transistor with an embedded first gate structure. This improves the gate in the SRAM from a planar shape to a recessed shape, thereby enabling the device to obtain a longer channel length and a better SNM under the same layout.

[0113] In some embodiments, the first gate structure includes: an isolation layer and a conductive layer formed on the isolation layer; wherein the surface of the conductive layer is lower than the surface of the substrate.

[0114] In some embodiments, the conductive layer in the static random access memory cell includes a metal layer and a polysilicon layer located on the metal layer.

[0115] In some embodiments, the first gate structure in the static random access memory cell further includes an insulating layer located on the polysilicon layer; wherein the surface of the insulating layer is flush with the surface of the substrate.

[0116] In some embodiments, the thickness of the isolation layer in the static random access memory cell and the size of the recessed channel array transistor satisfy a preset proportional relationship.

[0117] In some embodiments, the thickness of the isolation layer in the static random access memory cell is 15 to 15.

[0118] The features disclosed in the several methods or static random access memory cell embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or static random access memory cell embodiments.

[0119] The description of the static random access memory (SRAM) cell embodiments above is similar to the description of the method embodiments above, and has similar beneficial effects. For technical details not disclosed in the memory cell embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0120] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for forming a static random access memory memory cell, comprising: The method comprises: providing a substrate; wherein the substrate comprises at least a substrate and an active region formed in the substrate; forming a first mask pattern in the active region by using a self-aligned multi-pattern process; wherein the first mask pattern comprises first windows extending along a first direction and arranged along a second direction; etching the active region based on the first windows to form trenches in the active region; forming a second gate structure extending along the first direction in the trenches, comprising: forming an isolation layer on the inner surface of the trenches, forming a conductive layer in the trenches on the isolation layer; wherein the surface of the conductive layer is lower than the surface of the substrate, forming an insulating layer on the conductive layer, the surface of the insulating layer is flush with the surface of the substrate; trimming the second gate structure along the second direction to form a first gate structure; wherein in a memory comprising static random access memory cells, every two rows and every two rows of the first gate structure have the same opening position; forming a recessed channel array transistor based on the first gate structure; forming a static random access memory cell with six transistors based on the recessed channel array transistor.

2. The method of claim 1, wherein, The trimming the second gate structure along the second direction to form a first gate structure comprises: forming a second mask pattern on the surface of the substrate; wherein the second mask pattern comprises second windows extending along the second direction and arranged along the first direction; etching the second gate structure based on the second windows to form a first gate structure.

3. The method of claim 1, wherein, The forming a conductive layer in the trenches on the isolation layer comprises: forming a metal layer and a polysilicon layer in the trenches on the isolation layer in sequence.

4. The method according to claim 1 or 3, characterized in that, The thickness of the isolation layer and the size of the recessed channel array transistor satisfy a preset proportional relationship.

5. The method of claim 4, wherein, The thickness of the isolation layer is 15-25 Å.

6. The method of claim 3, wherein, After the forming a metal layer and a polysilicon layer in the trenches on the isolation layer in sequence, the method further comprises: forming the insulating layer on the polysilicon layer.

7. A static random access memory cell, comprising: Each of the static random access memory cells comprises six transistors, the six transistors comprising a first pull-up transistor, a second pull-up transistor, a first pull-down transistor, a second pull-down transistor, a first access transistor and a second access transistor, each of the transistors being a recessed channel array transistor, comprising: a substrate, the substrate comprising at least a substrate and an active region formed in the substrate; a first gate structure, the first gate structure being located in the substrate, extending along a first direction and arranged along a second direction; wherein in a memory comprising static random access memory cells, every two rows and every two rows of the first gate structure have the same opening position, the first gate structure comprising: an isolation layer and a conductive layer formed on the isolation layer; wherein the surface of the conductive layer is lower than the surface of the substrate; the first gate structure further comprises an insulating layer on the conductive layer, the surface of the insulating layer is flush with the surface of the substrate.

8. The static random access memory cell of claim 7, wherein, the conductive layer comprises: a metal layer and a polysilicon layer on the metal layer.

9. The static random access memory cell of claim 8, wherein, the insulating layer is on the polysilicon layer.

10. The static random access memory cell of claim 9, wherein, The metal layer is tungsten, and the insulating layer is silicon nitride.

11. The static random access memory cell of any one of claims 7 to 10, wherein, The thickness of the isolation layer and the size of the recessed channel array transistor satisfy a preset proportional relationship.

12. The static random access memory cell of claim 11, wherein, The thickness of the isolation layer is 15-25 Å.

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