Static random access memory structure and method of manufacturing the same

Abstract

The application provides a static random access memory structure and a preparation method thereof. The static random access memory structure comprises a substrate, an isolation structure, at least two static random access memory cells sharing a word line, and a plurality of active regions defined by the isolation structure on the substrate. Each static random access memory cell comprises at least two inverter groups and at least two transfer transistor groups. Each inverter group comprises two inverters cross-coupled, each inverter being formed by a pull-up transistor and a pull-down transistor stacked in the same active region along the vertical direction of the substrate. The plurality of active regions comprises at least two common regions shared by different static random access memory cells. Each transfer transistor group is formed by two transfer transistors stacked in the same common region along the vertical direction of the substrate, and the two transfer transistors in the same common region belong to different static random access memory cells. Thus, the coupled two static random access memory cells save 50% of the area.

Description

Static Random Access Memory Structure and Fabrication Method Technical Field

[0001] The embodiments in this application relate to the field of semiconductor device technology, and in particular to a static random access memory structure and its fabrication method. Background Technology

[0002] Static Random Access Memory (SRAM), as a key component of a chip, plays a crucial role in high-speed data storage, and its capacity significantly impacts the overall performance of the chip. Currently, the most widely used SRAM cell structure is a six-transistor (6T) configuration. However, this structure occupies a relatively large chip area in terms of physical layout, becoming a significant factor restricting chip integration and performance improvement.

[0003] Therefore, there is an urgent need for a static random access memory (SRAM) architecture that can effectively reduce the area occupied. Summary of the Invention

[0004] In view of this, several embodiments of this application aim to provide a static random access memory structure and its fabrication method, so that the two coupled static random access memory units can save 50% of the occupied area.

[0005] One embodiment of this application provides a static random access memory (SRAM) structure, comprising: a substrate; an isolation structure defining a plurality of active regions on the substrate; at least two SRAM cells sharing a word line, including at least two inverter groups and at least two transfer transistor groups; wherein each inverter group includes two cross-coupled inverters, each inverter being formed by stacking pull-up transistors and pull-down transistors in the same active region along the vertical direction of the substrate; the at least two transfer transistor groups are located between the at least two inverter groups; the plurality of active regions include at least two common regions shared by different SRAM cells; wherein each transfer transistor group is formed by stacking two transfer transistors in the same common region along the vertical direction of the substrate, and the two transfer transistors located in the same common region belong to different SRAM cells.

[0006] Optionally, each inverter and each transmission transistor group includes at least two channel doped layers arranged in a vertical direction along the substrate, and a common gate passing through the at least two channel doped layers in a vertical direction along the substrate; wherein the at least two channel doped layers and the common gate respectively form two transmission transistors in the transmission transistor group or a pull-up transistor and a pull-down transistor in the inverter.

[0007] Optionally, the at least two static random access memory (SRAM) cells include a first SRAM cell and a second SRAM cell; the at least two common regions include a first common region and a second common region; the two transfer transistor groups include a first transfer transistor group located in the first common region and a second transfer transistor group located in the second common region; wherein, the first transfer transistor group includes a first transfer transistor belonging to the first SRAM cell and a second transfer transistor belonging to the second SRAM cell; the first transfer transistor is stacked on the second transfer transistor; the second transfer transistor group includes a third transfer transistor belonging to the first SRAM cell and a fourth transfer transistor belonging to the second SRAM cell; the third transfer transistor is stacked on the fourth transfer transistor.

[0008] Optionally, the isolation structure includes a first isolation layer located between the inverter group and the transmission transistor group, and a second isolation layer located between the first transmission transistor group and the second transmission transistor group, the second isolation layer extending between different inverters in the inverter group; wherein the first transmission transistor group and the second transmission transistor group, as well as the different inverters in the inverter group, are all arranged symmetrically with respect to the second isolation layer.

[0009] Optionally, in each of the inverters, the pull-up transistor includes a first number of channel doped layers, and the pull-down transistor includes a second number of channel doped layers; in each group of transmission transistors, the transmission transistor includes a third number of channel doped layers; wherein the first number is less than the third number, and the third number is less than the second number.

[0010] Optionally, the sum of the first quantity and the second quantity is equal to twice the third quantity.

[0011] Optionally, in each of the inverters, the pull-up transistor includes a single channel doped layer, and the pull-down transistor includes three channel doped layers; in each group of transmission transistors, each transmission transistor includes two channel doped layers.

[0012] Optionally, each channel doped layer forms source and drain regions on both sides of the common gate; a contact structure is formed on the surface of the common gate and the source and drain regions; wherein multiple source and drain regions located in different channel doped layers and constituting the same transistor share a common contact structure; the common contact structure is in contact with the sidewall of at least one source and drain region.

[0013] Another embodiment of this application provides a method for fabricating a static random access memory (SRAM) structure. The method includes: providing a substrate; the substrate includes a subfloor, the substrate having a plurality of device regions formed thereon, with a first isolation layer separating adjacent device regions; wherein at least two initial channel doped layers stacked along the vertical direction of the substrate are formed on the device regions; etching the at least two initial channel doped layers in each device region to obtain at least two transition channel doped layers, and performing ion implantation on each transition channel doped layer to form source / drain regions; forming an initial common gate between the source / drain regions of each transition channel doped layer in the device region; etching the initial common gate to form a trench extending along the arrangement direction of the device regions, and forming a second isolation layer in the trench. The first isolation layer and the second isolation layer divide the plurality of devices into different active regions; at least two channel doped layers and a common gate are formed on the different active regions; wherein, the at least two channel doped layers in each active region form two transistors with the common gate; in at least four active regions, two transistors formed in the same active region serve as pull-up transistors and pull-down transistors in an inverter; at least two inverter groups are formed in the at least four active regions; in at least two active regions, two transistors formed in the same active region serve as transfer transistors belonging to different static random access memory (SRAM) cells; the at least two active regions serve as at least two common regions shared by different SRAM cells.

[0014] Optionally, the two active regions corresponding to the inverter group are located within the same device region; the at least two initial channel doped layers formed on the device region include a first type doped layer at the bottom and multiple second type initial doped layers stacked on the first type doped layer; in the step of etching the at least two initial channel doped layers in each device region to obtain at least two transition channel doped layers, and performing ion implantation on each transition channel doped layer to form source / drain regions, the process of etching and ion implanting the at least two initial channel doped layers on the device region corresponding to the inverter group includes: using photolithography and etching processes, sequentially etching each second type initial doped layer to form multiple second type doped layers located on both sides of the etching opening; the multiple second type doped layers and the first type doped layer constitute the at least two transition channels. A doped layer; wherein each second-type doped layer is covered with an oxide layer for isolation, and each second-type doped layer has an exposed end; the end is close to the etched opening and protrudes from the corresponding oxide layer along the extension direction of the first isolation layer; a first protective layer is filled at the bottom of the etched opening so that the first protective layer is flush with the height of the second-type doped layer at the bottom of the multilayer second-type doped layer; second-type ion implantation is performed on the end of each second-type doped layer to form source / drain regions in the multilayer second-type doped layer; the first protective layer is removed to expose a portion of the first-type doped layer; a second protective layer is formed on the multilayer second-type doped layer, and first-type ion implantation is performed on a portion of the first-type doped layer to form source / drain regions in the first-type doped layer.

[0015] The unexpected effect of the various embodiments provided in this application is that by stacking pull-up transistors and pull-down transistors vertically along the substrate in different active regions to form at least two inverter groups belonging to different static random access memory (SRAM) cells, and stacking two transfer transistors belonging to different SRAM cells vertically along the substrate in at least two common regions shared by different SRAM cells to form at least two transfer transistor groups, the two coupled SRAM cells in the SRAM structure occupy only the area of ​​six transistors (6T), saving 50% of the area. Attached Figure Description

[0016] Figures 1 and 2 are circuit diagrams of static random access memory (SRAM) cells in related technologies.

[0017] Figure 3 is a schematic diagram of the layout corresponding to Figure 2.

[0018] Figure 4 is a schematic diagram of the substrate provided in the method for fabricating a static random access memory structure according to an embodiment of this application.

[0019] Figure 5 is a schematic diagram of the preparation method of a static random access memory structure provided in an embodiment of this application, in which at least two transition channel doped layers and source / drain regions are formed.

[0020] Figures 6 to 10 are schematic diagrams of etching the second type of initial doped layers in a method for fabricating a static random access memory structure according to an embodiment of this application.

[0021] Figure 11 is a schematic diagram of the formation of the first protective layer in a method for preparing a static random access memory structure according to an embodiment of this application.

[0022] Figure 12 is a schematic diagram of the first type of ion implantation in the fabrication method of a static random access memory structure provided in an embodiment of this application.

[0023] Figure 13 is a schematic diagram of the formation of the second protective layer in the preparation method of the static random access memory structure provided in an embodiment of this application.

[0024] Figure 14 is a schematic diagram of the second type of ion implantation in the fabrication method of a static random access memory structure provided in an embodiment of this application.

[0025] Figure 15 is a schematic diagram of ion implantation in a method for fabricating a static random access memory structure according to another embodiment of this application.

[0026] Figure 16 is a schematic diagram of the oxide filling process in the fabrication method of a static random access memory structure provided in an embodiment of this application.

[0027] Figure 17 is a schematic diagram of the formation of the initial common gate in a method for fabricating a static random access memory structure according to an embodiment of this application.

[0028] Figure 18 is a schematic diagram of etching the initial common gate in a method for fabricating a static random access memory structure according to an embodiment of this application.

[0029] Figure 19 is a schematic diagram of the formation of the second isolation layer in a method for fabricating a static random access memory structure according to an embodiment of this application.

[0030] Figure 20 is a schematic diagram of the formation of a contact structure in a method for preparing a static random access memory structure according to an embodiment of this application.

[0031] Figure 21 is a schematic diagram of the static random access memory structure being formed in a method for preparing a static random access memory structure according to an embodiment of this application.

[0032] Figures 22 and 23 are schematic diagrams of the common contact structure in a static random access memory structure provided in another embodiment of this application.

[0033] Explanation of reference numerals in the attached figures:

[0034] 100. Static Random Access Memory (SRAM) structure; 102. Isolation structure; 103. Active region; 104. At least two common regions; 160. Channel doped layer; 170. Common gate; 1041. First common region; 1042. Second common region; 1021. First isolation layer; 1022. Second isolation layer; 1601. Source / drain region; 180. Contact structure; 181. Common contact structure; 210. Substrate; 211. Device region; 220. 1. At least two initial channel doped layers; 230. At least two transition channel doped layers; 240. Initial common gate; 250. Trench; 2201. First type doped layer; 2202. Second type initial doped layer; 310. Etched opening; 320. Second type doped layer; 330. Oxide layer; 3201. End; 340. First protective layer; 350. Second protective layer; aa. Extension direction of the first isolation layer; bb. Arrangement direction of the device region. Detailed Implementation

[0035] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0036] In this application, the accompanying drawings are not necessarily drawn to scale, and local features may be enlarged or reduced to more clearly show the details of the local features.

[0037] Unless otherwise stated, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in embodiments of this application are also intended to include the plural forms unless the context clearly indicates otherwise.

[0038] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0039] In the description of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. In other words, they should not be construed as limitations on this application.

[0040] In the description of this application, unless otherwise expressly defined, the terms "installation," "connection," "linking," "fixing," "setting," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can also refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0041] Static Random Access Memory (SRAM) is a core storage unit in modern integrated circuits, especially in high-performance processors, System-on-a-Chip (SoC), and caches. Its core value lies in its ability to achieve fast and stable data access without dynamic refresh (i.e., its "static" characteristic), providing the processor with real-time access capabilities. Currently, in chip designs pursuing higher computing power, integrating larger capacity SRAM cells has become a key means to improve chip performance.

[0042] As shown in Figures 1 to 3, current mainstream SRAM cells generally adopt a six-transistor (6T) structure, which specifically includes two cross-coupled inverters for data storage and two transfer transistors for read and write access. For example, in Figure 1, M1 and M2 form one inverter, M3 and M4 form another inverter, M5 and M6 are transfer transistors, and WL is the word line, BL, ... These are bit lines and complementary bit lines, Q, This is a storage node. In Figures 2 and 3, pull-up transistor PUL and pull-down transistor PDL form an inverter, pull-up transistor PUR and pull-down transistor PDR form another inverter, PGL and PGR are transfer transistors, and WL is the word line, BL, ... These are the bit line and the complementary bit line, respectively, and A and B represent memory nodes.

[0043] However, these SRAM cell structures require a large silicon area in terms of physical layout. For example, a typical 6T SRAM cell usually requires at least about 120F. 2 Up to 140F 2 The area (F is the feature size of the process) limits the total capacity of SRAM cells that can be integrated within a given chip size, thus restricting improvements in chip performance.

[0044] Therefore, there is an urgent need for a static random access memory (SRAM) architecture that can effectively reduce the area occupied.

[0045] Please refer to Figures 4 to 21. One embodiment of this application provides a method for fabricating a static random access memory (SRAM) structure. The fabrication method includes the following steps.

[0046] S110: Provides a substrate.

[0047] In this embodiment, as shown in FIG4, the substrate 210 includes a substrate and a first isolation layer 1021. The substrate has multiple device regions 211 formed thereon, which are independent of each other. The gaps between adjacent device regions 211 can be filled with the first isolation layer 1021 for isolation. The first isolation layer 1021 can be made of an insulating material, such as silicon dioxide. It should be noted that, for ease of distinguishing between the multiple different device regions 211, the first isolation layer 1021 filling the gaps between the device regions 211 is not shown in FIG4.

[0048] In this embodiment, at least two initial channel doped layers 220 stacked along the vertical direction of the substrate are formed on each device region 211, and adjacent initial channel doped layers are electrically isolated by an insulating material. Specifically, the initial channel doped layers can be formed by ion implantation into the Si layer. Depending on the type of implanted ions, the initial channel doped layers can have different doping types. For example, in the at least two initial channel doped layers 220 shown in FIG. 4, the initial channel doped layer relatively close to the substrate can be N-type doped, and the three initial channel doped layers stacked on the N-type doped initial channel doped layer can be P-type doped.

[0049] In some embodiments, the number of stacked layers of the initial channel doped layer can be flexibly set according to actual needs, such as two layers, three layers, six layers, etc., ensuring that at least two layers are set.

[0050] In this embodiment, referring to FIG4, the step of providing the substrate may include: sequentially and alternately depositing an OX / Si / OX / Si / OX / Si / OX stack on the substrate, where OX is an oxide. The Si layers may be ion implanted to form at least two initial channel doped layers 220. Then, the stack formed on the substrate is etched to distinguish different device regions 211. Finally, the etch gaps between the device regions 211 are filled with oxide to form a first isolation layer 1021, resulting in the substrate 210.

[0051] S120: Etch at least two initial channel doped layers in each device region to obtain at least two transition channel doped layers, and perform ion implantation on each transition channel doped layer to form source / drain regions.

[0052] In this embodiment, referring to Figures 4 and 5, at least two initial channel doped layers 220 in each device region 211 are etched to form at least two transition channel doped layers 230. Specifically, along the extension direction aa of the first isolation layer, each initial channel doped layer may include edge portions located on both sides and a main body portion located between the edge portions. The widths of the edge portions and the main body portions of each initial channel doped layer in the extension direction aa of the first isolation layer may be different. In this embodiment, etching may be performed only to the surface of the initial channel doped layer located at the bottom layer. In the formed at least two transition channel doped layers 230, the main bodies of the other three initial channel doped layers may be etched away, and the remaining edge portions on both sides serve as transition channel doped layers. It is understood that since the widths of the edge portions and the main bodies of each initial channel doped layer may be different, the step of etching at least two initial channel doped layers 220 in this embodiment may include multiple etching processes.

[0053] In some embodiments, the etching of at least two initial channel doped layers 220 may also remove the main body of the initial channel doped layer located at the bottom layer, that is, etching down to the oxide surface between the bottom initial channel doped layer and the substrate.

[0054] In this embodiment, after the main body of each initial channel doped layer is etched away, the remaining two side edges can form a symmetrical structure in the extension direction aa of the first isolation layer.

[0055] In this embodiment, as shown in FIG5, the width of each transition channel doped layer in the extension direction aa of the first isolation layer can decrease sequentially along the stacking direction. That is, any transition channel doped layer has a protruding portion in the extension direction aa of the first isolation layer relative to the transition channel doped layer above it. This portion serves as an ion implantation region, facilitating subsequent ion implantation to form source / drain regions.

[0056] In this embodiment, corresponding types of ions can be implanted into the ion implantation regions of each transition channel doped layer to form source / drain regions. For example, P-type ions, such as B ions, can be implanted into the ion implantation region of the bottom transition channel doped layer to serve as the source / drain regions of the PMOS. The other three layers can be implanted with N-type ions, such as P ions and As ions, to serve as the source / drain regions of the NMOS.

[0057] In some embodiments, among the multiple device regions, at least two are first target device regions for forming an inverter group, as shown in FIG4. The first target device region includes at least two initial channel doped layers 220, which may include a first type doped layer 2201 located at the bottom and multiple layers of second type initial doped layers 2202 stacked on the first type doped layer 2201. The first type doped layer 2201 may be an initial channel doped layer implanted with N-type ions in the Si layer, i.e., N-type doping, and the second type initial doped layer 2202 may be an initial channel doped layer implanted with P-type ions in the Si layer, i.e., P-type doping.

[0058] Referring to Figures 6 to 15. Figures 6 to 15 are schematic diagrams of the cross-sectional changes of the first target device region along the extension direction aa of the first isolation layer in step S120. As shown in Figures 6 to 15, in the step of etching at least two initial channel doped layers in each device region to obtain at least two transition channel doped layers, and performing ion implantation on each transition channel doped layer to form source / drain regions, the process of etching and ion implanting at least two initial channel doped layers on the first target device region may include:

[0059] S1201: Using photolithography and etching processes, each type II initial doped layer is etched sequentially to form a multilayer type II doped layer located on both sides of the etching opening.

[0060] In some embodiments, as shown in Figures 6 to 10, the etching of each second-type initial doped layer 2202 can be performed in multiple stages, with each etching targeting one second-type initial doped layer 2202 and stopping at the surface of the first-type doped layer 2201. As previously described, the main body of the multiple second-type initial doped layers 2202 can be etched away, forming etching openings 310. The remaining edge portions on both sides can serve as second-type doped layers 320. The multiple second-type doped layers 320 and the first-type doped layers 2201 constitute at least two transition channel doped layers 230. Each second-type doped layer 320 is covered with an oxide layer 330 for isolation.

[0061] In some embodiments, as shown in FIG10, each second type doped layer 320 has an exposed end 3201. The end 3201 is close to the etch opening 310 and protrudes from the corresponding oxide layer 330 along the first isolation layer extension direction aa.

[0062] S1202: Fill the bottom of the etched opening with a first protective layer so that the first protective layer is flush with the height of the second type doped layer located at the bottom layer in the multilayer second type doped layer.

[0063] In this embodiment, as shown in FIG11, a first protective layer 340 is formed at the bottom of the etched opening 310 using bottom self-filling to protect the exposed first type doped layer 2201 during ion implantation. Specifically, the first protective layer 340 can be made of photoresist or an insulating material such as silicon dioxide. The first protective layer 340 can be flush with the bottommost second type doped layer 320.

[0064] S1203: Perform first-type ion implantation at the end of each second-type doped layer to form source / drain regions in the multilayer second-type doped layers.

[0065] In some embodiments, as shown in FIG12, since only the ends 3201 of each second type doped layer 320 are exposed in the structure of FIG11, it is not necessary to set a photoresist, and the ends 3201 of each second type doped layer 320 can be directly implanted with the first type of ion, i.e., N-type ion implantation, to form the source / drain region 1601 shown in FIG12.

[0066] S1204: Remove the first protective layer.

[0067] Specifically, the first protective layer 340 is removed, exposing a portion of the first type doped layer 2201, which can then be ion implanted.

[0068] S1205: A second protective layer is formed on a multilayer second-type doped layer, and second-type ion implantation is performed on a portion of the first-type doped layer to form source / drain regions in the first-type doped layer.

[0069] In some embodiments, as shown in FIG13, a second protective layer 350 covering multiple layers of second type doped layers 320 is provided to protect the source / drain region 1601 that has been ion implanted in S1203, and second type ion implantation, i.e. P-type ion implantation, is performed on the exposed portion of the first type doped layer 2201 to form the source / drain region 1601 as shown in FIG14.

[0070] In some embodiments, etching of the multilayer initial channel doped layer and ion implantation of the source / drain regions are performed through steps S1201 to S1205. Only three photolithography steps are required to complete the fabrication of the multilayer stepped source / drain regions, which can reduce the process cost to a certain extent.

[0071] It should be noted that step S120 also targets a second target device region among multiple device regions used to form a transmission transistor group, as shown in Figure 4, which is located between two first target device regions. Each initial channel doped layer on the second target device region is of the second type of doping. In this embodiment, the etching and ion implantation process for at least two initial channel doped layers on the second target device region can be performed simultaneously with steps S1201 to S1203 described above. The difference is that, since the doping type of each initial channel doped layer is the same, the type of ions implanted to form the source / drain regions is also the same. It is not necessary to perform different types of ion implantation in separate steps; a single ion implantation is sufficient. Therefore, step S1202 is not required, and N-type ion implantation is performed directly through step S1203, as shown in Figure 15, to form the source / drain regions 1601 of each initial channel doped layer.

[0072] S130: An initial common gate is formed between the source and drain regions of each transition channel doped layer in the device region.

[0073] In this embodiment, as shown in Figures 16 and 17, oxide is first filled into the etched openings 310 formed in each device region, and then etched down to the surface of the lowest oxide layer in contact with the substrate, forming deep holes between the source and drain regions of each transition channel doped layer. The deep holes can be square, circular, or other shapes. Gate oxide and gate material are then deposited and filled into the deep holes to form the initial common gate 240. Excess material or thin layers formed in the peripheral regions during deposition can be removed using a CMP process.

[0074] S140: Etch the initial common gate to form a trench extending along the arrangement direction of the device region, and form a second isolation layer in the trench.

[0075] In this embodiment, as shown in Figures 18 and 19, and referring to Figure 17, trenches 250 extending along the arrangement direction bb of the device region can be formed by trench etching. In the vertical direction of the substrate, the trenches 250 can penetrate the initial common gate 240 and the first type doped layer 2201. Then, oxide is filled within the trenches 250 to form a second isolation layer 1022, achieving electrical isolation between different regions.

[0076] In this embodiment, the second isolation layer 1022 can divide the device region 211 into different active regions 103. After the initial common gate 240 is separated by the second isolation layer 1022, a common gate 170 belonging to two different active regions 103 is formed. In the different active regions 103, the remaining transition channel doped layers after etching in steps S130 and S140 are respectively used as channel doped layers 160 stacked in the vertical direction of the substrate. At least two channel doped layers 160 are formed in each active region 103, and the common gate 170 can be shared by at least two channel doped layers 160 to form at least two stacked transistors.

[0077] In this embodiment, the second isolation layer 1022 can work together with the first isolation layer 1021 to serve as an isolation structure 102 between different active regions 103 in the static random access memory structure.

[0078] In this embodiment, at least two channel doped layers 160 in each active region 103 form two stacked transistors with the common gate 170.

[0079] In this embodiment, within at least four active regions, two transistors formed in the same active region serve as pull-up and pull-down transistors in an inverter, respectively. Specifically, as shown in FIG19, along the arrangement direction bb of the device region, in the four active regions 103 located on both sides, the four channel doped layers 160 formed in the same active region 103 each include one N-type doped channel doped layer 160 and three P-type doped channel doped layers 160. The N-type doped channel doped layer 160 has P-type doped source / drain regions formed on both sides of the common gate 170, which can form a PMOS with the common gate 170 as a pull-up transistor. In the three P-type doped channel doped layers 160, each layer has N-type doped source / drain regions formed on both sides of the common gate 170, which can form a multi-channel NMOS with the common gate 170 as a pull-down transistor. It is understood that at least two inverter groups can be formed within at least four active regions 103, and the two active regions 103 corresponding to one inverter group are located in the same device region.

[0080] In this embodiment, within at least two active regions, two transistors formed in the same active region serve as transfer transistors belonging to different static random access memory (SRAM) cells. Specifically, as shown in FIG19, along the arrangement direction bb of the device regions, the two active regions in the middle serve as at least two common regions 104 shared by different SRAM cells, including a first common region 1041 and a second common region 1042. The four channel doped layers 160 formed therein are all P-type doped channel doped layers 160. Each layer has N-type doped source and drain regions located on both sides of the common gate 170. Therefore, the four channel doped layers 160 and the common gate 170 can respectively form two dual-channel NMOS, serving as two transfer transistors belonging to different SRAM cells.

[0081] S150: A contact structure is formed on the common gate and source / drain regions, and metal interconnects are made to form a static random access memory structure.

[0082] In this embodiment, as shown in FIG20, contact structures 180 are formed on each common gate 170 and source / drain region through CT (Contact) etching and metal deposition. It should be noted that, for ease of understanding and explanation, the first isolation layer 1021 and the second isolation layer 1022 are not shown in FIG20. Next, as shown in FIG21, the contact structures 180 on each common gate 170 and source / drain region are interconnected with metal to form a static random access memory (SRAM) structure 100. The SRAM structure 100 includes at least two SRAM cells, such as the two adjacent SRAM cells sharing a word line shown in FIG21 (FIG21 only shows the metal interconnection of one SRAM cell).

[0083] An unexpected effect of this embodiment is that by stacking pull-up transistors and pull-down transistors vertically along the substrate in different active regions to form at least two inverter groups belonging to different static random access memory (SRAM) cells, and stacking two transfer transistors belonging to different SRAM cells vertically along the substrate in at least two common regions shared by different SRAM cells to form at least two transfer transistor groups, the two coupled SRAM cells in the SRAM structure occupy only the area of ​​six transistors (6T), saving 50% of the area.

[0084] Please refer to Figure 21 and Figure 20 for further information. Figure 21 corresponds to the circuit schematic shown in Figure 1. Another embodiment of this application provides a static random access memory (SRAM) structure 100, including a substrate, an isolation structure, and at least two SRAM cells. The isolation structure defines multiple active regions on the substrate. In this embodiment, the SRAM structure 100 can be fabricated using the fabrication method for the SRAM structure provided in the foregoing embodiments. Therefore, the relevant descriptions and explanations of the SRAM structure 100 and its components can be found in the foregoing embodiments, and the same content will not be repeated here.

[0085] In this embodiment, the static random access memory (SRAM) structure 100 may include at least two SRAM cells sharing a word line. Since a 6T SRAM cell may include two cross-coupled inverters (i.e., an inverter group) and two transfer transistors (i.e., a transfer transistor group), it is understood that at least two SRAM cells may include at least two inverter groups and at least two transfer transistor groups. In this embodiment, the at least two transfer transistor groups may be located between the at least two inverter groups to facilitate metal interconnection.

[0086] In this embodiment, in the same inverter group, each inverter is formed by stacking pull-up transistors and pull-down transistors in the same active region along the vertical direction of the substrate.

[0087] In this embodiment, the multiple active regions include at least two common regions 104 shared by different static random access memory (SRAM) cells. Each transfer transistor group is formed by stacking two transfer transistors in the same common region along the vertical direction of the substrate, and the two transfer transistors located in the same common region belong to different SRAM cells.

[0088] Specifically, each inverter and each transfer transistor group includes at least two channel doped layers 160 arranged vertically along the substrate, and a common gate 170 extending through the at least two channel doped layers 160 vertically along the substrate. The at least two channel doped layers 160 and the common gate 170 respectively form two transfer transistors in the transfer transistor group or a pull-up transistor and a pull-down transistor in the inverter.

[0089] As shown in Figure 21, the static random access memory (SRAM) structure 100 may include a first SRAM cell and a second SRAM cell. The first SRAM cell includes transistors M1 to M6, and the second SRAM cell includes transistors M1' to M6' (M2' and M5' are not shown due to the viewing angle in Figure 21).

[0090] In the first static random access memory (SRAM) cell, M1 and M3 serve as pull-down transistors, and M2 and M4 serve as pull-up transistors. M1 and M2 include at least two channel doped layers 160 (shown as L1 to L4 in FIG. 21) stacked vertically on the same active region 103, and share a common gate 170 to form an inverter. Similarly, M3 and M4 form another inverter. In the second SRAM cell, M1' and M3' serve as pull-down transistors, and M2' and M4' serve as pull-up transistors. M1' and M2' also include at least two channel doped layers 160 stacked vertically on the same active region, and share a common gate 170 to form an inverter. Similarly, M3' and M4' form another inverter.

[0091] In some embodiments, at least two common regions 104 include a first common region 1041 and a second common region 1042. Two transmission transistor groups include a first transmission transistor group located in the first common region 1041 and a second transmission transistor group located in the second common region 1042.

[0092] The first transmission transistor group includes a first transmission transistor belonging to a first static random access memory (SRAM) cell and a second transmission transistor belonging to a second SRAM cell, with the first transmission transistor stacked on top of the second transmission transistor. The second transmission transistor group includes a third transmission transistor belonging to the first SRAM cell and a fourth transmission transistor belonging to the second SRAM cell, with the third transmission transistor stacked on top of the fourth transmission transistor.

[0093] Specifically, as shown in Figure 21, in the first static random access memory (SRAM) cell, M5 and M6 serve as the first and third transfer transistors, respectively, located in the first common region 1041 and the second common region 1042. In the second SRAM cell, M5' and M6' serve as the second and fourth transfer transistors, respectively, located in the first common region 1041 and the second common region 1042. M5 and M5' are stacked vertically in the first common region 1041 and share a common gate 170, forming a first transfer transistor group. Similarly, transfer transistors M6 and M6' form a second transfer transistor group. The common gate 170 shared by M5 and M5' and the common gate 170 shared by M6 and M6' can be connected to the same word line, allowing the first and second SRAM cells to share a word line.

[0094] An unexpected effect is that by stacking pull-up transistors and pull-down transistors vertically along the substrate in different active regions to form at least two inverter groups belonging to different static random access memory (SRAM) cells, and stacking two transfer transistors belonging to different SRAM cells vertically along the substrate in at least two common regions shared by different SRAM cells to form at least two transfer transistor groups, the two coupled SRAM cells in the SRAM structure occupy only the area of ​​six transistors (6T), saving 50% of the area.

[0095] In some embodiments, the isolation structure includes a first isolation layer located between an inverter group and a transmission transistor group, and a second isolation layer located between the first transmission transistor group and a second transmission transistor group, the second isolation layer extending between different inverters in the inverter group. The first transmission transistor group and the second transmission transistor group, as well as the different inverters in the inverter group, are all arranged symmetrically with respect to the second isolation layer.

[0096] It should be noted that, in the static random access memory structure 100 shown in Figure 21, for ease of distinction and understanding, the isolation structure filled between different active regions is not shown. The first isolation layer is actually filled in the gap between the inverter group and the transmission transistor group, and the second isolation layer is actually filled between different inverters and different transmission transistor groups. For details, please refer to Figure 19. The first isolation layer and the second isolation layer extend in different directions.

[0097] In some embodiments, transistors in a static random access memory (SRAM) structure can be arranged in a symmetrical layout to improve transistor performance matching within the SRAM cells.

[0098] In some embodiments, in each inverter, the pull-up transistor includes a first number of channel doped layers, and the pull-down transistor includes a second number of channel doped layers. In each group of transfer transistors, the transfer transistor includes a third number of channel doped layers. The first number is less than the third number, and the third number is less than the second number.

[0099] In some embodiments, since the more channel doped layers stacked on the same transistor, the greater the width-to-length ratio of its channel, different numbers of channel doped layers can be set according to the different performance requirements of different transistors in the static random access memory structure. That is, in the static random access memory structure, each transistor includes a number of channel doped layers that match its own performance requirements.

[0100] Specifically, in a static random access memory (SRAM) cell, the pull-down transistor can have the largest number of stacked channel doped layers, resulting in a large aspect ratio for the channel. This facilitates rapid discharge from ground during reads, significantly increasing the read speed of the SRAM cell. The pass transistor can have a medium number of stacked channel doped layers, resulting in a channel aspect ratio slightly lower than that of the pull-down transistor, which helps increase switching speed. The pull-up transistor can have the smallest number of channel doped layers, resulting in a minimal aspect ratio for the channel. It serves only for data retention and does not affect read speed. Thus, the SRAM structure can significantly improve read speed without increasing area.

[0101] In some embodiments, the sum of the first quantity and the second quantity is equal to twice the third quantity.

[0102] Specifically, when the number of channel doped layers of the pull-up and pull-down transistors in each inverter is twice the number of channel doped layers of each transmission transistor, the total number of stacked layers of each inverter group can be the same as the total number of stacked layers of the transmission transistor group. This makes the transistor stacking height on each active region consistent, which helps to improve the performance matching of transistors and facilitates subsequent processes.

[0103] Optionally, in each inverter, the pull-up transistor includes a single-layer channel doped layer, and the pull-down transistor includes three-layer channel doped layers. In each group of transfer transistors, each transfer transistor includes two layers of channel doped layers.

[0104] Specifically, as shown in Figure 21, taking the first static random access memory (SRAM) as an example, M1 and M3 have three stacked channel doped layers, namely L2, L3, and L4 in Figure 21; M2 and M4 have one channel doped layer 160, namely L1 in Figure 21; and M5 and M6 have two stacked channel doped layers 160. Furthermore, in some embodiments, the channel width-to-length ratio of each transistor can be further adjusted by controlling the thickness of each channel doped layer, thereby regulating the performance of the SRAM structure. For example, referring to Figure 21, if the thickness of each channel doped layer 160 satisfies L4=L2=xL3=xL1, then the channel width-to-length ratio of each transistor can satisfy M1 / M3:M5 / M6:M2 / M4=2x+1:x+1:1.

[0105] In some embodiments, each channel doped layer has source / drain regions formed on both sides of a common gate. Contact structures are formed on the surfaces of the common gate and the source / drain regions. Multiple source / drain regions located in different channel doped layers and constituting the same transistor share a common contact structure. The common contact structure contacts the sidewall of at least one source / drain region.

[0106] Specifically, referring to Figures 22 and 23, Figure 22 is a cross-sectional schematic diagram of the contact structure for M1, M2, M3, M4 or M1', M2', M3', M4', and Figure 23 is a cross-sectional schematic diagram of the contact structure for M5, M6, M5', M6'. As shown in Figure 22, the source / drain regions 1601 of M1 / M1' and M3 / M3' each share a common contact structure 181. The common contact structure 181 contacts the sidewalls of the source / drain regions 1601 of L4 and L3, which can effectively reduce contact resistance and reduce power consumption. Similarly, in Figure 23, the source / drain regions 1601 of M5, M6, M5', and M6' each share a common contact structure 181, and the common contact structure 181 contacts the sidewalls of the source / drain regions 1601 located in the upper channel doped layer of M5, M6, M5', and M6'.

[0107] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of the invention.

[0108] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0109] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0110] It is understood that in the description of this application, when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it may mean that it is directly above another layer or region, or that it contains other layers or regions between itself and another layer or region. Furthermore, if the component is flipped, the layer or region will be located "below" or "under" another layer or region.

[0111] The above description is merely a specific embodiment of this application, but the protection scope of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the protection scope of this application.

Claims

1. A static random access memory (SRAM) structure, characterized in that, include: Substrate; An isolation structure that defines a plurality of active regions on the substrate; At least two static random access memory (SRAM) cells sharing a word line include at least two inverter groups and at least two transfer transistor groups; the at least two SRAM cells include a first SRAM cell and a second SRAM cell; wherein each inverter group includes two cross-coupled inverters, each inverter being formed by stacking pull-up transistors and pull-down transistors in the same active region along the vertical direction of the substrate; the at least two transfer transistor groups are located between the at least two inverter groups; each inverter and each transfer transistor group includes at least two channel doped layers arranged along the vertical direction of the substrate, and a common gate passing through the at least two channel doped layers along the vertical direction of the substrate; The at least two channel doped layers respectively form two transmission transistors in a transmission transistor group or a pull-up transistor and a pull-down transistor in an inverter with the common gate; in each inverter, the pull-up transistor includes a first number of channel doped layers, and the pull-down transistor includes a second number of channel doped layers; in each transmission transistor group, the transmission transistor includes a third number of channel doped layers; the first number is less than the third number, and the third number is less than the second number; the sum of the first number and the second number is equal to twice the third number; the thickness of each channel doped layer is used as an adjustment parameter for the channel width-to-length ratio of each transistor; the plurality of active regions include different static... At least two common regions shared by random access memory (RAM) cells; wherein the at least two common regions include a first common region and a second common region; each transfer transistor group is formed by stacking two transfer transistors in the same common region along the vertical direction of the substrate, and the two transfer transistors located in the same common region belong to different static random access memory (SRAM) cells; the two transfer transistor groups include a first transfer transistor group located in the first common region and a second transfer transistor group located in the second common region; the first transfer transistor group includes a first transfer transistor belonging to a first SRAM cell and a second transfer transistor belonging to a second SRAM cell; the first transfer transistor... The transistors are stacked on the second transmission transistor; the second transmission transistor group includes a third transmission transistor belonging to a first static random access memory cell and a fourth transmission transistor belonging to a second static random access memory cell; the third transmission transistor is stacked on the fourth transmission transistor; the isolation structure includes a first isolation layer located between the inverter group and the transmission transistor group, and a second isolation layer located between the first transmission transistor group and the second transmission transistor group, the second isolation layer extending between different inverters in the inverter group; the first transmission transistor group and the second transmission transistor group, as well as the different inverters in the inverter group, are all arranged symmetrically with respect to the second isolation layer.

2. The static random access memory structure according to claim 1, characterized in that, In each of the inverters, the pull-up transistor includes a single channel doped layer, and the pull-down transistor includes three channel doped layers; in each group of transfer transistors, each transfer transistor includes two channel doped layers.

3. The static random access memory structure according to claim 1, characterized in that, Each channel doped layer forms source and drain regions on both sides of the common gate; a contact structure is formed on the surface of the common gate and the source and drain regions; wherein multiple source and drain regions located in different channel doped layers and constituting the same transistor share a common contact structure; the common contact structure is in contact with the sidewall of at least one source and drain region.

4. A method for fabricating a static random access memory (SRAM) structure, characterized in that, The fabrication method includes: providing a substrate; the substrate includes a substructure, the substrate having multiple device regions formed thereon, with a first isolation layer separating adjacent device regions; wherein at least two initial channel doped layers stacked along the vertical direction of the substrate are formed on the device regions; etching the at least two initial channel doped layers in each device region to obtain at least two transition channel doped layers, and performing ion implantation on each transition channel doped layer to form source / drain regions; forming an initial common gate between the source / drain regions of each transition channel doped layer in the device region; etching the initial common gate to form a trench extending along the arrangement direction of the device regions, and forming a second isolation layer in the trench; wherein the first isolation layer and the second isolation layer distinguish the multiple devices. The active regions are divided into different active regions; at least two channel doped layers and a common gate are formed on each active region; wherein, the at least two channel doped layers in each active region and the common gate respectively form two transistors; in at least four active regions, two transistors formed in the same active region respectively serve as pull-up transistors and pull-down transistors in an inverter; at least two inverter groups are formed in the at least four active regions; each inverter group includes two cross-coupled inverters; each inverter is formed by stacking the pull-up transistors and the pull-down transistors in the same active region along the vertical direction of the substrate; in at least two active regions, two transistors formed in the same active region respectively serve as transfer transistors belonging to different static random access memory cells, the formation of Two transistors in the same active region form a transfer transistor group; the different static random access memory (SRAM) cells include at least two transfer transistor groups; the at least two transfer transistor groups are located between the at least two inverter groups; the at least two active regions serve as at least two common regions shared by the different SRAM cells; each transfer transistor group is formed by stacking two transfer transistors in the same common region along the vertical direction of the substrate; the at least two common regions include a first common region and a second common region; the two transfer transistor groups include a first transfer transistor group located in the first common region and a second transfer transistor group located in the second common region; the first transfer transistor group and the second transfer transistor group... The transistor array, and the different inverters in the inverter array, are symmetrically arranged with respect to the second isolation layer; each inverter and each transmission transistor array includes at least two channel doped layers arranged vertically along the substrate, and a common gate extending through the at least two channel doped layers vertically along the substrate; the at least two channel doped layers and the common gate respectively form two transmission transistors in the transmission transistor array or a pull-up transistor and a pull-down transistor in the inverter; in each inverter, the pull-up transistor includes a first number of layers of the channel doped layer, and the pull-down transistor includes a second number of layers of the channel doped layer; in each transmission transistor array, the transmission transistor includes a third number of layers of the channel doped layer;Wherein, the first quantity is less than the third quantity, and the third quantity is less than the second quantity; the sum of the first quantity and the second quantity is equal to twice the third quantity; the thickness of each channel doped layer is used as an adjustment parameter for the channel width-to-length ratio of each transistor.

5. The preparation method according to claim 4, characterized in that, The two active regions corresponding to the inverter group are located within the same device region; the at least two initial channel doped layers formed on the device region include a first type doped layer at the bottom and multiple second type initial doped layers stacked on the first type doped layer; in the step of etching the at least two initial channel doped layers in each device region to obtain at least two transition channel doped layers, and performing ion implantation on each transition channel doped layer to form source / drain regions, the process of etching and ion implanting the at least two initial channel doped layers on the device region corresponding to the inverter group includes: using photolithography and etching processes, sequentially etching each second type initial doped layer to form multiple second type doped layers located on both sides of the etching opening; the multiple second type doped layers and the first type doped layer constitute the at least two transition channel doped layers. The system comprises: a layer; wherein each second-type doped layer is covered with an oxide layer for isolation, and each second-type doped layer has an exposed end; the end is close to the etched opening and protrudes from the corresponding oxide layer along the extension direction of the first isolation layer; a first protective layer is filled at the bottom of the etched opening so that the first protective layer is flush with the height of the second-type doped layer at the bottom of the multilayer second-type doped layer; second-type ion implantation is performed on the end of each second-type doped layer to form source / drain regions in the multilayer second-type doped layer; the first protective layer is removed to expose a portion of the first-type doped layer; a second protective layer is formed on the multilayer second-type doped layer, and first-type ion implantation is performed on a portion of the first-type doped layer to form source / drain regions in the first-type doped layer.

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