Method for testing semiconductor chip latch-up amplification factor

Abstract

This invention relates to a method for testing the latch-up amplification factor of semiconductor chips, and is connected to integrated circuit technology. The invention includes the following steps: (1) For a PMOS-NMOS structure, the source and substrate of the NMOS transistor are connected to GND, the source and well potential of the PMOS transistor are connected to a first external connection point, the first external connection point is connected to VCC, and the drain of the NMOS transistor and the drain of the PMOS transistor are connected to a second external connection point; (2) A current source is connected to the second external connection point; (3) The change in input current ΔI at the first external connection point is measured. VCC The latch-up amplification factor is calculated by the change in output current ΔIout at the second external connection point; (4) the input current at the first external connection point or the output current at the second external connection point is increased, and the process returns to step (3) until the chip burns out, thus obtaining the numerical curve of the amplification factor β in the current direction. This invention can provide accurate and comprehensive latch-up amplification factor data.

Description

Technical Field

[0001] This invention relates to integrated circuit technology. Background Technology

[0002] In the design and manufacturing of semiconductor integrated circuit products, preventing latch-up effects is an important safety consideration in circuit and layout design. Latch-ups can cause functional abnormalities in chips during testing and use, and may even burn out the chip.

[0003] A typical example is in synchronous buck DC / DC products, where both PMOS and NMOS are present in the power stage. This often results in the classic latch-up structure being unavoidable in parasitic configurations.

[0004] In this situation, according to the layout design rules given by FAB, it is impossible to completely avoid latch-up during chip operation.

[0005] The circuit structure of a synchronous BUCK-DC / DC power stage is as follows: Figure 1 As shown.

[0006] Since the area of ​​power transistors is dominant, synchronous DC / DC devices inevitably have PMOS and NMOS transistors placed close to each other in their layout. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a method for testing the latch-up amplification factor of semiconductor chips, which can quantitatively prevent the risk of latch-up in new products.

[0008] The technical solution adopted by the present invention to solve the aforementioned technical problem is a method for testing the latch-up amplification factor of a semiconductor chip, characterized by comprising the following steps:

[0009] (1) For the adjacent PMOS-NMOS structure, the source terminal and substrate of the NMOS transistor are connected to GND, the source terminal and well potential of the PMOS transistor are connected to the first external connection point, the first external connection point is connected to VCC, and the drain terminal of the NMOS transistor and the drain terminal of the PMOS transistor are connected to the second external connection point; the adjacent PMOS-NMOS structure includes a PMOS transistor and an NMOS transistor, the PMOS transistor includes a gate region and a source region and a drain region disposed in the N-well; the N-well is embedded in the P-type doped region;

[0010] (2) Connect a current source at the second external connection point;

[0011] (3) Measure the change in input current ΔI at the first external connection point. VCC The output current change ΔIout at the second external connection point is used to calculate the latch-up amplification factor β using the following formula:

[0012] ß=△I VCC / △Iout

[0013] (4) Increase the input current of the first external connection point or the output current of the second external connection point, return to step (3) until the chip burns out, and obtain the numerical curve of the amplification factor β in the current direction.

[0014] It also includes step (5):

[0015] Change the current direction of the current source connected to the second external connection point, and then proceed to step (3).

[0016] Step (3) is: measuring the current change ΔI at the first external connection point. VCC The current change ΔIout at the second external connection point is used to calculate the latch-up amplification factor β using the following formula:

[0017] ß = △I VCC / △Iout

[0018] Step (4) is to increase the current of the first external connection point or the current of the second external connection point, return to step (3), until the chip burns out, and obtain the numerical curve of the amplification factor β in the current direction.

[0019] The beneficial effect of this invention is that it can provide accurate and comprehensive latch-up amplification data, thus providing protection against the risk of latch-up in chips. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the circuit structure of a synchronous BUCK-DC / DC power stage.

[0021] Figure 2 This is a schematic diagram of the actual parasitic structure in a semiconductor chip.

[0022] Figure 3 It is the equivalent circuit diagram of the actual parasitic structure in a semiconductor chip. Detailed Implementation

[0023] The actual parasitic structures in semiconductor chips, such as Figure 2 and Figure 3 As shown, this forms the positive feedback loop of a PNP-NPN amplifier. If there is a drain current at the Iout terminal, the be-base junction of the second transistor Q2 is turned on, and the amplifier formed by the second transistor Q2 and Rwell enters the amplification region. The current flowing through Rsub increases, and the base potential of the first transistor Q1 decreases, thereby causing the amplifier formed by the first transistor Q1 and Rsub to enter the amplification region.

[0024] If the power supply current is limited to prevent the chip from burning out, this effect will pull the power supply current to its full capacity. Without some current limiting, the chip will burn out directly.

[0025] Let the amplifier gain of the PNP and Rsub processes be β1, and the amplifier gain of the NPN and Rwell processes be β2. The gain of the latch-up structure can be considered as:

[0026] ß = ß1 * ß2 = △I VCC / △Iout

[0027] Therefore, the present invention provides a method for testing the latch-up amplification factor of a semiconductor chip, comprising the following steps:

[0028] (1) For the adjacent PMOS-NMOS structure, the source terminal and substrate of the NMOS transistor are connected to GND, the source terminal and well potential of the PMOS transistor are connected to the first external connection point, the first external connection point is connected to VCC, and the drain terminal of the NMOS transistor and the drain terminal of the PMOS transistor are connected to the second external connection point; the adjacent PMOS-NMOS structure includes a PMOS transistor and an NMOS transistor, the PMOS transistor includes a gate region and a source region and a drain region disposed in the N-well; the N-well is embedded in the P-type doped region;

[0029] (2) Connect a current source at the second external connection point;

[0030] (3) Measure the change in input current ΔI at the first external connection point. VCC The output current change ΔIout at the second external connection point is used to calculate the latch-up amplification factor β using the following formula:

[0031] ß=△I VCC / △Iout

[0032] (4) Increase the input current of the first external connection point or the output current of the second external connection point, return to step (3) until the chip burns out, and obtain the numerical curve of the amplification factor β in the current direction.

[0033] (5) Change the current direction of the current source connected to the second external connection point, and then proceed to step (3).

[0034] This invention employs a specific external connection relationship for chips with adjacent PMOS and NMOS structures, and measures the amplification factor data under two conditions: applied current extraction and applied current sinking, to generate curves.

[0035] Specific testing process:

[0036] 1. Based on Figure 2The connection relationship is shown in the figure. The power supply normally supplies power, and the current Iout is drawn at the OUT terminal. The change of ß is recorded until the chip is burned out.

[0037] 2、Based on Figure 2 The connection relationship is shown in the figure. The power supply normally supplies power, and the current Iout is drawn at the OUT terminal. The change of ß is recorded until the chip is burned out.

[0038] The change curve of ß when the current is drawn and the change curve of ß when the current is filled can be used as an important basis for evaluating the performance of the chip.

Claims

1. A method of testing the latch-up amplification factor of a semiconductor chip, characterized in that, The method comprises the following steps: (1) for the PMOS-NMOS structure, the source of the NMOS tube is connected with the ground, the source of the PMOS tube is connected with the first external connection point, the first external connection point is connected with VCC, the drain of the NMOS tube is connected with the drain of the PMOS tube, and the drain of the PMOS tube is connected with the second external connection point; the PMOS-NMOS structure comprises a PMOS tube and an NMOS tube, the PMOS tube comprises a gate region, a source region and a drain region arranged in an N-well, and the N-well is embedded in a P-type doped region; (2) connecting a current source at the second external connection point; (3) measuring the input current variation ΔIin of the first external connection point VCC and the output current variation ΔIout of the second external connection point, and calculating the latch-up amplification factor β by the following equation: ß = △I VCC / △Iout (4) increasing the input current of the first external connection point or the output current of the second external connection point, returning to step (3), until the chip is burned out, and obtaining the numerical curve of the amplification multiple ß of the current direction.

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