A chip edge placement error determination method, device, apparatus, and storage medium

Abstract

The application discloses a chip edge placement error determination method and device, equipment and a storage medium, and relates to the technical field of optical proximity correction, and comprises the following steps: performing pixelization processing on the photoresist pattern edge of a chip simulation to obtain a target pixel; encoding the target pixel by using a preset encoding mode to obtain target pixel encoding; adaptively evaluating the target pixel encoding, and selecting a first target pixel from the target pixel corresponding to the target pixel encoding; generating a first target pixel population based on the first target pixel, and outputting a target adaptive value of the first target pixel population; and adjusting the parameters of a PID controller by using the target adaptive value to determine the chip edge placement error. The photoresist pattern edge is subjected to pixelization processing, and a suitable adaptive value is selected based on the adaptability evaluation of the target pixel encoding, and then the target adaptive value is adjusted to the parameters of the PID controller, so that the chip edge placement error is determined simply and conveniently.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of optical proximity correction technology, and in particular to a chip edge placement error determination method, device, equipment and storage medium. BACKGROUND

[0002] Optical proximity effect correction (OPC) is one of the important techniques widely used in chip lithography to improve image fidelity and process robustness. It can be generally divided into rule-based optical proximity effect correction (RBOPC) and model-based optical proximity effect correction (MBOPC). RBOPC mainly uses the geometric properties of the current neighborhood to modify the features. However, the local modification of the adjacent imaging distortion is mutually coupled, and due to its non-iterative correction process, RBOPC is not competitive at technology nodes below 90nm. MBOPC uses mathematical models to represent the image formation process and iteratively finds the global optimum of the objective function to improve the imaging quality. MBOPC is further divided into edge-based OPC and pixel-based OPC. Edge-based OPC divides the polygons on the mask into edges and corners, and through the movement of these edges and corners from the original position, it reduces the imaging distortion. The goal of this movement is to make the target contour match the contour of the image on the wafer at the preset observation points. Each iteration of OPC requires the re-computation of the target contour and the contour of the image on the wafer at the preset observation points, which has a considerable time and space complexity. This makes it urgent to solve the problem of fast convergence of OPC. However, the polygon division and the selection of observation points significantly affect the convergence of OPC. At the same time, fixed division requires edges to cooperate with adjacent edges to modify local imaging distortion, which limits the optimization freedom in edge-based OPC. Pixel-based OPC discretizes the mask into pixels and optimizes their transmittance. Pixel-based OPC is a high-dimensional nonlinear constrained optimization problem. It has higher optimization freedom than edge-based OPC and has greater potential to achieve better imaging performance. Similarly, pixel-based OPC, while enjoying excellent optimization capabilities brought by rich freedom, also faces huge computational load.

[0003] In summary, how to simply and conveniently determine the chip edge placement error in the chip lithography process, and how to obtain the global optimal solution in the correction process of the image edge with a high probability, while taking into account the local control of the edge, are technical problems to be solved in the field. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a chip edge placement error determination method, device, equipment and storage medium, which can simply and conveniently determine the chip edge placement error in the chip lithography process, and can obtain the global optimal solution in the correction process of the image edge with a high probability, while taking into account the local control of the edge. The specific scheme is as follows:

[0005] In a first aspect, the application discloses a chip edge placement error determination method, comprising:

[0006] pixelating a photoresist pattern edge of a chip simulation to obtain a target pixel of the photoresist pattern edge;

[0007] encoding the target pixel by using a preset encoding mode to obtain a target pixel encoding;

[0008] adaptively evaluating the target pixel encoding and selecting a first target pixel corresponding to the target pixel encoding that meets a preset screening condition rule from the target pixel corresponding to the target pixel encoding;

[0009] generating a first target pixel population based on the first target pixel and outputting a target fitness value of the first target pixel population;

[0010] adjusting parameters of a PID controller by using the target fitness value to determine a chip edge placement error.

[0011] Optionally, the encoding the target pixel by using a preset encoding mode to obtain a target pixel encoding comprises:

[0012] encoding the target pixel by using Gray encoding, initializing the target pixel, and obtaining a target pixel encoding; wherein an iteration number of the initialization is zero.

[0013] Optionally, the adaptively evaluating the target pixel encoding comprises:

[0014] adaptively evaluating the target pixel encoding by using a preset evaluation function to obtain a fitness value of the target pixel encoding.

[0015] Optionally, the selecting a first target pixel corresponding to the target pixel encoding that meets a preset screening condition rule from the target pixel corresponding to the target pixel encoding comprises:

[0016] determining whether the fitness value of the target pixel encoding meets a preset fitness value, and if not, determining a maximum fitness value and a corresponding first target pixel from all the fitness values.

[0017] Optionally, the generating a first target pixel population based on the first target pixel and outputting a target fitness value of the first target pixel population comprises:

[0018] generating a first target pixel population based on the first target pixel, and selecting a target pixel to be crossed from the first target pixel population;

[0019] The to-be-mated target pixel is mated to generate a new target pixel;

[0020] A new target population is generated based on the new target pixel and first target pixels other than the to-be-mated target pixel, and a new target fitness value of the new target pixel population is output.

[0021] Optionally, the generating a first target pixel population based on the first target pixel and outputting a target fitness value of the first target pixel population comprises:

[0022] A first target pixel population is generated based on the first target pixel, and a to-be-mutated target pixel is selected from the first target pixel population;

[0023] The to-be-mated target pixel is mated to generate a new target pixel;

[0024] A new target population is generated based on the new target pixel and first target pixels other than the to-be-mutated target pixel, and a new target fitness value of the new target pixel population is output.

[0025] Optionally, the chip edge placement error determination method further comprises:

[0026] The number of operations of outputting the target fitness value of the first target pixel population is compared with a preset iteration number, and if the number of operations is less than the preset iteration number, the adaptive evaluation of the target pixel code is performed.

[0027] In a second aspect, the present application discloses a chip edge placement error determination device, comprising:

[0028] A first pixel acquisition module is configured to perform pixelization processing on a photoresist pattern edge of a chip simulation to obtain a target pixel of the photoresist pattern edge;

[0029] A pixel code module is configured to encode the target pixel using a preset encoding method to obtain a target pixel code;

[0030] A second pixel acquisition module is configured to adaptively evaluate the target pixel code and select a first target pixel corresponding to a target pixel code meeting a preset screening condition rule from target pixels corresponding to the target pixel code;

[0031] A population determination module is configured to generate a first target pixel population based on the first target pixel and output a target fitness value of the first target pixel population;

[0032] An error determination module is configured to adjust parameters of a PID controller using the target fitness value to determine a chip edge placement error.

[0033] In a third aspect, the present application discloses an electronic device, comprising:

[0034] a memory for storing a computer program;

[0035] a processor for executing the computer program to implement the steps of the chip edge placement error determination method disclosed above.

[0036] In a fourth aspect, the present application discloses a computer readable storage medium for storing a computer program; wherein the computer program is executed by a processor to implement the steps of the chip edge placement error determination method disclosed above.

[0037] It can be seen that the present application discloses a chip edge placement error determination method, comprising: pixelizing the edge of a photoresist pattern of a chip simulation to obtain a target pixel of the edge of the photoresist pattern; encoding the target pixel by using a preset encoding mode to obtain a target pixel code; adaptively evaluating the target pixel code and selecting a first target pixel corresponding to a target pixel code meeting a preset screening condition rule from the target pixel corresponding to the target pixel code; generating a first target pixel population based on the first target pixel and outputting a target fitness value of the first target pixel population; and adjusting parameters of a PID controller by using the target fitness value to determine a chip edge placement error. It can be seen that by pixelizing the edge of the photoresist pattern, the local properties of the imaged edge can be maximally utilized, the local control is good, and by selecting a suitable fitness value, i.e., a global optimal solution, based on the adaptive evaluation of the target pixel code, the global optimal solution is combined and applied to the parameter adjustment of the PID controller, so that the PID controller is applied to the optical proximity correction to simply and conveniently determine the chip edge placement error. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of the provided drawings.

[0039] Figure 1 A chip edge placement error determination method flowchart disclosed by the present application;

[0040] Figure 2 A specific chip edge placement error determination method flowchart disclosed by the present application;

[0041] Figure 3A flow chart of a PID controller parameter determination method based on a genetic algorithm is disclosed in the present application.

[0042] Figure 4 A chip edge placement error determination device structure schematic diagram is disclosed in the present application.

[0043] Figure 5 An electronic device structure diagram is disclosed in the present application. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0045] Optical proximity correction is one of the important techniques widely used in chip lithography to improve image fidelity and process robustness. It can be generally divided into rule-based optical proximity correction and model-based optical proximity correction. RBOPC mainly uses the geometric properties of the current neighborhood to modify the features. However, the local modification of the neighboring imaging distortion is mutually coupled, and due to its non-iterative correction process, RBOPC is not competitive at technology nodes below 90 nm. MBOPC uses mathematical models to represent the image formation process and iteratively finds the global optimum of the objective function to improve the imaging quality. MBOPC is further divided into edge-based OPC and pixel-based OPC. Edge-based OPC divides the polygons on the mask into edges and corners, and through the movement of these edges and corners from the original position, it reduces the imaging distortion. The goal of this movement is to make the target contour match the contour of the image on the wafer at the preset observation points. Each iteration of OPC requires the recalculation of the target contour and the contour of the image on the wafer at the preset observation points, and the time and space complexity of this calculation is quite large. This makes it urgent to solve the problem of fast convergence of OPC. However, the polygon division and the selection of observation points significantly affect the convergence of OPC. At the same time, fixed division requires edges to cooperate with adjacent edges to modify local imaging distortion, which limits the optimization freedom in edge-based OPC. Pixel-based OPC discretizes the mask into pixels and optimizes their transmittance. Pixel-based OPC is a high-dimensional nonlinear constrained optimization problem. It has higher optimization freedom than edge-based OPC and has greater potential to achieve better imaging performance. Similarly, pixel-based OPC, while enjoying excellent optimization capabilities brought by rich freedom, also faces huge computational load.

[0046] To this end, the embodiment of the present application provides a chip edge placement error determination scheme, which can determine the chip edge placement error simply and conveniently in the chip lithography process, can obtain the global optimal solution in the correction process of the image edge with a large probability, and takes into account the local control of the edge.

[0047] Referring to Figure 1 The embodiment of the present application discloses a chip edge placement error determination method, comprising:

[0048] Step S11: performing pixelization processing on the photoresist pattern edge of the chip simulation to obtain a target pixel of the photoresist pattern edge.

[0049] In this embodiment, since optical proximity correction is needed in the chip lithography technology, the optical proximity correction is to correct the distortion errors such as the line width ratio design wide or narrow and the round corner by moving the edge of the pattern on the mask plate or adding an additional polygon. The goal is to ensure that the edge of the designed pattern in the production process is completely etched, so as to make the circuit produced on the silicon wafer consistent with the original circuit as much as possible. And in the optical proximity correction, it includes edge-based proximity correction and pixel-based proximity correction. In order to have higher optimization freedom, the photoresist pattern edge of the chip simulation is pixelized, that is, the mask is discretized into pixels and the transmittance is optimized.

[0050] Step S12: encoding the target pixel by using a preset encoding mode to obtain a target pixel code.

[0051] In this embodiment, the target pixel is encoded by using Gray coding, the target pixel is initialized and processed, and a target pixel code is obtained; wherein the iteration number of the initialization is zero. It can be understood that based on the above-mentioned optical proximity effect problem of the pixel, the target pixel is assigned by using the {0, -1, 1} encoding mode, the target pixel code is obtained, that is, the chromosome coding in the genetic algorithm, and the population initialization is realized. The chromosome coding mode can further include but is not limited to binary coding, floating point coding, and letter coding, etc.; the implementation mode of the population initialization can further include but is not limited to rule-based optical proximity effect correction (Rule-based OPC), wherein the key of the rule-based optical proximity effect correction is the correction rule. This rule specifies how to correct various exposure patterns. Its form and content will greatly affect the OPC data processing efficiency and correction accuracy, and can realize the initialization process of the population.

[0052] Step S13: adaptively evaluating the target pixel code, and selecting a first target pixel corresponding to the target pixel code that meets the preset screening condition rule from the target pixels corresponding to the target pixel code.

[0053] In this embodiment, the preset evaluation function is used to adaptively evaluate the target pixel coding to obtain an adaptation value of the target pixel coding. It can be understood that the circuit / line / edge placement error square can be used to calculate the target pixel coding to obtain the adaptation value of the target pixel coding, that is, the adaptation value of the chromosome, to evaluate the advantages and disadvantages of each chromosome. After obtaining the adaptation value of the target pixel coding, the target pixel corresponding to the maximum adaptation value is selected from the target pixel coding corresponding to the adaptation value of the group as the first target pixel and saved.

[0054] Step S14: generating a first target pixel population based on the first target pixel, and outputting a target adaptation value of the first target pixel population.

[0055] In this embodiment, a first target pixel population is generated based on the first target pixel, and a target pixel to be crossed is selected from the first target pixel population; the target pixel to be crossed is processed to generate a new target pixel; a new target population is generated based on the new target pixel and the first target pixel except the target pixel to be crossed, and a new target adaptation value of the new target pixel population is output. It can be understood that the probability selection algorithm is used to select the group chromosomes to generate a population of the same size N. The probability selection algorithm can randomly select the group chromosomes according to the proportion of the adaptation value of each chromosome in the sum of the adaptation values of all chromosomes in the group; and the chromosomes are selected from the population according to the probability p to cross. The new offspring chromosomes enter the new population, and the chromosomes that are not crossed are directly copied into the new population. In the chromosome crossing stage, whether each chromosome can be crossed is determined by the crossing probability P. The specific process is: for each chromosome, if random(0, 1) is less than the probability p, it means that the chromosome can be crossed, otherwise the chromosome is directly copied into the new population without crossing. The size of the new population is unchanged. It should be noted that the size of the new population is consistent with that of the original population.

[0056] In this embodiment, a first target pixel population is generated based on the first target pixel, and a target pixel to be crossed is selected from the first target pixel population; the target pixel to be crossed is processed to generate a new target pixel; a new target population is generated based on the new target pixel and the first target pixel except the target pixel to be crossed, and a new target adaptation value of the new target pixel population is output. It can be understood that the probability selection algorithm is used to select the group chromosomes to generate a population of the same size N. The probability selection algorithm can randomly select the group chromosomes according to the proportion of the adaptation value of each chromosome in the sum of the adaptation values of all chromosomes in the group; and the chromosomes are selected from the population according to the probability p to cross. The new offspring chromosomes enter the new population, and the chromosomes that are not crossed are directly copied into the new population. In the chromosome crossing stage, whether each chromosome can be crossed is determined by the crossing probability P. The specific process is: for each chromosome, if random(0, 1) is less than the probability p, it means that the chromosome can be crossed, otherwise the chromosome is directly copied into the new population without crossing. The size of the new population is unchanged. It should be noted that the size of the new population is consistent with that of the original population.

[0057] Step S15: adjusting parameters of the PID controller by using the target fitness value to determine the chip edge placement error.

[0058] In this embodiment, the obtained target fitness value is used to adjust the parameters of the PID controller. It can be understood that the PID parameter adjustment technology does not make good use of the mutual influence between each circuit / line / edge. Due to the width limitation of pinch and bridge, each circuit / line / edge will be in a state of fighting for itself. In this way, there is a lack of overall control of the OPC process, and the genetic algorithm strategy can extract the most competitive features of the overall circuit / line / edge / pixel at a specific location and pass them to the next generation. This strategy indirectly captures the local mutual influence between each circuit / line / edge / pixel, so that the target fitness value obtained by the genetic algorithm strategy can better adjust the PID parameters, and then use the PID controller with added PID parameters for control to generate an edge placement error; the edge placement error is an index for measuring the quality of optical proximity correction, and in addition, a small edge placement error means that the simulated pattern is close to the design pattern.

[0059] It can be seen that the application discloses a chip edge placement error determination method, which comprises: performing pixelization processing on a photoresist pattern edge of a chip simulation to obtain a target pixel of the photoresist pattern edge; encoding the target pixel by using a preset encoding mode to obtain a target pixel code; adaptively evaluating the target pixel code and selecting a first target pixel corresponding to the target pixel code that meets a preset screening condition rule from the target pixel corresponding to the target pixel code; generating a first target pixel population based on the first target pixel and outputting a target fitness value of the first target pixel population; and adjusting parameters of a PID controller by using the target fitness value to determine a chip edge placement error. It can be seen that by performing pixelization processing on the photoresist pattern edge, the local properties of the imaged edge can be maximally utilized, the local control is good, and a suitable fitness value, that is, a global optimal solution, is selected based on the adaptive evaluation of the target pixel code. The global optimal solution is combined and applied to the adjustment of the parameters of the PID controller, so that the PID controller is applied to optical proximity effect correction, and the chip edge placement error is simply and conveniently determined.

[0060] Referring to Figure 2 The embodiment of the application discloses a specific chip edge placement error determination method. Compared with the previous embodiment, the technical solution is further described and optimized. Specifically,

[0061] Step S21: pixelizing the photoresist pattern edge of the chip simulation to obtain a target pixel of the photoresist pattern edge.

[0062] Step S22: encoding the target pixel by using a preset encoding mode to obtain a target pixel code.

[0063] Step S23: adaptively evaluating the target pixel code by using a preset evaluation function to obtain an adaptive value of the target pixel code.

[0064] Step S24: judging whether the adaptive value of the target pixel code meets a preset adaptive value, and if not, determining a maximum adaptive value and a corresponding first target pixel from all the adaptive values.

[0065] In the embodiment, as shown in FIG. 1, after obtaining the adaptive value of each target pixel code, it is judged whether the adaptive value meets the preset adaptive value. If the adaptive value meets the preset adaptive value, the adaptive value is directly output as a target adaptive value. If the adaptive value does not meet the preset adaptive value, the maximum adaptive value and the corresponding target pixel are screened out as the first target pixel. The first target pixel is used to enter an iteration operation. Figure 3

[0066] Step S25: judging a size relationship between an operation number of outputting the maximum adaptive value of the first target pixel population and a preset iteration number, and if the operation number is less than the preset iteration number, the adaptive evaluation of the target pixel code is executed until the target adaptive value is obtained.

[0067] In the embodiment, the first target pixel population where the first target pixel is located is sequentially subjected to random algorithm operation, mating operation and mutation operation to obtain a next target pixel population and an adaptive value until the adaptive value meets the preset adaptive value, the iteration process is stopped, and the adaptive value is output as the target adaptive value. Alternatively, a preset iteration number is set, and when the iteration number meets the preset iteration number, the current adaptive value is output as the target adaptive value. Alternatively, an error between the adaptive value in the iteration process and the target adaptive value is within a preset adaptive value error range, and the current adaptive value is output as the target adaptive value.

[0068] Step S26: adjusting parameters of a PID controller by using the target adaptive value to determine a chip edge placement error.

[0069] The more detailed processing procedures in steps S21, S22, S23 and S26 are described in the foregoing disclosed embodiments, and will not be repeated here.

[0070] ​Therefore, the genetic algorithm has better global search ability, can obtain the global optimal solution with a large probability, and the pixel-based OPC can maximize the use of the local properties of the imaging edge, and the local control is better, and finally the PID controller is applied to the OPC process of the chip to determine the edge placement error of the chip, and reduce the defects of too many iteration times and low performance in the OPC process.

[0071] Referring to Figure 4 The chip edge placement error determination device is also disclosed by the embodiment of the application, and comprises:

[0072] The first pixel acquisition module 11 is configured to perform pixelization processing on the simulated photoresist pattern edge of the chip to obtain a target pixel of the photoresist pattern edge.

[0073] The pixel encoding module 12 is configured to encode the target pixel by using a preset encoding mode to obtain a target pixel code.

[0074] The second pixel acquisition module 13 is configured to adaptively evaluate the target pixel code and select a first target pixel corresponding to the target pixel code that meets a preset screening condition rule from the target pixel corresponding to the target pixel code.

[0075] The population determination module 14 is configured to generate a first target pixel population based on the first target pixel and output a target fitness value of the first target pixel population.

[0076] The error determination module 15 is configured to adjust parameters of a PID controller by using the target fitness value to determine the edge placement error of the chip.

[0077] It can be seen that the chip simulation photoresist pattern edge is pixelated to obtain a target pixel of the photoresist pattern edge; the target pixel is encoded by using a preset encoding mode to obtain a target pixel code; the target pixel code is adaptively evaluated, and a first target pixel corresponding to the target pixel code meeting a preset screening condition rule is selected from the target pixel corresponding to the target pixel code; a first target pixel population is generated based on the first target pixel, and a target fitness value of the first target pixel population is output; and the target fitness value is used to adjust parameters of a PID controller to determine a chip edge placement error. It can be seen that by pixelating the photoresist pattern edge, the local properties of the imaging edge can be maximally utilized, the local control is good, and the appropriate fitness value, that is, the global optimal solution, is selected based on the adaptive evaluation of the target pixel code. The global optimal solution is combined and applied to the parameter adjustment of the PID controller, so that the PID controller is applied to the optical proximity effect correction to simply and conveniently determine the chip edge placement error.

[0078] Further, the embodiment of the present application further discloses an electronic device, Figure 5 The electronic device 20 is shown in the structure diagram according to an exemplary embodiment, and the content in the figure cannot be considered as any limitation on the use range of the present application.

[0079] Figure 5 The electronic device 20 is shown in the structure diagram according to an exemplary embodiment, and the content in the figure cannot be considered as any limitation on the use range of the present application.

[0080] In the embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol followed by the communication interface 24 can be any communication protocol applicable to the technical solution of the present application, which is not limited here; the input and output interface 25 is used to obtain external input data or output data to the outside, and the specific interface type can be selected according to the specific application needs, which is not limited here.

[0081] The processor 21 can include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 can be implemented in at least one of a hardware form of a DSP (Digital Signal Processing), an FPGA (Field-Programmable Gate Array), a PLA (Programmable Logic Array). The processor 21 can also include a main processor and a coprocessor, the main processor being a processor for processing data in a wake-up state, also known as a CPU (Central Processing Unit), and the coprocessor being a low-power processor for processing data in a standby state. In some embodiments, the processor 21 can be integrated with a GPU (Graphics Processing Unit) that is responsible for rendering and drawing the content required to be displayed by the display screen. In some embodiments, the processor 21 can also include an AI (Artificial Intelligence) processor for processing computing operations related to machine learning.

[0082] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a magnetic disk or an optical disk, etc., and the resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage mode can be temporary storage or permanent storage.

[0083] The operating system 221 is used to manage and control each hardware device and the computer program 222 on the electronic device 20 to realize the operation and processing of the processor 21 on the mass data 223 in the memory 22, and can be Windows Server, Netware, Unix, Linux, etc. In addition to including the computer program capable of completing the chip edge placement error determination method disclosed in any of the preceding embodiments executed by the electronic device 20, the computer program 222 can further include a computer program capable of completing other specific work. The data 223 can include data received by the electronic device from an external device, as well as data collected by the self input / output interface 25, etc.

[0084] Further, the present application also discloses a computer readable storage medium for storing a computer program; wherein the computer program is executed by the processor to realize the chip edge placement error determination method disclosed in the preceding embodiments. The specific steps of the method can refer to the corresponding content disclosed in the preceding embodiments, and will not be repeated here.

[0085] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0086] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions using different methods for each specific application, but such implementation should not be considered beyond the scope of this application. The steps of the methods or algorithms described in connection with the embodiments disclosed herein can be implemented directly in hardware, software modules executed by a processor, or a combination of both. Software modules can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0087] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0088] The present invention has provided a detailed description of a chip edge placement error determination method, apparatus, device, and storage medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for determining chip edge placement error, characterized in that, include: The edges of the photoresist pattern in the chip simulation are pixelated to obtain the target pixels at the edges of the photoresist pattern. The target pixel is encoded using a preset encoding method to obtain the target pixel code; An adaptive evaluation is performed on the target pixel code, and a first target pixel corresponding to the target pixel code that meets the preset screening criteria is selected from the target pixels corresponding to the target pixel code; A first target pixel population is generated based on the first target pixel, and the target fitness value of the first target pixel population is output. The parameters of the PID controller are adjusted using the target adaptation value to determine the chip edge placement error.

2. The method for determining chip edge placement error according to claim 1, characterized in that, The step of encoding the target pixel using a preset encoding method to obtain the target pixel encoding includes: The target pixel is encoded using Gray coding, the target pixel is initialized, and the target pixel code is obtained; wherein the number of iterations for initialization is zero.

3. The method for determining chip edge placement error according to claim 1, characterized in that, The adaptive evaluation of the target pixel encoding includes: An adaptive evaluation is performed on the target pixel code using a preset evaluation function to obtain the adaptive value of the target pixel code.

4. The method for determining chip edge placement error according to claim 3, characterized in that, The step of selecting a first target pixel from the target pixels corresponding to the target pixel code that meets the preset filtering criteria includes: Determine whether the fitness value of the target pixel encoding conforms to the preset fitness value. If it does not conform, determine the maximum fitness value and the corresponding first target pixel from all the fitness values.

5. The method for determining chip edge placement error according to claim 1, characterized in that, The step of generating a first target pixel population based on the first target pixel and outputting the target fitness value of the first target pixel population includes: A first target pixel population is generated based on the first target pixel, and all first target pixel codes in the first target pixel population are obtained, and a target pixel code to be mated is selected from the first target pixel codes; The target pixel codes to be mated are processed to generate new target pixel codes; A new target pixel code population is generated based on the new target pixel code and the first target pixel code other than the target pixel code to be mated, and the new target fitness value of the new target pixel code population is output.

6. The method for determining chip edge placement error according to claim 1, characterized in that, The step of generating a first target pixel population based on the first target pixel and outputting the target fitness value of the first target pixel population includes: A first target pixel population is generated based on the first target pixel, and all first target pixel codes in the first target pixel population are obtained, and a target pixel code to be mutated is selected from the first target pixel codes; The target pixel code to be mutated is mutated to generate a new target pixel code; A new target pixel code population is generated based on the new target pixel code and the first target pixel code excluding the target pixel code to be mutated, and the new target fitness value of the new target pixel code population is output.

7. The method for determining chip edge placement error according to claim 5 or 6, characterized in that, Also includes: Determine the relationship between the number of operations that output the new target fitness value of the new target pixel encoding population and the preset number of iterations. If the number of operations is less than the preset number of iterations, then proceed to the step of performing an fitness evaluation on the target pixel encoding in the new target pixel encoding population, using the new target pixel encoding population as input.

8. A device for determining chip edge placement error, characterized in that, include: The first pixel acquisition module is used to perform pixelation processing on the edge of the photoresist pattern in chip simulation in order to obtain the target pixel of the photoresist pattern edge. A pixel encoding module is used to encode the target pixel using a preset encoding method to obtain the target pixel encoding; The second pixel acquisition module is used to perform adaptive evaluation on the target pixel code and select a first target pixel that corresponds to the target pixel code that meets the preset screening condition rules from the target pixels corresponding to the target pixel code; The population determination module is used to generate a first target pixel population based on the first target pixel and output the target fitness value of the first target pixel population. An error determination module is used to adjust the parameters of the PID controller using the target adaptation value in order to determine the chip edge placement error.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the chip edge placement error determination method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, Used to store a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the chip edge placement error determination method as described in any one of claims 1 to 7.

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