A high-speed self-balancing storage control method and storage medium

Abstract

The present invention discloses a high-speed self-balancing storage control method and storage medium. The present invention abstracts a physical control layer for managing and adapting physical storage space, and the physical control layer mainly includes a group of control keywords. The present invention adopts a cyclic writing method for the physical storage space, which naturally has the characteristics of write balancing, thereby avoiding bad blocks caused by repeated erasing of a single storage space. The present invention establishes a hash map of logical addresses and physical addresses, and the read and write time complexity is O(1). The present invention establishes a logical page cache on the operation end, further abstracts the logical writing, and the write operation can adopt any length, thereby meeting the characteristics of "short write and long storage". The reading of the present invention can be carried out in two ways, one is to use the logical address as the base address to read data of any length; the other is to use the data content as the keyword and use an algorithm search method to read specific byte data.

Description

Technical Field

[0001] The invention relates to a high-speed self-balancing storage control method and a storage medium, belonging to the field of information technology. Background Art

[0002] With the development of flash memory technology, the storage space of flash memory media is getting larger and larger, and the cost is getting lower and lower. Nandflash is a typical flash memory, which is characterized by block-page-byte as the partition structure, and generally uses page as the read and write unit and block as the erase unit. This characteristic of the block storage structure has asymmetric read, write and erase operations when used, which increases the difficulty of storage system management and sets physical restrictions for the use of this medium.

[0003] In order to perform standardized management, it is generally necessary to use a file system to format the storage medium and use the abstract interface of the file system for read and write management. In small embedded devices, the main MCU structure is relatively simple, the logical function is relatively single, and there is a lack of a large file system operating environment, which makes it difficult to manage such block storage devices in embedded devices. Summary of the invention

[0004] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a high-speed self-balancing storage control method and a storage medium.

[0005] To achieve the above object, the present invention provides a high-speed self-balancing storage control method, comprising:

[0006] Step 1, initializing the physical interface of the block storage device;

[0007] Step 2, using the physical interface of the storage device to read the hardware information;

[0008] Step 3, calculating the physical storage structure of the hardware according to the hardware information, and initializing the value of the physical control keyword;

[0009] Step 4, initialize the cycle keyword to a preset initial value;

[0010] Step 5, calculate the number of operable logic units logic_unit_num;

[0011] Step 6, assign the operable logic unit number logic_unit_num to the logic_unit_num keyword;

[0012] Step 7, read the last stored next_write_address from the logical address storage area. If reading next_write_address fails, set next_write_address to the default start address and go to step 8. If reading next_write_address succeeds, go directly to step 8.

[0013] Step 8: Apply for cache page storage space in the memory. The size of the cache page storage space is logic_unit_capacity. If the application for cache page storage space fails, repeat this step.

[0014] Preferably, the physical control keywords include the number of storage blocks block_nums of the physical device, the number of pages page_nums of a single storage block of the physical device, the number of single page bytes page_bytes of the smallest page of the physical device, the smallest operable logical unit block logic_unit_capacity, whether to automatically cycle write cycle, the number of logical units logic_unit_num and the next writable logical unit address next_write_address.

[0015] Preferably, step 5, calculate the number of operable logic units logic_unit_num:

[0016] logic_unit_num =

[0017] (block_nums+1)*(page_nums+1)*((page_bytes+1) / (logic_unit_capacity+1))-1.

[0018] Preferably, in step 9, if the application for cache page storage space is successful, the data is written into the cache page and the process proceeds to step 10;

[0019] Step 10, determine whether the cache page is full of data, if so, go to step 11, otherwise go to step 9;

[0020] Step 11, get the variable value in the logical address next_write_address, set logic_unit_capacity=next_write_address, according to logic_unit_num =

[0021] (block_nums+1)*(page_nums+1)*((page_bytes+1) / (logic_unit_capacity+1))-1, calculate block_nums, page_nums and page_bytes.

[0022] Preferably, in step 12, if the physical storage address is a block boundary or a page boundary, then an erase operation is performed and the process proceeds to step 13, otherwise the process proceeds directly to step 13;

[0023] Step 13, accumulate the variable value in next_write_address and update the variable value in next_write_address.

[0024] Preferably, step 14, determine whether the variable value in next_write_address is successfully written into the logical address storage area, if so, proceed to step 15, otherwise proceed to step 12;

[0025] Step 15, store the variable value of next_write_address into the logical address storage area, and go to step 10.

[0026] Preferably, in step 91, before entering step 9, the following steps are performed:

[0027] Determine whether the cache address of the storage area is empty. If so, go to step 9. If not, obtain the variable value in next_write_address and use the mapping formula logic_unit_num =

[0028] (block_nums+1)*(page_nums+1)*((page_bytes+1) / (logic_unit_capacity+1))-1, let logic_unit_capacity=next_write_address, calculate block_nums, page_nums and page_bytes.

[0029] Step 92: Read the specified amount of data into the logical address storage area.

[0030] Preferably, the data includes picture data and text data in byte form.

[0031] An electronic device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of any one of the above methods when executing the program.

[0032] A computer-readable storage medium stores a computer program, which implements the steps of any of the above methods when executed by a processor.

[0033] The beneficial effects achieved by the present invention are:

[0034] In the first aspect, the present invention is mainly used to solve the read-write inconsistency problem based on block storage devices, abstracting a physical control layer for managing and adapting physical storage space. The physical control layer mainly includes a group of control keywords for managing and adapting physical storage space.

[0035] Secondly, the present invention adopts a sequential cyclic writing method for the physical storage space, which naturally has a write-balanced characteristic, thereby avoiding bad blocks caused by repeated erasing and writing of a single storage space.

[0036] In a third aspect, the present invention establishes a hash map of logical addresses and physical addresses, so that the read and write time complexity is O(1).

[0037] Fourthly, the present invention establishes a logical page cache on the operating end and further abstracts the logical write. The write operation can adopt any length to meet the characteristics of "short write and long storage". A logical page cache mechanism is established during the erasing process to meet the writing of data of any length.

[0038] In the fifth aspect, the present invention can be read in two ways. One is to use the logical address as the base address to read data of any length; the other is to use the data content as the keyword and use an algorithm search method to read specific byte data. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is a structural diagram of the local storage of BMS system data;

[0040] Figure 2 This is the block diagram of the Nandflash block storage hardware;

[0041] Figure 3 It is a framework diagram of the present invention;

[0042] Figure 4 It is an abstract control class and physical storage structure diagram;

[0043] Figure 5 is a logic flow chart of the present invention;

[0044] Figure 6 It is a logical schematic diagram of cache page writing of the present invention. DETAILED DESCRIPTION

[0045] The following embodiments are only used to more clearly illustrate the technical solutions of the present invention, and are not intended to limit the protection scope of the present invention.

[0046] The present invention is achieved through the following technical solutions:

[0047] In a first aspect, the present invention abstracts a physical control layer for managing and adapting physical storage space, and the physical control layer mainly includes a group of control keywords.

[0048] Secondly, the present invention adopts a cyclic writing method for the physical storage space, which naturally has the characteristic of write balancing, thereby avoiding bad blocks caused by repeated erasing and writing of a single storage space.

[0049] In a third aspect, the present invention establishes a hash map of logical addresses and physical addresses, and the read and write time complexity is O(1).

[0050] Fourthly, the present invention establishes a logical page cache on the operation side, further abstracts the logical write, and the write operation can adopt any length, thereby satisfying the characteristic of "short write, long memory".

[0051] In the fifth aspect, the present invention can be read in two ways. One is to use the logical address as the base address to read data of any length; the other is to use the data content as the keyword and use an algorithm search method to read specific byte data.

[0052] (1) Device hardware structure and logical ports

[0053] Nandflash is a typical block storage device, which is characterized by a block-page-byte partition structure, and generally uses a page as a read and write unit and a block as an erase unit.

[0054] Figure 1 This is a diagram of the data localization storage structure of the BMS system. The left side shows the physical interface of the Nandflash block storage device and various logic control modules. The Nandflash block storage device and the main control chip use the high-speed SPI bus as the physical channel for communication, and data exchange is carried out through the serial controller of the Nandflash block storage device.

[0055] Figure 2 The figure is a structural diagram of a Nandflash block storage device, in which the Nandflash block storage device is mainly composed of 1024 storage blocks, each block contains 64 storage pages, and each storage page can store 2048 bytes.

[0056] (2) Overall framework structure

[0057] Figure 3This is the overall framework diagram of the present invention, which adopts software and hardware abstraction and layered architecture. The specific physical block storage structure is at the bottom layer, the driver interface layer is responsible for driving the specific physical hardware, and abstracting the device driver interface to the upper layer. The abstract interface layer is the storage block control system that calls the abstract API interface for the upper layer. The data write cache and read algorithm are supported by the interface definition method, which has good dynamics and strong scalability. The data includes image data and text data in byte form.

[0058] (3) Data structure

[0059] Figure 4 The left side is the data structure of the abstract control class, and the right side is the physical storage structure diagram corresponding to some key control words. Among them, block_nums represents the number of storage blocks of the actual physical storage medium, page_nums represents the number of storage pages of each storage block, page_bytes represents each storage page, logic_unit_capacity represents the minimum operable logical unit block, that is, the logical page size, cycle represents whether to automatically cycle write, logic_unit_num represents the number of operable logical units, next_write_address is the next writable logical unit address, txcnt represents the number of remaining writable bytes of the logical page, and txbuff is the address of the logical page cache space.

[0060] Assume that the physical structure of a block storage device is 1024 blocks, each block contains 64 physical pages, and each physical page contains 2048 bytes that can be stored. Then, block_nums = 1023, page_nums = 63, page_bytes = 2047. Assume that the minimum number of bytes that can be written to the storage device at a time is 512, you can set logic_unit_capacity = 511, and the calculation formula between logic_unit_num and physical parameters is logic_unit_num =

[0061] (block_nums+1)*(page_nums+1)*((page_bytes+1) / (logic_unit_capacity+1))-1, this formula is the address mapping relationship formula.

[0062] (4) Logical structure

[0063] Figure 5 To control the logic flow chart, it is mainly divided into three parts: initialization part, erase part and data read part.

[0064] (A) Initialization part

[0065] Step 1: Initialize the physical interface of the block storage device.

[0066] Step 2: Call the feature information reading interface function to read the hardware information.

[0067] Step 3, calculate the physical storage structure of the hardware according to the hardware information, and initialize the value of the physical control keyword, the physical control keyword includes block_nums, page_nums, page_bytes, logic_unit_capacity, cycle, logic unit number logic_unit_num and next_write_address.

[0068] Among them, block_nums represents the number of storage blocks of the physical device, page_nums represents the number of pages of a single storage block of the physical device, page_bytes represents the number of bytes of a single page of the smallest page of the physical device, and logic_unit_capacity represents the minimum number of logical storage units preset by the user.

[0069] Step 4: Initialize the cycle keyword to a preset initial value according to the globally predefined setting parameters. The keyword controls whether old data is overwritten during the cyclic writing process.

[0070] Step 5, calculate the number of operable logic units logic_unit_num according to the formula;

[0071] The calculation formula is logic_unit_num =

[0072] (block_nums+1)*(page_nums+1)*((page_bytes+1) / (logic_unit_capacity+1))-1. This formula is mainly based on the maximum number of bytes that the hardware device can store, divided by the preset number of logical storage units, to get the number of operable logical units. This formula linearly maps the physical storage address with the logical operation address to form a hash mapping structure with a search complexity of O(1).

[0073] Step 6, assign the calculated operable logic unit quantity to the logic_unit_num keyword;

[0074] Step 7, read the last logical address next_write_address to be written from the logical address storage area, the specific storage area is called the logical address storage area. The main function of this area is to memorize the value of the next_write_address variable of the last operation, and each time the variable is modified, a variable write will be triggered.

[0075] If reading the logical address next_write_address fails, the logical address next_write_address is set as the default starting address and the process goes to step 8. If reading the logical address next_write_address succeeds, the process goes directly to step 8.

[0076] Step 8, such as Figure 6 As shown, the system will first apply for cache page storage space in the memory, and the cache page storage space is logic_unit_capacity. If the cache page storage space application is successful, go to step 9, otherwise repeat this step. The cache page is free at the beginning, and gradually fills up as data is written. During each write process, the erase check mechanism will be triggered, and the erase part logic is as follows.

[0077] (B) Erase part

[0078] Step 9, the system calls the write data interface, and the data is first written into the cache page in the form of a byte stream. There is no restriction on the organizational structure of the data, and the user can define the size and format of each data write, and then proceed to step 10.

[0079] Step 10, determine whether the cache page is full of data, if so, go to step 11, otherwise go to step 9;

[0080] Step 11, obtain the variable value in the logical address next_write_address, according to the mapping formula logic_unit_num = (block_nums + 1) * (page_nums + 1) * ((page_bytes + 1) / (logic_unit_capacity + 1)) - 1, let logic_unit_capacity = next_write_address, and calculate the corresponding block_nums, page_nums, and page_bytes.

[0081] Step 12, since the physical storage block is generally erased at the block or page boundary, it is necessary to check the block_nums, page_nums, and page_bytes parameters before writing, which constitute the physical storage address. If the physical storage address is a block boundary or a page boundary, the erase operation is performed and the process proceeds to step 13, otherwise the process proceeds directly to step 13;

[0082] Step 13, accumulate the variable value in next_write_address and update the variable value in next_write_address;

[0083] Step 14, determine whether the variable value in next_write_address is successfully written into the logical address storage area, if yes, proceed to step 15, otherwise proceed to step 12;

[0084] Step 15, store the variable value of next_write_address into the logical address storage area, and go to step 10.

[0085] like Figure 6 As shown in the figure, when calling the write data interface, this part of the logic will first write the data to the cache page. If the cache page data is not full, it will return directly and wait for subsequent data to be written.

[0086] If the cache page data is full, the physical parameters of the actual storage area, namely block_nums, page_nums, and page_bytes parameters, are calculated based on the variable value in the current next_write_address according to the formula logic_unit_num = (block_nums+1)*(page_nums+1)*((page_bytes+1) / (logic_unit_capacity+1))-1. For example, the block area, page area, page offset address, etc.

[0087] Before the actual writing is performed, it will first check whether it is a block boundary, and execute the block erase instruction according to the parameter information. After the erase is executed, the variable value in next_write_address will be modified first, and the variable value of next_write_address will be stored in the logical address storage area, and then the actual data writing will be performed.

[0088] (C) Read data part

[0089] Step 91, before determining whether to call the data writing interface, first perform the following steps:

[0090] Determine whether the cache address of the area to be stored is empty. If so, proceed to step 9. If not, obtain the variable value in the logical address next_write_address.

[0091] According to the mapping formula logic_unit_num =

[0092] (block_nums+1)*(page_nums+1)*((page_bytes+1) / (logic_unit_capacity+1))-1 and the variable value in the logical address next_write_address, let logic_unit_capacity=next_write_address, calculate block_nums, page_nums and page_bytes.

[0093] Step 92, calling the actual data reading interface to read the specified amount of data into the logical address storage area.

[0094] When calling the data read interface, this part of the logic will first check whether the address of the area to be stored is empty. If the cache address is not empty, the physical parameters of the actual storage area, such as the block area, page area, page offset address, etc., are calculated according to the formula based on the passed in logical address. Then the actual data read interface is called to read the specified amount of data into the area to be stored. Since the actual physical address is stored in sequence, the corresponding logical address is also stored linearly. Therefore, based on sequential storage, if the stored data is also encoded in sequence, it can support searching for data based on the search algorithm.

[0095] The present invention is mainly used to solve the reading and writing inconsistency problem based on block storage devices. The main method is to use a set of control keywords to manage and adapt physical storage space, and establish a hash map of physical addresses and logical storage addresses, so that the time complexity of reading and writing is O(1). The actual writing of the method of the present invention at the physical layer is sequential writing, which naturally has a write balance feature, and can avoid bad blocks caused by repeated erasing and writing of a single storage unit. During the writing process, bad block storage can be identified and skipped through logical control, and the compatibility is good. A logical page cache mechanism is established during the erasing process to meet the writing of data of any length. When reading data, the logical address sequence is read, and an ordered search algorithm can be supported. The present invention has strong applicability, high stability and reliability.

[0096] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0097] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0098] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0099] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A high-speed self-balancing storage control method, characterized in that: include: Step 1, initializing the physical interface of the block storage device; Step 2, using the physical interface of the storage device to read the hardware information; Step 3, calculate the physical storage structure of the hardware according to the hardware information, and initialize the value of the physical control keyword, which includes the number of storage blocks of the physical device block_nums, the number of pages of a single storage block of the physical device page_nums, the number of bytes of a single page of the smallest page of the physical device page_bytes, the minimum operable logical unit block logic_unit_capacity, whether to automatically cycle write cycle, the number of logical units logic_unit_num and the next writable logical unit address next_write_address; Step 4, initialize the cycle keyword to a preset initial value; Step 5, calculate the number of operable logic units logic_unit_num: logic_unit_num = (block_nums+1)*( page_nums+1)*((page_bytes+1) / (logic_unit_capacity+1))-1; Step 6, assign the operable logic unit number logic_unit_num to the logic_unit_num keyword; Step 7, read the last stored next_write_address from the logical address storage area. If reading next_write_address fails, set next_write_address to the default start address and go to step 8. If reading next_write_address succeeds, go directly to step 8. Step 8: Apply for cache page storage space in the memory. The size of the cache page storage space is logic_unit_capacity. If the cache page storage space application fails, repeat this step. Step 9: If the application for cache page storage space is successful, the data is written into the cache page and the process goes to step 10; Step 10, determine whether the cache page is full of data, if so, go to step 11, otherwise go to step 9; Step 11, get the variable value in the logical address next_write_address, set logic_unit_capacity=next_write_address, according to logic_unit_num = (block_nums+1)*(page_nums+1)*((page_bytes+1) / (logic_unit_capacity+1))-1, calculate block_nums, page_nums and page_bytes.

2. A high-speed self-balancing storage control method according to claim 1, characterized in that: Also includes: Step 12, if the physical storage address is a block boundary or a page boundary, perform an erase operation and proceed to step 13, otherwise directly proceed to step 13; Step 13, accumulate the variable value in next_write_address and update the variable value in next_write_address.

3. A high-speed self-balancing storage control method according to claim 2, characterized in that: Also includes: Step 14, determine whether the variable value in next_write_address is successfully written into the logical address storage area, if yes, proceed to step 15, otherwise proceed to step 12; Step 15, store the variable value of next_write_address into the logical address storage area, and go to step 10.

4. A high-speed self-balancing storage control method according to claim 1, characterized in that: Step 91, before entering step 9, perform the following steps: Determine whether the cache address of the storage area is empty. If so, go to step 9. If not, obtain the variable value in next_write_address and use the mapping formula logic_unit_num = (block_nums+1)*(page_nums+1)*((page_bytes+1) / (logic_unit_capacity+1))-1, let logic_unit_capacity=next_write_address, calculate block_nums, page_nums and page_bytes; Step 92: Read the specified amount of data into the logical address storage area.

5. A high-speed self-balancing storage control method according to claim 1, characterized in that: The data includes image data and text data in byte form.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the method according to any one of claims 1 to 5 are implemented.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

Images