In-line storage device and its device management method

Abstract

The present application discloses an embedded storage device and a device management method thereof. The embedded storage device includes a plurality of storage devices. The device management method includes obtaining firmware versions of the plurality of storage devices respectively, and aligning a transmission configuration of at least one of the plurality of storage devices downward according to the firmware versions of the plurality of storage devices to determine a final available transmission configuration, and performing read / write operations on the plurality of storage devices with the same final available transmission configuration.

Description

Technical Field

[0001] This application relates to the technical field of storage devices, and more particularly to an embedded storage device and a device management method thereof. Background Technology

[0002] To meet the demands of thinner and lighter mobile devices with larger memory capacities, an embedded memory with small size, high integration, and low complexity has been proposed. Typically, embedded memory includes multiple embedded multi-media cards as storage components and a controller that manages these multiple embedded multi-media cards.

[0003] Since each embedded memory can use multiple embedded multimedia cards, and these embedded multimedia cards may come from different manufacturers, the embedded multimedia cards within a single embedded memory may have different specifications and firmware.

[0004] To perform read and write operations on multiple embedded multimedia cards, the controller frequently switches read / write modes and speeds in response to the specifications and firmware of the embedded multimedia cards. This increases the power consumption of the embedded memory and further increases the likelihood of jitter in the embedded multimedia cards. This situation is even more pronounced in products with large memory capacities, making compatibility between multiple embedded multimedia cards difficult.

[0005] Therefore, how to provide an embedded memory that can be easily compatible with multiple embedded multimedia cards is a problem that the industry urgently needs to solve. Summary of the Invention

[0006] This application provides an embedded storage device and its device management method, which can solve the problem of incompatibility between multiple embedded multimedia cards in existing embedded memory.

[0007] To address the aforementioned technical problems, one embodiment of this application provides a device management method for an embedded storage device, the embedded storage device including multiple storage devices, the device management method including: determining the firmware versions of the multiple storage devices respectively; based on the firmware versions of the multiple storage devices, down-aligning the transmission configuration of at least one of the multiple storage devices to determine the final available transmission configuration; and enabling the multiple storage devices to perform read and write operations with the same final available transmission configuration.

[0008] Another embodiment of this application provides an embedded storage device including a main control circuit coupled to the plurality of storage devices and used to execute a device management method for the embedded storage device.

[0009] In the embodiments of this application, the embedded storage device enables multiple storage devices to perform read and write operations with the same transmission configuration. Therefore, the embedded storage device does not need to frequently switch read and write modes and read and write speeds to perform read and write operations on multiple storage devices, effectively reducing the overall power consumption of the embedded storage device and reducing jitter. This allows the manufacturing of the embedded storage device to be free from concerns about the specifications and firmware differences of the storage devices, and can also increase the number of storage devices, thereby achieving the goal of easily being compatible with a large number of storage devices.

[0010] To make the above-mentioned features and advantages of this application more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0011] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0012] Figure 1 This is a schematic diagram of the architecture of the embedded storage device of this application.

[0013] Figure 2 This is another schematic diagram of the embedded storage device of this application.

[0014] Figure 3 A schematic diagram of the equipment management method of this application.

[0015] Figure 4 Another schematic diagram of the equipment management method of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0017] Please see Figure 1 , Figure 1 This is a schematic diagram of the architecture of the embedded storage device of this application. The embedded storage device 1 includes a main control circuit 100, a first storage device 200a, and a second storage device 200b. The main control circuit 100 is used to send instruction signals to the first storage device 200a and the second storage device 200b, so that the first storage device 200a and the second storage device 200b respond to the instruction signals and perform corresponding operations. For example, executing the device management method and read / write operations of the embedded storage device 1.

[0018] In this embodiment, two storage devices (first storage device 200a and second storage device 200b) are used as an example for illustration, but the storage devices in this application are not limited to two.

[0019] In some embodiments, the first storage device 200a and the second storage device 200b may be embedded multimedia card chips, which include a memory array (not shown) for storing data and controller circuitry (not shown) for controlling the memory array. In some embodiments, the aforementioned memory array may be flash memory.

[0020] Please see Figure 2 , Figure 2 This is a schematic diagram of the architecture of the embedded storage device 1 of this application. Further, the main control circuit 100 includes a processor circuit 110, a first storage control circuit 120a, a second storage control circuit 120b, a first interface circuit 130a, a second interface circuit 130b, a configuration circuit 140, and a clock circuit 150. The processor circuit 110 is coupled to the first storage control circuit 120a and the second storage control circuit 120b. The first storage control circuit 120a and the second storage control circuit 120b are coupled to the configuration circuit 140, and the first storage control circuit 120a is coupled to the first interface circuit 130a, while the second storage control circuit 120b is coupled to the second interface circuit 130b. The first interface circuit 130a is coupled to the first storage device 200a, the second interface circuit 130b is coupled to the second storage device 200b, and both the first and second interface circuits are coupled to the clock circuit 150. The configuration circuit 140 is also coupled to the clock circuit 150.

[0021] The processor circuit 110 controls the first storage control circuit 120a and the second storage control circuit 120b, enabling them to execute the device management method of the embedded storage device 1 and read / write operations on the first storage device 200a and the second storage device 200b. In one embodiment, the processor circuit 110 may be (but is not limited to) a central processing unit (CPU), a multiprocessor, a pipelined processor, a distributed processing system, etc.

[0022] The first storage control circuit 120a and the second storage control circuit 120b are respectively used to respond to the processor circuit 110, causing the configuration circuit 140 to generate transmission configuration data. The first storage control circuit 120a and the second storage control circuit 120b are used to individually generate instruction signals provided to the first storage device 200a and the second storage device 200b. The clock circuit 150, in response to the transmission configuration data from the configuration circuit 140, generates a corresponding clock signal and provides the clock signal to the first interface circuit 130a and the second interface circuit 130b. The first interface circuit 130a and the second interface circuit 130b are used to individually provide the instruction signal and the clock signal to the first storage device 200a and the second storage device 200b. Therefore, the first storage device 200a and the second storage device 200b can respond to the received instruction signal and clock signal to perform corresponding transmission configuration settings or read / write operations.

[0023] In this embodiment, the transmission configuration includes the transmission mode configuration of the storage device and the corresponding clock frequency configuration. The transmission mode configuration is the bus rate mode used by the first storage device 200a and the second storage device 200b, such as High Speed ​​DDR, HS200, HS400, etc.

[0024] For further explanation of the device management method for embedded storage device 1, please refer to [link / reference needed]. Figure 2 and Figure 3 , Figure 3This is a schematic diagram of an embodiment of the device management method of this application. The device management method for the embedded storage device 1 is used to downward align the transmission configuration of at least one of a plurality of storage devices to determine the final available transmission configuration, and to enable the plurality of storage devices to perform read and write operations with the same final available transmission configuration. In step S310, power-on initialization is performed. The embedded storage device 1 is powered on and performs initialization operations on the first storage device 200a and the second storage device 200b. In step S320, the firmware versions of the plurality of storage devices are obtained. In this step, the processor circuit 110 obtains the firmware versions of the plurality of storage devices respectively. In this embodiment, the processor circuit 110 causes the first storage control circuit 120a and the second storage control circuit 120b to individually obtain the current firmware version of the first storage device 200a and the second storage device 200b. For example, the first storage control circuit 120a and the second storage control circuit 120b are individually controlled by an instruction signal to call the current firmware version data of the first storage device 200a and the second storage device 200b. In step S330, it is determined whether the firmware versions of the plurality of storage devices are the same. In this embodiment, after the processor circuit 110 obtains the current firmware version data of the first storage device 200a and the second storage device 200b, it compares the current firmware version data to confirm whether the firmware versions of the first storage device 200a and the second storage device 200b are the same. If the determination in step S330 is no, step S340 is executed; otherwise, step S350 is executed.

[0025] In step S340, the transmission configurations of multiple storage devices are downward aligned. When the firmware versions of the multiple storage devices are different, the transmission configuration of at least one of the multiple storage devices is downward aligned according to the firmware versions of the multiple storage devices. A preset transmission configuration is generated based on the firmware versions of the multiple storage devices, and the transmission configuration of at least one of the multiple storage devices is updated with the preset transmission configuration. Since the firmware versions of the first storage device 200a and the second storage device 200b are determined to be different in step S330, it means that the transmission configurations that the two storage devices can choose to use are different. Therefore, in order to make the two storage devices operate with the same transmission configuration, in this step, the processor circuit 110 causes the configuration circuit 140 to generate a preset transmission configuration based on the firmware versions of the multiple storage devices, and updates the transmission configuration of at least one of the multiple storage devices with the preset transmission configuration. Furthermore, based on the determination result, the processor circuit 110 will cause the configuration circuit 140 to generate a transmission configuration that can also be executed by storage devices with older firmware versions as a preset transmission configuration, and update the transmission configuration of storage devices with newer firmware versions to the preset transmission configuration. In other words, the transmission configuration of the storage devices with newer firmware versions will be down-aligned to the transmission configuration that can be executed by storage devices with older firmware versions. For example, when the processor circuit 110 determines that the firmware version of the first storage device 200a is version 5.1 and the firmware version of the second storage device 200b is version 4.5 based on the current firmware version data, the processor circuit 110 will adjust the transmission configuration of the first storage device 200a to a configuration that can be executed by firmware version 4.5. For example, updating from HS400 mode to high-speed DDR mode with a clock frequency of 52MHz.

[0026] In one embodiment, the preset transmission configuration is a transmission configuration that can be executed by storage devices with older firmware versions and has the highest data transfer rate. That is, steps S330 and S340 are used to determine the transmission configuration that can be operated by both the first storage device 200a and the second storage device 200b.

[0027] In step S350, a self-test procedure is executed for multiple storage devices. The multiple storage devices perform the self-test procedure to determine the optimal available transmission configuration for each of the multiple storage devices. The optimal available transmission configuration is the transmission configuration that each of the multiple storage devices can execute and has the highest transmission rate, and the transmission rate of the optimal available transmission configuration is less than or equal to the transmission rate of a preset transmission configuration. In this embodiment, the processor circuit 110 causes the first storage device 200a and the second storage device 200b to perform a self-test procedure with a preset transmission configuration to determine the optimal available transmission configuration that each of the first storage device 200a and the second storage device 200b can actually execute. The optimal available transmission configuration is the transmission configuration that each of the first storage device 200a and the second storage device 200b can execute and has the highest transmission rate, and the transmission rate of the optimal available transmission configuration is less than or equal to the transmission rate of the preset transmission configuration.

[0028] In embodiments where the firmware versions of the first storage device 200a and the second storage device 200b are determined to be the same, the first storage device 200a and the second storage device 200b will use the transmission configuration with the highest transmission rate among the same firmware versions as the preset transmission configuration. For example, when the firmware versions of both the first storage device 200a and the second storage device 200b are determined to be version 4.5, the preset transmission configuration will be set to high-speed DDR mode with a clock frequency of 52MHz.

[0029] In step S360, it is determined whether the optimal available transfer configurations of the multiple storage devices match. In this step, the processor circuit 110 tests the optimal available transfer configurations obtained in step S350 on the first storage device 200a and the second storage device 200b respectively to confirm whether the optimal available transfer configurations that the first storage device 200a and the second storage device 200b can actually execute match (e.g., whether they can operate normally under the optimal available transfer configuration). If the determination is no in step S360, step S370 is executed; otherwise, step S390 is executed.

[0030] In step S370, the transfer configurations of multiple storage devices are downward aligned. When the best available transfer configurations of multiple storage devices do not match, the transfer configurations of at least one of the multiple storage devices are downward aligned. A preset available transfer configuration is generated based on the mismatched best available transfer configurations of the multiple storage devices, and the transfer configuration of at least one of the multiple storage devices is updated with the preset available transfer configuration. In this embodiment, similar to step S340, the processor circuit 110, based on the best available transfer configurations of the multiple storage devices, causes the configuration circuit 140 to generate a preset available transfer configuration, and updates the transfer configuration of at least one of the multiple storage devices with the preset available transfer configuration. Further, based on the determination result of step S370, the processor circuit 110 causes the configuration circuit 140 to generate a transfer configuration that can be executed by both the first storage device 200a and the second storage device 200b as the preset available transfer configuration. For example, when the optimal available transmission configuration of the first storage device 200a is high-speed DDR mode with a clock frequency of 52MHz, and the optimal available transmission configuration of the second storage device 200b is high-speed SDR mode with a clock frequency of 52MHz, the processor circuit 110 adjusts the transmission configuration of the first storage device 200a to high-speed SDR mode with a clock frequency of 52MHz.

[0031] In step S380, a self-test procedure is executed for multiple storage devices. In this embodiment, similar to step S350, the processor circuit 110 causes the first storage device 200a and the second storage device 200b to perform a self-test procedure using a preset available transfer configuration as the self-test configuration, thereby updating the optimal available transfer configuration that is actually executable for each of the first storage device 200a and the second storage device 200b. After step S380, the process returns to step S360 to again determine whether the optimal available transfer configurations of the multiple storage devices match.

[0032] In step S390, the best available transfer configuration is used as the final available transfer configuration for the multiple storage devices. When the best available transfer configurations of the multiple storage devices match each other, the multiple storage devices use the matching best available transfer configuration as the final available transfer configuration. In this embodiment, since the best available transfer configurations that the first storage device 200a and the second storage device 200b can each execute are the same, the processor circuit 110 uses the current best available transfer configuration as the final available transfer configuration, causing the first storage device 200a and the second storage device 200b to perform subsequent read and write operations with the final available transfer configuration, and then ends the self-test program.

[0033] Please refer to Figure 4 , Figure 4This is a schematic diagram of an embodiment of the device management method. Further, step S350 or step S380 includes steps S410 to S470, and in this embodiment, a storage device (first storage device 200a or second storage device 200b) and a storage control circuit (first storage control circuit 120a or second storage control circuit 120b) are used for illustration. First, the storage device performs a transmission test and a receive test with the current transmission configuration. If the transmission test and receive test of the storage device fail, the transmission configuration is adjusted downwards, and transmission and receive tests are performed again. If the transmission test and receive test of the storage device succeed, the current transmission configuration is taken as the best available transmission configuration for the storage device. In step S410, a transmission test is performed. In this embodiment, the processor circuit 110 causes the storage control circuit to perform a transmission test, so that instructions and data are provided to the storage device at different phases under the current transmission configuration. In step S420, it is determined whether the transmission test is successful. If it is successful, step S440 is performed; otherwise, step S430 is performed. In this embodiment, the processor circuit 110 responds to the transmission test results of different phases of the storage device under the current transmission configuration and determines whether the transmission test of the storage device under the current transmission configuration is successful. Specifically, when the transmission test result of at least one phase of the storage device under the current transmission configuration is successful, the processor circuit 110 determines that the transmission test result of the storage device under the current transmission configuration is successful.

[0034] In step 430, the transmission configuration is downgraded. Since the transmission test result of the storage device in the current transmission configuration failed in step S420, the processor circuit 110 downgrades the transmission configuration of the storage device and then performs step S410 again. This downgrade involves updating the current transmission configuration with a clock frequency or transmission mode configuration lower than the current transmission configuration. For example, the current transmission configuration is downgraded from high-speed DDR mode to high-speed SDR mode, or the current clock frequency configuration is downgraded from 52MHz to 50MHz.

[0035] In step S440, a receive test is performed. In this embodiment, based on a successful transmission test, the processor circuit 110 further causes the storage control circuit to perform a receive test, so that instructions and data are provided and written to the storage device at different phases under the current transmission configuration.

[0036] In step S450, it is determined whether the reception test was successful. If the determination is yes, proceed to step S470 and return to step S360 above; otherwise, proceed to step S460. In this embodiment, the processor circuit 110 responds to the reception test results of different phases of the storage device under the current transmission configuration and determines whether the reception test of the storage device under the current transmission configuration was successful. Specifically, if the reception test result of at least one phase of the storage device under the current transmission configuration is successful, the processor circuit 110 determines that the reception test result of the storage device under the current transmission configuration is successful. That is, the current transmission configuration is the best available transmission configuration for the storage device and is the transmission configuration with the highest transmission rate among the transmission configurations that the storage device can execute.

[0037] In step S460, the transmission configuration is downgraded. Since the processor circuit 110 failed the reception test of the storage device in the current transmission configuration in step S450, the processor circuit 110 downgrades the transmission configuration of the storage device and then performs step S440 again. The downgrade is similar to step S430, so it will not be described again here.

[0038] In summary, the embedded storage device of this application can confirm the operable transmission configuration of multiple storage devices, enabling multiple storage devices to perform read and write operations with the same transmission configuration. Therefore, the embedded storage device of this application does not need to frequently switch read and write modes and speeds to perform read and write operations on multiple storage devices, effectively reducing the overall power consumption of the embedded storage device and reducing jitter. This allows the manufacturing of the embedded storage device to be free from consideration of differences in storage device specifications and firmware, and increases the number of storage devices that can be accommodated, achieving the goal of easily being compatible with a large number of storage devices. In addition, the downward alignment of the transmission configuration of the storage devices can quickly obtain the transmission configuration with the highest transmission rate when all storage devices are operable, speeding up device initialization and effectively improving the overall operating efficiency of the embedded storage device.

[0039] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0040] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms fall within the scope of protection of this application.

Claims

1. A device management method for an embedded storage device, the embedded storage device comprising multiple storage devices, characterized in that, The steps of the equipment management method include: The firmware versions of the multiple storage devices were determined respectively; Based on the firmware versions of the plurality of storage devices, the transport configuration of at least one of the plurality of storage devices is down-aligned to determine the final available transport configuration; and Enable the plurality of storage devices to perform read and write operations with the same ultimately available transfer configuration; The step of down-aligning the transmission configuration of at least one of the plurality of storage devices to determine the final available transmission configuration includes: The plurality of storage devices are made to perform a self-test procedure to determine the optimal available transmission configuration for each of the plurality of storage devices, wherein the optimal available transmission configuration is the transmission configuration that each of the plurality of storage devices can execute and has the highest transmission rate. When the optimal available transport configurations of the plurality of storage devices do not match, the transport configurations of at least one of the plurality of storage devices are down-aligned.

2. The device management method for an embedded storage device as described in claim 1, characterized in that, The step of down-aligning the transfer configuration of at least one of the plurality of storage devices to determine the final available transfer configuration includes: When the firmware versions of the plurality of storage devices are different from each other, the transmission configuration of at least one of the plurality of storage devices is down-aligned.

3. The device management method for an embedded storage device as described in claim 1, characterized in that, The step of down-aligning the transfer configuration of at least one of the plurality of storage devices to determine the final available transfer configuration includes: When the optimal available transport configurations of the plurality of storage devices match each other, the plurality of storage devices use the matched optimal available transport configuration as the final available transport configuration.

4. The device management method for an embedded storage device as described in claim 2, characterized in that, When the firmware versions of the plurality of storage devices are different from each other, the step of down-aligning the transport configuration of at least one of the plurality of storage devices includes: A preset transmission configuration is generated based on the firmware version of the plurality of storage devices, and the transmission configuration of at least one of the plurality of storage devices is updated with the preset transmission configuration, wherein the transmission rate of the optimal available transmission configuration is less than or equal to the transmission rate of the preset transmission configuration.

5. The device management method for an embedded storage device as described in claim 1, characterized in that, When the optimal available transport configurations of the plurality of storage devices do not match, the step of down-aligning the transport configurations of at least one of the plurality of storage devices includes: A preset available transport configuration is generated based on the optimal available transport configurations that do not match the plurality of storage devices, and the transport configuration of at least one of the plurality of storage devices is updated with the preset available transport configuration.

6. The device management method for an embedded storage device as described in claim 1, characterized in that, The self-test procedure includes: The storage device is configured to perform both transmit and receive tests using the current transmit configuration. When the transmission test and the reception test of the storage device fail, the transmission configuration is adjusted downwards, and the transmission test and the reception test are performed again; and When the transmission test and the reception test of the storage device are successful, the current transmission configuration is taken as the optimal available transmission configuration of the storage device.

7. The device management method for an embedded storage device as described in claim 6, characterized in that, The downward adjustment of the transmission configuration is to update the current transmission configuration with a clock frequency configuration or transmission mode configuration that is lower than the current transmission configuration.

8. An embedded storage device, characterized in that, include, The main control circuit, coupled to the plurality of storage devices, is used to execute the device management method of claim 1.

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