Shared command shifter system and method

Abstract

The present application relates to shared command shifter systems and methods. The systems and methods described herein relate to a device that can receive multiple commands and generate a common command indicating a matching data signal between each of the multiple commands. The device can include a first latch that receives a shifted flag and outputs a shifted command in response to a first enable signal. The device can include a shifter, wherein a first shifter can receive the common command and a last shifter can be coupled to the first latch. The last shifter can receive a shifter common command and can generate the first enable signal using the shifted common command.

Description

Technical Field

[0001] The present disclosure relates generally to memory devices, and more particularly, to systems and methods for merging different memory commands into a common command to enable more efficient command shifting. Background Art

[0002] This section is intended to introduce the reader to various aspects of the technology that may be related to various aspects of the technology described and / or claimed below. It is believed that this discussion helps to provide the reader with background information to promote a better understanding of various aspects of the present disclosure. Therefore, it should be understood that these statements should be read in this light, and not as an admission of the prior art.

[0003] In general, a computing system may include electronic devices that communicate information via electrical signals during operation. For example, a computing system may include a processor communicatively coupled to a memory device, such as a dynamic random access memory (DRAM) device arranged on a dual in-line memory module (DIMM). In this manner, the processor may communicate with the memory device to, for example, retrieve executable instructions, retrieve data to be processed by the processor, and / or store data output from the processor.

[0004] In response to memory commands, such as read commands, write commands, etc., data may be exchanged between the memory device and the processor. The memory commands may be transmitted through a command shifter. The corresponding commands may be transmitted through a corresponding command shifter. However, as the complexity of the device increases, the amount of space (e.g., footprint) dedicated to the command shifter may increase, which may increase the overall size of the computing subsystem and / or the memory device. Summary of the invention

[0005] In one aspect, the present application provides a device comprising: an input stage configured to receive multiple commands and generate a common command indicating a matching data signal between each of the multiple commands; a first latch configured to receive a shifted flag and output the shifted command in response to a first enable signal; and a command shifter comprising multiple shifters, wherein a first shifter of the multiple shifters is configured to couple to the input stage to receive the common command, wherein a second shifter of the multiple shifters is configured to couple to the first latch, and wherein the second shifter receives the common command from the first shifter and generates the first enable signal using the common command.

[0006] In another aspect, the present application provides a method of operating a memory device, comprising: receiving a first memory command via an input stage of a circuit; generating a common command via the input stage, the common command including a portion of the first memory command that matches a portion of a second memory command also received at the input stage; shifting the common command via a command shifter of the circuit; transmitting a first enable signal via the command shifter to a storage and processing stage of a flag decoder, the flag decoder being configured to transmit a decoded flag corresponding to the first memory command, wherein the first enable signal is generated in response to shifting the common command through a corresponding shifter of the command shifter; and transmitting a second enable signal via the command shifter to a clock gate of the flag decoder, wherein the clock gate is configured to receive a shifted command flag from the storage and processing stage, wherein the clock gate is configured to transmit the first command in response to the second enable signal to align the timing of the first command with an edge of the second enable signal, and wherein the first command is transmitted in conjunction with the shifted command.

[0007] In another aspect, the present application provides a system comprising: a command decoder configured to receive instructions from a processing circuit system of a host device and generate multiple memory commands based on the instructions; a shift circuit system coupled to the command decoder, wherein the shift circuit system is configured to receive the multiple memory commands from the command decoder and transmit the multiple memory commands after shifting the multiple memory commands, wherein in order to transmit the multiple memory commands, the shift circuit system is configured to: receive the multiple memory commands; transmit a data signal as a common command via a command shifter, the data signal including a signal common to each of the multiple memory commands; transmit a data signal including signals that are different between subsets of the multiple memory commands via a flag decoder; and capture the multiple memory commands as multiple shifted memory commands from an output from the command shifter and an output from the flag decoder; and a memory storage body control circuit system configured to receive the multiple shifted memory commands. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure may be better understood after reading the following detailed description and referring to the accompanying drawings, in which:

[0009] Figure 1 is a block diagram of a memory device according to an embodiment;

[0010] Figure 2 According to an embodiment, a command shifter and a flag decoder are included. Figure 1 a block diagram of a portion of a memory device;

[0011] Figure 3 is the input to the embodiment according to Figure 2 A timing diagram of signals of a command shifter and / or a flag decoder;

[0012] Figure 4 is a method for generating a common command according to an embodiment Figure 3 The signal and Figure 2 A timing diagram of a command shifter shifting some of the signals generated by the common command;

[0013] Figure 5 According to the embodiment Figure 3 The input command flag and the Figure 2 The sign decoder shifts the input sign and produces a subsequently shifted input sign compared to the Figure 4 Timing diagram of common commands;

[0014] Figure 6 is compared to the resulting shifted command transmitted from the flag decoder according to an embodiment Figure 4 The common order and Figure 5 The timing diagram of the shifted input flag;

[0015] Figure 7 A command shifter and an address shifter stage according to an embodiment of the present invention Figure 2 A block diagram of a logo decoder; and

[0016] Figure 8 A command shifter and a sampling stage according to an embodiment Figure 2 Block diagram of the logo decoder. DETAILED DESCRIPTION

[0017] One or more specific embodiments will be described below. In order to provide a brief description of these embodiments, not all features of the actual implementation will be described in this specification. It should be understood that in the development process of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions are made to achieve the specific goals of the developer, such as complying with system-related and enterprise-related constraints that may vary between various implementations. In addition, it should be understood that such development efforts may be complex and time-consuming, but will be a routine of design, construction, and manufacture for those skilled in the art who benefit from this disclosure.

[0018] When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements in addition to the listed elements. Additionally, it should be understood that references to "one embodiment" or "an embodiment" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

[0019] In general, a computing system may include electronic devices that communicate information via electrical signals during operation. For example, an electronic device in a computing system may include a processor communicatively coupled to a memory. In this manner, in response to a memory command to read or write data, the processor may communicate with the memory to retrieve executable instructions, retrieve data to be processed by the processor, store data output from the processor, or any combination thereof.

[0020] Memory commands transmitted within a computing system may be transmitted through one or more command shifters. Typically, memory commands may be transmitted one by one through the command shifters. As the complexity of the system increases, an increasing amount of the footprint of the computing system may be dedicated to the command shifters, and an increasing amount of processing time may be devoted to the shift operations. For purposes of discussion, the commands discussed may be converted to memory commands. However, it should be understood that any suitable group of commands transmitted within or between computing systems and having a common command portion (e.g., matching data bits) may be transmitted using the systems and methods described herein.

[0021] Sometimes, groups of memory commands may be shifted by the same amount. However, when groups of memory commands are processed together, the operational requirements and size of the computing device may be improved (e.g., reduced). Thus, the agent passes individual commands through individual shifters, and a single command shifter may be used to process a "common command." One or more flags may be set with the incoming common command, which contains information for decoding the corresponding command being shifted. The flags may be decoded as the command shift occurs. Thus, when the shifted common command arrives at the exit point from the command shifter, the decode type is ready and can be used to split the common command into one of multiple transmission or processing paths.

[0022] By using the same shifter to process groups of memory commands, the circuitry footprint dedicated to the command shifter and the processing time dedicated to the shift operations can be reduced. For example, by combining the shift operations, the footprint for processing four memory commands and two memory addresses can be reduced to 1 / 6 of its original footprint, which achieves a 6:1 area savings. In addition, managing the timing constraints of a single command shifter versus multiple command shifters may be less complex.

[0023] The processing of common commands may also reduce the number of flags associated with an incoming command to be processed, which may reduce the time taken to decode. For example, a command may be transmitted by an address flag to identify the target memory location, and a command may be transmitted by a type flag to identify whether it is a read or write command and to identify the type of read or write command. However, when processing common commands, some flags may be processed at a time offset from the common command shift. Therefore, the common command decoding operation may become faster because the command shifter may begin shifting the common command before all flags for each command arrive.

[0024] Additional benefits may arise from using a common command shift operation. For example, when a memory controller receives a command, the transmission of the command may introduce a delay. The delay may be an offset from the timing of the transmission, such as the transmission between the command source and the command decoder. However, such delays may be compensated for by using a back-off operation that uses multiple clocks to advance sequential stages of a shifter that shifts a common command compared to the same sequential shift clock. By shifting each stage of the shifter using multiple clocks with different clock transitions, the encoded shifter stages may be used to advance the command at a steadily increasing rate to compensate and counteract the delay. Thus, the shifted command output from the final stage of the shifter may be output in response to a clock signal having a time period that is less than the time period of the clock signal that operates the first stage of the shifter.

[0025] Now turning to the figures, Figure 1 is a simplified block diagram illustrating certain features of memory device 10. Specifically, Figure 1 The block diagram of FIG. 1 is a functional block diagram illustrating certain functionality of the memory device 10. According to one embodiment, the memory device 10 may be a fifth generation double data rate synchronous double data rate dynamic random access memory (DDR5 SDRAM) device. Various features of the DDR5 SDRAM may permit reduced power consumption, increased bandwidth, and increased storage capacity compared to previous generations of DDR SDRAM.

[0026] The memory device 10 may include a plurality of memory banks 12. For example, the memory banks 12 may be DDR5 SDRAM memory banks. The memory banks 12 may be provided on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). Each DIMM may include a plurality of SDRAM memory chips (e.g., x8 or x16 memory chips), as will be appreciated. Each SDRAM memory chip may include one or more memory banks 12. The memory device 10 represents a portion of a single memory chip (e.g., SDRAM chip) having a plurality of memory banks 12. For DDR5, the memory banks 12 may be further arranged to form bank groups. For example, for an 8-gigabit (Gb) DDR5 SDRAM, the memory chip may include 16 memory banks 12, arranged into 8 bank groups, each bank group including 2 memory banks. For example, for 16Gb DDR5 SDRAM, the memory chip may include 32 memory banks 12, arranged into 8 bank groups, each bank group including 4 memory banks. Various other configurations, organizations, and sizes of the memory banks 12 on the memory device 10 may be utilized depending on the application and design of the overall system.

[0027] The memory device 10 may include a command interface 14 and an input / output (I / O) interface 16 configured to exchange (e.g., receive and transmit) signals with an external device. The command interface 14 is configured to provide a plurality of signals (e.g., signal 8) from an external device (not depicted), such as a processor or controller. The processor or controller may provide various signals 8 to the memory device 10 to facilitate the transmission and reception of data to be written to or read from the memory device 10.

[0028] As will be appreciated, the command interface 14 may include a plurality of circuits, such as a clock input circuit 18 and a command address input circuit 20, such as to permit proper processing of the signal 8. The command interface 14 may receive one or more clock signals from an external device. In general, double data rate (DDR) memories utilize a differential pair of system clock signals referred to as a true clock signal (Clk_t) and a complementary clock signal (Clk_c). A positive clock edge of DDR refers to the point at which a rising true clock signal (Clk_t) crosses a falling complementary clock signal (Clk_c), while a negative clock edge indicates a transition of a falling true clock signal (Clk_t) and a rise of a complementary clock signal (Clk_c). Commands (e.g., read commands, write commands, refresh commands) typically enter on the positive edge of the clock signal, and data is transmitted or received on both the positive and negative clock edges.

[0029] The clock input circuit 18 receives the true clock signal (Clk_t) and the complementary clock signal (Clk_c) and generates an internal clock signal (CLK). The internal clock signal (CLK) is supplied to an internal clock generator 30, such as a delay locked loop (DLL) circuit. The internal clock generator 30 generates a phase-controlled internal locked clock signal (LCLK) based on the received internal clock signal (CLK). The phase-controlled internal locked clock signal (LCLK) is supplied to, for example, the I / O interface 16 and is used as a timing signal for determining the output timing of read data.

[0030] The internal clock signal (CLK) may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal (CLK) may be provided to a command decoder 32. The command decoder 32 may receive the command signal from the command bus 34 and may decode the command signal to provide various internal commands. For example, the command decoder 32 may provide the command signal to the internal clock generator 30 via the bus 36 to coordinate the generation of the phase-controlled internal locked clock signal (LCLK). The phase-controlled internal locked clock signal (LCLK) may be used to clock data, such as through the I / O interface 16.

[0031] The command decoder 32 may decode commands such as read commands, write commands, mode register set commands, activate commands, etc., and provide access to the specific memory bank 12 corresponding to the command via the bus path 40. As will be appreciated, the memory device 10 may include various other decoders, such as row decoders and column decoders, to facilitate access to the memory banks 12. In one embodiment, each memory bank 12 includes a bank control block 22 that provides the necessary decoding (e.g., row decoders and column decoders) and other operations, such as timing control and data control, to facilitate execution of commands to and from the memory bank 12. The memory banks 12 and bank control blocks 22 may be collectively referred to as a memory array.

[0032] The memory device 10 performs operations such as read commands and write commands based on command / address signals received from an external device such as a processor. In one embodiment, the command / address bus may be a 14-bit bus (CA<13:0>) for accommodating command / address signals. The command / address signals are clocked to the command interface 14 using clock signals (Clk_t and Clk_c). The command interface may include a command address input circuit 20 that is configured to receive and transmit commands to provide access to the memory banks 12 through, for example, a command decoder 32. In addition, the command interface 14 may receive a chip select signal (CS_n). The CS_n signal causes the memory device 10 to process commands incoming on the CA<13:0> bus. Access to a particular memory bank 12 within the memory device 10 is encoded on the CA<13:0> bus by a command.

[0033] In addition, the command interface 14 may be configured to receive a plurality of other command signals. For example, a command / address on-die termination (CA_ODT) signal may be provided to facilitate proper impedance matching within the memory device 10. For example, a reset command (RESET_n) may be used to reset the command interface 14, a status register, a state machine, etc. during power-up. The command interface 14 may also receive a command / address inversion (CAI) signal, which may be provided to, for example, invert the state of the command / address signal (CA<13:0>) on the command / address bus depending on the command / address routing of the particular memory device 10. A mirror (MIR) signal may also be provided to facilitate mirroring functionality. Based on the configuration of multiple memory devices in a particular application, the MIR signal may be used to multiplex signals so that they may be swapped for implementing a particular routing of signals to the memory device 10. Various signals for facilitating testing of the memory device 10, such as a test enable (TEN) signal, may also be provided. For example, the TEN signal may be used to place the memory device 10 in a test mode for connectivity testing.

[0034] The command interface 14 may also be used to provide an alert signal (ALERT_n) to a system processor or controller for certain errors that may be detected. For example, if a cyclic redundancy check (CRC) error is detected, an alert signal (ALERT_n) may be transmitted from the memory device 10. Other alert signals may also be generated. In addition, the bus and pins used to transmit the alert signal (ALERT_n) from the memory device 10 may be used as input pins during certain operations, such as the connectivity test mode performed using the TEN signal as described above.

[0035] By transmitting and receiving data signals 44 through the I / O interface 16, data can be sent to and from the memory device 10, thereby utilizing the command and timing signals discussed above. More specifically, data can be sent to or retrieved from the memory bank 12 through the data path 46, which includes a plurality of bidirectional data buses. Data I / O signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For certain memory devices, such as DDR5 SDRAM memory devices, the I / O signals can be divided into upper and lower bytes. For example, for a x16 memory device, the I / O signals can be divided into upper and lower I / O signals, such as DQ<15:8> and DQ<7:0>, corresponding to the upper and lower bytes of the data signals.

[0036] To allow for higher data rates within the memory device 10, certain memory devices, such as DDR memory devices, may utilize a data strobe signal, commonly referred to as a data strobe (DQS) signal. The DQS signal is driven by an external processor or controller that sends data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For a read command, the DQS signal is actually an additional data output (DQ) signal with a predetermined pattern. For a write command, the DQS signal is used as a clock signal to capture the corresponding input data. Like the clock signal (Clk_t and Clk_c), the DQS signal may be provided as a differential pair (DQS_t and DQS_c) of data strobe signals to provide differential pair signaling during read and write. For certain memory devices, such as DDR5 SDRAM memory devices, the differential pair of DQS signals can be divided into upper and lower data select signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c), which correspond to, for example, upper and lower bytes of data sent to and from the memory device 10.

[0037] An impedance (ZQ) calibration signal may also be provided to the memory device 10 through the I / O interface 16. The ZQ calibration signal may be provided to a reference pin and may be used to tune the output driver and on-die termination (ODT) value by adjusting the pull-up and pull-down resistors of the memory device 10 in changes in process, voltage, and temperature (PVT) values. Because PVT characteristics may affect the ZQ resistor value, the ZQ calibration signal may be provided to the ZQ reference pin for adjusting the resistance to calibrate the input impedance to a known value. As will be appreciated, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and a ground (GND) or low supply voltage (VSS) external to the memory device 10 (GND / VSS). This resistor acts as a reference for adjusting the internal on-die termination (ODT) and drive strength of the I / O pins.

[0038] In addition, a loopback signal (LOOPBACK) may be provided to the memory device 10 through the I / O interface 16. The loopback signal may be used during a test or debug phase to set the memory device 10 into a mode where the signal is looped back through the memory device 10 through the same pin. For example, the loopback signal may be used to set up the memory device 10 to test the data output of the memory device 10. The loopback may include both data and strobe, or may include a data pin to provide data and / or strobe. This is generally intended for monitoring data captured by the memory device 10 at the I / O interface 16.

[0039] Various other components may also be incorporated into the memory device 10, such as a power supply circuit (for receiving high power supply (VDD) and VSS signals), a mode register (for defining various modes of programmable operation and configuration), a read / write amplifier (for amplifying signals during read / write operations), a temperature sensor (for sensing the temperature of the memory device 10), etc. Figure 1 1 is a block diagram to highlight certain functional features of the memory device 10 to assist in the subsequent detailed description.

[0040] In some embodiments, the memory device 10 may be disposed in a host device (physically integrated into or otherwise connected to the host device) or otherwise coupled to the host device. The host device may include any of a computing system, a desktop computer, a laptop computer, a pager, a cellular phone, a personal assistant, a portable audio player, a control circuit, a camera, etc. The host device may also be a network node, such as a router, a server, or a client (e.g., one of the computers of the types previously described). The host device may be some other kind of electronic device, such as a copier, a scanner, a printer, a game console, a television, a set-top video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, or a medical device, etc. As with many other terms used herein, the terms used to describe these various examples of the system may share some referents, and therefore should not be interpreted narrowly by means of the other items listed.

[0041] Thus, a host device may generally be a processor-based device that may include a processor, such as a microprocessor, that controls system functions and processing of requests in the host device. In addition, any host processor may include multiple processors that share system control. The host processor may be coupled directly or indirectly to additional system elements of the host device such that the host processor controls the operation of the host device by executing instructions that may be stored within the host device or external to the host device.

[0042] As discussed above, data may be written to and read from the memory device 10, for example, by a host device, whereby the memory device 10 acts as a volatile memory, such as a double data rate DRAM (e.g., DDR5 SDRAM). In some embodiments, the host device may also include a separate non-volatile memory, such as a read-only memory (ROM), a random access memory (RAM), a personal computer RAM (PC-RAM), a silicon-oxide-nitride-oxide-silicon (SONOS) memory, a metal-oxide-nitride-oxide-silicon (MONOS) memory, a polysilicon floating gate-based memory, and / or other types of flash memory of various architectures (e.g., NAND memory, NOR memory, etc.), as well as other types of memory devices (e.g., storage devices), such as a solid-state drive (SSD), a multimedia media card (MMC), a secure digital (SD) card, a flash memory (CF) card, or any other suitable device. In addition, it should be appreciated that the host device may include one or more external interfaces, such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Small Computer System Interface (SCSI), Institute of Electrical and Electronics Engineers (IEEE) 1394 (Firewire), or any other suitable interface, and one or more input devices for allowing a user to input data into the host device, such as by using buttons, switch elements, keyboard, light pen, stylus, mouse, and / or voice recognition system. The host device may also optionally include output devices such as a display coupled to the processor, and a network interface device such as a network interface card (NIC) for interfacing with a network such as the Internet. As will be appreciated, the host device may include many other components depending on the application of the host device.

[0043] The host device is operable to transfer data to the memory device 10 for storage, and may read data from the memory device 10 to perform various operations at the host device. Therefore, to facilitate these data transfers, in some embodiments, the I / O interface 16 may include a data transceiver that operates to receive and transmit DQ signals to and from the I / O interface 16.

[0044] Keeping the above in mind, Figure 21 is a block diagram of shift circuitry of a memory device 10 that includes, for example, a command shifter 60 within a command decoder 32, between the command decoder 32 and the command interface 14, or other suitable circuitry. The shift circuitry may receive a memory command communicated to a control circuitry (e.g., the memory bank control circuitry 22) to instruct the performance of a memory operation, such as a refresh operation, a read operation, a write operation, etc. For ease of discussion, the command shifter 60 is described as being included within the command decoder 32. The command shifter 60 may be coupled to a flag decoder 62 that processes flags that at least partially overlap in time with the shifting of a common command 64.

[0045] The command shifter 60 may receive a common command 64 at a logic gate 66 input stage. The common command 64 may be a logical result output from a logic gate 66 (e.g., an OR gate). The logic gate 66 may receive commands 68 (e.g., command A 68A, command B 68B, command C 68C, and command D 68D) and output the common command 64 in response to an activation voltage level. The edges of the respective commands 68 (e.g., rising edge, falling edge) may be spaced apart in time relative to each other according to a duration, such as 8 clock cycles between a rising edge of command A 68A and a rising edge of command B 68B. The logic gate 66 output may switch over time in response to the input command signal 68. In response to transmitting the command 68 over time via the logic gate 66, this may generate a common command 64 having multiple pulses.

[0046] The command shifter 60 may include shifters 70 (shifter 70A, shifter 70B, shifter 70C, shifter 70D, shifter 70E). The shifters 70 may be latch circuit systems coupled in series and may include any number of shift circuit systems n. Each shifter 70 may latch an input signal in response to an edge (e.g., rising edge, falling edge) of a clock signal 72. The shifters 70 may be D flip-flops, set-reset (SR) flip-flops, input / output latches, AND logic gates, OR logic gates, NOR logic gates, NAND logic gates, inverters, or any suitable combinational logic circuit systems that generate signals or hold states for transmission in response to a clock transition, such as a rising edge of a clock signal 72. The shifter 70A may receive a common command 64 and transmit the common command 64 in response to a change in the clock signal 72. After sequential transmission through each of the shifters 70, the common command 64 may be transmitted to the flag decoder 62 as an enable signal 74. The enable signal 74 may cause the transmission of the shifted commands 76 (shifted command A 76A, shifted command B 76B, shifted command C 76C, shifted command D 76D).

[0047] The flag decoder 62 may receive a first command flag 82 and a second command flag 84 at the decoder 86. The first command flag 82 may correspond to a read (RD) flag. The second command flag 84 may correspond to a non-target (NT) flag. The first command flag 82 and the second command flag 84 may together define the type of the memory command as a read command (e.g., RD=1, NT=0), a read non-target command (e.g., RD=1, NT=1), a write command (e.g., RD=0, NT=0), or a write non-target command (e.g., RD=0, NT=1).

[0048] The decoder 86 may be a 2:4 decoder that generates four signals from two signals, but any appropriately sized decoder may be used. The decoder 86 may generate four decoded command flags 88 (decoded command flag 88A, decoded command flag 88B, decoded command flag 88C, decoded command flag 88D) using the first command flag 82 and the second command flag 84. The first command flag 82 and the second command flag 84 may be written to the decoder 86 and may represent values ​​associated with the command 68 over time. The flag decoder 62 may decode the value of the information transmitted as the first command flag 82 and the second command flag 84 to generate an indication of a specific command type to be processed before being output from the flag decoder 62 via the shifted command 76.

[0049] An intermediate storage stage, namely a storage and processing stage 90, may be used to create a suitable holding margin for the decoded command flags 88 before reaching an exit stage (e.g., clock gate 80). The first command flag 82 and the second command flag 84 may be received and / or processed at a relatively faster rate than the shift common command 64. The storage and processing stage 90 may latch the value of the decoded command flag 88 until an enable signal 92 is received that triggers the output of the shifted flags 94 (shifted flag A 94A, shifted flag B 94B, shifted flag C 94C, shifted flag D 94D) from the clock gate 80 over time, respectively.

[0050] Thus, the storage and processing stage 90 can ensure that there is a 1:1 correspondence between the output shifted flags 78 and the shifted common command output from the command shifter 60 as the enable signal 74. The holding margin of the storage and processing stage 90 can be such that the reception of the shifted flags 94 at the exit stage (e.g., the corresponding clock gate 80) occurs before the edge of the enable signal 92. The enable signal 92 can cause the shifted flags 94 to be transmitted from the clock gate 80 as the shifted command 76 or through the shifted command 76. For example, the corresponding clock gate 80 can transmit the signal as the corresponding shifted command 76 after aligning the signal to the edge of the enable signal 74, and can append the corresponding shifted flags 94 to the beginning or end of the shifted command 76. The clock gate 80 receives different shifted flags 94 at different times relative to each other, so that different edges of the enable signal 74 clock out different corresponding shifted commands 76. The timing of the corresponding shifted command 76 output from the flag decoder 62 may be aligned to correspond to the start time of receipt of the enable signal 74 at the clock gate 80 .

[0051] To elaborate, Figures 3 to 6 60 and / or flag decoder 62. The timing diagram illustrates digital logic signals that vary between a logic low voltage level (e.g., “0”) and a logic high voltage level (e.g., “1”). It should be understood that any suitable voltage levels may be used as the logic high voltage level and / or the logic low voltage level. The labels used for the timing diagram correspond to Figure 2 of the mark, and therefore Figures 2 to 6 are mentioned together in this article.

[0052] Figure 3 is a timing diagram of the command 68 , the first command flag 82 , and the second command flag 84 . Figure 2 The logic gate 66 may receive a command 68 that initiates a shift operation of the command shifter 60. The flag decoder 62 may receive a first command flag 82 and a second command flag 84 in association with the command shifter 60 receiving the command 68. The respective command 68 is substantially aligned in time with the transmission of the first command flag 82 and the second command flag 84 of their corresponding values.

[0053] To elaborate, the pulse of command A 68A is generally aligned with the rising edge of the first command flag 82. The flag of command A 68A may be sampled at time 106 (e.g., a time duration generally corresponding to "1"), such as approximately 7.5 nanoseconds (ns). When sampled, the flag of command A 68A corresponds to a combination of RD=1 and NT=0. As described above, this combination of flags may indicate a read command. Therefore, command A 68A may indicate a read command. At time 106, command A 68A may be inactive and pulse transmission may be completed. The flag decoder 62 may align the value of the sampled flag with the timing of the command A 68A pulse in response to the enable signal 92 and the enable signal 74 to regenerate the command A 68A pulse from the shift of the common command 64.

[0054] Similar sampling may occur again at approximately 10 ns (e.g., "2"), 12.5 ns (e.g., "3"), and 15 ns (e.g., "4"). The sampling may generate a flag corresponding to command B 68B for the RD=1 and NT=1 combination, a flag corresponding to command C 68C for the RD=0 and NT=0 combination, and a flag corresponding to command D 68D for the RD=0 and NT=1 combination. Thus, command B 68B may indicate a read non-target command, command C 68C may indicate a write command, and command D 68D may indicate a write non-target command.

[0055] Figure 4 6 is a timing diagram of the command 68 and the common command 64 sampled after the different shifters 70 during the entire shift period. The command 68 can be a logic gate 66 at Figure 2 , for starting the shift operation. When the common command 64 is sampled after being transmitted through the first shifter (e.g., shift (1)) of the shifter 70, the common command at shift (1) (e.g., signal 108) may correspond to the sampled result. It should be noted that Figure 2 Examples of may have any number of shifters 70, but for purposes of description, Figures 3 to 6 Six shifters are described, called the first shifter (shift(1)), the second shifter (shift(2)), the third shifter (shift(3)), the fourth shifter (shift(4)), the fifth shifter (shift(5)), and the sixth shifter (shift(6)). Similar to Figure 2, logic gate 66 may be coupled to the input of the first shifter, the fourth shifter may be coupled to storage and processing stage 90 to transmit enable signal 92, and the sixth shifter may be coupled to clock gate 80 to transmit enable signal 74. Similarly, when the common command 64 is sampled after transmission through the second shifter (e.g., shift (2)) of shifter 70, the common command at shift (2) (e.g., signal 110) may correspond to the sampled result. Likewise, the common command at shift (3) (e.g., signal 112) may correspond to the output from the third shifter, the common command at shift (4) (e.g., signal 114) may correspond to the output from the fourth shifter, the common command at shift (5) (e.g., signal 116) may correspond to the output from the fifth shifter, and the common command at shift (6) (e.g., signal 118) may correspond to the output from the sixth shifter. As can be appreciated from the timing diagram, the common command 64 is incrementally shifted through each shifter 70 over time. As the common commands 64 are shifted through the command shifter 60, each respective timing duration between pulses corresponding to each command 68 remains unchanged when compared to the sequential duration between initially received pulses of the commands 68. For example, the time period between the rising edge of command A 68A and the rising edge of command B 68B may be substantially maintained at duration 120 throughout transmission through the command shifter 60.

[0056] To further explain the processing relationship between the flag and the common command 64, Figure 5 8 is a timing diagram that includes a common command (e.g., signal 108) at shift (1) (e.g., generally indicating common command 64 before shifting occurs) compared to the timing of flags through various stages of flag decoding and shifting performed by flag decoder 62. The first command flag 82 and the second command flag 84 are shown in the timing diagram as they would be received by decoder 86. Decoder 86 decodes the first command flag 82 and the second command flag 84 into respective command flags and may generate decoded command flag 88. It should be noted that respective rising edges of decoded command flag 88 are aligned with respective rising edges of respective command pulses (e.g., pulse "A", pulse "B", pulse "C", pulse "D") of the common command (e.g., signal 108) at shift (1). The decoded flag 88 may be received at storage and processing stage 90 at staggered times, as may be appreciated from the relative timing of the timing diagram signals.

[0057] To latch the decoded command flags 88, the common command 64 may be latched as the common command at shift (4) (e.g., signal 114) by the command shifter 60 after four cycles and transmitted to the storage and processing stage 90 as the enable signal 92. Since the pulse timing of the common command at shift (4) (e.g., signal 114) is aligned with the rising edge of the decoded command flags 88, the storage and processing stage 90 may capture corresponding ones of the decoded command flags 88 in response to the corresponding pulses, although the same enable signal 92 is transmitted to each storage and processing stage 90. For example, the decoded flag A 88A is latched at pulse "A", the decoded flag B 88B is latched at pulse "B", etc. In response to receiving the pulse of the common command (e.g., signal 114) at shift (4) as the enable signal 92, the corresponding storage and processing stage 90 may output the shifted flags 94, respectively.

[0058] The clock gate 80 may receive the active pulse of the common command (eg, signal 118) at shift (6) transmitted as the enable signal 74, respectively, via the shift flag 94 and wait for transmission, as in Figure 6 Detailed description in. Figure 6 is a timing diagram illustrating common command 64 after different shifters 70, shifted flags 94, and shifted commands 76. Each clock gate 80 may receive a corresponding one of the shifted flags 94 over time and wait for a corresponding enable signal 74 pulse before transmitting each corresponding one of the shifted flags 94 via a reconstructed shifted command 76. In response to a corresponding pulse of common command 64 output from the sixth shifter (e.g., common command at shift (6), signal 118), clock gate 80 may transmit shifted command 76.

[0059] Many types of signals may be transmitted through the command shifter 60. For example, similar to the first command flag 82 and the second command flag 84, any address associated with the group of commands 68 transmitted through the command shifter 60 may be processed. Figure 7 60, flag decoder 62, and address stage 140 (e.g., address stage 140A, address stage 140B). Address stage 140A may receive a burst-on-the-fly (BC-OTF) address 142 (e.g., a burst-chopping address) during a time period that partially overlaps with first command flag 82, second command flag 84, and command 68. Similar to first command flag 82 and second command flag 84, BC-OTF address 142 may vary with each command 68 (e.g., within a certain period of time). Figure 592). The address stage 140A may transmit the value of the BC-OTF address 142 to the address stage 140B in response to the enable signal 92. The address stage 140B may wait to transmit the value of the BC-OTF address 142 until the enable signal 92 is received. The address stage 140B may transmit the value of the BC-OTF address 142 as the shifted BC-OTF address 144 in response to the enable signal 74. The timing of the corresponding shifted flag 94 and the shifted command 76 may be aligned with the shifted BC-OTF address 144 outputted respectively.

[0060] In some embodiments, some commands may have a portion of the matching data, rather than a fully matched signal. A hybrid shift operation may be used to use a portion of the matching data as a common command. A hybrid shift operation may use a sampling block to isolate the matching data from the command group. Unmatched data may be transmitted via the flag decoder 62 similar to a flag or as a flag. This may be further beneficial when the command group to be transmitted via the common command includes one or more commands that are not normally associated with command flags, such as a mode register write (MRW).

[0061] Figure 860 and flag decoder 62 that implement a hybrid shift operation using sampling circuitry 160 as an input stage. For example, read training and write leveling commands may use a mode register write (MRW) command that is not associated with the signal to be decoded via flag decoder 62. Therefore, even though the MRW command may be shifted through command shifter 60 along with other commands 68, a command for the MRW command would not be output from clock gate 80 because the active shifted flags of shifted flags 94 would not correspond to the MRW command. To address this issue, portions of command 68 signals that are similar between commands 68 may be used instead of the entire command as a common command 64. Sampling circuitry 160 may generate a common command 64 by identifying matching data signals between each command 68. This identification may involve identifying which address bits or other data signals are shared (e.g., common) by each command 68. In some cases, the sampling circuit system 160 may also identify which data in the command 68 does not match, and may transmit the mismatched or uncommon data between the commands 68 via the flag decoder 62, similar to the command flags 82, 84 to be used as the shifted flags 94 when capturing the shifted command 76. Thus, in some cases, the command 68 transmitted to the command shifter 60 may bypass the logic gate 66 (or, as shown, exclude the logic gate 66 entirely), and the sampling circuit system 160 may sample a subset of the data bits transmitted as the command 68. The sampling circuit system 160 may transmit any number of common bits between the commands 160 as a common command 64, such as two bits, three bits, or more. In fact, this example emphasizes the flexibility of including a shared command shifter 60 in an electronic device and its ability to be a subset of the entire transmission path and have similar segment or clock mode signal transmission. Table 1 may detail the example command signals and provide a visualization of the common bits between the various commands 68.

[0062] Table 1

[0063] Function (command type) Address Bit 0 Address Bit 1 Address Bit 2 Address Bit 3 Address Bit 4 Mode Register Write (MRW) 1 0 1 0 0 Write (WR) 1 0 1 1 0 Write NT (WR-NT) 1 0 1 1 0 Read (RD) 1 0 1 1 1

[0064] In Table 1, each of the MRW, WR, WR-NT, and RD functions (e.g., command 68) has matching logic states for address bit 0 and address bit 1. Thus, command shifter 60 may shift the logic states for address bit 0 and address bit 1 when any of the listed functions are transmitted together as a common command 64. Address bit 2, address bit 3, and address bit 4 may be transmitted along with any additional flag or address signals via flag decoder 62, provided that the timing of the various additional information is aligned with the timing of enable signal 92 at storage and processing stage 90 and enable signal 74 at clock gate 80. These systems and methods may be applied to the transmission of any suitable command or communication signal that transmits logic data having a signal value, such as a particular communication application, data processing application, etc.

[0065] exist Figure 4 , although the duration 120 is described as being maintained during the shifting process, it should be noted that the duration 120 may be intentionally varied (e.g., phase shifted) to compensate for transmission delays in the transmitted commands 68 via command backoff. For example, the timing of the clock signal 72 may be adjusted to gradually compensate for changes or delays expected or experienced by the various commands 68. This may improve operational efficiency by combining the compensation operation with the shifting operation of the command shifter 60.

[0066] Thus, the present disclosure may describe systems and methods for achieving more efficient command and signal shifting within an electronic device. By using the same shifter to process groups of memory commands, the circuit system footprint dedicated to the command shifter and the processing time dedicated to the shift operation can be reduced. For example, by combining the shift operations, the footprint for processing four memory commands and two memory addresses can be reduced to 1 / 6 of its original footprint, which achieves a 6:1 area savings. In addition, managing the timing constraints of a single command shifter relative to multiple command shifters may be less complex. The encoding shifter stage described herein may produce additional benefits, such as the ability to perform a fallback operation while performing a shift operation. The processing of common commands may also reduce the number of flags associated with the incoming commands to be processed, which may reduce the time spent decoding.

[0067] Although various modifications and alternative forms may occur in the present disclosure, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed. In fact, the present disclosure is intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0068] The technology presented and claimed herein is referenced and applied to substantial objects and specific examples of a practical nature that improve the art in a demonstrable manner and are therefore not abstract, intangible, or purely theoretical. In addition, if any claim appended to the end of this specification contains one or more elements that are expressed as "means for [performing] [the function] ..." or "steps for [performing] [the function] ...", it is intended that such elements will be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim containing elements specified in any other manner, it is not intended that such elements will be interpreted in accordance with 35 U.S.C. 112(f).

Claims

1. A device comprising: an input stage configured to receive a plurality of commands and generate a common command indicative of a matching data signal between each of the plurality of commands; a first latch configured to receive a shifted flag and output a shifted command in response to a first enable signal; and A command shifter comprising a plurality of shifters, wherein a first shifter of the plurality of shifters is configured to couple to the input stage to receive the common command, wherein a second shifter of the plurality of shifters is configured to couple to the first latch, and wherein the second shifter receives the common command from the first shifter and generates the first enable signal using the common command.

2. The device according to claim 1, comprising: A third shifter is disposed between the first shifter and the second shifter, wherein the third shifter is configured to generate a second enable signal in response to receiving the common command and transmit the second enable signal to a second latch.

3. The device of claim 2, wherein the second latch is coupled to the third shifter, and wherein the second latch is configured to receive a decoded flag and output the decoded flag in response to the second enable signal.

4. The apparatus of claim 3 , comprising a decoder configured to generate four decoded flags based at least in part on two command flags corresponding to the plurality of commands, wherein the four decoded flags include the decoded flag, and wherein the value of each of the two command flags includes a value for each of the plurality of commands over time.

5. The apparatus of claim 1, wherein the input stage comprises sampling circuitry configured to identify the matching data signals between each of the plurality of commands based at least in part on identifying which address bits are shared by each of the plurality of commands.

6. The device of claim 5, wherein the sampling circuitry is configured to output the address bits as the common command.

7. The device of claim 6, wherein any remaining address bits of the plurality of commands are configured to be transmitted via a flag decoder, the flag decoder configured to recapture the plurality of commands based on the remaining address bits in response to outputting the common command from the second shifter.

8. The apparatus of claim 1, wherein the input stage comprises an OR logic gate.

9. The apparatus of claim 1, wherein a pair of address stages transmit burst chopping addresses during a time period that partially overlaps with transmission of the common command.

10. The apparatus of claim 1, wherein the plurality of commands comprises a read command, a read non-target command, a write command, a write non-target command, or any combination thereof.

11. A method of operating a memory device, comprising: receiving a first memory command via an input stage of the circuit; generating, via the input stage, a common command comprising a portion of the first memory command that matches a portion of a second memory command also received at the input stage; shifting the common command via a command shifter of the circuit; transmitting a first enable signal via the command shifter to a storage and processing stage of a flag decoder, the flag decoder configured to transmit a decoded flag corresponding to the first memory command, wherein the first enable signal is generated in response to shifting the common command through a corresponding shifter of the command shifter; and A second enable signal is transmitted via the command shifter to a clock gate of the flag decoder, wherein the clock gate is configured to receive a shifted command flag from the storage and processing stage, wherein the clock gate is configured to transmit a first command in response to the second enable signal to align timing of the first command with an edge of the second enable signal, and wherein the first command is transmitted in conjunction with the shifted command. 12 . The method of claim 11 , comprising generating the second enable signal as the common command via the command shifter.

13. The method according to claim 11, comprising: The first enable signal is transmitted via the command shifter to a plurality of storage and processing stages of the flag decoder, wherein the plurality of storage and processing stages includes the storage and processing stage.

14. The method of claim 13, wherein the plurality of storage and processing stages are configured to transmit respective decoded flags including the decoded flags at different times corresponding to rising edges of the common command.

15. The method of claim 14, wherein the respective decoded flags each comprise a combination of logic signals indicating a memory command type, the memory command type comprising a read command type, a read non-target command type, a write command type, and a write non-target command type.

16. A system comprising: a command decoder configured to receive instructions from processing circuitry of a host device and to generate a plurality of memory commands based on the instructions; a shift circuitry coupled to the command decoder, wherein the shift circuitry is configured to receive the plurality of memory commands from the command decoder and to transmit the plurality of memory commands after shifting the plurality of memory commands, wherein to transmit the plurality of memory commands, the shift circuitry is configured to: receiving the plurality of memory commands; transmitting a data signal as a common command via a command shifter, the data signal comprising a signal common to each of the plurality of memory commands; transmitting, via a flag decoder, a data signal including a signal that differs between subsets of the plurality of memory commands; and capturing the plurality of memory commands from an output from the command shifter and an output from the flag decoder as a plurality of shifted memory commands; and A memory bank control circuitry is configured to receive the plurality of shifted memory commands.

17. The system of claim 16, wherein the shift circuitry is configured to compensate for transmission delays during transmission of the plurality of memory commands through the command shifter via a fallback operation.

18. The system of claim 16, wherein the data signal common to each of the plurality of memory commands is generated in response to a logic gate that switches an output based on a corresponding active level of each of the plurality of memory commands.

19. The system of claim 16, wherein the shift circuitry comprises: an input stage configured to receive the plurality of memory commands and generate the common command; a first latch configured to receive a shifted flag corresponding to the data signal and to output a shifted command of the plurality of shifted memory commands in response to a first enable signal; and wherein the command shifter comprises a plurality of shifters, wherein a first shifter of the plurality of shifters is coupled to the input stage to receive the common command, wherein a last shifter of the plurality of shifters is coupled to the first latch, and wherein the last latch receives the common command from the first shifter and generates the first enable signal using the common command.

20. The system of claim 16, wherein the memory bank control circuitry is configured to write or read data from a memory bank in response to the plurality of shifted memory commands.

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