Semiconductor memory device and method of operating a semiconductor memory device

Abstract

The present technology relates to a semiconductor memory device and a method of operating a semiconductor memory device. The semiconductor memory device includes a memory block including a plurality of memory cells configured to be programmed to an erased state and a plurality of programmed states; a voltage generation circuit configured to generate a read voltage to be applied to a word line of the memory block during a read operation; and a read-write circuit connected to a bit line of the memory block and configured to latch data during the read operation by sensing a potential level of a sense node based on a cell current of the plurality of memory cells within a predetermined time unit; wherein the read voltage is continuously applied to the word line in a predetermined period, and gradually increases according to time in the predetermined period.

Description

Technical Field

[0001] This disclosure relates to electronic devices, and more particularly to semiconductor memory devices performing multilevel sensing operations and methods of operating semiconductor memory devices. Background Technology

[0002] Semiconductor memory devices are memory devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). Semiconductor memory devices are mainly divided into volatile memory devices and non-volatile memory devices.

[0003] Volatile memory devices are memory devices in which stored data is lost when power is cut off. Volatile memory devices include Static RAM (SRAM), Dynamic RAM (DRAM), and Synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices in which stored data is retained even when power is cut off. Non-volatile memory devices include Read-Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Flash Memory, Phase-Change RAM (PRAM), Magnetic RAM (MRAM), Resistive RAM (RRAM), and Ferroelectric RAM (FRAM). Flash memory is mainly divided into NOR and NAND types. Summary of the Invention

[0004] According to embodiments of the present disclosure, a semiconductor memory device may include: a memory block comprising a plurality of memory cells configured to be programmed into an erase state and a plurality of programmed states; a voltage generating circuit configured to generate a read voltage to be applied to a word line of the memory block during a read operation; and a read / write circuit connected to a bit line of the memory block and configured to latch data during a read operation by sensing the potential level of a sensing node based on the cell current of the plurality of memory cells within a predetermined time unit; wherein the read voltage is continuously applied to the word line during the predetermined time period and gradually increases over time during the predetermined time period.

[0005] According to embodiments of the present disclosure, a semiconductor memory device may include: a memory block including a plurality of memory cells configured to be programmed into an erase state and a plurality of programmed states; a voltage generating circuit configured to generate a read voltage to be applied to a word line of the memory block during a read operation; and a page buffer connected to a bit line of the memory block and configured to precharge a sensing node connected to the bit line to a first level during a read operation, and to detect the time it takes for the sensing node to decrease from the first level to a second level according to the programming state of a selected memory cell among the plurality of memory cells connected to the bit line, in order to latch data, and the read voltage increases over time.

[0006] According to embodiments of the present disclosure, a method of operating a semiconductor memory device may include the steps of: applying a read voltage that increases over time to selected word lines commonly connected to at least one or more memory cells; sensing cell currents of bit lines respectively connected to at least one or more memory cells for each of a plurality of predetermined time periods; and determining data stored in at least one or more memory cells by combining data sensed in the plurality of time periods. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0008] Figure 2 Examples include Figure 1 A diagram of a semiconductor memory device in a memory device.

[0009] Figure 3 This is a diagram illustrating a three-dimensional storage block.

[0010] Figure 4 is a specific example Figure 3 The circuit diagram of any one of the memory blocks shown.

[0011] Figure 5 This is an example Figure 4 The circuit diagram of the memory string is shown.

[0012] Figure 6 This is an example Figure 2 A diagram of the page buffer.

[0013] Figure 7 This is an example Figure 6 A diagram of a first embodiment of the latch assembly.

[0014] Figure 8 This is a diagram illustrating a first embodiment of a control signal generator.

[0015] Figure 9 This is a threshold voltage distribution diagram illustrating the erase state, multiple programming states, and read voltage.

[0016] Figure 10 This is a graph illustrating the cell current in the erase state and multiple programming states.

[0017] Figure 11A , Figure 11B and Figure 11C This is a graph illustrating the read voltage according to an embodiment of the present disclosure.

[0018] Figure 12 This is an example Figure 7 The signal waveform diagram of the operation of the latch component is shown.

[0019] Figure 13 This is an example from Figure 7 The diagram shows the data values ​​output by the latch component.

[0020] Figure 14 This is an example Figure 6 A figure of a second embodiment of the latch assembly.

[0021] Figure 15 This is a diagram illustrating a second embodiment of the control signal generator.

[0022] Figure 16 This is an example Figure 14 The signal waveform diagram of the operation of the latch component is shown.

[0023] Figure 17 This is an example from Figure 14 The diagram shows the data values ​​output by the latch component.

[0024] Figure 18 This is a diagram illustrating another implementation of a memory system.

[0025] Figure 19 This is a diagram illustrating another implementation of a memory system.

[0026] Figure 20 This is a diagram illustrating another implementation of a memory system.

[0027] Figure 21 This is a diagram illustrating another implementation of a memory system. Detailed Implementation

[0028] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are merely illustrative of embodiments based on the concepts of this disclosure. Embodiments based on the concepts of this disclosure may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0029] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0030] Embodiments of this disclosure provide a semiconductor memory device and a method for operating the semiconductor memory device, which can perform read operations on multiple programming states during a read operation while a gradually increasing read voltage is applied to the word line.

[0031] According to this technology, in various embodiments, read operations on multiple programming states can be performed during a read operation while a gradually increasing read voltage is applied to the word line, thereby reducing read operation time.

[0032] Figure 1 This is a block diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0033] Reference Figure 1 The memory system 1000 includes a memory device 1100, a controller 1200, and a host 1300. The memory device 1100 includes a plurality of semiconductor memory devices 100. The plurality of semiconductor memory devices 100 may be grouped into multiple groups. Although the host 1300 is shown and described as being included in the memory system 1000 in embodiments of this disclosure, the memory system 1000 may be configured to include only the controller 1200 and the memory device 1100, and the host may be configured to be located outside the memory system 1000.

[0034] exist Figure 1 In this context, multiple groups GR1 to GRn of the memory device 1100 communicate with the controller 1200 via the first channel CH1 to the nth channel CHn, respectively. (See below for further details.) Figure 2 Each semiconductor memory device 100 is described.

[0035] Each of groups GR1 to GRn is configured to communicate with controller 1200 via a common channel. Controller 1200 is configured to control multiple semiconductor memory devices 100 of memory device 1100 via multiple channels CH1 to CHn.

[0036] Controller 1200 is connected between host 1300 and memory device 1100. Controller 1200 is configured to access memory device 1100 in response to a request from host 1300. For example, controller 1200 is configured to control read, program, erase, and background operations of memory device 1100 in response to a host command Host_CMD received from host 1300. During a programming operation, host 1300 may send address ADD and data to be programmed DATA along with host command Host_CMD, and during a read operation, host 1300 may send address ADD along with host command Host_CMD. During a programming operation, controller 1200 sends a command corresponding to the programming operation and data to be programmed DATA to memory device 1100. During a read operation, controller 1200 sends a command corresponding to the read operation to memory device 1100, receives data DATA from memory device 1100, and sends the received data DATA to host 1300. Controller 1200 is configured to provide an interface between memory device 1100 and host 1300. Controller 1200 is configured to drive firmware for controlling memory device 1100.

[0037] The host 1300 includes portable electronic devices such as computers, PDAs, PMPs, MP3 players, cameras, camcorders, or mobile phones. The host 1300 can request programming, reading, and erasing operations from the memory system 1000 via the host command Host_CMD. The host 1300 can send the host command Host_CMD, data DATA, and address ADD corresponding to a programming operation to the controller 1200 for programming operations on the memory device 1100, and can send the host command Host_CMD and address ADD corresponding to a reading operation to the controller 1200 for reading operations. In this case, the address ADD can be the logical address (logical address block) of the data.

[0038] The controller 1200 and the memory device 1100 can be integrated into a single semiconductor memory device. As an implementation, the controller 1200 and the memory device 1100 can be integrated into a single semiconductor memory device to configure a memory card. For example, the controller 1200 and the memory device 1100 can be integrated into a single semiconductor memory device to configure memory cards such as PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, or micro MMC), SD cards (SD, mini SD, micro SD, or SDHC), and universal flash memory (UFS).

[0039] As another example, the memory system 1000 is configured to be one of the following: a computer, an ultra-mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless telephone, a mobile phone, a smartphone, an e-book reader, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3D television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder and a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices for configuring a home network, one of various electronic devices for configuring a computer network, one of various electronic devices for configuring a telematics network, an RFID device, or one of various components for configuring a computing system.

[0040] As an implementation, the memory device 1100 or memory system 1000 can be mounted in various types of packages. For example, the memory device 1100 or memory system 1000 can be packaged and mounted in methods such as package-on-package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic chip carrier with leads (PLCC), plastic dual in-line package (PDIP), a die-in-wafflepack, die-on-chip (COB), ceramic dual in-line package (CERDIP), plastic quad flat package (MQFP), thin quad flat package (TQFP), small outline package (SOIC), shrunk small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), and wafer-level fabrication stacked package (WSP).

[0041] Figure 2 Examples include Figure 1 A diagram of a semiconductor memory device in a memory device.

[0042] Reference Figure 2The semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read / write circuit 130, control logic 140, and a voltage generation circuit 150. The address decoder 120, read / write circuit 130, and voltage generation circuit 150 can be defined as peripheral circuitry 160 that performs read operations on the memory cell array 110. In embodiments, peripheral circuitry 160 can perform programming or erasing operations. The control logic 140 can be implemented in hardware, software, or a combination of both. For example, the control logic 140 can be a control logic circuitry that operates according to a processor and / or algorithm executing control logic code.

[0043] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz. The multiple memory blocks BLK1 to BLKz are connected to the address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz are connected to the read / write circuitry 130 via bit lines BL1 to BLm. Each memory block in the multiple memory blocks BLK1 to BLKz includes multiple memory cells. As an implementation, the multiple memory cells are non-volatile memory cells. Multiple memory cells connected to a single word line can be defined as a page. That is, the memory cell array 110 can be configured with multiple pages.

[0044] Each of the multiple memory blocks BLK1 to BLKz in the memory cell array 110 includes multiple memory strings. Each memory string includes a drain selection transistor, multiple memory cells, and a source selection transistor connected in series between a bit line and a source line. Additionally, each memory string may include transfer transistors between the source selection transistor and the memory cell, and between the drain selection transistor and the memory cell, and may also include pipe gate transistors between the memory cells. A detailed description of the memory cell array 110 will be described later.

[0045] Each of the multiple memory cells can store multiple data bits, such as multi-level cell (MLC), three-level cell (TLC), or four-level cell (QLC).

[0046] Address decoder 120 is connected to memory cell array 110 via word line WL. Address decoder 120 is configured to operate in response to address decoder control signals AD_signals generated in control logic 140. Address decoder 120 receives address ADDR via an input / output buffer (not shown) inside semiconductor memory device 100.

[0047] Address decoder 120 can decode the row address of the received address ADDR, and can apply multiple operating voltages, including a programming voltage Vpgm generated by voltage generation circuit 150, a read voltage Vread, a pass voltage Vpass, and a verification voltage Vverify, to multiple memory cells of memory cell array 110 according to the decoded row address.

[0048] Address decoder 120 is configured to decode the column address of the received address ADDR. Address decoder 120 sends the decoded column address Yi to read / write circuit 130.

[0049] The address ADDR received during programming or reading operations includes the block address, row address, and column address. Address decoder 120 selects a memory block and a word line based on the block address and row address. The column address is decoded by address decoder 120 and provided to read / write circuitry 130.

[0050] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0051] The read / write circuit 130 includes multiple page buffers PB1 to PBm. These page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. During a read or verification operation, the page buffers PB1 to PBm can perform a data sensing operation to sense the programming state of the memory cells connected to the bit lines BL1 to BLm. During the data sensing operation, each page buffer PB1 to PBm can latch data based on the cell current of the selected memory cell connected to the corresponding bit line. For example, each page buffer PB1 to PBm can sense the potential of the sensing node at multiple time points, varying based on the cell current of the selected memory cell connected to the corresponding bit line, and latch the data value corresponding to the sensing result. For example, each page buffer PB1 to PBm can latch data corresponding to the potential level of the sensing node at each of multiple set time points. At this time, a read voltage, which increases with time, is applied to the word line connected to the selected memory cell.

[0052] The read / write circuit 130 operates in response to the page buffer control signal PB_signals output from the control logic 140.

[0053] As an implementation, the read / write circuit 130 may include a page buffer (or page register), a column selection circuit, etc.

[0054] Control logic 140 is connected to address decoder 120, read / write circuit 130, and voltage generation circuit 150. Control logic 140 receives commands (CMD) via input / output buffers (not shown) of semiconductor memory device 100. Control logic 140 is configured to control the overall operation of semiconductor memory device 100 in response to commands (CMD). For example, control logic 140 receives commands (CMD) corresponding to programming operations and, in response to the received commands (CMD), generates and outputs address decoder control signals AD_signals for controlling address decoder 120, page buffer control signals PB_signals for controlling read / write circuit 130, and voltage generation circuit control signals VG_signals for controlling voltage generation circuit 150. Additionally, control logic 140 receives commands (CMD) corresponding to read operations and, in response to the received commands (CMD), generates and outputs address decoder control signals AD_signals for controlling address decoder 120, page buffer control signals PB_signals for controlling read / write circuit 130, and voltage generation circuit control signals VG_signals for controlling voltage generation circuit 150.

[0055] During programming operations, voltage generation circuit 150 generates a programming voltage Vpgm, a pass voltage Vpass, and a verification voltage Vverify according to the control signal VG_signals output from control logic 140, and outputs these voltages to address decoder 120. Conversely, during read operations, voltage generation circuit 150 generates a read voltage Vread and a pass voltage Vpass according to the control signal VG_signals output from control logic 140, and outputs both voltages to address decoder 120. The read voltage Vread generated by voltage generation circuit 150 can be a voltage that gradually increases over time. For example, a read voltage Vread can increase linearly or exponentially over time. Alternatively, a read voltage Vread can increase by a predetermined step voltage at predetermined time intervals. That is, a read voltage Vread can increase in a step manner over time. As used herein, the term "predetermined" (e.g., predetermined step voltage, predetermined time interval, predetermined time unit, predetermined time, and predetermined period) refers to determining the value of a parameter before it is used in a process or algorithm. In some implementations, the parameter value is determined before the process or algorithm begins. In other implementations, the parameter value is determined during the process or algorithm, but before it is used in the process or algorithm.

[0056] The voltage generating circuit 150 according to an embodiment of the present disclosure can generate a read voltage that gradually increases over time during a read operation on a memory cell in which a plurality of data bits are stored.

[0057] Figure 3 This is a diagram illustrating a three-dimensional storage block.

[0058] Reference Figure 3 The three-dimensional memory blocks BLK1 to BLKz can be arranged to be spaced apart from each other along the direction Y extending from bit lines BL1 to BLm. For example, the first memory block BLK1 to the z-th memory block BLKz can be arranged to be spaced apart from each other along the second direction Y and include a plurality of memory cells stacked along the third direction Z. (See below for further details.) Figure 4 and Figure 5 The configuration of any one of the storage blocks from the first storage block BLK1 to the z-th storage block BLKz is described in detail.

[0059] Figure 4 is a specific example Figure 3 The circuit diagram of any one of the memory blocks shown.

[0060] Figure 5 This is an example Figure 4 The circuit diagram of the memory string is shown.

[0061] Reference Figure 4 and Figure 5 Each memory string ST can be connected between bit lines BL1 to BLm and the source line SL. As an example, a memory string ST connected between the first bit line BL1 and the source line SL will be described.

[0062] A memory string ST may include source select transistors SST, memory cells F1 to Fn (n being a positive integer), and drain select transistors DST connected in series between the source line SL and the first bit line BL1. The gates of the source select transistors SST included in different memory strings ST connected to different bit lines BL1 to BLm may be connected to the first source select line SSL0 and the second source select line SSL1. For example, source select transistors SST that are adjacent to each other in the second direction Y may be connected to the same source select line. For example, assuming that the source select transistors SST are arranged sequentially along the second direction Y, the gates of source select transistors SST arranged in the first direction X starting from the first source select transistor SST and included in different strings ST, and the gates of source select transistors SST arranged in the first direction X starting from the second source select transistor SST and included in different strings ST, may be connected to the first source select line SSL0. Additionally, the gates of source selection transistors SST arranged in the first direction X starting from the third source selection transistor SST and included in different strings ST, and the gates of source selection transistors SST arranged in the first direction X starting from the fourth source selection transistor SST and included in different strings ST, can be connected to the second source selection line SSL1.

[0063] The gates of memory cells F1 to Fn can be connected to word lines WL1 to WLn, and the gate of drain select transistor DST can be connected to any one of the first drain select line DSL0 to the fourth drain select line DSL3.

[0064] In a drain-select transistor (DST), the gates of transistors arranged in the first direction X can be connected to the same drain-select line (e.g., DSL0), but transistors arranged in the second direction Y can be connected to different drain-select lines DSL1 to DSL3. For example, assuming the drain-select transistors DST are arranged sequentially along the second direction Y, the gates of drain-select transistors DST arranged in the first direction X starting from the first drain-select transistor DST and included in different strings ST can be connected to the first drain-select line DSL0. Drain-select transistors DST arranged in the second direction Y starting from the drain-select transistor DST connected to the first drain-select line DSL0 can be sequentially connected to the second drain-select lines DSL1 to the fourth drain-select lines DSL3. Therefore, within a selected memory block, memory strings ST connected to selected drain-select lines can be selected, and memory strings ST connected to the remaining unselected drain-select lines can be left unselected.

[0065] Memory cells connected to the same word line can form a page PG. Here, a page refers to a physical page. For example, in a string ST connected to the first bit line BL1 to the m-th bit line BLm, a group of memory cells connected to the same word line in the first direction X is called a page PG. For example, in the first memory cell F1 connected to the first word line WL1, memory cells arranged along the first direction X can form a page PG. Cells arranged in the second direction Y in the first memory cell F1 that are commonly connected to the first word line WL1 can be divided into different pages. Therefore, when the first drain select line DSL0 is the selected drain select line and the first word line WL1 is the selected word line, the page connected to the first drain select line DSL0 becomes the selected page among the multiple page PGs connected to the first word line WL1. Pages that are commonly connected to the first word line WL1 but connected to the unselected second drain select lines DSL1 to the fourth drain select lines DSL3 become unselected pages.

[0066] In the figure, a source-select transistor (SST) and a drain-select transistor (DST) are included in a string ST. However, according to a semiconductor memory device, multiple source-select transistors (SST) and multiple drain-select transistors (DST) can be included in a string ST. Additionally, according to the memory device, dummy cells can be included between the source-select transistors (SST), memory cells F1 to Fn, and drain-select transistors (DST). In an embodiment, the dummy cells may not store user data like normal memory cells F1 to Fn, but can instead be used to improve the electrical characteristics of each string ST.

[0067] Figure 6 This is an example Figure 2 A diagram of the page buffer.

[0068] Figure 2 The multiple page buffers PB1 to PBm shown can be configured similarly to each other. For ease of description, Figure 6 It shows Figure 2 Page buffer PB1 is one of the multiple page buffers PB1 to PBm.

[0069] Reference Figure 6 The page buffer PB1 may include a bit line selector 131, a sensor 132, a precharger 133, a latch assembly 134, and a data output circuit 135.

[0070] Bit line selector 131 is connected between the corresponding bit line BL1 and sensor 132, and is electrically connected to the corresponding bit line BL1 and sensor 132 during read operations.

[0071] Sensor 132 is connected between bit line selector 131 and sensing node SO. During a read operation, sensor 132 connects sensing node SO and bit line BL1 connected via bit line selector 131, and evaluates sensing node SO based on the current in bit line BL1. For example, sensor 132 reduces the potential of sensing node SO, which is pre-charged to a first level, to a second level based on the current in bit line BL1, and the time it takes for the potential to decrease to the second level decreases as the current in bit line BL1 increases. That is, during a read operation, the potential of sensing node SO is reduced from the first level to the second level based on the cell current of the selected memory cell connected to bit line BL1. Furthermore, the time it takes for the potential of sensing node SO to decrease from the first level to the second level decreases as the cell current in the selected memory cell increases, and the time it takes for the potential of sensing node SO to decrease from the first level to the second level increases as the cell current decreases.

[0072] The precharger 133 is connected to the sensing node SO, precharges the bit line BL1 to a set level via the sensor 132 and the bit line selector 131, and precharges the sensing node SO to a first level during a read operation.

[0073] The latch component 134 is connected to the sensing node SO and latches data by sensing the potential level of the sensing node SO at predetermined intervals.

[0074] Data output circuit 135 is connected to the output terminal Q of latch assembly 134. <m:1>Between the bit output line BITOUT, which serves as the output terminal of the page buffer PB1, and the data output circuit 135 receives the data latched in the latch assembly 134 and outputs the data to the bit output line BITOUT.

[0075] Figure 7 This is an example Figure 6 A diagram of a first embodiment of the latch assembly.

[0076] Reference Figure 7 The latch assembly 134 includes multiple latch stages 134A to 134D. It can be configured according to... Figure 2 The number of latch stages 134A to 134D included in the latch assembly 134 is adjusted by the number of data bits that can be stored in the memory cells included in the memory cell array 110. For example, when the memory cells are MLC, the latch assembly 134 may include three latch stages, and when the memory cells are TLC, the latch assembly 134 may include seven latch stages. Additionally, when the memory cells are QLC, the latch assembly 134 may include fifteen latch stages.

[0077] The latch stage 134A may include a first transistor T1, a first inverter IV1, a second inverter IV2, and a second transistor T2.

[0078] The first transistor T1 is connected between the sensing node SO and the first node ND1, and is turned on or off in response to the first latch signal PLS1. The first inverter IV1 and the second inverter IV2 are connected in parallel in opposite directions between the first node ND1 and the second node ND2. That is, the first inverter IV1 and the second inverter IV2 are configured as a latch between the first node ND1 and the second node ND2. The second transistor T2 is connected between the second node ND2 and the output terminal Q. <1> It is between, and turns on or off in response to the data output signal DO.

[0079] In response to the first latch signal PLS1, the first transistor T1 sends the first data D1, corresponding to the potential of the sensing node SO, to the first node ND1. The first inverter IV1 and the second inverter IV2 receive and latch the first data D1, invert the first data D1, and send the inverted first data to the second transistor T2. The second transistor T2, in response to the data output signal DO, outputs the inverted first data to the output terminal Q. <1> .

[0080] For example, when the sensing node SO is at a first level, which is a pre-charge level, the first transistor T1, in response to the first latch signal PLS1, sends first data D1 with a potential of the first level to the first node ND1. The first inverter IV1 and the second inverter IV2 receive the first data D1 with the first level potential and control the first node ND1 to a logic high level and the second node ND2 to a logic low level. The second transistor T2, in response to the data output signal DO, outputs the inverted first data with a logic low level to the output terminal Q. <1> .

[0081] For example, when sensing node SO is discharged to the second level, the first transistor T1, in response to the first latch signal PLS1, sends first data D1 with a potential of the second level to the first node ND1. The first inverter IV1 and the second inverter IV2 receive the first data D1 with the potential of the second level and control the first node ND1 to a logic low level and the second node ND2 to a logic high level. The second transistor T2, in response to the data output signal DO, outputs the inverted first data with a logic high level to the output terminal Q. <1> .

[0082] The latch stage 134B may include a third transistor T3, a third inverter IV3, a fourth inverter IV4, and a fourth transistor T4.

[0083] The third transistor T3 is connected between the sensing node SO and the third node ND3, and is turned on or off in response to the second latch signal PLS2. The third inverter IV3 and the fourth inverter IV4 are connected in anti-parallel between the third node ND3 and the fourth node ND4. That is, the third inverter IV3 and the fourth inverter IV4 are configured as a latch between the third node ND3 and the fourth node ND4. The fourth transistor T4 is connected between the fourth node ND4 and the output terminal Q. <2> It is between, and turns on or off in response to the data output signal DO.

[0084] Since the operation of latch level 134B is similar to that of latch level 134A, its detailed description is omitted.

[0085] The latch stage 134C may include a fifth transistor T5, a fifth inverter IV5, a sixth inverter IV6, and a sixth transistor T6.

[0086] The fifth transistor T5 is connected between sensing node SO and the fifth node ND5, and is turned on or off in response to the third latch signal PLS3. The fifth inverter IV5 and the sixth inverter IV6 are connected in anti-parallel between the fifth node ND5 and the sixth node ND6. That is, the fifth inverter IV5 and the sixth inverter IV6 are configured as a latch between the fifth node ND5 and the sixth node ND6. The sixth transistor T6 is connected between the sixth node ND6 and the output terminal Q. <3> It is between, and turns on or off in response to the data output signal DO.

[0087] Since the operation of latch-level 134C is similar to that of latch-level 134A, its detailed description is omitted.

[0088] The latch stage 134D may include a seventh transistor T7, a seventh inverter IV7, an eighth inverter IV8, and an eighth transistor T8.

[0089] The seventh transistor T7 is connected between the sensing node SO and the seventh node ND7, and is turned on or off in response to the m-th latch signal PLSm. The seventh inverter IV7 and the eighth inverter IV8 are connected in anti-parallel between the seventh node ND7 and the eighth node ND8. That is, the seventh inverter IV7 and the eighth inverter IV8 are configured as a latch between the seventh node ND7 and the eighth node ND8. The eighth transistor T8 is connected between the eighth node ND8 and the output terminal Q. <m>It is between, and turns on or off in response to the data output signal DO.

[0090] Since the operation of latch-level 134D is similar to that of latch-level 134A, its detailed description is omitted.

[0091] Figure 8 This is a diagram illustrating a first embodiment of a control signal generator.

[0092] Control signal generator 141 generates and outputs first latch signals PLS1 to m-th latch signals PLSm in response to a clock signal CLK that toggles at a predetermined period. Each latch signal from first latch signal PLS1 to m-th latch signal PLSm has an activation period during which each latch signal from first latch signal PLS1 to m-th latch signal PLSm is activated for a predetermined time period. The first latch signals PLS1 to m-th latch signals PLSm are activated sequentially.

[0093] In response to the clock signal CLK, the control signal generator 141 can generate and output a data output signal DO, which is activated for a predetermined time period after the last activated latch signal among the first latch signal PLS1 to the m-th latch signal PLSm (that is, the m-th latch signal PLSm) is activated.

[0094] The control signal generator 141 can be included Figure 2 The control logic is in 140.

[0095] Figure 9 This is a threshold voltage distribution diagram illustrating the erase state, multiple programming states, and read voltage. In Figure 9 In the diagram, the x-axis indicates the threshold voltage Vth, and the y-axis indicates the number of memory cells No.

[0096] Figure 10 This is a graph illustrating the cell current in the erase state and multiple programming states. Figure 10 In the middle, the x-axis indicates the word line voltage V. WL The Y-axis indicates the cell current Icell.

[0097] In embodiments of this disclosure, as an example, will be described. Figure 5 The multiple memory cells F1 to Fn shown are in the case of MLC.

[0098] Reference Figure 9 and Figure 10 , Figure 5 The multiple memory cells F1 to Fn shown are programmed into an erase state E and multiple programming states PV1 to PV3. The erase state E and the multiple programming states PV1 to PV3 have different threshold voltage distributions. (As shown...) Figure 9 As shown, the threshold voltage distribution of programming state PV1 is higher than that of erase state E, and the threshold voltage distribution of programming state PV2 is higher than that of programming state PV1. Furthermore, the threshold voltage distribution of programming state PV3 is higher than that of programming state PV2.

[0099] During a read operation, when a read voltage Vread is applied to the word lines of multiple memory cells F1 to Fn, the memory cells corresponding to the erase state E and programming states PV1 and PV2 are turned on, and the memory cells corresponding to the programming state PV3 are turned off. At this time, as... Figure 10 As shown, when read voltages Vr1, Vr2, or Vr3 are applied to the word line, the cell current of multiple memory cells F1 to Fn varies depending on the corresponding erase state E and multiple programming states PV1 to PV3. For example, the cell current of the memory cell corresponding to erase state E is the largest for the read voltages Vr1, Vr2, or Vr3 applied to the word line, while the cell current of the memory cell corresponding to programming state PV3 is the smallest for the read voltages Vr1, Vr2, or Vr3 applied to the word line. Furthermore, the cell current of the memory cell corresponding to programming state PV1 for the read voltages Vr1, Vr2, or Vr3 is smaller than the cell current of the memory cell corresponding to erase state E, and larger than the cell current of the memory cell corresponding to programming state PV2 for the read voltages Vr1, Vr2, or Vr3. The cell current of the memory cell corresponding to programming state PV2 with respect to read voltages Vr1, Vr2, or Vr3 is smaller than the cell current of the memory cell corresponding to programming state PV1 with respect to read voltages Vr1, Vr2, or Vr3, and larger than the cell current of the memory cell corresponding to programming state PV3. Additionally, as... Figure 10 As shown, the cell current values ​​of multiple memory cells F1 to Fn corresponding to the erase state E and the programming states PV1, PV2, and PV3 vary according to the potential level of the read voltage applied to the word line. For example, when the read voltage increases from the first level Vr1 to the second level Vr2, the change in cell current Icell of programming state PV1 is relatively large compared to programming state PV3 and erase state E, and when the read voltage increases from the second level Vr2 to the third level Vr3, the change in cell current Icell of programming state PV2 can be relatively large compared to programming state PV3 and erase state E.

[0100] As described above, when a read voltage Vread, whose potential level gradually increases over time, is applied to the word line, the cell currents and their changes in the amount of cell current for the multiple memory cells F1 to Fn, programmed into erase state E and multiple programming states PV1 to PV3, differ depending on the programmed erase state E and the multiple programming states PV1 to PV3. Therefore, when the sensing node connected to the bit line and page buffer of the selected memory cell is electrically connected during a read operation, the time it takes for the potential of the sensing node, pre-charged to the first level, to decrease to the second level changes based on the cell current of the selected memory cell. For example, as the cell current increases, the time it takes for the potential of the sensing node to decrease from the first level to the second level decreases, and as the cell current decreases, the time it takes for the potential of the sensing node to decrease from the first level to the second level increases.

[0101] Figures 11A to 11C This is a graph illustrating the read voltage according to an embodiment of the present disclosure.

[0102] Reference Figure 11A During a read operation, a read voltage Vread is applied to the selected word line and can gradually increase linearly over time. A read voltage Vread can include multiple read voltages Vr corresponding to various time points t. For example, the read voltage Vr2 at the second time point t2 can have a potential higher than the read voltage Vr1 at the first time point t1 by a set value, and the read voltage Vr3 at the third time point t3 can have a potential higher than the read voltage Vr2 at the second time point t2 by a set value. Furthermore, as... Figure 11A As shown, for an implementation, a read voltage Vread can be gradually increased by increasing linearly with time, which is different from increasing exponentially with time or increasing gradually with time (e.g., as...). Figure 11C (as shown in the image) on the contrary.

[0103] Additionally, refer to Figure 11B During a read operation, a read voltage Vread applied to the selected word line increases exponentially over time. A read voltage Vread can include multiple read voltages Vr corresponding to various time points t. For example, the read voltage Vr2 at the second time point t2 may have a potential higher than the read voltage Vr1 at the first time point t1 by a first set value, and the read voltage Vr3 at the third time point t3 may have a potential higher than the read voltage Vr2 at the second time point t2 by a second set value, where the second set value may be greater than the first set value.

[0104] Additionally, refer to Figure 11C During a read operation, a read voltage Vread applied to a selected word line can have different potential levels in multiple time periods. A read voltage Vread can include multiple read voltages Vr corresponding to various durations or time periods, whereby the read voltage Vr has a selected level. In an implementation, the read voltage Vread can be increased in each time period, thereby increasing the read voltage Vread in a stepwise manner. For example, a first-level read voltage Vr1 can be applied in a first time period, a second-level read voltage Vr2 can be applied in a second time period, and a third-level read voltage Vr3 can be applied in a third time period.

[0105] Figure 12 This is an example Figure 7 The signal waveform diagram of the operation of the latch component is shown.

[0106] Figure 13 This is an example from Figure 7 The diagram shows the data values ​​output by the latch component.

[0107] See below for reference Figures 12 to 13 This describes a read operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0108] In embodiments of this disclosure, a memory cell connected to a selected word line is described as an MLC programmed to an erase state E and multiple programming states PV1 to PV3. Figure 7 The latch assembly 134 includes examples of three latch levels (e.g., 134A, 134B, and 134C).

[0109] During a read operation, voltage generation circuit 150 generates a read voltage Vread and a pass voltage Vpass according to the control signal VG_signals output from control logic 140, and outputs the read voltage Vread and the pass voltage Vpass to address decoder 120. Address decoder 120 applies the read voltage Vread generated by voltage generation circuit 150 to the selected word line (e.g., WL1) of the selected memory block (e.g., BLK1). Address decoder 120 applies the pass voltage Vpass generated by voltage generation circuit 150 to the unselected word lines (e.g., WL2 to WLn) of the selected memory block (e.g., BLK1).

[0110] like Figure 9 As shown, a read voltage Vread generated by the voltage generating circuit 150 can be lower than the threshold voltage of programming state PV3, which has the highest threshold voltage distribution among the erase state E and the multiple programming states PV1 to PV3, and can be higher than the threshold voltage of programming state PV2, which is adjacent to programming state PV3, which has the highest threshold voltage distribution. For example, a read voltage Vread can be the intermediate voltage value between two programming states PV2 and PV3, which have a relatively highest threshold voltage distribution among the erase state E and the multiple programming states PV1 to PV3. Additionally, as... Figures 11A to 11C As shown, a read voltage Vread can be a voltage whose potential level gradually increases over time.

[0111] The multiple page buffers PB1 to PBm of the read / write circuit 130 sense the programming status of the memory cell F1 connected to the selected word line WL1 via bit lines BL1 to BLm.

[0112] Since multiple page buffers PB1 to PBm perform sensing operations in a similar manner to each other, the following description of the operation of page buffer PB1 sensing the programming state of memory cells connected to the corresponding bit line BL1 is used as an example.

[0113] The precharger 133 precharges bit line BL1 to a precharge level via sensor 132 and bit line selector 131. Additionally, the precharger 133 precharges sensing node SO to a first level VH.

[0114] When a read voltage Vread is applied to the selected word line WL1, a cell current flowing through bit line BL1 is generated according to the programming state of the memory cell F1 connected to bit line BL1. For example, the cell current can be maximum when memory cell F1 is in erase state E, and minimum when memory cell F1 is in programming state PV3.

[0115] Bit line selector 131 and sensor 132 are electrically connected to bit line BL1 and sensing node SO, and the sensing node SO is evaluated based on the cell current of memory cell F1. That is, the cell current corresponding to the programming state of memory cell F1 flows through bit line BL1. The sensing node SO connected to bit line BL1 is lowered from a first level VH to a second level VL based on the cell current, and the time for the sensing node SO to lower from the first level VH to the second level VL is adjusted according to the magnitude of the cell current. As a result, the time for the potential of the sensing node SO to lower from the first level VH to the second level VL is adjusted according to the programming state of the memory cell.

[0116] For example, when the selected memory cell F1 is in erase state E with the lowest threshold voltage distribution, the cell current of bit line BL1 is at its maximum, and the time for the potential of sensing node SO to decrease from the first level VH to the second level VL is the shortest. For example, when the selected memory cell F1 is in erase state E, the potential of sensing node SO discharges to the second level VL within the first time period. At this time, the read voltage applied in the first time period can have a relatively low potential level compared to the read voltage applied in the second and third time periods. In addition, compared to the case where a read voltage with a constant potential (e.g., Vr2) is applied from the first to the third time periods (dashed line), the discharge time of the memory cell in erase state E can be increased.

[0117] For example, when the selected memory cell F1 is in programming state PV1, which has a threshold voltage distribution higher than that of erase state E, the cell current of bit line BL1 is smaller than that corresponding to erase state E, and the time for the potential of sensing node SO to decrease from the first level VH to the second level VL is longer than that corresponding to erase state E. For example, when the selected memory cell F1 is in programming state PV1, the potential of sensing node SO is discharged to the second level VL during the second time period. At this time, the read voltage applied in the second time period can have a relatively higher potential level compared to the read voltage applied in the first time period, and a relatively lower potential level compared to the read voltage applied in the third time period. In addition, compared to the case where a read voltage with a constant potential (e.g., Vr2) is applied from the first to the third time periods (dashed line), the discharge time of the memory cell in programming state PV1 can be increased.

[0118] For example, when the selected memory cell F1 is in programming state PV2, which has a higher threshold voltage distribution than programming state PV1, the cell current of bit line BL1 is smaller than the cell current corresponding to programming state PV1, and the time for the potential of sensing node SO to decrease from the first level VH to the second level VL is longer than the time corresponding to programming state PV1. For example, when the selected memory cell F1 is in programming state PV2, the potential of sensing node SO is discharged to the second level VL during the third time period. At this time, the read voltage applied in the third time period can have a relatively higher potential level compared to the read voltage applied in the first and second time periods. In addition, compared to the case where a read voltage with a constant potential (e.g., Vr2) is applied from the first to the third time periods (dashed line), the discharge time of the memory cell in programming state PV2 can be reduced.

[0119] For example, when the selected memory cell F1 is in programming state PV3 with the highest threshold voltage distribution, the cell current of bit line BL1 is at its minimum.

[0120] Control signal generator 141 generates and outputs first latch signals PLS1 to third latch signals PLS3 in response to a clock signal CLK that switches at a predetermined period. Each of the first latch signals PLS1 to third latch signals PLS3 has an activation period during which each of the first latch signals PLS1 to third latch signals PLS3 is activated for a predetermined time period. The first latch signals PLS1 to third latch signals PLS3 are activated sequentially.

[0121] For example, the first latch signal PLS1 is activated during a predetermined time period from the point when the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell in the erase state E, to the point before the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell in the programming state PV1. For example, the first latch signal PLS1 is activated during a predetermined time period within a first time period.

[0122] For example, the second latch signal PLS2 is activated during a predetermined time period from the point when the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell of the programming state PV1 to the point before the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell of the programming state PV2. For example, the second latch signal PLS2 is activated during a predetermined time period within the second time period.

[0123] For example, the third latch signal PLS3 is activated during a predetermined time period after the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell of the programming state PV2. For example, the third latch signal PLS3 is activated during a predetermined time period within the third time period.

[0124] The plurality of corresponding latch stages 134A to 134C of latch assembly 134 sequentially latch data in response to corresponding first latch signal PLS1 to third latch signal PLS3.

[0125] For example, in response to the first latch signal PLS1, latch stage 134A latches the first data D1 corresponding to the potential of sensing node SO from the time point when the potential level of sensing node SO decreases from the first level VH to the second level VL through the memory cell in erase state E to the time point before the potential level of sensing node SO decreases from the first level VH to the second level VL through the memory cell in programming state PV1. That is, latch stage 134A latches the first data D1 corresponding to the potential of sensing node SO during the first time period.

[0126] For example, in response to the second latch signal PLS2, latch stage 134B latches the second data D2 corresponding to the potential of sensing node SO from the time point when the potential level of sensing node SO decreases from the first level VH to the second level VL through the memory cell of programming state PV1 to the time point before the potential level of sensing node SO decreases from the first level VH to the second level VL through the memory cell of programming state PV2. That is, latch stage 134B latches the second data D2 corresponding to the potential of sensing node SO during the second time period.

[0127] For example, in response to the third latch signal PLS3, latch stage 134C latches the third data D3 corresponding to the potential of sensing node SO after the potential level of sensing node SO decreases from the first level VH to the second level VL through the memory cell of programming state PV2. That is, latch stage 134C latches the third data D3 corresponding to the potential of sensing node SO during the third time period.

[0128] Each of the multiple latch stages 134A to 134C of the latch assembly 134 outputs the latched data to the output terminal Q<3:1> in response to the data output signal DO.

[0129] For example, when the selected memory cell F1 connected to bit line BL1 is in erase state E, the sensing node SO drops to the second level VL during the first to third time periods. Therefore, multiple latch stages 134A, 134B, and 134C latch the first data D1 to the third data D3 at logic low levels and output the first data to the third data, inverted to logic high levels, to output terminals Q<3:1>. That is, each output terminal in Q<3:1> outputs a "1" data corresponding to a logic high level.

[0130] For example, when the selected memory cell F1 connected to bit line BL1 is in programming state PV1, the sensing node SO does not reach the second level VL in the first time period, and the sensing node SO drops to the second level VL in the second and third time periods. Therefore, latch stage 134A latches the first data D1 at a logic high level, while latch stages 134B and 134C latch the second data D2 and the third data D3 at a logic low level. Therefore, the output terminal Q... <1> The output terminal Q corresponds to a "0" data level low. <2> and Q <3> Outputs a "1" data corresponding to a logic high level.

[0131] For example, when the selected memory cell F1 connected to bit line BL1 is in programming state PV2, the sensing node SO does not reach the second level VL in the first and second time periods, and the sensing node SO drops to the second level VL in the third time period. Therefore, the corresponding latch stages 134A and 134B latch the first data D1 and the second data D2 at logic high level, while the latch stage 134C latches the third data D3 at logic low level. Therefore, the output terminal Q <1> and Q <2> Each output terminal in the circuit outputs a "0" data corresponding to a logic low level, while output terminal Q... <3> Outputs a "1" data corresponding to a logic high level.

[0132] For example, when the selected memory cell F1 connected to bit line BL1 is in programming state PV3, the sensing node SO does not drop to the second level VL during the first to third time periods. Therefore, multiple latch stages 134A, 134B, and 134C latch the first data D1 to the third data D3 at logic high level and output the first data to the third data inverted to logic low level to the output terminal Q<3:1>. That is, each output terminal in output terminal Q<3:1> outputs "0" data corresponding to the logic low level.

[0133] The data output circuit 135 receives data from the output terminal Q<3:1> and outputs the most significant bit (MSB) and least significant bit (LSB) data as bit read data DATA to the bit output line BITOUT based on the received data.

[0134] As described above, according to embodiments of this disclosure, during a read operation of a memory cell storing multiple data bits, while a gradually increasing read voltage is applied to the word line, the programming state of the memory cell can be sensed by sensing the time point when the sensing node SO drops to a second level. Therefore, in this embodiment, the operation speed of the read operation can be improved, and the area of ​​the circuit generating the read voltage can be reduced by using only one read voltage instead of multiple read voltages. Furthermore, in this embodiment, the cell current corresponding to a relatively high programming state is increased according to a gradually increasing read voltage, and thus the corresponding operation period can be set earlier (e.g., ...). Figure 12 (The third time period). Therefore, in the implementation, the read operation time can be reduced.

[0135] In the above embodiments, such as Figure 9 As shown, a read voltage Vread applied to the selected word line is lower than the threshold voltage of programming state PV3, which has the highest relative threshold voltage distribution among the erase state E and the multiple programming states PV1 to PV3, and higher than the threshold voltage of programming state PV2, which is adjacent to programming state PV3, which has the highest threshold voltage distribution.

[0136] In another embodiment, a read voltage Vread can be a voltage higher than the threshold voltage of programming state PV3, which has the highest threshold voltage distribution among the erase state E and the plurality of programming states PV1 to PV3. During a read operation according to another embodiment, when a read voltage Vread higher than the threshold voltage of programming state PV3 is applied to a selected word line, the bit line corresponding to the memory cell programmed to erase state E and the plurality of programming states PV1 to PV3 has a different cell current. Therefore, the time it takes for the potential level of sensing node SO to decrease from a first level to a second level varies depending on the programming state of the memory cell. Latch assembly 134 can latch data corresponding to the potential level of sensing node SO at multiple set time points to sense the programming state of the memory cell.

[0137] Figure 14 This is an example Figure 6 A figure of a second embodiment of the latch assembly.

[0138] Reference Figure 14 The latch assembly 134 includes multiple latch stages 134E to 134H. It can be configured according to... Figure 2 The number of latch stages 134E to 134H included in the latch assembly 134 is adjusted by the number of data bits that can be stored in the memory cells included in the memory cell array 110. For example, when the memory cells are MLC, the latch assembly 134 may include three latch stages, and when the memory cells are TLC, the latch assembly 134 may include seven latch stages. In addition, when the memory cells are QLC, the latch assembly 134 may include fifteen latch stages.

[0139] Each of the multiple latch stages 134E to 134H can be configured by a D flip-flop.

[0140] The latch stage 134E latches data corresponding to the potential level of the sensing node SO in response to the rising edge of the latching signal PLS, and outputs the latched data to the output terminal Q in response to the falling edge of the latching signal PLS. <1> .

[0141] The 134F latch stage latches from the output terminal Q in response to the rising edge of the latch switching signal PLS. <1> The received data is output to the output terminal Q in response to the falling edge of the latch signal PLS. <2> .

[0142] The 134G latch stage latches from the output terminal Q in response to the rising edge of the latch switching signal PLS. <2> The received data is output to the output terminal Q in response to the falling edge of the latch signal PLS. <3> .

[0143] Latch stage 134H latches from output terminal Q in response to the rising edge of the latch switching signal PLS. <m-1>The received data is output to the output terminal Q in response to the falling edge of the latch signal PLS. <m>.

[0144] For example, the latch stage 134E latches data corresponding to the potential of the sensing node SO in response to the first rising edge of the latch signal PLS, and outputs the latched data to the output terminal Q in response to the first falling edge of the latch signal PLS. <1> .

[0145] Latch stage 134E latches new data corresponding to the potential of sensing node SO in response to the second rising edge of latch signal PLS, and latch stage 134F latches data from output terminal Q in response to the second rising edge of latch signal PLS. <1> The received data. That is, latch stage 134F latches the data output from latch stage 134E in response to the second rising edge. Latch stage 134E outputs the latched data to output terminal Q in response to the second falling edge of the latch signal PLS. <1> Furthermore, the latch stage 134F responds to the second falling edge of the latch signal PLS by outputting the latched data to the output terminal Q. <2> .

[0146] Latch stage 134E latches new data corresponding to the potential of sensing node SO in response to the third rising edge of latch signal PLS, and latch stage 134F latches data from output terminal Q in response to the third rising edge of latch signal PLS. <1> The received data, and the latch stage 134G latches the data from the output terminal Q in response to the third rising edge of the latch signal PLS. <2> The received data. The latch stage 134E responds to the third falling edge of the latch signal PLS by outputting the latched data to the output terminal Q. <1> The latch stage 134F responds to the third falling edge of the latch signal PLS by outputting the latched data to the output terminal Q. <2> Furthermore, the latch stage 134G responds to the third falling edge of the latch signal PLS by outputting the latched data to the output terminal Q. <3> .

[0147] As described above, whenever the latch signal PLS switches, the multiple latch stages 134E to 134H of the latch assembly 134 latch data corresponding to the potential of the sensing node SO, and send the data latched during the previous switch of the latch signal PLS to the next latch stage.

[0148] Figure 15 This is a diagram illustrating a second embodiment of the control signal generator.

[0149] Reference Figure 15 The control signal generator 142 generates and outputs a latch signal PLS that switches multiple times in response to the switching clock signal CLK. The control signal generator 142 can be included in... Figure 2 The control logic is in 140.

[0150] The timing of the rising edge when the latch signal PLS transitions from low to high and the timing of the falling edge when the latch signal PLS transitions from high to low can be set based on the cell current corresponding to each of the erase state and multiple programming states.

[0151] Figure 16 This is an example Figure 14 The signal waveform diagram of the operation of the latch component is shown.

[0152] Figure 17 This is an example from Figure 14 The diagram shows the data values ​​output by the latch component.

[0153] See below for reference Figures 2 to 6 , Figure 9 , Figure 10 , Figures 11A to 11C and Figures 14 to 17 This describes a read operation of a semiconductor memory device according to an embodiment of the present disclosure.

[0154] In embodiments of this disclosure, a memory cell connected to a selected word line is described as an MLC programmed to an erase state E and multiple programming states PV1 to PV3. Figure 14 The latch assembly 134 includes examples of three latch levels (e.g., 134E, 134F, and 134G).

[0155] During a read operation, voltage generation circuit 150 generates a read voltage Vread and a pass voltage Vpass according to the control signal VG_signals output from control logic 140, and outputs these two voltages to address decoder 120. Address decoder 120 applies the read voltage Vread generated by voltage generation circuit 150 to the selected word line (e.g., WL1) of the selected memory block (e.g., BLK1). Address decoder 120 applies the pass voltage Vpass generated by voltage generation circuit 150 to the unselected word lines (e.g., WL2 to WLn) of the selected memory block (e.g., BLK1). The read voltage Vread can be, for example,... Figures 11A to 11C The voltage shown is gradually increasing over time.

[0156] like Figure 9 As shown, a read voltage Vread generated by the voltage generating circuit 150 can be lower than the threshold voltage of programming state PV3, which has the highest threshold voltage distribution among the erase state E and the plurality of programming states PV1 to PV3, and can be higher than the threshold voltage of programming state PV2, which is adjacent to programming state PV3, which has the highest threshold voltage distribution. For example, a read voltage Vread can be the intermediate voltage value between two programming states PV2 and PV3, which have relatively highest threshold voltage distributions among the erase state E and the plurality of programming states PV1 to PV3. More specifically, a read voltage Vread can be a voltage that gradually increases over time between the threshold voltage value of the maximum number of memory cells in the memory cells corresponding to programming state PV2 and the threshold voltage value of the maximum number of memory cells in the memory cells corresponding to programming state PV3.

[0157] As another implementation, a read voltage Vread can be a voltage higher than the threshold voltage of programming state PV3, which has the highest threshold voltage distribution among the erase state E and the plurality of programming states PV1 to PV3.

[0158] The multiple page buffers PB1 to PBm of the read / write circuit 130 sense the programming status of the memory cell F1 connected to the selected word line WL1 via bit lines BL1 to BLm.

[0159] Since multiple page buffers PB1 to PBm perform sensing operations in a similar manner to each other, the following description of the operation of page buffer PB1 sensing the programming state of memory cells connected to the corresponding bit line BL1 is used as an example.

[0160] The precharger 133 precharges bit line BL1 to a precharge level via sensor 132 and bit line selector 131. Additionally, the precharger 133 precharges sensing node SO to a first level VH.

[0161] When a read voltage Vread is applied to the selected word line WL1, a cell current flowing through bit line BL1 is generated according to the programming state of the memory cell F1 connected to bit line BL1. For example, the cell current can be maximum when memory cell F1 is in erase state E, and minimum when memory cell F1 is in programming state PV3.

[0162] Bit line selector 131 and sensor 132 are electrically connected to bit line BL1 and sensing node SO, and the sensing node SO is evaluated based on the cell current of memory cell F1. That is, the cell current corresponding to the programming state of memory cell F1 flows through bit line BL1. The sensing node SO connected to bit line BL1 is lowered from a first level VH to a second level VL based on the cell current, and the time for the sensing node SO to lower from the first level VH to the second level VL is adjusted according to the magnitude of the cell current. As a result, the time for the potential of the sensing node SO to lower from the first level VH to the second level VL is adjusted according to the programming state of the memory cell.

[0163] For example, when the selected memory cell F1 is in erase state E with the lowest threshold voltage distribution, the cell current of bit line BL1 is at its maximum, and the time for the potential of sensing node SO to decrease from the first level VH to the second level VL is the shortest. For example, when the selected memory cell F1 is in erase state E, the potential of sensing node SO discharges to the second level VL within the first time period. At this time, the read voltage applied in the first time period can have a relatively low potential level compared to the read voltage applied in the second and third time periods. In addition, compared to the case where a read voltage with a constant potential (e.g., Vr2) is applied from the first to the third time periods (dashed line), the discharge time of the memory cell in erase state E can be increased.

[0164] For example, when the selected memory cell F1 is in programming state PV1, which has a threshold voltage distribution higher than that of erase state E, the cell current of bit line BL1 is smaller than that corresponding to erase state E, and the time for the potential of sensing node SO to decrease from the first level VH to the second level VL is longer than that corresponding to erase state E. For example, when the selected memory cell F1 is in programming state PV1, the potential of sensing node SO is discharged to the second level VL during the second time period. At this time, the read voltage applied in the second time period can have a relatively higher potential level compared to the read voltage applied in the first time period, and a relatively lower potential level compared to the read voltage applied in the third time period. In addition, compared to the case where a read voltage with a constant potential (e.g., Vr2) is applied from the first to the third time periods (dashed line), the discharge time of the memory cell in programming state PV1 can be increased.

[0165] For example, when the selected memory cell F1 is in programming state PV2, which has a higher threshold voltage distribution than programming state PV1, the cell current of bit line BL1 is smaller than the cell current corresponding to programming state PV1, and the time for the potential of sensing node SO to decrease from the first level VH to the second level VL is longer than the time corresponding to programming state PV1. For example, when the selected memory cell F1 is in programming state PV2, the potential of sensing node SO is discharged to the second level VL during the third time period. At this time, the read voltage applied in the third time period can have a relatively higher potential level compared to the read voltage applied in the first and second time periods. In addition, compared to the case where a read voltage with a constant potential (e.g., Vr2) is applied from the first to the third time periods (dashed line), the discharge time of the memory cell in programming state PV2 can be reduced.

[0166] For example, when the selected memory cell F1 is in programming state PV3 with the highest threshold voltage distribution, the cell current of bit line BL1 is at its minimum.

[0167] The control signal generator 142 generates and outputs a latch signal PLS that switches multiple times in response to a clock signal CLK that switches at a predetermined period.

[0168] For example, the first switching period of the latch signal PLS can be included in a first time period, which is the time from the point when the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell of the erase state E to the point before the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell of the programming state PV1. That is, the first rising edge and the first falling edge of the latch signal PLS can be included in the first time period.

[0169] For example, the second switching period of the latch signal PLS can be included in the second time period, which is the time from the point when the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell of the programming state PV1 to the point before the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell of the programming state PV2. That is, the second rising edge and the second falling edge of the latch signal PLS can be included in the second time period.

[0170] For example, the third switching period of the latch signal PLS can be included in the third time period, which is the period after the potential level of the sensing node SO decreases from the first level VH to the second level VL through the memory cell of the programming state PV2. That is, the third rising edge and the third falling edge of the latch signal PLS can be included in the third time period.

[0171] The timing of the rising and falling edges of the latch signal PLS can be set based on the cell current corresponding to each of the erase state E and the multiple programming states PV1 to PV3. More specifically, the timing of the rising and falling edges of the latch signal PLS can be based on... Figure 6 The sensing node is set according to the time point when the cell current corresponding to each of the erase state and multiple programming states decreases from the first level VH, which is the pre-charge level, to the second level VL.

[0172] Each of the multiple latch stages 134E to 134G of the latch assembly 134 latches data in response to the latch signal PLS.

[0173] For example, during the first period of the latch signal PLS's first switching, latch stage 134E latches data corresponding to the potential of sensing node SO in response to the rising edge of latch signal PLS. For example, when memory cell F1 is in erase state E, latch stage 134E latches "0" data corresponding to the potential of sensing node SO dropping to the second level VL. Latch stage 134E outputs the latched "0" data to output terminal Q in response to the falling edge of latch signal PLS. <1> For example, when memory cell F1 is in any of the programming states PV1, PV2, and PV3, latch stage 134E latches a "1" data corresponding to a potential of sensing node SO that is higher than the second level VL. Latch stage 134E outputs the latched "1" data to output terminal Q in response to the falling edge of the latch signal PLS. <1> .

[0174] During the second time period of the second switching of the latch signal PLS, latch stage 134F receives and latches data output from latch stage 134E in response to the rising edge of latch signal PLS, and latch stage 134E latches data corresponding to the potential of sensing node SO. For example, when memory cell F1 is in erase state E or programming state PV1, latch stage 134E latches "0" data corresponding to the potential of sensing node SO dropping to the second level VL. For example, when memory cell F1 is in either programming state PV2 or PV3, latch stage 134E latches "1" data corresponding to the potential of sensing node SO above the second level VL.

[0175] The 134E latch stage responds to the falling edge of the latch signal PLS by outputting the latched data to the output terminal Q. <1> The latch stage 134F responds to the falling edge of the latch signal PLS by outputting the latched data to the output terminal Q. <2> .

[0176] During the third time period of the third switching of the latch signal PLS, latch stage 134G receives and latches data output from latch stage 134F in response to the rising edge of latch signal PLS, latch stage 134F receives and latches data output from latch stage 134E in response to the rising edge of latch signal PLS, and latch stage 134E latches data corresponding to the potential of sensing node SO. For example, when memory cell F1 is in erase state E, programming state PV1, or programming state PV2, latch stage 134E latches "0" data corresponding to the potential of sensing SO dropping to the second level VL. For example, when memory cell F1 is in programming state PV3, latch stage 134E latches "1" data corresponding to the potential of sensing node SO above the second level VL.

[0177] The 134E latch stage responds to the falling edge of the latch signal PLS by outputting the latched data to the output terminal Q. <1> The latch stage 134F responds to the falling edge of the latch signal PLS by outputting the latched data to the output terminal Q. <2> The latch stage 134G responds to the falling edge of the latch signal PLS by outputting the latched data to the output terminal Q. <3> .

[0178] The data output circuit 135 receives data from the output terminal Q<3:1> and outputs the MSB data and LSB data as bit read data DATA to the output line BITOUT based on the received data.

[0179] As described above, according to embodiments of this disclosure, during a read operation of a memory cell in which multiple data bits are stored, the programming state of the memory cell can be sensed by sensing the point in time when the sensing node SO drops to a second level while a read voltage is applied to the word line. Therefore, in this embodiment, the operation speed of the read operation can be improved, and the area of ​​the circuitry generating the read voltage can be reduced by using only one read voltage instead of multiple read voltages.

[0180] Figure 18 This is a diagram illustrating another implementation of a memory system.

[0181] Reference Figure 18 The memory system 30000 can be implemented as a cellular phone, smartphone, tablet PC, personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 1100 and a memory controller 1200 capable of controlling the operation of the memory device 1100. The memory controller 1200 can control data access operations of the memory device 1100, such as programming, erasing, or reading operations, under the control of the processor 3100.

[0182] Data programmed in memory device 1100 can be output via display 3200 under the control of memory controller 1200.

[0183] The radio transceiver 3300 can transmit and receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed by the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and send the processed signals to the memory controller 1200 or the display 3200. The memory controller 1200 can program the signals processed by the processor 3100 into the memory device 1100. Alternatively, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the converted radio signals to an external device via the antenna ANT. The input device 3400 can be a device capable of inputting control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200, so that the display 3200 outputs data from the memory controller 1200, data from the radio transceiver 3300, or data from the input device 3400.

[0184] According to the embodiments, the memory controller 1200, which can control the operation of the memory device 1100, can be implemented as part of the processor 3100, or it can be implemented as a chip separate from the processor 3100. Additionally, it can be implemented through... Figure 1 The example controller 1200 shown implements the memory controller 1200.

[0185] Figure 19 This is a diagram illustrating another implementation of a memory system.

[0186] Reference Figure 19 The memory system 40000 can be implemented as a personal computer (PC), tablet PC, netbook, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player or MP4 player.

[0187] The memory system 40000 may include a memory device 1100 and a memory controller 1200 capable of controlling the data processing operations of the memory device 1100.

[0188] The processor 4100 can output data stored in the storage device 1100 via the display 4300 based on data input through the input device 4200. For example, the input device 4200 can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard.

[0189] The processor 4100 can control the overall operation of the memory system 40000 and control the operation of the memory controller 1200. According to an embodiment, the memory controller 1200, which can control the operation of the memory device 1100, can be implemented as part of the processor 4100 or as a separate chip from the processor 4100. Alternatively, it can be implemented through… Figure 1 The example controller 1200 shown implements the memory controller 1200.

[0190] Figure 20 This is a diagram illustrating another implementation of a memory system.

[0191] Reference Figure 20 The memory system 50000 can be implemented as an image processing device, such as a digital camera, a mobile phone equipped with a digital camera, a smartphone equipped with a digital camera, or a tablet PC equipped with a digital camera.

[0192] The memory system 50000 includes a memory device 1100 and a memory controller 1200 capable of controlling data processing operations (e.g., programming operations, erasing operations, or reading operations) of the memory device 1100.

[0193] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals. The converted digital signals can be sent to the processor 5100 or the memory controller 1200. Under the control of the processor 5100, the converted digital signals can be output through the display 5300 or stored in the memory device 1100 through the memory controller 1200. Furthermore, under the control of the processor 5100 or the memory controller 1200, the data stored in the memory device 1100 can be output through the display 5300.

[0194] According to the implementation, the memory controller 1200, which can control the operation of the memory device 1100, can be implemented as part of the processor 5100, or it can be implemented as a chip separate from the processor 5100. Additionally, it can be implemented through... Figure 1 The example controller 1200 shown implements the memory controller 1200.

[0195] Figure 21 This is a diagram illustrating another implementation of a memory system.

[0196] Reference Figure 21 The memory card system 70000 can be implemented as a memory card or a smart card. The memory card system 70000 may include a memory device 1100, a memory controller 1200, and a card interface 7100.

[0197] The memory controller 1200 can control data exchange between the memory device 1100 and the card interface 7100. According to embodiments, the card interface 7100 can be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but is not limited to these. Alternatively, it can be... Figure 1 The example controller 1200 shown implements the memory controller 1200.

[0198] Card interface 7100 can interface for data exchange between host 60000 and memory controller 1200 according to the protocol of host 60000. According to the implementation, card interface 7100 can support Universal Serial Bus (USB) protocol and IC-USB protocol. Here, card interface can refer to hardware, software installed in the hardware, or signal transmission method capable of supporting the protocol used by host 60000.

[0199] When the memory card system 70000 is connected to the host interface 6200 of a host 60000, such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box, the interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200 under the control of the microprocessor 6100.

[0200] Although this disclosure has been described with reference to limited embodiments and accompanying drawings, this disclosure is not limited to the embodiments described above, and those skilled in the art to which this disclosure pertains can make various changes and modifications based on the disclosed description.

[0201] Cross-reference to related applications

[0202] This application claims priority to Korean Patent Application No. 10-2021-0136966, filed on October 14, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.< / m> < / m>

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: A storage block comprising a plurality of memory cells, the plurality of memory cells being programmed to an erase state and a plurality of programmed states; A voltage generating circuit that generates a read voltage to be applied to the word line of the memory block during a read operation; as well as A read / write circuit is connected to the bit line of the memory block and latches data during the read operation by sensing the potential level of the sensing node based on the cell current of the plurality of memory cells within a predetermined time unit. The read voltage is continuously applied to the word line during a predetermined time period, and gradually increases over time during the predetermined time period. The read / write circuit detects the time it takes for the potential of the sensing node to decrease from the first level to the second level by pre-charging the sensing node to the first level once and then sensing the potential of the sensing node multiple times at predetermined time intervals during the predetermined period, and latches the data based on the detected time.

2. The semiconductor memory device according to claim 1, wherein, During the read operation, when the read voltage is applied, the cell current of the plurality of memory cells varies based on the erase state and the plurality of programming states.

3. The semiconductor memory device according to claim 1, wherein, During the read operation, the cell current of the plurality of memory cells varies according to the potential level of the read voltage.

4. The semiconductor memory device according to claim 1, wherein, The read voltage is lower than the threshold voltage of the programming state, which has the highest threshold voltage distribution among the erase state and the plurality of programming states.

5. The semiconductor memory device according to claim 1, wherein, The read voltage is the voltage that increases between the two programming states that have the highest threshold voltage distribution among the erase state and the plurality of programming states.

6. The semiconductor memory device according to claim 1, wherein, The read voltage increases linearly, exponentially, or gradually over time.

7. The semiconductor memory device according to claim 1, wherein, The read / write circuit includes multiple page buffers connected to corresponding bit lines. Each of the plurality of page buffers includes: Bit line selector, wherein the bit line selector connects any one of the bit lines to the sensing node; A precharger precharges the potential of the sensing node to the first level; and A latch component that latches the data by detecting the time it takes for the potential of the sensing node to decrease from a first level to a second level.

8. The semiconductor memory device according to claim 7, wherein, Each of the plurality of page buffers further includes a data output circuit that receives the data output from a plurality of output terminals of the latch assembly and outputs the data to an external location.

9. The semiconductor memory device according to claim 7, wherein, The latch assembly includes multiple latch stages, and Each of the plurality of latch stages latches data corresponding to the potential of the sensing node in response to any one of a plurality of latch signals that are activated sequentially.

10. The semiconductor memory device according to claim 9, wherein, Each of the plurality of latch stages includes: A first transistor is connected between the sensing node and the first node, and is turned on in response to any one of the plurality of latch signals; A latch, the latch being connected between the first node and the second node; and The second transistor is connected between the second node and the output terminal and is turned on in response to a data output signal.

11. The semiconductor memory device according to claim 7, wherein, The latch assembly includes multiple latch stages, and Each of the plurality of latch stages latches data corresponding to the potential of the sensing node in response to multiple switching latch signals.

12. The semiconductor memory device according to claim 11, wherein, The latch assembly includes: The first latch stage latches data corresponding to the potential of the sensing node in response to the rising edge of the latch signal, and outputs the latched data to the first output terminal in response to the falling edge of the latch signal. A second latch stage, which latches data received from the first output terminal in response to the rising edge of the latch signal, and outputs the latched data to the second output terminal in response to the falling edge; and The third latch stage latches data received from the second output terminal in response to the rising edge of the latch signal, and outputs the latched data to the third output terminal in response to the falling edge.

13. The semiconductor memory device according to claim 12, wherein, Each of the plurality of latch stages is configured by a D flip-flop.

14. A semiconductor memory device, the semiconductor memory device comprising: A storage block comprising a plurality of memory cells, the plurality of memory cells being programmed to an erase state and a plurality of programmed states; A voltage generating circuit that generates a read voltage to be applied to the word line of the memory block during a read operation; as well as A page buffer, connected to the bit line of the memory block, precharges a sensing node connected to the bit line to a first level during the read operation and detects the time it takes for the sensing node to drop the first level to a second level based on the programming state of a selected memory cell among the plurality of memory cells connected to the bit line, in order to latch data. Wherein, the reading voltage increases over time, and The page buffer detects the time it takes for the potential of the sensing node to drop from the first level to the second level by precharging the sensing node to the first level once and then sensing the potential of the sensing node multiple times at predetermined time intervals during a predetermined period, and latches the data based on the detected time.

15. The semiconductor memory device according to claim 14, wherein, The reading voltage increases linearly, exponentially, or gradually over time.

16. The semiconductor memory device of claim 14, wherein, The read voltage is lower than the threshold voltage of the programming state, which has the highest threshold voltage distribution among the erase state and the plurality of programming states.

17. The semiconductor memory device of claim 14, wherein, The read voltage is the voltage that increases between the two programming states that have the highest threshold voltage distribution among the erase state and the plurality of programming states.

18. A method of operating a semiconductor memory device, the method comprising the following steps: A read voltage that increases over time is applied to a selected word line that is commonly connected to at least one memory cell; The sensing node corresponding to the at least one memory cell is precharged to a first level; The time it takes for the potential of the sensing node to decrease from the first level to the second level is detected by repeatedly sensing the potential of the sensing node at predetermined time intervals. as well as The data stored in the at least one memory unit is determined based on the detected time.

19. The method according to claim 18, wherein, The reading voltage increases linearly, exponentially, or gradually over time.

20. The method according to claim 18, wherein, The read voltage is the voltage that increases between two programming states that have the highest threshold voltage distribution among the programming states of the at least one memory cell.

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