Method of manufacturing a semiconductor device

Abstract

The application provides a manufacturing method of a semiconductor device. The method can etch the substrate on both sides of each gate structure in a MOS region to form a first source-drain groove for forming a source and a drain, then deposit a source-drain material once in the first source-drain groove to form a source-drain epitaxial layer, then form a dielectric layer on the substrate, etch the dielectric layer so that the etched dielectric layer only serves as a blocking layer of a short channel device, and then fill the first source-drain groove of a long channel device with a second source-drain material deposition process, thereby avoiding the influence of a pattern effect and forming a source-drain epitaxial layer on the source and the drain of the short channel device and the long channel device. The application grows the epitaxial material in the source-drain groove of the short channel and the long channel device in batches, does not need to adjust the parameters of epitaxial growth, guarantees that the epitaxial concentration is not affected, does not need to increase a mask layer, saves the integrated cost, reduces the complexity, and avoids defects caused by the increase of the mask layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a method for manufacturing a semiconductor device. BACKGROUND

[0002] At advanced technology nodes, it is necessary to embed stress material in the source and drain to increase the carrier mobility of the channel, thereby improving the performance of the device. However, as the size of the short channel device continues to shrink at advanced nodes, the size difference between the short channel MOS device and the long channel MOS device becomes larger, and the volume difference of the source / drain U-shaped trench also becomes larger. Therefore, higher requirements are placed on the epitaxial process, that is, a certain thickness of the stress material layer needs to be deposited in the source / drain U-shaped trench of the MOS device of different sizes in one chip. However, the epitaxial process has certain limitations, and the thickness of the stress material layer deposited in the trench is greatly affected by the size of the MOS device pattern, and the growth rate differs under different pattern sizes. For example, as shown in the NMOS SiP epitaxial process, when the source / drain trench of the short channel NMOS device is already filled with the stress material layer, the source / drain trench of the long channel NMOS device has only grown a small part of the stress material layer. Figure 1

[0003] The prior art adjusts the growth parameters of the epitaxial process, but since the growth parameters also have a close influence on the concentration of the epitaxial material, the difficulty of adjusting the growth parameters increases when the concentration is not affected; or by increasing the mask layer, the short channel and long channel devices are grown in different regions, but the production cost and integration complexity are increased. SUMMARY

[0004] The purpose of the present application is to provide a method for manufacturing a semiconductor device, so that the performance and yield of the short channel MOS device and the long channel MOS device in the same chip can meet the design requirements at the same time.

[0005] To solve the above technical problems, the present application provides a method for manufacturing a semiconductor device, which comprises:

[0006] providing a semiconductor substrate, wherein the semiconductor substrate comprises a first long channel and a first short channel with the same conductivity type and different channel lengths in a MOS region;

[0007] etching the semiconductor substrate to form a first source / drain trench in the first long channel and the first short channel, respectively;

[0008] synchronously performing first source / drain material epitaxial growth in each first source / drain trench to form a first source / drain epitaxial layer, wherein the first source / drain epitaxial layer fills the first source / drain trench of the first short channel but does not fill the first source / drain trench of the first long channel;

[0009] ​forming a first dielectric layer on the semiconductor substrate, the first dielectric layer fully covering the first source-drain epitaxial layer in the first short channel but still not filling the first source-drain trench in the first long channel;

[0010] etching the first dielectric layer to remove all the first dielectric layer in the first long channel and simultaneously remove part of the first dielectric layer covering the surface of the first source-drain epitaxial layer in the first short channel, so that the remaining first dielectric layer still fully covers the first source-drain epitaxial layer in the first short channel;

[0011] performing second source-drain material epitaxial growth in the first source-drain trench of the first long channel to form a second source-drain epitaxial layer, the second source-drain epitaxial layer filling the first source-drain trench of the first long channel;

[0012] etching the remaining first dielectric layer to at least re-expose the first source-drain epitaxial layer in the first short channel.

[0013] Optionally, the channel length of the first long channel can be 80nm-140nm, and the channel length of the first short channel can be 15nm-32nm.

[0014] Optionally, the semiconductor substrate can further include a second long channel and a second short channel with the same conductivity type and different channel lengths in the MOS region, and the conductivity type of the second long channel is different from that of the first long channel.

[0015] The manufacturing method can further include:

[0016] Before etching the semiconductor substrate to form the first source-drain trench in the first long channel and the first short channel respectively, the second long channel and the second short channel are masked;

[0017] And / or, the manufacturing method can further include:

[0018] Before etching the semiconductor substrate to form the first source-drain trench, or after forming the second source-drain epitaxial layer, the method can further include:

[0019] Masking the first long channel and the first short channel, and etching the semiconductor substrate to form a second source-drain trench in the second long channel and the second short channel respectively;

[0020] Synchronously performing third source-drain material epitaxial growth in each of the second source-drain trenches to form a third source-drain epitaxial layer, the third source-drain epitaxial layer filling the second source-drain trench of the second short channel but not filling the second source-drain trench of the second long channel;

[0021] forming a second dielectric layer on the semiconductor substrate, the second dielectric layer fully covering the third source-drain epitaxial layer in the second short channel but still not filling the second source-drain trench of the second long channel;

[0022] etching the second dielectric layer to remove all the second dielectric layer in the second long channel and simultaneously remove part of the second dielectric layer on the surface of the third source-drain epitaxial layer in the second short channel, so that the remaining second dielectric layer still fully covers the third source-drain epitaxial layer in the second short channel;

[0023] performing fourth source-drain material epitaxial growth in the second source-drain trench of the second long channel to form a fourth source-drain epitaxial layer, the fourth source-drain epitaxial layer filling the second source-drain trench of the second long channel;

[0024] etching the remaining second dielectric layer to at least re-expose the third source-drain epitaxial layer in the second short channel.

[0025] Optionally, when the conductivity type of the first long channel and the first short channel is N-channel type, the material of the first source-drain epitaxial layer and the second source-drain epitaxial layer includes monocrystalline silicon doped with phosphorus ions and / or carbon phosphosilicon; when the conductivity type of the first long channel and the first short channel is P-channel type, the material of the first source-drain epitaxial layer and the second source-drain epitaxial layer includes germanium silicon doped with boron ions.

[0026] Optionally, the material of the first dielectric layer can include at least one of silicon dioxide, silicon nitride and aluminum trioxide; and / or, the material of the second dielectric layer can include at least one of silicon dioxide, silicon nitride and aluminum trioxide.

[0027] Optionally, a gate structure and a side wall covering the sidewalls on both sides of the gate structure are formed on the semiconductor substrate of the first long channel, the first short channel, the second long channel and the second short channel; wherein the first dielectric layer fills the device gap above the first source-drain trench of the first short channel and covers the sidewalls of the side wall of the first long channel, and / or the second dielectric layer fills the device gap above the second source-drain trench of the second short channel and covers the sidewalls of the side wall of the second long channel.

[0028] Optionally, the width of the first source-drain trench of the first short channel can be 20nm-50nm, and the width of the first source-drain trench of the first long channel can be 60nm-120nm.

[0029] Optionally, the etching process of the first dielectric layer or the second dielectric layer can be a dry etching process, and the dry etching process is a SiCoNi dry etching process provided by an EPI machine.

[0030] Optionally, the etching process of the first dielectric layer or the second dielectric layer can be a wet etching process, and the etching solution of the wet etching process can include phosphoric acid.

[0031] Optionally, the step of providing the semiconductor substrate can include:

[0032] providing a semiconductor substrate, and forming a gate oxide layer, a control gate layer and a patterned hard mask layer on the semiconductor substrate;

[0033] masking the patterned hard mask layer, etching the control gate layer and the gate oxide layer to form a plurality of discrete gate structures.

[0034] Compared with the prior art, the technical scheme of the present application has at least one of the following beneficial effects:

[0035] In the manufacturing method of the semiconductor device provided by the present application, for the first long channel and the first short channel of the MOS region with the same conductive type and different channel lengths, the semiconductor substrate on both sides of each gate structure in the MOS region is etched first to form a first source-drain trench for forming a source and a drain, then a source-drain material is deposited in the first source-drain trench once to form a source-drain epitaxial layer, then a dielectric layer is formed on the semiconductor substrate, and the dielectric layer is etched again, so that the etched dielectric layer only serves as a barrier layer of the short channel device, and a second source-drain material deposition process is used to fill the first source-drain trench of the long channel device, thereby avoiding the pattern effect and forming a source-drain epitaxial layer on the source and the drain of the short channel device and the long channel device. The present application grows epitaxial material in the source-drain trench of the short channel and the long channel device in batches, which does not need to adjust the parameters of epitaxial growth, ensures that the epitaxial concentration is not affected, does not need to increase a mask layer, saves the integration cost, reduces the complexity, and avoids defects caused by the increase of the mask layer. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 is a structure diagram of a source-drain epitaxial layer of a device in a long channel MOS region and a short channel MOS region formed synchronously in the prior art;

[0037] Figure 2 is a flow chart of a manufacturing method of a semiconductor device provided by the present application;

[0038] Figures 3a to 3g is a structure diagram of a semiconductor device in a manufacturing process in an embodiment of the present application;

[0039] Wherein, the reference signs are as follows:

[0040] 100 / 200 - semiconductor substrate; 101 - device isolation structure;

[0041] 111 - gate oxide layer; 112 - control gate layer;

[0042] 113 - patterned hard mask layer; 210 - gate structure;

[0043] 220 - side wall; 102 - first source-drain trench;

[0044] 150 / 250 - hard mask layer; 151 - patterned photoresist layer;

[0045] 160 / 260 - first source-drain epitaxial layer; 170 / 170' - first dielectric layer;

[0046] 180 - second source-drain epitaxial layer; 1 - first long channel;

[0047] 2 - second long channel; 3 - second short channel;

[0048] 4 - first short channel. DETAILED DESCRIPTION

[0049] The present application provides a semiconductor device manufacturing method to make the performance and yield of short channel MOS devices and long channel MOS devices in the same chip meet the design requirements at the same time.

[0050] Reference Figure 2 , Figure 2 A semiconductor device manufacturing method flow chart is provided for the embodiments of the present application. Specifically, the semiconductor device manufacturing method comprises the following steps:

[0051] Step S100, providing a semiconductor substrate, the semiconductor substrate comprising MOS regions of the same conductivity type and different channel lengths of first long channels and first short channels.

[0052] Step S200, etching the semiconductor substrate to form first source-drain trenches in the first long channel MOS regions and the first short channel MOS regions, respectively.

[0053] Step S300, synchronously performing first source-drain material epitaxial growth in each of the first source-drain trenches to form first source-drain epitaxial layers, the first source-drain epitaxial layers filling the first source-drain trenches of the first short channel MOS regions but not filling the first source-drain trenches of the first long channel MOS regions.

[0054] Step S400, forming a first dielectric layer on the semiconductor substrate, the first dielectric layer covering the first source-drain epitaxial layer in the first short channel completely, but still not filling the first source-drain trench of the first long channel.

[0055] Step S500, etching the first dielectric layer to remove all the first dielectric layer covering in the first long channel, and at the same time remove part of the first dielectric layer covering on the surface of the first source-drain epitaxial layer in the first short channel, so that the remaining first dielectric layer still covers the first source-drain epitaxial layer in the first short channel completely.

[0056] Step S600, performing second source-drain material epitaxial growth in the first source-drain trench of the first long channel MOS region to form a second source-drain epitaxial layer, which fills the first source-drain trench of the first long channel MOS region.

[0057] Step S700, etching the remaining first dielectric layer to at least re-expose the first source-drain epitaxial layer in the first short channel MOS region.

[0058] That is, in the manufacturing method of the semiconductor device provided by the present application, for the first long channel and the first short channel of the MOS region with the same conductive type and different channel lengths, the semiconductor substrate on both sides of each gate structure in the MOS region is etched first to form a first source-drain trench for forming a source and a drain, then a first source-drain material is deposited in the first source-drain trench to form a source-drain epitaxial layer, then a dielectric layer is formed on the semiconductor substrate, and the dielectric layer is etched again, so that the etched dielectric layer only serves as a barrier layer for the short channel device, and a second source-drain material deposition process is used to fill the first source-drain trench of the long channel device, thereby avoiding the pattern effect and forming a complete source-drain epitaxial layer for the source and the drain of the short channel device and the long channel device. The present application grows epitaxial material in the short channel and the long channel device source-drain trench in stages, without the need to adjust the epitaxial growth parameters, ensuring that the epitaxial concentration is not affected; and without the need to increase the mask layer, saving the integration cost, reducing the complexity, and avoiding defects caused by the increase of the mask layer.

[0059] The semiconductor device manufacturing method provided by the present application will be further described below in conjunction with the accompanying Figures 3a to 3g and specific embodiments. According to the following description, the advantages and features of the present application will be more apparent. It should be noted that the drawings are greatly simplified and use non-precise proportions, only to facilitate and clarify the purpose of assisting in the description of the embodiments of the present application.

[0060] Figures 3a to 3g is a structure schematic diagram of a semiconductor device in the manufacturing process of an embodiment of the present application.

[0061] In step S100, referring to Fig. 1, Figure 3a As shown in Fig. 1, a semiconductor substrate 100 is provided, which is used to provide a platform for subsequent processes to generate long channel MOS devices and short channel MOS devices. The material of the semiconductor substrate 100 is selected from single crystal silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate 100 can also be selected from silicon, germanium, gallium arsenide or germanium-silicon compound, or the semiconductor substrate 100 can also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate. The material of the semiconductor substrate can be suitable for process requirements or easy to integrate; the semiconductor substrate 100 can also be other semiconductor materials. Exemplarily, in the embodiment of the present application, the semiconductor substrate 100 is a silicon substrate. The semiconductor substrate 100 includes a first long channel 1 and a first short channel 4 with the same conductivity type and different channel lengths in a MOS region, and the semiconductor substrate 100 also includes a second long channel 2 and a second short channel 3 with the same conductivity type and different channel lengths in a MOS region, and the conductivity type of the second long channel 2 is different from that of the first long channel 1. Furthermore, the semiconductor substrate 100 of the first long channel 1, the first short channel 4, the second long channel 2 and the second short channel 3 are all formed with a gate structure 210 and a side wall 220 covering the sidewalls of the gate structure 210 on both sides.

[0062] The channel length of the first long channel 1 (the second long channel 2) can be 80nm-140nm, and the channel length of the first short channel 4 (the second short channel 3) can be 15nm-32nm.

[0063] Generally, in the process of integrated circuit manufacturing, a plurality of MOS devices, for example, a plurality of CMOS devices, need to be formed on a chip, and each CMOS device includes an NMOS tube and a PMOS tube. In practical applications, according to the size of the channel length of the device, the NMOS tube and the PMOS tube can be divided into long channel NMOS tube (PMOS tube) or short channel NMOS tube (PMOS tube). Exemplarily, in the embodiment of the present application, four MOS regions can be formed on the semiconductor substrate 100, wherein the long channel NMOS tube 110n of the MOS region 1 and the long channel PMOS tube 110p of the MOS region 2 constitute a long channel CMOS tube; the short channel PMOS tube 120p of the MOS region 3 and the short channel NMOS tube 120n of the MOS region 4 constitute another short channel CMOS tube.

[0064] Optionally, the present application provides a way to form a corresponding gate structure 210 on each MOS region, which specifically includes the following steps:

[0065] First, a semiconductor substrate 100 is provided, and a gate oxide layer 111, a control gate layer 112 and a patterned hard mask layer 113 are formed on the semiconductor substrate 100;

[0066] The control gate layer 112 and the gate oxide layer 111 are etched with the patterned hard mask layer 113 as a mask to form a plurality of discrete gate structures 210.

[0067] In step S200, referring to Fig. 1, the semiconductor substrate 100 is etched to form first source-drain trenches 102 in the first long channel 1 and the first short channel 4, respectively. Figure 3b The first source-drain trench 102 in the first short channel 4 can have a width of 20-50 nm, and the first source-drain trench 102 in the first long channel 1 can have a width of 60-120 nm. The gate oxide layer 111 can be silicon dioxide, the control gate layer 112 can be polysilicon, and the patterned hard mask layer 113 can be silicon nitride.

[0068] In this embodiment, the manufacturing process can be performed separately according to the conductive type of the devices in the MOS region. Before etching the semiconductor substrate 100 to form the first source-drain trenches 102 in the first long channel 1 and the first short channel 4, respectively, the second long channel 2 and the second short channel 3 are masked. For example, when forming NMOS tubes on the semiconductor substrate 100, a hard mask layer of a certain thickness is first formed on the surface of the semiconductor substrate 100 to cover each MOS device on the surface of the semiconductor substrate 100, and the material of the hard mask layer can be silicon nitride or silicon dioxide. Then, a patterned photoresist layer 151 is formed on the surface of the hard mask layer to mask the PMOS tubes formed on the semiconductor substrate 100, and then a dry etching process is performed on the semiconductor substrate 100 to form corresponding first source-drain trenches 102 in the semiconductor substrate 100 on both sides of the NMOS tubes in the first long channel 1 and the first short channel 4. At this time, since the hard mask layer formed on the PMOS devices in the second long channel 2 and the second short channel 3 is covered by the patterned photoresist layer during the dry etching process, the hard mask layer 150 of the PMOS devices is masked after the etching process, as shown in Fig. 2. Figure 3b The depth of the first source-drain trench 102 can be 40-60 nm.

[0069] In step S300, referring to Fig. 1, Figure 3cAs shown, the first source-drain epitaxial growth is simultaneously performed in each of the first source-drain trenches 102 to form a first source-drain epitaxial layer 160, which fills the first source-drain trenches 102 of the first short channel 4 but does not fill the first source-drain trenches 102 of the first long channel 1. The material of the first source-drain epitaxial layer 160 can include monocrystalline silicon doped with phosphorus ions and / or carbon phosphosilicon.

[0070] In step S400, with reference to Figure 3d As shown, a first dielectric layer 170 is formed on the semiconductor substrate 100, which fully covers the first source-drain epitaxial layer 160 in the first short channel 4 but still does not fill the first source-drain trenches 102 in the first long channel 1. The first dielectric layer 170 fills the device gap above the first source-drain trenches 102 of the first short channel 4 and covers the sidewall of the sidewall 220 of the first long channel 1.

[0071] In this embodiment, a vapor deposition process can be used to deposit a first dielectric layer 170 with a certain thickness on the semiconductor substrate 100, so that the first dielectric layer 170 completely fills the gap between two adjacent gate structures 210 in the second long channel 2 and the second short channel 3, and the gap between two adjacent gate structures 210 in the first short channel 4. Since the first source-drain trenches 102 of the first long channel 1 are not filled by the first source-drain epitaxial layer 160 in step S300, when the first dielectric layer 170 is formed on the surface, the first dielectric layer 170 can only form a first dielectric layer 170 with a certain thickness on the surface of the first source-drain epitaxial layer 160 in the first source-drain trenches 102 of the first long channel 1 and on the sidewall 220 of the gate structure 210, but cannot fill the first source-drain trenches 102 of the first long channel 1. Based on this feature, the first dielectric layer 170 can be used as an etching stop layer or hard mask layer for subsequent etching steps without the need for a second source-drain epitaxial growth device, thereby ultimately achieving the purpose of forming source and drain regions by performing one source-drain epitaxial growth on a short channel MOS device and performing two-step source-drain epitaxial growth on a long channel MOS device.

[0072] Further, in step S500, with reference to Figure 3e As shown, the first dielectric layer 170 is etched to remove all the first dielectric layer 170 covering the first long channel 1, and at the same time remove part of the first dielectric layer 170 covering the surface of the first source-drain epitaxial layer 160 in the first short channel 4, so that the remaining first dielectric layer 170' still fully covers the first source-drain epitaxial layer 160 in the first short channel 4.

[0073] wherein the first dielectric layer 170 is removed to form a first source-drain trench 102 in the first long channel 1 and a second source-drain trench 103 in the second long channel 2, as shown in Figure 3e The etching process of the first dielectric layer 170 can be a dry etching process, such as a SiCoNi dry etching process provided by an EPI machine, or a wet etching process. When the etching process is a wet etching process, the etching solution can include phosphoric acid. The position and thickness of the first dielectric layer 170 removed by the etching process can be controlled by controlling the dosage of the etching solution and the etching time according to actual needs.

[0074] In step S600, the second source-drain material is epitaxially grown in the first source-drain trench 102 of the first long channel 1 to form a second source-drain epitaxial layer 180, as shown in Figure 3f The material of the second source-drain epitaxial layer 180 can include monocrystalline silicon doped with phosphorus ions and / or carbon phosphosilicon.

[0075] In this embodiment, for the first long channel and the first short channel in the MOS region with the same conductivity type and different channel lengths, the semiconductor substrate on both sides of each gate structure in the MOS region is etched first to form a source-drain trench for forming a source and a drain. Then, a first source-drain material is deposited in the first source-drain trench to form a first source-drain epitaxial layer. Then, a dielectric layer is formed on the semiconductor substrate, and the dielectric layer is etched so that the etched dielectric layer only serves as a barrier layer for the device in the short channel MOS region. Then, a second source-drain material deposition process is adopted to fill the first source-drain trench of the device in the long channel MOS region, thereby avoiding the influence of the pattern effect and forming a source-drain epitaxial layer for the source and the drain of the short channel device and the long channel device. The epitaxial material is grown in the source-drain trench of the short channel and the long channel device in batches, which does not need to adjust the parameters of epitaxial growth, thereby ensuring that the epitaxial concentration is not affected. Moreover, no mask layer is needed, which saves the integration cost, reduces the complexity, and avoids defects caused by the addition of the mask layer.

[0076] Optionally, the method for manufacturing the semiconductor device provided by the present application can further include:

[0077] Before etching the semiconductor substrate 100 to form the first source-drain trench 102, or after forming the second source-drain epitaxial layer 180, the method can further include:

[0078] First, the first long channel 1 and the first short channel 4 are masked, and the semiconductor substrate 100 is etched to form a second source-drain trench (not shown) in the second long channel 2 and the second short channel 3, respectively.

[0079] Then, third source-drain material epitaxial growth is synchronously performed in each of the second source-drain trenches to form a third source-drain epitaxial layer (not shown), which fills the second source-drain trench of the second short channel 3 but does not fill the second source-drain trench of the second long channel 2 (not shown);

[0080] Afterwards, a second dielectric layer (not shown) is formed on the semiconductor substrate 100, which fully covers the second source-drain epitaxial layer in the second short channel 3 but still does not fill the second source-drain trench of the second long channel;

[0081] The second dielectric layer is etched to remove all the second dielectric layer covering in the second long channel 2, and at the same time, remove part of the second dielectric layer covering on the surface of the third source-drain epitaxial layer in the second short channel 3, so that the remaining second dielectric layer still fully covers the third source-drain epitaxial layer in the second short channel 3;

[0082] Secondly, fourth source-drain material epitaxial growth is performed in the second source-drain trench of the second long channel 2 to form a fourth source-drain epitaxial layer (not shown), which fills the second source-drain trench of the second long channel 2;

[0083] Finally, the remaining second dielectric layer is etched to at least re-expose the third source-drain epitaxial layer in the second short channel 3.

[0084] The material of the second dielectric layer can include at least one of silicon dioxide, silicon nitride and aluminum trioxide. The second dielectric layer fills the device gap above the second source-drain trench of the second short channel MOS region 3, and covers the sidewall of the sidewall of the second long channel MOS region.

[0085] In the embodiment, the source and drain of the PMOS device can be formed on the semiconductor substrate 100 first, or the source and drain of the PMOS device can be formed after the source and drain of the NMOS device. The present application does not make specific limitation thereon. When the source and drain of the PMOS device are formed on the semiconductor substrate 100 first, the NMOS region on the semiconductor substrate 100 can be shielded by a photoresist layer, and then the source and drain of the PMOS device are formed by the steps described in the present application for forming the source and drain of the NMOS device.

[0086] In step S700, referring to Figure 3g The remaining first dielectric layer 170' is etched to at least re-expose the first source-drain epitaxial layer 160 in the first short channel 4.

[0087] In this embodiment, after forming the source and drain of the devices in the first long channel 1 and the first short channel 4, the first dielectric layer 170' formed on the semiconductor substrate 100 can be removed.

[0088] Optionally, the material of the first dielectric layer 170 can include at least one of silicon dioxide, silicon nitride and aluminum trioxide; and / or, the material of the second dielectric layer includes at least one of silicon dioxide, silicon nitride and aluminum trioxide.

[0089] It should be noted that the material of the first dielectric layer 170 can be aluminum trioxide, and has the following beneficial effects: when the first dielectric layer 170 (aluminum trioxide film layer) is removed by a sulfuric acid wet method, the source and drain of the short channel MOS device and the long channel MOS device formed on the semiconductor substrate 100 are filled with the source and drain epitaxial layer. The etching selectivity of sulfuric acid to aluminum trioxide is higher than the etching selectivity of the material filled in the device isolation structure 101 and the patterned hard mask layer 113 in the gate structure 210, thereby avoiding the loss of the control gate 112 in the device isolation structure 101 and the gate structure 210 when the first dielectric layer 170 is removed.

[0090] In summary, for the first long channel and the first short channel with the same conductivity type and different channel lengths in the MOS region, the semiconductor substrate on both sides of each gate structure in the MOS region can be etched first to form a first source and drain trench for forming the source and drain, then the source and drain material is deposited once in the first source and drain trench to form a source and drain epitaxial layer, then a dielectric layer is formed on the semiconductor substrate, and the dielectric layer is etched again, so that the etched dielectric layer only serves as a barrier layer for the short channel device, and the first source and drain trench of the long channel device is filled by a second source and drain material deposition process, thereby avoiding the pattern effect, and the source and drain of the short channel device and the long channel device are completely formed with the source and drain epitaxial layer. The present application grows epitaxial material in the short channel and long channel device source and drain trench in batches, which does not need to adjust the parameters of epitaxial growth, ensures that the epitaxial concentration is not affected, does not need to increase the mask layer, saves the integration cost, reduces the complexity, and avoids the defects caused by the increase of the mask layer.

[0091] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting; it is not intended to exclude myriad other embodiments of the present application that other present or future devices perform the same function under a different name. It must be noted that, as used in the specification and the appended claims, the singular forms "a," "an" and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a component" can include a plurality of such components. In this specification and in the claims, the term "when" should be understood to mean "whereupon" or "in response to" the happening of the recited condition or event; the phrase "if it is determined" should be understood to mean "in response to a determination that" the recited condition or event has occurred. The terms "application" and "program" refer to one or more computer programs, software components, or modules stored on one or more computer-readable storage media and implemented on one or more computer systems. Unless otherwise specified, all of the applications discussed herein can be stored on the one or more computer-readable storage media, and implemented on one or more computer systems. The terms "computer-readable storage media" and "computer-readable storage medium" include, but are not limited to, one or more types of tangible memory, such as volatile memory (e.g., random access memory, or "RAM"), non-volatile memory (e.g., read-only memory, or "ROM"), or a combination of volatile and non-volatile memory. The terms "computer-readable storage media" and "computer-readable storage medium" also include, but are not limited to, one or more types of tangible media suitable for storing electronic data, such as compact discs (CDs), DVDs, hard disk drives, or any other tangible media suitable for storing electronic data.

[0092] Each of the embodiments described in this specification has at least one aspect in common with at least one other embodiment described in this specification. Accordingly, unless otherwise indicated, the embodiments described in this specification are not mutually exclusive and can be implemented in combination with each other. Moreover, unless otherwise indicated, embodiments that are described in this specification can be implemented in any combination.

[0093] The preferred embodiments of the present application have been disclosed herein above. It should be understood that the application can be carried out without those specific embodiments, details, and examples. Wherefore, the scope of the present application is not intended to be limited to the particular embodiments described in the specification. As such, alterations, modifications, and improvements, in addition to those specifically described in the specification, are intended to be included within the spirit and scope of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate comprising a first long channel and a first short channel of a MOS region having the same conductivity type and different channel lengths; Etching the semiconductor substrate to form first source-drain trenches in the first long channel and the first short channel respectively; Synchronously performing epitaxial growth of a first source / drain material in each of the first source / drain trenches to form a first source / drain epitaxial layer, wherein the first source / drain epitaxial layer fills the first source / drain trench of the first short channel but does not fill the first source / drain trench of the first long channel; forming a first dielectric layer on the semiconductor substrate, wherein the first dielectric layer fully covers the first source and drain epitaxial layer in the first short channel but does not completely fill the first source and drain trenches in the first long channel; Etching the first dielectric layer to remove all of the first dielectric layer covering the first long channel, and simultaneously removing a portion of the first dielectric layer covering the surface of the first source and drain epitaxial layer in the first short channel, so that the remaining first dielectric layer still fully covers the first source and drain epitaxial layer in the first short channel; performing epitaxial growth of a second source / drain material in the first source / drain trench of the first long channel to form a second source / drain epitaxial layer, wherein the second source / drain epitaxial layer fills the first source / drain trench of the first long channel; The remaining first dielectric layer is etched to re-expose at least the first source / drain epitaxial layer in the first short channel.

2. The manufacturing method according to claim 1, wherein The channel length of the first long channel is 80 nm to 140 nm, and the channel length of the first short channel is 15 nm to 32 nm.

3. The manufacturing method according to claim 1, wherein The semiconductor substrate further includes a second long channel and a second short channel having the same conductivity type as the MOS region and different channel lengths, and the second long channel has a different conductivity type from the first long channel; The manufacturing method further comprises: Before etching the semiconductor substrate to form first source-drain trenches in the first long channel and the first short channel, respectively, masking the second long channel and the second short channel; And / or, the manufacturing method further comprises: Before etching the semiconductor substrate to form the first source-drain trench, or after forming the second source-drain epitaxial layer, the method further includes: Masking the first long channel and the first short channel, and etching the semiconductor substrate to form second source and drain trenches in the second long channel and the second short channel, respectively; Synchronously performing epitaxial growth of a third source / drain material in each of the second source / drain trenches to form a third source / drain epitaxial layer, wherein the third source / drain epitaxial layer fills the second source / drain trenches of the second short channel but does not fill the second source / drain trenches of the second long channel; forming a second dielectric layer on the semiconductor substrate, wherein the second dielectric layer fully covers the third source and drain epitaxial layer in the second short channel but does not completely fill the second source and drain trenches of the second long channel; Etching the second dielectric layer to remove all of the second dielectric layer covering the second long channel, and simultaneously removing a portion of the second dielectric layer covering the surface of the third source and drain epitaxial layer in the second short channel, so that the remaining second dielectric layer still fully covers the third source and drain epitaxial layer in the second short channel; performing epitaxial growth of a fourth source / drain material in the second source / drain trench of the second long channel to form a fourth source / drain epitaxial layer, wherein the fourth source / drain epitaxial layer fills the second source / drain trench of the second long channel; The remaining second dielectric layer is etched to re-expose at least the third source / drain epitaxial layer in the second short channel.

4. The manufacturing method according to claim 3, wherein: When the conductivity type of the first long channel and the first short channel is N-channel, the material of the first source / drain epitaxial layer and the second source / drain epitaxial layer includes single crystal silicon and / or silicon carbon phosphide doped with phosphorus ions; when the conductivity type of the first long channel and the first short channel is P-channel, the material of the first source / drain epitaxial layer and the second source / drain epitaxial layer includes germanium silicide doped with boron ions.

5. The manufacturing method according to claim 3, wherein: The material of the first dielectric layer includes at least one of silicon dioxide, silicon nitride and aluminum oxide; and / or the material of the second dielectric layer includes at least one of silicon dioxide, silicon nitride and aluminum oxide.

6. The manufacturing method according to claim 3, wherein: A gate structure and sidewalls covering the sidewalls on both sides of the gate structure are formed on the semiconductor substrate of the first long channel, the first short channel, the second long channel, and the second short channel; wherein the first dielectric layer fills the device gap above the first source / drain trench of the first short channel and covers the sidewalls of the sidewalls of the first long channel, and / or the second dielectric layer fills the device gap above the second source / drain trench of the second short channel and covers the sidewalls of the sidewalls of the second long channel.

7. The manufacturing method according to claim 1, wherein: The width of the first source-drain trench of the first short channel is 20 nm to 50 nm, and the width of the first source-drain trench of the first long channel is 60 nm to 120 nm.

8. The manufacturing method according to claim 3, wherein: The etching process for etching the first dielectric layer or the second dielectric layer is a dry etching process, and the dry etching process is: a SiCoNi dry etching process provided by an EPI machine.

9. The manufacturing method according to claim 3, wherein: The etching process for etching the first dielectric layer or the second dielectric layer is a wet etching process, and an etching solution of the wet etching process includes phosphoric acid.

10. The manufacturing method according to any one of claims 1 to 9, characterized in that: The step of providing the semiconductor substrate comprises: Providing a semiconductor substrate, and forming a gate oxide layer, a control gate layer and a patterned hard mask layer on the semiconductor substrate; The control gate layer and the gate oxide layer are etched using the patterned hard mask layer as a mask to form a plurality of discrete gate structures.

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