An inverter and a control method thereof

Abstract

The application discloses an inverter which is composed of a switched capacitor circuit and a bridge switching circuit; the switched capacitor circuit and the bridge switching circuit are connected with each other; the bridge switching circuit is composed of a left half bridge switching circuit and a right half bridge switching circuit; the left half bridge switching circuit and the right half bridge switching circuit are connected with the switched capacitor circuit respectively. The inverter contains a single direct current input source, six switching tubes, one capacitor and one inductor; the process of charging and discharging of the capacitor in a capacitor period realizes self-balancing of the capacitor voltage, each capacitor keeps the same working state, and stable output of the inverter is realized.

Description

Technical Field

[0001] This invention belongs to the field of inverter technology, and particularly relates to an inverter and its control method. Background Technology

[0002] Traditional inverters consist of a front-end switching unit and a rear-end H-bridge connected in parallel. The front-end unit controls the number of output voltage levels, while the rear-end circuit converts the voltage levels from positive to negative. Traditional inverters employ a relatively complex control method, resulting in a high voltage variation rate and high harmonic distortion. While they control a stable positive and negative stepped waveform based on the switching transistor operating sequence, the rear-end H-bridge is subjected to the accumulated voltage from the front-end, causing the switching transistors to withstand significant reverse peak voltages. This leads to excessively high total voltage stress on the circuit, limiting its application in high-voltage environments. Summary of the Invention

[0003] To address the above problems, this invention proposes an inverter and its control method.

[0004] The inverter consists of a switched capacitor circuit and a bridge switching circuit; the switched capacitor circuit and the bridge switching circuit are interconnected.

[0005] The switched capacitor circuit includes a power supply V. in Switches S3 and S4, capacitor C1, and inductor L1; the power supply V in The positive terminal of the capacitor is connected to the drain of switching transistor S3 and the drain of switching transistor S4 through the first circuit node. The source of switching transistor S3 is connected to the positive terminal of capacitor C1 through the second circuit node. The negative terminal of capacitor C1 is connected to the source of switching transistor S4 and one end of inductor L1 through the third circuit node. The other end of inductor L1 is connected to power supply V through the fourth circuit node. in Negative terminal connection;

[0006] The bridge switching circuit comprises a left half-bridge switching circuit and a right half-bridge switching circuit; the left half-bridge switching circuit and the right half-bridge switching circuit are respectively connected to the switched capacitor circuit.

[0007] The left half-bridge switching circuit includes switching transistor S1 and switching transistor S2; the drain of switching transistor S1 is connected to power supply V through the first circuit node. in The positive terminal of transistor S2 is connected to the drain of transistor S3, and the drain of transistor S4. The source of transistor S2 is connected to power supply V through the fourth circuit node. in The negative terminal of the switch S2 is connected, and the drain of the switch S2 is connected to the source of the switch S1 through the fifth circuit node;

[0008] The right half-bridge switching circuit includes switching transistors S5 and S6; the drain of switching transistor S5 is connected to the source of switching transistor S3 and the positive terminal of capacitor C1 through a second circuit node, and the source of switching transistor S6 is connected to the inductor and power supply V through a fourth circuit node. in The negative terminal of the switch S5 is connected, and the source of the switch S5 is connected to the drain of the switch S6 through the sixth circuit node.

[0009] It also includes an inductive impedance Z1; the inductive impedance Z1 is connected to the left half-bridge switching circuit through the fifth circuit node, and the inductive impedance Z1 is also connected to the right half-bridge switching circuit through the sixth circuit node.

[0010] The power supply V in It is an independent DC power supply.

[0011] With the switching transistor S3 turned on, the power supply V in The capacitor C1 is charged through the switching transistor S3 and the inductor L1.

[0012] When the capacitor C1 is fully charged, the voltage across its terminals is the same as that of the power supply V. in The voltages are equal.

[0013] The present invention also proposes a cascaded inverter, which is formed by cascading multiple inverters as described above.

[0014] The sixth circuit node of the previous inverter is connected to the fifth circuit node of the next inverter to form a cascade.

[0015] The cascaded inverter also includes an inductive impedance Z, which is formed by multiple inductive impedances Z1 connected in series.

[0016] One end of the inductive impedance Z is connected to the fifth circuit node of the first cascaded inverter, and the other end of the inductive impedance Z is connected to the sixth circuit node of the last cascaded inverter.

[0017] The present invention also proposes a control method for an inverter, the method comprising generating a drive signal; controlling the switching transistors of the inverter as described above to turn on or off through the drive signal, so that the inverter operates in five operating states and outputs five voltage levels;

[0018] The generation of the drive signal involves comparing four triangular carrier waves and sinusoidal modulation waves of the same amplitude to obtain different forms of square waves; and logically combining the different forms of square waves to generate drive signals for each switch.

[0019] The present invention also proposes an inverter system, the system comprising an inverter and a controller; the inverter is the inverter described above; the controller is used to generate drive signals to control the inverter.

[0020] The present invention also proposes an inverter control system, the control system comprising an inverter and a controller; the controller is a controller that executes the inverter control method described above to control the inverter.

[0021] Compared with existing technologies, the inverter circuit proposed in this invention includes a separate DC input source, six switching transistors, one capacitor, and one inductor. Based on the switching sequence and the capacitor charging / discharging relationship, it achieves a stepped-wave output of positive and negative voltage levels. The charging / discharging process within the capacitor cycle achieves self-balancing of the capacitor voltage and stable inverter output. The circuit topology adopts a diamond bridge structure, eliminating the need for an H-bridge to achieve voltage polarity conversion. Inductive components improve the circuit output and capacitor charging / discharging performance, thus benefiting circuit protection. The proposed circuit structure reduces the reverse peak voltage experienced by each switching transistor while allowing it to withstand higher input voltages. It is easily modularized and expandable, possessing a high capability to extend to more voltage levels. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a circuit structure diagram of the inverter according to an embodiment of the present invention.

[0024] Figure 2 This is a cascaded inverter structure diagram according to an embodiment of the present invention.

[0025] Figure 3 This is a diagram illustrating the carrier pulse width modulation strategy of an embodiment of the present invention.

[0026] Figure 4 This is a logic diagram of the switching transistor drive signal in an embodiment of the present invention.

[0027] Figure 5(a) is a schematic diagram of the current flow path under the condition of output 0 level in an embodiment of the present invention.

[0028] Figure 5(b) shows the output +V of the embodiment of the present invention. in A schematic diagram of the current flow path under level conditions.

[0029] Figure 5(c) shows the output -V of an embodiment of the present invention. in A schematic diagram of the current flow path under level conditions.

[0030] Figure 5(d) shows the output +2V of the embodiment of the present invention.in A schematic diagram of the current flow path under level conditions.

[0031] Figure 5(e) shows the output -2V of an embodiment of the present invention. in A schematic diagram of the current flow path under level conditions.

[0032] Figure 6 This is a circuit voltage stress diagram under different output levels according to an embodiment of the present invention.

[0033] Figure 7(a) is a diagram of the driving signals of the switching transistors S1 and S2 in an embodiment of the present invention.

[0034] Figure 7(b) is a diagram of the driving signals of the switching transistors S3 and S4 in an embodiment of the present invention.

[0035] Figure 7(c) is a diagram of the driving signals of the switching transistors S5 and S6 in an embodiment of the present invention.

[0036] Figure 8 This is a graph showing the voltage change of capacitor C1 during the charging and discharging process according to an embodiment of the present invention.

[0037] Figure 9(a) is a waveform diagram of the inverter output voltage according to an embodiment of the present invention.

[0038] Figure 9(b) is a waveform diagram of the inverter output current according to an embodiment of the present invention.

[0039] Figure 9(c) is an FFT analysis diagram of the inverter output current in an embodiment of the present invention.

[0040] Figure 10(a) is a waveform diagram of the output voltage of the inverter in an embodiment of the present invention when the DC input voltage is 10V.

[0041] Figure 10(b) is a waveform diagram of the output voltage of the inverter in an embodiment of the present invention when the DC input voltage is 50V.

[0042] Figure 10(c) is a waveform diagram of the output voltage of the inverter in this embodiment of the invention when the DC input voltage is 100V. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] This invention patent primarily focuses on improving the circuit structure of SCMLI (Switched Capacitor Multilevel Inverter), proposing a novel inverter: an inverter circuit employing a diamond-shaped structure to achieve multilevel output. Unlike other bridge circuits, it solves the problem of high voltage stress inherent in traditional switched capacitor inverters, simplifying the complexity of the circuit control loop. The introduction of inductive components in the charging and output voltage loops avoids peak voltage fluctuations during capacitor charging, reducing output current distortion. This protects the circuit while extending its lifespan and reducing component costs, effectively realizing the inverter's boost function and broadening the application scenarios of multilevel inverters.

[0045] like Figure 1 As shown, the inverter consists of a switched capacitor circuit and a bridge switching circuit; the switched capacitor circuit and the bridge switching circuit are interconnected.

[0046] The switched capacitor circuit includes a power supply V. in Switches S3 and S4, capacitor C1, and inductor L1; the power supply V in The positive terminal of the capacitor is connected to the drain of switching transistor S3 and the drain of switching transistor S4 through the first circuit node. The source of switching transistor S3 is connected to the positive terminal of capacitor C1 through the second circuit node. The negative terminal of capacitor C1 is connected to the source of switching transistor S4 and one end of inductor L1 through the third circuit node. The other end of inductor L1 is connected to power supply V through the fourth circuit node. in Negative terminal connection;

[0047] The bridge switching circuit comprises a left half-bridge switching circuit and a right half-bridge switching circuit; the left half-bridge switching circuit and the right half-bridge switching circuit are respectively connected to the switched capacitor circuit.

[0048] The left half-bridge switching circuit includes switching transistor S1 and switching transistor S2; the drain of switching transistor S1 is connected to power supply V through the first circuit node. in The positive terminal of transistor S2 is connected to the drain of transistor S3, and the drain of transistor S4. The source of transistor S2 is connected to power supply V through the fourth circuit node. in The negative terminal of the switch S2 is connected, and the drain of the switch S2 is connected to the source of the switch S1 through the fifth circuit node;

[0049] The right half-bridge switching circuit includes switching transistors S5 and S6; the drain of switching transistor S5 is connected to the source of switching transistor S3 and the positive terminal of capacitor C1 through a second circuit node, and the source of switching transistor S6 is connected to the inductor and power supply V through a fourth circuit node. in The negative terminal of the switch S5 is connected, and the source of the switch S5 is connected to the drain of the switch S6 through the sixth circuit node.

[0050] Figure 1The circuit topology features a symmetrical arrangement of switching transistors at both ends, resembling a rhombus shape. Internally, it comprises capacitors, power supplies, and power devices. This multilevel inverter structure includes an independent input power supply V. in Independent nonlinear components: capacitor C1 and inductor L1, six switching transistors S1-S6, and inductive impedance Z1; the power supply V in It is an independent DC power supply; the inductive impedance Z1 is connected to the left half-bridge switching circuit through the fifth circuit node, and the inductive impedance Z1 is also connected to the right half-bridge switching circuit through the sixth circuit node; in the rhomboid structure, the switching transistors S1, S2 and S5, S6 together form a bridge circuit to realize positive and negative polarity voltage output; inductive devices are introduced into both the charging circuit and the output voltage circuit of capacitor C1 to improve the performance of nonlinear components and ensure the stability of the output; the charging and discharging state of the capacitor is controlled according to the operating sequence of the switching transistors; the input power supply V in The capacitor is charged according to the conduction rules in the closed loop; with switch S3 on, the power supply V... in Capacitor C1 is charged via switch S3 and inductor L1; when capacitor C1 is fully charged, the voltage across its terminals is the same as that of the power supply V. in The voltages are equal; the DC source V in the circuit in The capacitor C1, in conjunction with the various switching transistors, provides power through the fifth and sixth circuit nodes, ultimately achieving 0 and ±V. in ±2V in It has a total of 5 output levels, with a maximum output voltage gain of 2 times.

[0051] Meanwhile, after the inductor L1 is introduced, the charging and discharging of capacitor C1, especially the voltage during the discharge process, is relatively smooth; in contrast, without the inductor L1, the charging and discharging of capacitor C1 fluctuates drastically. The inductive impedance Z1 includes both purely resistive and inductive parts. Without the inductive component, the output waveform is a stepped wave, but now the output is a sine wave, indicating that the harmonic distortion rate is significantly reduced after adding the inductive component.

[0052] The most significant feature of the inverter topology proposed in this invention is its ease of cascading into multiple modular circuits. This allows for the implementation of more voltage levels, which is beneficial for expanding its boost function. For example... Figure 2 As shown in the figure, the present invention further proposes a cascaded inverter, which is formed by cascading multiple inverters; the sixth circuit node of the previous inverter is connected to the fifth circuit node of the next inverter to form a cascade.

[0053] The cascaded inverter also includes an inductive impedance Z, which is formed by multiple inductive impedances Z1 connected in series. One end of the inductive impedance Z is connected to the fifth circuit node of the first cascaded inverter, and the other end of the inductive impedance Z is connected to the sixth circuit node of the last cascaded inverter.

[0054] This invention also proposes a control method for an inverter, the method comprising generating a drive signal; controlling the switching transistors of the inverter as described in claim 1 to be turned on or off through the drive signal, so that the inverter operates in five operating states and outputs five voltage levels;

[0055] The generation of the drive signal involves comparing four triangular carrier waves and sinusoidal modulation waves of the same amplitude to obtain different forms of square waves; and logically combining the different forms of square waves to generate drive signals for each switch.

[0056] This paper summarizes three research methods for multi-level inverters: carrier phase shifting, harmonic elimination, and carrier pulse width stacking. Based on different application scenarios and comparisons, this invention selects the carrier pulse width stacking method to study the proposed topology. The carrier pulse width stacking method compares triangular carriers of the same amplitude with a sinusoidal modulated wave to obtain different forms of square waves. These different square waves are then logically combined and input into switching devices, achieving the inverter output according to a specific timing sequence. The output five-level inverter requires comparing four types of triangular carriers of the same amplitude with a sinusoidal wave. The carrier pulse width modulation strategy is as follows... Figure 3 As shown. Simultaneously, the logic relationship of the driving signals is obtained according to the carrier pulse width stacking method as follows: Figure 4 As shown.

[0057] To simplify circuit analysis, the embodiments of this invention make the following assumptions: 1) The capacitance parameters of the switching transistors are ignored; 2) Heat loss and other losses on the load are neglected; 3) All other components in the circuit are ideal components. Table 1 shows the corresponding relationship between the switching states of switching transistors S1-S6, the output voltage, and the charging and discharging states of capacitor C1. The operating states of each component are represented in the same way as before. The charging and discharging time of capacitor C1 is consistent within one cycle, and it has the same voltage ripple coefficient, which meets the requirement of self-balancing of capacitor charging and discharging voltage.

[0058] Table 1. Switching status and capacitor charging / discharging status at various output voltages.

[0059]

[0060]

[0061] Figure 5 shows a schematic diagram of the inverter current flow path according to an embodiment of the present invention. Figure 5(a) shows the current flow path when the output is at a 0-level, with S2, S3, and S6 remaining on, and S1, S4, and S5 remaining off; DC power supply V... in S3 forms a circuit to charge C1, so that the voltage across C1 reaches the input source voltage V. in Due to the freewheeling effect, S2 and S6 form a positive current loop with the load, and no voltage drop is generated across the load at this time.

[0062] Figure 5(b) shows the output +V in A schematic diagram of the current flow path under level conditions, with S2, S3, and S5 remaining on, and S1, S4, and S6 remaining off. DC power supply V in Together with S3, they form a circuit to charge C1, bringing the voltage across C1 to the power supply voltage V. in S2, S3 and DC power supply V in A series circuit is formed to supply power to the load so that the output voltage across its terminals is equal to V. in At this time, the inverter outputs +V in Level.

[0063] Figure 5(c) shows the output -V in A schematic diagram of the current flow path under level conditions, with S1, S3, and S6 remaining on, and S2, S4, and S5 remaining off. DC power supply V in The circuit formed by S3 charges C1, bringing its voltage to the power supply voltage V. in Simultaneously, the DC power supply forms a series circuit with S1 and S6 to supply power to the load until the output voltage across its terminals equals the input source voltage. At this point, its terminals are -V. in Level.

[0064] Figure 5(d) shows the output +2V. in The diagram illustrates the current flow path under level conditions. S2, S4, and S5 remain on, while S1, S3, and S7 remain off, forming a closed conducting loop. DC power supply V in The circuit is powered by S2, S4, S5, and C1, and the combined voltage gain is twice the voltage output, resulting in a 2V inverter output. in Level.

[0065] Figure 5(e) shows the output -2V. in A schematic diagram of the current flow path under level conditions, with S1, S3, S4, and S6 remaining on, and S2 and S5 remaining off. DC power supply V in The circuit is powered by S1, S3, S4, S6, and C1, resulting in a voltage gain of 2x. At this point, the voltage across the load is -2V.in Level.

[0066] Based on the circuit's modes and properties, the voltage across capacitor C1 during charging is similar to that of the power supply V. in The voltages are the same. Under normal operating conditions, the switching transistors in the off state experience a voltage drop from the input source, known as the reverse peak voltage. When switching transistors S1, S2, S5, and S6 are off, the reverse peak voltage across them is equal to the power supply voltage V. in Half of the voltage, the reverse peak voltage of switches S3 and S4 across the power supply is the power supply voltage V. in Voltage. The maximum peak voltage of the switching transistor shall not exceed the input source voltage V. in The voltage, compared to a full-bridge structure, effectively reduces the accumulated voltage, improving the circuit properties. (By...) Figure 6 It can be seen that the proposed topology has the highest total voltage stress when the output level is twice that of the circuit.

[0067] This invention also proposes an inverter system, which includes an inverter and a controller; the inverter is the inverter described above; the controller is used to generate drive signals to control the inverter.

[0068] This invention also proposes an inverter control system, which includes an inverter and a controller; the controller is a controller that executes the inverter control method described above to control the inverter.

[0069] To verify the correctness of the theoretical analysis of the proposed low-voltage stress inverter, the proposed topology was simulated using PSIM software. The input source voltage of the topology was 20V, and the same type of components were used in both circuit topologies. Figure 7 shows the drive signal waveforms using the carrier pulse width stacking method with a modulation wave of 50Hz and a carrier wave of 2kHz. Figure 7(a) shows the drive signal diagrams of switches S1 and S2, Figure 7(b) shows the drive signal diagrams of switches S3 and S4, and Figure 7(c) shows the drive signal diagrams of switches S5 and S6. The pulse waveform diagrams of switches S1-S7 in Figure 7 are consistent with the theoretical analysis.

[0070] Figure 8 The figure shows the voltage change curve of capacitor C1 during the charging and discharging process. According to the waveform shown, the voltage of capacitor C1 changes with the switching sequence. When the charging voltage reaches its peak voltage, there are no drastic fluctuations or jumps. After reaching a stable state, the voltage gradually decreases during discharging, changing stably within the period, effectively reducing the heat generation of the device.

[0071] Figure 9 shows the FFT diagrams of the inverter output voltage, load current, and output current in an embodiment of the present invention. As can be seen from the inverter output voltage waveform in Figure 9(a) and the inverter output current waveform in Figure 9(b), the inverter in this embodiment achieves a maximum five-level stepped waveform output, with a peak output voltage of 40V and a peak output current of 0.4A. The load current waveform also closely approximates an ideal sinusoidal stepped waveform. The THD of the output current in the current FFT analysis diagram in Figure 9(c) is 16.3%, which meets the requirements within a certain range, fully verifying the feasibility of this circuit achieving five-level output.

[0072] Figure 10 shows the voltage waveforms of the inverter under different DC input voltages. Figure 10(a) shows the output voltage waveform when the DC input voltage of the inverter is 10V, Figure 10(b) shows the output voltage waveform when the DC input voltage of the inverter is 50V, and Figure 10(c) shows the output voltage waveform when the DC input voltage of the inverter is 100V. Changing the input voltage changes the maximum gain of the corresponding output voltage, but does not change the number of output levels, and the maximum gain is still twice the input voltage.

[0073] Although specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. Those skilled in the art should understand that modifications to the technical solutions described in the above embodiments or equivalent substitutions of some technical features may be made without departing from the scope and spirit of the present invention, and all such modifications or substitutions are within the protection scope of the present invention.

Claims

1. An inverter, characterized in that, The inverter consists of a switched capacitor circuit and a bridge switching circuit; the switched capacitor circuit and the bridge switching circuit are interconnected. The switched capacitor circuit includes a power supply V. in Switches S3 and S4, capacitor C1, and inductor L1; the power supply V in The positive terminal of the capacitor is connected to the drain of switching transistor S3 and the drain of switching transistor S4 through the first circuit node. The source of switching transistor S3 is connected to the positive terminal of capacitor C1 through the second circuit node. The negative terminal of capacitor C1 is connected to the source of switching transistor S4 and one end of inductor L1 through the third circuit node. The other end of inductor L1 is connected to power supply V through the fourth circuit node. in Negative terminal connection; The bridge switching circuit comprises a left half-bridge switching circuit and a right half-bridge switching circuit; the left half-bridge switching circuit and the right half-bridge switching circuit are respectively connected to the switched capacitor circuit. The left half-bridge switching circuit includes switching transistor S1 and switching transistor S2; the drain of switching transistor S1 is connected to power supply V through the first circuit node. in The positive terminal of transistor S2 is connected to the drain of transistor S3 and the drain of transistor S4. The source of transistor S2 is connected to the other end of inductor L1 and power supply V through the fourth circuit node. in The negative terminal of the switch S2 is connected, and the drain of the switch S2 is connected to the source of the switch S1 through the fifth circuit node; The right half-bridge switching circuit includes switching transistors S5 and S6; the drain of switching transistor S5 is connected to the source of switching transistor S3 and the positive terminal of capacitor C1 through a second circuit node, and the source of switching transistor S6 is connected to the other end of inductor L1 and power supply V through a fourth circuit node. in The negative terminal of the switch S5 is connected, and the source of the switch S5 is connected to the drain of the switch S6 through the sixth circuit node.

2. The inverter according to claim 1, characterized in that, It also includes an inductive impedance Z1; the inductive impedance Z1 is connected to the left half-bridge switching circuit through the fifth circuit node, and the inductive impedance Z1 is also connected to the right half-bridge switching circuit through the sixth circuit node.

3. The inverter according to claim 1, characterized in that, The power supply V in It is an independent DC power supply.

4. The inverter according to claim 1, characterized in that, With the switching transistor S3 turned on, the power supply V in The capacitor C1 is charged through the switching transistor S3 and the inductor L1.

5. The inverter according to claim 4, characterized in that, When the capacitor C1 is fully charged, the voltage across its terminals is the same as that of the power supply V. in The voltages are equal.

6. A cascaded inverter, characterized in that, The cascaded inverter is formed by cascading multiple inverters as described in claim 1. The sixth circuit node of the previous inverter is connected to the fifth circuit node of the next inverter to form a cascade.

7. The cascaded inverter according to claim 6, characterized in that, The cascaded inverter also includes an inductive impedance Z, which is formed by multiple inductive impedances Z1 connected in series. One end of the inductive impedance Z is connected to the fifth circuit node of the first cascaded inverter, and the other end of the inductive impedance Z is connected to the sixth circuit node of the last cascaded inverter.

8. A control method for an inverter, characterized in that, The method includes generating a drive signal; controlling the switching transistors of the inverter as described in claim 1 to be turned on or off via the drive signal, so that the inverter operates in five operating states and outputs five different voltage levels; The generation of the drive signal involves comparing four triangular carrier waves and sinusoidal modulation waves of the same amplitude to obtain different forms of square waves; and logically combining the different forms of square waves to generate drive signals for each switch.

9. An inverter system, characterized in that, The system includes an inverter and a controller; the inverter is the inverter as described in claim 1; the controller is used to generate drive signals to control the inverter.

10. An inverter control system, characterized in that, The control system includes an inverter and a controller; the controller is a controller that performs the inverter control method as described in claim 8 to control the inverter.

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