A fast phase correction method for signal simulator based on DRFM module

Abstract

The present invention discloses a method for rapid phase correction of a signal simulator based on a DRFM module. The signal simulator has two operating modes: a normal operating mode and a phase correction operating mode. In the phase correction operating mode, the FPGA chip of the DRFM module generates an intermediate frequency pulse signal, which is output to a power splitter module via the DA chip of the DRFM module. The power splitter module inputs the intermediate frequency pulse signal into the switch module via an intermediate frequency closed-loop correction circuit, and then inputs the intermediate frequency pulse signal into the AD chip of the DRFM module via the switch module. The computer control module performs phase analysis on the intermediate frequency pulse signal generated by the FPGA chip and the intermediate frequency pulse signal collected by the FPGA chip via the AD chip, for phase correction of the signal simulator. The present invention has the characteristics of a simple and rapid phase correction process, and no need for manual intervention.

Description

Technical Field

[0001] The invention belongs to the technical field of signal simulators, and in particular relates to a fast phase correction method of a signal simulator based on a DRFM module. Background Art

[0002] With the rapid development of electronic technology, DRFM (Digital Radio Frequency Memory) technology has become a mainstream signal processing and signal generation technology in radio frequency simulation systems, semi-physical simulation systems, and electronic warfare equipment. Signal simulators with DRFM modules as their core can directly digitize radio frequency signals for processing and storage, realizing the simulation of target echo signals, interference signals, radiation signals, and other signals.

[0003] A DRFM module typically consists of an AD chip, a DA chip, an FPGA chip, and memory. Because the operating clocks of the AD and DA chips differ from those of the FPGA chip, and because data transmission delays between the AD and FPGA chips, and between the DA and FPGA chips, fluctuate, the transfer function phase of the DRFM module itself can change randomly with each power cycle. (The transfer function phase remains unchanged after power is cycled.) Some simulation systems or equipment require multiple DRFM-based signal simulators, each with a defined phase relationship between the simulator channels. Each power cycle requires calibrating the DRFM module's phase.

[0004] Currently, phase correction is commonly performed using instruments (such as vector network analyzers) or specialized equipment. This requires manual intervention, is complex and time-consuming, and requires operators to be familiar with the operation of the instrumentation. Furthermore, some equipment cannot tolerate the time-consuming calibration process, resulting in equipment malfunction. Summary of the Invention

[0005] In order to solve the deficiencies in the prior art, the present invention provides a fast phase correction method for a signal simulator based on a DRFM module, which has the characteristics of a simple and fast phase correction process and no need for manual intervention.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] In a first aspect, a signal simulator is provided, comprising: a down-conversion module, a DRFM module, an up-conversion module, a frequency synthesis module, a computer control module, and an intermediate frequency closed-loop correction circuit; the frequency synthesis module provides a clock signal for the down-conversion module, the DRFM module, and the up-conversion module; the computer control module is electrically connected to the FPGA chip of the DRFM module; the signal simulator has two operating modes: a normal operating mode and a phase correction operating mode; in the normal operating mode, the down-conversion module receives a radio frequency input signal and converts the radio frequency input signal into an intermediate frequency input signal, and the intermediate frequency input signal is input into the AD chip of the DRFM module via a switch module; the DRFM module modulates the intermediate frequency input signal and converts it into an intermediate frequency output signal , then output to the power division module through the DA chip of the DRFM module, and then input to the up-conversion module through the power division module, and the up-conversion module converts the intermediate frequency output signal into an RF output signal; in the phase correction working mode, the FPGA chip of the DRFM module generates an intermediate frequency pulse signal, which is output to the power division module through the DA chip of the DRFM module, and the power division module inputs the intermediate frequency pulse signal into the switch module through the intermediate frequency closed-loop correction circuit, and then inputs into the AD chip of the DRFM module through the switch module, and the computer control module performs phase analysis on the intermediate frequency pulse signal generated by the FPGA chip and the intermediate frequency pulse signal collected by the FPGA chip through the AD chip, for phase correction of the signal simulator.

[0008] Furthermore, the intermediate frequency closed-loop correction circuit includes a low-pass filter, the input end of the low-pass filter is electrically connected to one of the output ends of the power division module, and the output end of the low-pass filter is electrically connected to one of the input ends of the switch module.

[0009] Furthermore, the DRFM module further includes a storage chip, and the storage chip is electrically connected to the FPGA chip of the DRFM module.

[0010] In a second aspect, a phase correction method for a signal simulator is provided, wherein the signal simulator is the signal simulator described in the first aspect, and the method comprises: the signal simulator is kept powered on, an intermediate frequency pulse signal is generated in the FPGA chip of the DRFM module, and is output through the DA chip; the intermediate frequency pulse signal passes through an intermediate frequency closed-loop correction circuit, is collected by the AD chip, and is sent to the FPGA chip; the FPGA chip sends the intermediate frequency output signal collected by the AD chip and the intermediate frequency pulse signal generated by the FPGA chip to a computer control module; and the computer control module uses the least squares method to calculate the phase difference between the intermediate frequency output signal collected by the AD chip and the intermediate frequency pulse signal generated by the FPGA chip, and records it as (Φ DA +Φ AD )记录 After the signal simulator is powered off, power it on again and repeat the above steps to obtain the Φ after this power-on. AD +Φ DA Value, recorded as (Φ DA +Φ AD ) 本次 ; Input the RF input signal to the signal simulator and perform phase modulation in the DRFM module. The modulation value is (Φ DA +Φ AD ) 本次 -(Φ DA +Φ AD ) 记录 , completing the phase correction of the signal simulator.

[0011] Furthermore, before the FPGA chip of the DRFM module generates the intermediate frequency pulse signal, a vector network analyzer is used to measure the phase difference between the RF output signal and the RF input signal of the signal simulator and record it as Φ OUT -Φ IN , used to verify the modulation value of phase correction, the verification condition is: Equation Φ OUT -Φ IN =(Φ DA +Φ AD ) 本次 -(Φ DA +Φ AD ) 记录 Established.

[0012] Furthermore, when the phases of a plurality of the signal simulators need to be corrected to be consistent, the phase of each of the signal simulators is corrected respectively first, and then the phases of the remaining signal simulators are adjusted based on one of the signal simulators.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] (1) The present invention receives a radio frequency input signal through a down-conversion module and converts the radio frequency input signal into an intermediate frequency input signal, which is then input into the AD chip of the DRFM module via a switch module; the DRFM module converts the intermediate frequency input signal into an intermediate frequency output signal, which is then output to the power splitter module via a DA chip; the power splitter module inputs one of the intermediate frequency output signals into the switch module via an intermediate frequency closed-loop correction circuit, and then inputs the signal into the AD chip of the DRFM module via the switch module; the FPGA chip of the DRFM module inputs the intermediate frequency output signal collected by the AD chip and the transmission signal of the intermediate frequency output signal into a computer control module for phase analysis, which is used for phase correction of a signal simulator, and has the characteristics of a simple and fast phase correction process, and no need for manual intervention;

[0015] (2) The present invention realizes a fast, automatic, high-precision, digital phase correction method for a signal simulator based on DRFM technology. No instrument is required, and the correction process does not require human intervention. The device automatically corrects after power-on. The correction speed is fast, the accuracy is high, and the adaptability is strong. It can meet the phase consistency correction requirements of multiple signal simulator channels based on DRFM modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of the composition principle of a signal simulator based on a DRFM module;

[0017] Figure 2 This is a schematic diagram of the phase correction principle of a signal simulator based on a DRFM module provided by an embodiment of the present invention (wherein the frequency synthesis module is not drawn). DETAILED DESCRIPTION

[0018] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0019] Example 1:

[0020] like Figure 1 As shown in FIG, a signal simulator based on a DRFM module usually includes a down-conversion module, a DRFM module, an up-conversion module, a frequency synthesizer module, and a computer control module, wherein the DRFM module includes an AD chip, a DA chip, an FPGA chip, a storage chip, and the like.

[0021] like Figure 2 As shown, this embodiment provides a signal simulator based on a DRFM module, including: a down-conversion module, a DRFM module, an up-conversion module, a frequency synthesizer module, a computer control module and an intermediate frequency closed-loop correction circuit.

[0022] The frequency synthesizer module provides clock signals for the down-conversion module, DRFM module and up-conversion module.

[0023] The computer control module is electrically connected to the FPGA chip of the DRFM module. The signal simulator has two working modes: normal working mode and phase correction working mode.

[0024] In normal working mode, the down-conversion module receives the RF input signal and converts it into an intermediate frequency input signal. The intermediate frequency input signal is input into the AD chip of the DRFM module through the switch module. The DRFM module modulates the intermediate frequency input signal and converts it into an intermediate frequency output signal. The signal is then output to the power splitter module through the DA chip of the DRFM module. The signal is then input into the up-conversion module through the power splitter module. The up-conversion module converts the intermediate frequency output signal into an RF output signal.

[0025] In the phase correction working mode, the FPGA chip of the DRFM module generates an intermediate frequency pulse signal, which is output to the power division module through the DA chip of the DRFM module. The power division module inputs the intermediate frequency pulse signal into the switch module through the intermediate frequency closed-loop correction circuit, and then inputs it into the AD chip of the DRFM module through the switch module. The computer control module performs phase analysis on the intermediate frequency pulse signal generated by the FPGA chip and the intermediate frequency pulse signal collected by the FPGA chip through the AD chip for phase correction of the signal simulator.

[0026] The intermediate frequency closed-loop correction circuit includes a low-pass filter, an input end of the low-pass filter is electrically connected to one of the output ends of the power division module, and an output end of the low-pass filter is electrically connected to one of the input ends of the switch module.

[0027] The DRFM module further includes a memory chip, which is electrically connected to the FPGA chip of the DRFM module.

[0028] The phase correction principle is as follows.

[0029] After the signal simulator is powered on, the power state remains unchanged. At this time, the phase difference between the AD chip and the FGPA chip caused by the clock and transmission delay jitter is Φ AD , the phase difference between the DA chip and the FGPA chip is Φ DA To determine the value, the initial phase of the RF input signal input by the signal simulator is Φ IN , the phase difference caused by other parts of the signal simulator except the AD chip and DA chip is Φ Δ , then the phase of the RF output signal Φ OUT for:

[0030] Φ OUT =Φ IN +Φ AD +Φ DA +Φ Δ

[0031] Among them, Φ AD and Φ DA It is a fixed value after each power-on, and it will change randomly between each power-on, which is the phase that needs to be corrected. Δ is a fixed value related to the total electrical length of all devices in the circuit except the AD chip and DA chip. The above formula can be converted into the following formula, that is, the phase difference between the RF output signal and the RF input signal (the phase difference caused by the electrical length of the signal simulator) is composed of three parts: Φ AD , Φ DA and Φ Δ :

[0032] Φ OUT -Φ IN =Φ AD+Φ DA +Φ Δ

[0033] The phase difference caused by the electrical length of the signal simulator can be measured by a vector network analyzer. AD +Φ DA The value of Φ can be obtained AD +Φ DA Value and Φ OUT -Φ IN The corresponding relationship.

[0034] Φ AD +Φ DA The value is measured as follows.

[0035] A point frequency pulse (intermediate frequency pulse signal) is generated in the FPGA chip of the DRFM module and played out through the DA chip. The output intermediate frequency pulse signal enters the low-pass filter in the intermediate frequency closed-loop correction circuit after passing through the power divider of the power divider module, and then enters the AD chip after switching through the switch in the switch module. The AD chip collects the intermediate frequency pulse signal and sends it to the FPGA chip. The FPGA chip transmits the collected intermediate frequency pulse signal and its own output signal (digital baseband, that is, the transmission signal of the intermediate frequency output signal) to the computer control module, and the computer control module performs phase analysis on these two signals.

[0036] The phase of the generated point frequency pulse is Φ1, and the phase of the signal after output by the DA chip is Φ1+Φ DA After correcting the intermediate frequency closed-loop branch, the signal phase is Φ1+Φ DA +Φ 支 (Φ 支 The phase of the intermediate frequency closed-loop branch includes the influence of cables, power dividers, switches, and low-pass filters, which is a fixed value. After being collected by the AD chip, it is sent to the FPGA chip. The signal phase is Φ1+Φ DA +Φ 支 +Φ AD , compared with the generated pulse signal phase Φ1, the increase of Φ DA +Φ 支 +Φ AD , where Φ 支 Is a fixed value. Send the collected signal and the transmitted signal (digital baseband) to the computer control module, and use the least square method in the computer control module to obtain Φ DA +Φ 支 +Φ AD value, fixed value Φ 支 The same applies to each power-up. DA +Φ AD No impact, can be ignored.

[0037] The Φ is measured by a vector network analyzer. OUT -Φ IN The value can be measured by generating a signal internally and closing the intermediate frequency loop. AD +Φ DA Value, record this Φ DA +Φ AD and Φ OUT -Φ IN value.

[0038] After power off, power on again and then use the internal intermediate frequency self-closed loop to measure the Φ after this power on. AD +Φ DA Value, according to the Φ of this measurement AD +Φ DA Value and recorded Φ DA +Φ AD The difference between the values ​​is used to perform phase compensation on the signal received by the simulator in FPGA. The compensation amount is (Φ DA +Φ AD ) 本次 -(Φ DA +Φ AD ) 记录 , which ensures that the phase difference between the simulator output signal and the input signal is the recorded Φ OUT -Φ IN value.

[0039] Since the correction is performed at the intermediate frequency, the measured Φ DA +Φ AD It is independent of the input signal frequency and does not require frequency traversal when performing phase correction, which can greatly shorten the correction time. It only needs to measure Φ with a vector network analyzer. OUT -Φ IN Frequency traversal is performed at the same time, and this work only needs to be done once, and there is no need to do it every time calibration is performed.

[0040] The signal simulator based on the DRFM module described in the present invention can perform fast, automatic, and high-precision digital correction of the phase without the need for instruments and manual intervention in the correction process. The equipment automatically corrects after power-on, with fast correction speed, high precision, and strong adaptability, and can meet the phase consistency correction requirements of multiple signal simulator channels based on the DRFM module.

[0041] Example 2:

[0042] Based on the signal simulator based on the DRFM module described in Example 1, this embodiment provides a phase correction method for the signal simulator, wherein the signal simulator is the signal simulator described in Example 1, and the method includes:

[0043] 1. After the signal simulator is powered on, the phase difference between the output signal and the input signal of the signal simulator is measured using a vector network analyzer and recorded as Φ OUT -Φ IN ;

[0044] 2. The signal simulator remains powered on, and an intermediate frequency pulse signal is generated in the FPGA chip of the DRFM module. The intermediate frequency pulse signal is output through the DA chip. After passing through the intermediate frequency closed-loop correction circuit, the AD chip collects the signal and sends it to the FPGA chip.

[0045] 3. The FPGA chip sends the intermediate frequency output signal collected by the AD chip and the intermediate frequency pulse signal generated by the FPGA chip to the computer control module;

[0046] 4. In the computer control module, the least square method is used to calculate the phase difference between the intermediate frequency output signal collected by the AD chip and the intermediate frequency pulse signal generated by the FPGA chip, and the phase difference is recorded as (Φ DA +Φ AD ) 记录 ;

[0047] 5. After the signal simulator is powered off, power it on again and repeat steps 2 to 4 to obtain the Φ after this power-on. AD +Φ DA Value, recorded as (Φ DA +Φ AD ) 本次 ;

[0048] 6. Input the RF input signal to the signal simulator and perform phase modulation in the DRFM module. The modulation value is (Φ DA +Φ AD ) 本次 -(Φ DA +Φ AD ) 记录 , complete the phase correction of the signal simulator; the phase difference between the RF output signal and the RF input signal of the signal simulator measured in step 1 can be used to verify the modulation value of the phase correction. The verification condition is: Equation Φ OUT -Φ IN =(Φ DA +Φ AD ) 本次 -(Φ DA +Φ AD ) 记录 Established;

[0049] 7. When multiple DRFM-based signal simulators are used and the phase difference between each simulator channel is required to be consistent, steps 1 to 6 can be performed for each simulator channel separately. After completion, the phase difference between the output signal and the input signal of each simulator channel is fixed. Furthermore, by using one channel as a reference and compensating for the fixed phase difference between the channels, the phase difference between multiple simulator channels can be consistent.

[0050] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A signal simulator, characterized in that include: Down-conversion module, DRFM module, up-conversion module, frequency synthesizer module, computer control module and intermediate frequency closed-loop correction circuit; The frequency synthesis module provides a clock signal for the down-conversion module, the DRFM module and the up-conversion module; the computer control module is electrically connected to the FPGA chip of the DRFM module; The signal simulator has two working modes: normal working mode and phase correction working mode; In normal working mode, the down-conversion module receives a radio frequency input signal and converts the radio frequency input signal into an intermediate frequency input signal. The intermediate frequency input signal is input into the AD chip of the DRFM module via the switch module. The DRFM module modulates the intermediate frequency input signal and converts it into an intermediate frequency output signal. The intermediate frequency output signal is then output to the power splitter module via the DA chip of the DRFM module. The intermediate frequency output signal is then input into the up-conversion module via the power splitter module. The up-conversion module converts the intermediate frequency output signal into a radio frequency output signal. In the phase correction working mode, the FPGA chip of the DRFM module generates an intermediate frequency pulse signal, which is output to the power division module through the DA chip of the DRFM module. The power division module inputs the intermediate frequency pulse signal into the switch module through the intermediate frequency closed-loop correction circuit, and then inputs the intermediate frequency pulse signal into the AD chip of the DRFM module through the switch module. The computer control module performs phase analysis on the intermediate frequency pulse signal generated by the FPGA chip and the intermediate frequency pulse signal collected by the FPGA chip through the AD chip for phase correction of the signal simulator.

2. The signal simulator according to claim 1, wherein The intermediate frequency closed-loop correction circuit includes a low-pass filter, the input end of the low-pass filter is electrically connected to one of the output ends of the power division module, and the output end of the low-pass filter is electrically connected to one of the input ends of the switch module.

3. The signal simulator according to claim 1, wherein The DRFM module further includes a memory chip, which is electrically connected to the FPGA chip of the DRFM module.

4. A phase correction method for a signal simulator, characterized in that: The signal simulator is the signal simulator according to any one of claims 1 to 3, and the method comprises: The signal simulator remains powered on, and an intermediate frequency pulse signal is generated in the FPGA chip of the DRFM module. The intermediate frequency pulse signal is output through the DA chip. After passing through the intermediate frequency closed-loop correction circuit, the AD chip collects the intermediate frequency pulse signal and sends it to the FPGA chip. The FPGA chip sends the intermediate frequency output signal collected by the AD chip and the intermediate frequency pulse signal generated by the FPGA chip to the computer control module; The phase difference between the intermediate frequency output signal collected by the AD chip and the intermediate frequency pulse signal generated by the FPGA chip is calculated using the least squares method in the computer control module and recorded as (Φ DA +Φ AD ) 记录 ; After the signal simulator is powered off, power it on again and repeat the above steps to obtain the Φ after this power-on. AD +Φ DA Value, recorded as (Φ DA +Φ AD ) 本次 ; Input the RF input signal to the signal simulator and perform phase modulation in the DRFM module. The modulation value is (Φ DA +Φ AD ) 本次 -(Φ DA +Φ AD ) 记录 , completing the phase correction of the signal simulator.

5. The phase correction method of the signal simulator according to claim 4, characterized in that: Before the FPGA chip of the DRFM module generates the intermediate frequency pulse signal, the phase difference between the RF output signal and the RF input signal of the signal simulator is measured using a vector network analyzer and recorded as Φ OUT -Φ IN , used to verify the modulation value of phase correction, the verification condition is: Equation Φ OUT -Φ IN =(Φ DA +Φ AD ) 本次 -(Φ DA +Φ AD ) 记录 Established.

6. The phase correction method of a signal simulator according to claim 4, characterized in that: When the phases of the plurality of signal simulators need to be corrected to be consistent, the phase of each signal simulator is corrected respectively first, and then the phases of the remaining signal simulators are adjusted based on one of the signal simulators.

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