An Asynchronous Fuzzy Communication Method and System in a Differentiated Model

Abstract

The present invention relates to an asynchronous fuzzy communication method and system in a differential model. The method includes the following steps: Asynchronous fuzzy connection: The host computer sends a first communication data frame to the chip; the chip determines whether the data at a preset position in the received first communication data frame meets a first preset condition, and the length of the preset position is less than the data length of the first communication data frame; if it meets the condition, the chip sends a first confirmation data frame to the host computer; if it does not meet the condition, the communication with the host computer ends; when the host computer receives the first confirmation data frame, an asynchronous fuzzy connection is established with the chip. By adopting fuzzy connection, the effective information is reasonably compressed, and the problem of asynchronous communication connection in the differential model is solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and particularly to an asynchronous fuzzy communication method and system in a differential model. Background Art

[0002] An integrated circuit is a microelectronic device or component. Using a certain process, components such as transistors, resistors, capacitors, and inductors required in a circuit, as well as the wiring, are interconnected and fabricated on a small piece or a few small pieces of semiconductor wafers or dielectric substrates, and then encapsulated in a package to form a micro-structure with the required circuit functions; all components are integrated as a whole in structure, which has taken a big step forward in the miniaturization, low power consumption, intelligence, and high reliability of electronic components. It is represented by the letter "IC" in the circuit.

[0003] Regarding the process discreteness problem in the current integrated circuit field, there is a gap between the design indexes of a general system clock circuit (such as an RC oscillator) and the chip fabrication indexes, or the accuracy of the circuit design indexes is poor and can only be accurate to a certain range. In this way, when the chip communicates externally (based on the baud rate calculation of the system clock), errors (differences) may occur. To solve this possible differential error, generally, a synchronous communication method such as SPI or a complex internal phase-locked loop circuit is used.

[0004] However, the synchronous communication method has the following problems: generally, it is more complex than asynchronous communication and requires more IO port resources; the external communication link of the chip is also more complex, which is disadvantageous in low-cost, low-power, and small-scale scenarios. Using a complex internal phase-locked loop circuit has the following problems: the chip internal is more complex, which is disadvantageous in low-cost, low-power, and small-scale scenarios. Summary of the Invention

[0005] In view of the above problems, the present application provides an asynchronous fuzzy communication method in a differential model to solve the problem that asynchronous communication is difficult due to possible differential errors in the external communication of the chip.

[0006] To achieve the above object, the inventor provides an asynchronous fuzzy communication method in a differential model, including the following steps:

[0007] Asynchronous fuzzy connection: The host computer sends a first communication data frame to the chip;

[0008] The chip determines whether the data at a preset position in the received first communication data frame meets a first preset condition, and the length of the preset position is less than the data length of the first communication data frame;

[0009] If it meets the condition, the chip sends a first confirmation data frame to the host computer;

[0010] If not satisfied, end the communication with the host computer;

[0011] When the host computer receives the first confirmation data frame, determine whether the first confirmation data frame meets the second preset condition;

[0012] If satisfied, establish an asynchronous fuzzy connection with the chip.

[0013] In some embodiments, the first communication data frame includes two different eight - bit hexadecimal numbers sent continuously;

[0014] The asynchronous fuzzy connection specifically includes the following steps:

[0015] The host computer continuously sends two different eight - bit hexadecimal numbers to the chip;

[0016] The chip determines whether the data at the first preset position of the first received eight - bit hexadecimal number is equal to the first preset value;

[0017] If not equal, clear the frame counter and end the communication with the host computer;

[0018] If equal, continue to determine whether the data at the second preset position of the later - received eight - bit hexadecimal number is equal to the second preset value;

[0019] If not equal, clear the frame counter and end the communication with the host computer;

[0020] If equal, increment the frame counter by one;

[0021] Determine whether the frame counter is full;

[0022] If full, send the first confirmation data frame to the host computer;

[0023] If not full, send the second confirmation data frame to the host computer;

[0024] When the host computer receives the first confirmation data frame, establish an asynchronous fuzzy connection with the chip;

[0025] When the host computer receives the second confirmation data frame, continue to send the first communication data frame to the chip.

[0026] In some embodiments, the steps "When the host computer receives the first confirmation data frame, establish an asynchronous fuzzy connection with the chip; when the host computer receives the second confirmation data frame, continue to send the first communication data frame to the chip" specifically include the following steps:

[0027] The host computer determines whether the data at the third preset position of the first confirmation data frame or the second confirmation data frame sent by the chip is equal to the third preset value;

[0028] If they are equal, the host computer receives the first confirmation data frame and establishes an asynchronous fuzzy connection with the chip;

[0029] If they are not equal, the host computer receives the second confirmation data frame and continues to send the first communication data frame to the chip.

[0030] In some embodiments, the two different eight - bit hexadecimal numbers continuously sent in the first communication data frame are the eight - bit hexadecimal number 00 and the eight - bit hexadecimal number FF respectively, and the first confirmation data frame is the eight - bit hexadecimal number 00.

[0031] In some embodiments, the following steps are further included:

[0032] Asynchronous error correction: After the host computer and the chip establish a fuzzy connection, the host computer sends a calibration data frame to the chip;

[0033] The chip calibrates according to the received calibration data frame. If the calibration is completed, it returns a first feedback data frame to the host computer. If the calibration is not completed, it returns a second feedback data frame to the host computer;

[0034] The host computer receives the first feedback data frame, and the asynchronous error correction is completed;

[0035] The host computer receives the second feedback data frame and resends the calibration data frame to the chip.

[0036] In some embodiments, the asynchronous error correction specifically includes the following steps:

[0037] After the host computer and the chip establish a fuzzy connection, the host computer sends a calibration data frame to the chip;

[0038] The chip calibrates according to the received calibration data frame. The chip selects hard calibration or soft calibration according to the configuration. The hard calibration is to correct the system clock factor, and the soft calibration is to correct the baud rate reference line;

[0039] When hard calibration is selected, the system clock frequency will be corrected and the adjustment of the system clock factor will be started;

[0040] When soft calibration is selected, the baud rate reference line is corrected, the adjustment of the baud rate reference line is started, and it is converted into a baud rate correction factor;

[0041] Judge whether the calibration reaches the accuracy target. If it reaches, the calibration is completed and a first feedback data frame is returned to the host computer;

[0042] If it does not reach, the calibration is not completed and a second feedback data frame is returned to the host computer;

[0043] The host computer receives the first feedback data frame, completes asynchronous error correction, and stores the adjustment configuration for hard calibration or the baud rate correction factor for soft calibration in the non-volatile memory;

[0044] The host computer receives the second feedback data frame and resends the calibration data frame to the chip.

[0045] In some embodiments, the method further includes the following steps:

[0046] Asynchronous precise connection: After asynchronous error correction is completed, the host computer sends a second communication data frame to the chip;

[0047] The chip determines whether the received second communication data frame meets a third preset condition;

[0048] If it meets the condition, the chip returns a third confirmation data frame to the host computer;

[0049] If it does not meet the condition, the communication with the host computer ends;

[0050] When the host computer receives the third confirmation data frame, it establishes an asynchronous precise connection with the chip.

[0051] In some embodiments, the asynchronous precise connection specifically includes the following steps:

[0052] After asynchronous error correction is completed, the host computer sends a second communication data frame to the chip;

[0053] The chip determines whether the data of the received second communication data frame is equal to a fourth preset value;

[0054] If it is not equal, the frame counter is cleared and the communication with the host computer ends;

[0055] If it is equal, the frame counter increments by one;

[0056] Determine whether the frame counter is full

[0057] If the frame count is full, the chip returns a third confirmation data frame to the host computer;

[0058] If the frame count is not full, the chip returns a fourth confirmation data frame to the host computer;

[0059] When the host computer receives the third confirmation data frame, it establishes an asynchronous precise connection with the chip;

[0060] When the host computer receives the fourth confirmation data frame, it continues to send a second confirmation data frame to the chip.

[0061] In some embodiments, the steps "When the host computer receives the third confirmation data frame, it establishes an asynchronous precise connection with the chip; when the host computer receives the fourth confirmation data frame, it continues to send a second confirmation data frame to the chip" specifically include the following steps:

[0062] The host computer determines whether the data in the third confirmation data frame or the data in the fourth confirmation data frame received is equal to the fifth preset value;

[0063] If it is equal, the host computer receives the third confirmation data frame and establishes an asynchronous precise connection with the chip;

[0064] If it is not equal, the host computer receives the fourth confirmation data frame and continues to send the second confirmation data frame to the chip.

[0065] Another technical solution is also provided: an asynchronous fuzzy communication system in a differential model, including a host computer and a chip;

[0066] When the host computer is used to establish an asynchronous fuzzy connection with the chip, it sends a first communication data frame to the chip, and when it receives the first confirmation data frame, it determines whether the first confirmation data frame meets the second preset condition; if it meets, it establishes an asynchronous fuzzy connection with the chip.

[0067] The chip is used to determine whether the data at the preset position in the received first communication data frame meets the first preset condition, and the length of the preset position is less than the data length of the first communication data frame; if it meets, it sends the first confirmation data frame to the host computer; if it does not meet, it ends the communication with the host computer.

[0068] Different from the prior art, in the above technical solution, when the host computer and the chip attempt to connect, the host computer sends a first communication data frame to the chip. When the chip receives the first communication data frame sent by the host computer, it determines whether the data at the preset position in the received first communication data frame meets the first preset condition, where the length of the preset position is less than the data length of the first communication data frame; and due to the on-chip clock error of the chip, the chip only determines whether the data at the preset position of the first communication data frame meets a condition lower than the first preset condition, concentrating the error in the data of other positions; when the chip determines that the first preset condition is met, it returns the first confirmation data frame, otherwise it disconnects the communication with the host computer; when the host computer receives the first confirmation data frame, it completes the asynchronous fuzzy connection between the chips. By adopting fuzzy connection, the effective information is reasonably compressed, and the problem of asynchronous communication connection in the differential model is solved.

[0069] The relevant records in the above invention content are only an overview of the technical solution of this application. In order to enable those of ordinary skill in the art to more clearly understand the technical solution of this application, and then to implement it according to the content recorded in the description and the drawings, and in order to make the above objects, other objects, features and advantages of this application more easily understood, the following is described in conjunction with the specific embodiments of this application and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0070] The accompanying drawings are only used to illustrate the principles, implementation methods, applications, features, effects, etc. of the specific embodiments of the present application and other related contents, and should not be considered as a limitation to the present application.

[0071] In the drawings of the specification:

[0072] Figure 1 It is a schematic structural diagram of a communication data frame format described in the specific embodiment;

[0073] Figure 2 It is a schematic flowchart of an asynchronous fuzzy connection of the asynchronous fuzzy communication method in the differential model described in the specific embodiment;

[0074] Figure 3 It is a schematic flowchart of an asynchronous error correction of the asynchronous fuzzy communication method in the differential model described in the specific embodiment;

[0075] Figure 4 It is a schematic flowchart of an asynchronous precise connection of the asynchronous fuzzy communication method in the differential model described in the specific embodiment;

[0076] Figure 5 It is a schematic flowchart of an asynchronous fuzzy communication method in the differential model described in the specific embodiment;

[0077] Figure 6 It is a schematic flowchart of an asynchronous fuzzy connection described in the specific embodiment;

[0078] Figure 7 It is another schematic flowchart of an asynchronous fuzzy connection described in the specific embodiment;

[0079] Figure 8 It is a schematic flowchart of an asynchronous error correction described in the specific embodiment;

[0080] Figure 9 It is another schematic flowchart of an asynchronous error correction described in the specific embodiment;

[0081] Figure 10 It is a schematic flowchart of an asynchronous precise connection described in the specific embodiment;

[0082] Figure 11 It is another schematic flowchart of an asynchronous precise connection described in the specific embodiment;

[0083] Figure 12 It is a schematic structural diagram of an asynchronous fuzzy communication system in the differential model described in the specific embodiment.

[0084] The descriptions of the reference numerals involved in the above-mentioned drawings are as follows:

[0085] 410, host computer,

[0086] 420. Chip Detailed implementation manners

[0087] To describe in detail the possible application scenarios, technical principles, specific implementable solutions, achievable purposes and effects of this application, etc., the following will be described in detail in combination with the listed specific embodiments and with reference to the accompanying drawings. The embodiments described herein are only used to more clearly illustrate the technical solutions of this application, so they are only examples and cannot be used to limit the protection scope of this application.

[0088] Referring to "embodiments" in this article means that the specific features, structures or characteristics described in combination with the embodiments can be included in at least one embodiment of this application. The term "embodiment" appearing in various positions in the specification does not necessarily refer to the same embodiment, nor does it particularly limit its independence or relevance to other embodiments. In principle, in this application, as long as there is no technical contradiction or conflict, the technical features mentioned in each embodiment can be combined in any way to form corresponding implementable technical solutions.

[0089] Unless otherwise defined, the meanings of the technical terms used in this article are the same as those generally understood by those skilled in the technical field to which this application belongs; the use of the relevant terms in this article is only to describe specific embodiments and is not intended to limit this application.

[0090] In the description of this application, the phrase "and / or" is an expression used to describe the logical relationship between objects, indicating that there can be three relationships. For example, A and / or B means: there is A, there is B, and there is both A and B at the same time. In addition, the character " / " in this article generally represents an "or" logical relationship between the associated objects before and after.

[0091] In this application, terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual quantity, primary-secondary or order relationship, etc. between these entities or operations.

[0092] Without more limitations, in this application, the expressions such as "including", "comprising", "having" or other similar expressions used in the statements are intended to cover non-exclusive inclusion. These expressions do not exclude that there may be other elements in the process, method or product including the said elements, so that the process, method or product including a series of elements may not only include those defined elements, but also include other elements not explicitly listed, or also include elements inherent to this process, method or product.

[0093] Similar to the understanding in the Examination Guidelines, in this application, expressions such as "greater than", "less than", "exceeding", etc. are understood as not including the number itself; expressions such as "above", "below", "within", etc. are understood as including the number itself. In addition, in the description of the embodiments of this application, the meaning of "multiple" is two or more (including two), and similar expressions related to "many" are also understood in this way, such as "multiple groups", "multiple times", etc., unless otherwise clearly and specifically defined.

[0094] In the description of the embodiments of this application, the spatially related expressions used, such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "vertical", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the specific embodiment or the drawing, and is only for the convenience of describing the specific embodiments of this application or for the reader to understand, rather than indicating or implying that the device or component referred to must have a specific position, a specific orientation, or be constructed or operated in a specific orientation, so it cannot be understood as a limitation to the embodiments of this application.

[0095] Unless otherwise clearly specified or limited, in the description of the embodiments of this application, the terms such as "installed", "connected", "connected", "fixed", "set", etc. should be understood in a broad sense. For example, the "connection" can be a fixed connection, a detachable connection, or an integral setting; it can be a mechanical connection, an electrical connection, or a communication connection; it can be directly connected, or indirectly connected through an intermediate medium; it can be the communication between two elements or the interaction relationship between two elements. For those skilled in the art to which this application belongs, the specific meanings of the above terms in the embodiments of this application can be understood according to specific circumstances.

[0096] As Figure 1 For the communication data frame format shown, in this application, the communication between the host computer and the chip adopts an asynchronous communication data frame format. Among them, S represents the start bit, D0~D7 represent the communication data content, 8 bits of data are transmitted per frame, D0 is the low bit, D7 is the high bit, and T represents the stop bit. Specifically, for the common UART protocol, S is 0 and T is 1. The idle bit is an optional bit and can be omitted in most cases. This application expands the detailed discussion with S being 0 and T being 1. When D[7:0] == 8'h00, a low-level voltage with a baud rate width of 9 bits will be generated, which is a basis for the subsequent discussion of asynchronous error correction.

[0097] Please refer to Figure 2, this embodiment provides an asynchronous fuzzy communication method in a differential model, which is applied to an asynchronous fuzzy communication method in a differential model. The system includes a host computer and a chip. When the host computer attempts to connect to the chip, it uses the asynchronous fuzzy communication method in the differential model. The method includes the following steps:

[0098] Asynchronous fuzzy connection:

[0099] Step S110: The host computer sends a first communication data frame to the chip;

[0100] Step S120: The chip determines whether the data at a preset position in the received first communication data frame meets a first preset condition, and the length of the preset position is less than the data length of the first communication data frame;

[0101] If it meets, execute step S130: The chip sends a first confirmation data frame to the host computer;

[0102] If it does not meet, execute step S140: End the communication with the host computer;

[0103] Step S150: When the host computer receives the first confirmation data frame, determine whether the first confirmation data frame meets a second preset condition;

[0104] If it meets, execute step S160: Establish an asynchronous fuzzy connection with the chip.

[0105] If it does not meet, return to step S110.

[0106] When the host computer and the chip attempt to connect, the host computer sends a first communication data frame to the chip. When the chip receives the first communication data frame sent by the host computer, it determines whether the data at a preset position in the received first communication data frame meets a first preset condition, where the length of the preset position is less than the data length of the first communication data frame; due to the on-chip clock error of the chip, the chip only determines whether the data at the preset position of the first communication data frame meets a condition lower than the first preset condition, concentrating the error in the data at other positions; when the chip determines that the first preset condition is met, it returns a first confirmation data frame, otherwise it disconnects the communication with the host computer; when the host computer receives the first confirmation data frame, it completes the asynchronous fuzzy connection between the chips. By adopting fuzzy connection, the effective information is reasonably compressed to solve the problem of asynchronous communication connection in the differential model.

[0107] In some embodiments, the first communication data frame includes two different eight-digit hexadecimal numbers sent continuously;

[0108] The asynchronous fuzzy connection specifically includes the following steps:

[0109] The host computer continuously sends two different eight-digit hexadecimal numbers to the chip;

[0110] The chip determines whether the data at the first preset position of the first received eight-digit hexadecimal number is equal to the first preset value;

[0111] If it is not equal, clear the frame counter and end the communication with the host computer;

[0112] If it is equal, continue to determine whether the data at the second preset position of the subsequently received eight-digit hexadecimal number is equal to the second preset value;

[0113] If it is not equal, clear the frame counter and end the communication with the host computer;

[0114] If it is equal, increment the frame counter by one;

[0115] Determine whether the frame counter is full;

[0116] If it is full, send the first confirmation data frame to the host computer;

[0117] If it is not full, send the second confirmation data frame to the host computer;

[0118] When the host computer receives the first confirmation data frame, establish an asynchronous fuzzy connection with the chip;

[0119] When the host computer receives the second confirmation data frame, continue to send the first communication data frame to the chip.

[0120] The host computer continuously sends two different eight - bit hexadecimal numbers to the chip. The chip first determines whether the data at the first preset position of the eight - bit hexadecimal number received first is equal to the first preset value. Due to the existence of errors in the chip, the errors are compressed in the data at positions other than the first preset position, and usually the error does not exceed 25%. Therefore, the first preset position is the data at positions D0 - D5. In other embodiments, the first preset position can also be set as the data at positions D2 - D7. When it is determined that it is equal to the first preset value, the chip then determines whether the data at the second preset position of the next eight - bit hexadecimal number is equal to the second preset value. Among them, the second preset position is different from the first preset position. For example, when the first preset position is at positions D0 - D5, the second preset position is at positions D2 - D7; when the first preset position is at positions D2 - D7, the second preset position is at positions D0 - D5. In the embodiment, other positions can also be selected as the first preset position and the second preset position, as long as it is ensured that the errors can be concentrated at positions other than the first preset position or the second preset position. Then, when it is determined that the data at the second preset position of the next eight - bit hexadecimal number is equal to the second preset value, the frame counter increments by one, and it is determined whether the frame counter is full. If it is full, the first confirmation data frame is returned; if it is not full, the second confirmation data frame is returned. When the host computer receives the first confirmation data frame, it establishes a fuzzy connection with the chip; if it receives the second confirmation data frame, it continues to send the first communication data frame to the chip. In other embodiments, the host computer can also continuously send two identical eight - bit hexadecimal numbers. When the chip receives two identical eight - bit hexadecimal numbers, it determines whether the data at the first preset position of the first - received eight - bit hexadecimal number is equal to the first preset value, and determines whether the data at the second preset position of the second - received eight - bit hexadecimal number is equal to the second preset value.

[0121] In some embodiments, the two different eight - bit hexadecimal numbers continuously sent in the first communication data frame are the eight - bit hexadecimal number 00 and the eight - bit hexadecimal number FF respectively. The preferred sending order of the two different eight - bit hexadecimal numbers can be set according to actual needs. Preferably, the host computer can first send the eight - bit hexadecimal number 00 and then send the eight - bit hexadecimal number FF. Using the eight - bit hexadecimal number 00 (8’h00) and the eight - bit hexadecimal number FF (8’hFF) can preferably solve the problem of effective signal compression, can achieve an effective connection, and at the same time can also shield illegal (abnormal) connection interference; it can also eliminate the problem of error accumulation in fast connection.

[0122] In some embodiments, the steps “When the host computer receives the first confirmation data frame, it establishes an asynchronous fuzzy connection with the chip; when the host computer receives the second confirmation data frame, it continues to send the first communication data frame to the chip” specifically include the following steps:

[0123] The host computer determines whether the data at the third preset position of the first confirmation data frame or the second confirmation data frame sent by the chip is equal to the third preset value;

[0124] If it is equal, the host computer receives the first confirmation data frame and establishes an asynchronous fuzzy connection with the chip;

[0125] If it is not equal, the host computer receives the second confirmation data frame and continues to send the first communication data frame to the chip.

[0126] When the host computer receives the confirmation data frame sent by the chip, it judges whether the data at the third preset position of the received data frame is equal to the third preset value. The first confirmation data frame uses the eight-bit hexadecimal number FE (8’hFE), and the third preset position is the D2-D7 positions, concentrating the error at the D0-D1 positions. The purpose of using the eight-bit hexadecimal number FE (8’hFE) for the first confirmation data frame is to make D0 = 0, maximizing the avoidance of error interference with the host computer's S(0) bit judgment; the second confirmation data frame uses the eight-bit hexadecimal number 00 (8’h00), and the feedback code of 00 in eight-bit hexadecimal can also solve the problem of signal effective compression; when it is judged that the data at the third preset position is equal to the third preset value, it is considered that the first confirmation data frame is received, and the host computer and the chip complete the establishment of an asynchronous fuzzy connection. When it is judged that the data at the third preset position is not equal to the third preset value, it is considered that the second confirmation data frame is received, and the host computer continues to send the first communication data frame to the chip.

[0127] As Figure 3 shown, in some embodiments, the following steps are further included:

[0128] Asynchronous error correction:

[0129] Step S210: After the host computer and the chip establish a fuzzy connection, the host computer sends a calibration data frame to the chip;

[0130] Step S220: The chip calibrates according to the received calibration data frame. If the calibration is completed, then step S230: returns the first feedback data frame to the host computer. If the calibration is not completed, then step S240: returns the second feedback data frame to the host computer;

[0131] Step S250: The host computer receives the first feedback data frame, and the asynchronous error correction is completed;

[0132] Step S260: The host computer receives the second feedback data frame and resends the calibration data frame to the chip.

[0133] After the host computer establishes an asynchronous fuzzy connection with the chip, the host computer sends a calibration data frame to the chip. The chip calibrates according to the received calibration data frame. If the calibration is completed, the chip returns a first feedback data frame to the host computer. If the calibration is not completed, the chip feeds back a second feedback data frame to the host computer. When the host computer receives the first feedback data frame, the asynchronous error correction is completed. When the host computer receives the second feedback data frame, it resends the calibration data frame to the chip for calibration again. Through asynchronous error correction, the errors existing in the communication are eliminated. Specifically, the asynchronous error correction includes the following steps:

[0134] After the host computer establishes a fuzzy connection with the chip, the host computer sends a calibration data frame to the chip;

[0135] The chip calibrates according to the received calibration data frame. The chip selects hard calibration or soft calibration according to the configuration. The hard calibration is to correct the system clock factor, and the soft calibration is to correct the baud rate reference line;

[0136] When hard calibration is selected, the system clock frequency will be corrected and the adjustment of the system clock factor will be started, where the adjustment includes coarse adjustment, fine adjustment and precision adjustment;

[0137] When soft calibration is selected, the baud rate reference line will be corrected and the adjustment of the baud rate reference line will be started, where the adjustment includes coarse adjustment, fine adjustment and precision adjustment, and it will be converted into a baud rate correction factor;

[0138] Judge whether the calibration reaches the accuracy target. If it reaches, the calibration is completed and a first feedback data frame is returned to the host computer;

[0139] If it does not reach, the calibration is not completed and a second feedback data frame is returned to the host computer;

[0140] When the host computer receives the first feedback data frame, the asynchronous error correction is completed, and the adjustment configuration of the hard calibration or the baud rate correction factor of the soft calibration is stored in the non-volatile memory;

[0141] When the host computer receives the second feedback data frame, it resends the calibration data frame to the chip.

[0142] Among them, the calibration data frame uses the eight-bit hexadecimal number 00 (8’h00), the first feedback data frame uses the eight-bit hexadecimal number 55 (8’h55), and the second feedback data frame uses the eight-bit hexadecimal number AA (8’hAA); By taking error elimination as the main task, including hard calibration and soft calibration, the two-dimensional calibration strategy has universality and can be widely applied to processor design, especially in scenarios of miniaturization, low cost, low power consumption and uncontrollable process dispersion.

[0143] Such as Figure 4 shown, in some embodiments, the following steps are further included:

[0144] Asynchronous precise connection:

[0145] Step S310: After the asynchronous error correction is completed, the host computer sends a second communication data frame to the chip;

[0146] Step S320: The chip determines whether the received second communication data frame meets the third preset condition;

[0147] If it meets the condition, execute Step S330: The chip returns a third confirmation data frame to the host computer;

[0148] If it does not meet the condition, execute Step S340: End the communication with the host computer;

[0149] Execute Step S350: When the host computer receives the third confirmation data frame, establish an asynchronous precise connection with the chip.

[0150] After the asynchronous error correction is completed, verification is performed through the asynchronous precise connection. After the asynchronous correction is completed, the host computer sends a second communication data frame to the chip. The chip determines whether the received second communication data frame meets the third preset condition. If it meets the condition, it returns a third confirmation data frame to the host computer. If it does not meet the condition, it ends the communication with the host computer. Specifically, the asynchronous precise connection specifically includes the following steps:

[0151] After the asynchronous error correction is completed, the host computer sends a second communication data frame to the chip;

[0152] The chip determines whether the data of the received second communication data frame is equal to the fourth preset value;

[0153] If it is not equal, clear the frame counter and end the communication with the host computer;

[0154] If it is equal, increment the frame counter by one;

[0155] Determine whether the frame counter is full

[0156] If the frame count is full, the chip returns a third confirmation data frame to the host computer;

[0157] If the frame count is not full, the chip returns a fourth confirmation data frame to the host computer;

[0158] When the host computer receives the third confirmation data frame, establish an asynchronous precise connection with the chip;

[0159] When the host computer receives the fourth confirmation data frame, continue to send a second confirmation data frame to the chip.

[0160] Among them, the second communication data frame uses the eight-digit hexadecimal number AA (8’hAA), the third confirmation data frame uses the eight-digit hexadecimal number 55 (8’h55), and the third confirmation data frame uses the eight-digit hexadecimal number AA (8’hAA).

[0161] In some embodiments, the steps "the host computer receives the third confirmation data frame and establishes an asynchronous precise connection with the chip; the host computer receives the fourth confirmation data frame and continues to send the second confirmation data frame to the chip" specifically include the following steps:

[0162] The host computer determines whether the data of the third confirmation data frame or the data of the fourth confirmation data frame received is equal to a fifth preset value;

[0163] If it is equal, the host computer receives the third confirmation data frame and establishes an asynchronous precise connection with the chip;

[0164] If it is not equal, the host computer receives the fourth confirmation data frame and continues to send the second confirmation data frame to the chip.

[0165] As Figure 5 shown, in another embodiment, an asynchronous fuzzy communication method in a differential model includes asynchronous fuzzy connection establishment, asynchronous error correction, and asynchronous precise connection establishment.

[0166] The asynchronous fuzzy connection establishment part is detailed as Figure 6 , 8’h00 represents the 8-bit hexadecimal number 00. The off-chip system (host computer) attempts to connect to the on-chip system (chip):

[0167] The first step: The off-chip sends 8’h00. Due to the on-chip clock error (the error generally does not exceed 25%), therefore, the on-chip system only judges D0~D5 (D[5:0] == 6’h00), and the error will be concentrated in D6 and D7;

[0168] The second step: The off-chip sends 8’hFF. At this time, the error will be in D0 and D1. Therefore, the on-chip system only judges D2~D7 (D[7:2] == 6’h3f);

[0169] The third step: After the on-chip receives two frames of data of D[5:0] == 6’h00 and D[7:2] == 6’h3f continuously, the frame count is incremented by 1;

[0170] (1) If the frame count is full, 8’hFE will be sent. At this time, the host computer will receive it and judge D[7:2] == 6’h3f, indicating that the asynchronous fuzzy connection establishment is completed; the purpose of sending 8’hFE is to make D0 = 0, maximizing the avoidance of error interference with the host computer's S(0) bit judgment;

[0171] (2) If the frame count is not full, 8’h00 will be sent. At this time, the host computer also judges D[7:2], which must not be equal to 6’h3f, to indicate that the host computer starts to circularly send 8’h00 + 8’hFF.

[0172] The advantages of the information 8’h00 + 8’hFF + 8’hFE(8’h00) are as follows:

[0173] (1) 8’h00 + 8’hFF preferably solves the problem of effective signal compression, can achieve effective connection, and at the same time, can also shield illegal (abnormal) connection interference; it can also eliminate the problem of error accumulation in fast connection;

[0174] (2) The feedback code of 8’hFE(8’h00) can also solve the problem of effective signal compression.

[0175] As Figure 7 shown, the analysis of the process of establishing an asynchronous fuzzy connection is as follows:

[0176] S01: Start;

[0177] S02: 8’h00 is sent from outside the chip;

[0178] S03: After the chip receives it, the chip internally judges D[5:0] == 6’h00; if it holds, go to S04, otherwise go to S12, indicating that an abnormal message is received, the frame counter will be cleared, and the communication will end;

[0179] S04: 8’hFF is sent from outside the chip;

[0180] S05: After the chip receives it, the chip internally judges D[7:2] == 6’h3f; if it holds, go to S06, otherwise go to S12, indicating that an abnormal message is received, the frame counter will be cleared, and the communication will end;

[0181] S06: The chip has received a set of correct data (D[5:0] == 6’h00 and D[7:2] == 6’h3f), and the frame counter is incremented by 1;

[0182] S07: Judge whether the frame counter is full. If it is full, go to S09, otherwise go to S08;

[0183] S08: The chip internally outputs 8’h00 for feedback to indicate that the host computer circularly sends;

[0184] S09: The chip internally outputs 8’hFE for feedback to indicate entering the asynchronous error correction link;

[0185] S10: The host computer outside the chip judges whether it has received D[7:2] == 6’h3f. If it has received it, it means that the establishment of the asynchronous fuzzy connection is completed and it will enter the asynchronous error correction link S11. Otherwise, it will enter S02;

[0186] S11: Proceed to the next process;

[0187] S12: When an exception message is received, the frame counter will be cleared and the communication will end;

[0188] S13: End abnormally.

[0189] The asynchronous error correction part is detailed as Figure 8 . The off-chip system (host computer) sends a calibration reference signal to the on-chip system (chip):

[0190] First step: The off-chip sends 8’h00, and the on-chip will sample the low level with a 9-bit width as the calibration reference;

[0191] Second step: The on-chip selects to correct the system clock factor (hard calibration) or correct the baud rate baseline (soft calibration) according to the configuration, and performs coarse adjustment, fine adjustment, and precise adjustment; Each time the on-chip receives 8’h00 (low level with a 9-bit width), a calibration is started (the coarse adjustment or fine adjustment or precise adjustment changes one level).

[0192] Third step: The on-chip is based on the result of this calibration;

[0193] (1) If the calibration is completed, 8’h55 will be sent back. At this time, the host computer will receive it and judge whether D[7:0] == 8’h55, indicating that the asynchronous error correction is completed;

[0194] (2) If it is not completed, 8’hAA will be sent back. At this time, the host computer also judges D[7:0], and at this time it must not be equal to 8’h55 to indicate that the host computer starts to circularly send the calibration reference signal (8’h00).

[0195] As Figure 9 shown: The process analysis of the asynchronous error correction part is as follows:

[0196] S21: The establishment of the asynchronous fuzzy connection is completed;

[0197] S22: The off-chip sends 8’h00;

[0198] S23: The on-chip selects to correct the system clock factor (hard calibration) or correct the baud rate baseline (soft calibration) according to the configuration; If it is hard calibration, it will transfer to S24, otherwise it will transfer to S25;

[0199] S24: The on-chip starts hard calibration, will correct the system clock frequency, and start coarse adjustment, fine adjustment, and precise adjustment;

[0200] S25: The on-chip starts soft calibration, will correct the baud rate baseline, start coarse adjustment, fine adjustment, and precise adjustment, and convert it into a baud rate correction factor;

[0201] S26: Determine whether the accuracy target is reached. If the calibration is completed, go to S08; otherwise, go to S07;

[0202] S27: The on-chip feedback outputs 8’hAA to indicate that the host computer sends in a loop;

[0203] S28: The on-chip feedback outputs 8’h55 to indicate entering the asynchronous precise connection establishment phase;

[0204] S29: The off-chip host computer determines whether it receives D[7:0] == 8’h55. If it receives it, it means that the asynchronous error correction is completed and it will enter the storage calibration information phase S10; otherwise, it will go to S02;

[0205] S30: Write the coarse adjustment, fine adjustment, precision adjustment (hard calibration) or baud rate correction factor (soft calibration) into the non-volatile memory;

[0206] S31: Enter the next process.

[0207] The asynchronous precise connection establishment part is detailed as Figure 10 . The off-chip system (host computer) sends a connection signal to the on-chip system (chip):

[0208] First step: The off-chip sends 8’hAA; the on-chip system determines D[7:0] == 6’hAA,

[0209] Second step: After the on-chip receives D[7:0] == 6’hAA, the frame count is incremented by 1;

[0210] (1) If the frame count is full, it will send 8’h55. At this time, the host computer will receive it and determine D[7:0] == 8’h55, indicating that the asynchronous fuzzy connection establishment is completed;

[0211] (2) If the frame count is not full, it will send 8’hAA. At this time, the host computer also determines D[7:0],

[0212] At this time, it must not be equal to 8’h55 to indicate that the host computer starts to send 8’hAA in a loop.

[0213] Figure 11 As shown, the process analysis of the asynchronous precise connection establishment part is as follows:

[0214] S41: The asynchronous error correction is completed;

[0215] S42: The off-chip sends 8’hAA;

[0216] S43: After the chip receives it, the on-chip determines D[7:0] == 8’hAA; if it holds, go to S44, if not, go to S50, indicating that an abnormal message is received, and the frame counter will be cleared and the communication will end;

[0217] S44: The chip receives a frame of correct data, and the frame counter is incremented by 1;

[0218] S45: Determine whether the frame counter is full. If it is full, go to S07; otherwise, go to S06;

[0219] S46: The on-chip feedback outputs 8’hAA to indicate that the host computer should send data in a loop;

[0220] S47: The on-chip feedback outputs 8’h55 to indicate completion;

[0221] S48: The off-chip host computer determines whether it has received D[7:0] == 6’h55. If it has received it, it means that the asynchronous precise connection establishment is completed, and it will enter the asynchronous error correction step S09; otherwise, it will enter S02;

[0222] S49: Completed;

[0223] S50: An abnormal message is received, the frame counter will be cleared, and the communication will end;

[0224] S51: Abnormal end.

[0225] To solve the asynchronous communication connection problem in the differential model, fuzzy connection is adopted to reasonably compress the effective information.

[0226] Taking error elimination as the main task, including hard calibration and soft calibration, the two-dimensional calibration strategy is extensive.

[0227] Taking precise asynchronous connection as the final verification means.

[0228] It has the following advantages:

[0229] It solves the problem of difficult asynchronous communication in the traditional differential model;

[0230] The system has few IO resources (at most two IOs), few hardware resources (a simple clock circuit is used on-chip), and small process limitations (the influence of process dispersion will be reduced);

[0231] The system is simplified, and asynchronous communication (such as UART communication) has a better application technology (off-chip resources) foundation.

[0232] It can be widely applied to processor design, especially in scenarios of miniaturization, low cost, low power consumption, and uncontrollable process dispersion.

[0233] Please refer to Figure 12 , in another embodiment, an asynchronous fuzzy communication system in a differential model includes a host computer 410 and a chip 420, which are used to execute the asynchronous fuzzy communication method in the differential model in the above embodiment;

[0234] When the host computer 410 is used to establish an asynchronous fuzzy connection with the chip 420, it sends a first communication data frame to the chip 420, and when receiving the first confirmation data frame, determines whether the first confirmation data frame meets the second preset condition; if it meets, an asynchronous fuzzy connection is established with the chip 420.

[0235] The chip 420 is used to determine whether the data at a preset position in the received first communication data frame meets the first preset condition, and the length of the preset position is less than the data length of the first communication data frame; if it meets, a first confirmation data frame is sent to the host computer 410; if it does not meet, the communication with the host computer 410 is ended.

[0236] When the host computer 410 and the chip 420 attempt to connect, the host computer 410 sends a first communication data frame to the chip 420. When the chip 420 receives the first communication data frame sent by the host computer, it determines whether the data at a preset position in the received first communication data frame meets the first preset condition, where the length of the preset position is less than the data length of the first communication data frame; due to the on-chip clock error of the chip, the chip 420 only determines whether the data at the preset position of the first communication data frame meets a condition lower than the first preset condition, concentrating the error in the data at other positions; when the chip 420 determines that the first preset condition is met, it returns a first confirmation data frame, otherwise it disconnects the communication with the host computer 410; when the host computer 410 receives the first confirmation data frame, the asynchronous fuzzy connection between the host computer 410 and the chip 420 is completed. By adopting fuzzy connection, the effective information is reasonably compressed, and the problem of asynchronous communication connection in the differential model is solved.

[0237] Finally, it should be noted that although the above embodiments have been described in the text and drawings of the specification of this application, the patent protection scope of this application cannot be limited thereby. Any technical solutions obtained by equivalent structure or equivalent process substitution or modification based on the essential concept of this application, using the content recorded in the text and drawings of the specification of this application, as well as those directly or indirectly implementing the technical solutions of the above embodiments in other related technical fields, are all included in the patent protection scope of this application.

Claims

1. An asynchronous fuzzy communication method in a differential model, characterized in that It includes the following steps: Asynchronous fuzzy connection: The host computer sends the first communication data frame to the chip; The chip determines whether the data at the preset position in the received first communication data frame meets the first preset condition. The length of the preset position is less than the data length of the first communication data frame, and the preset position is the position representing the communication data except for the start bit and the stop bit; If it meets, the chip sends the first confirmation data frame to the host computer; If it does not meet, the communication with the host computer ends; When the host computer receives the first confirmation data frame, it determines whether the data at the preset position in the first confirmation data frame meets the second preset condition; If it meets, an asynchronous fuzzy connection is established with the chip.

2. The asynchronous fuzzy communication method in the differential model according to claim 1, wherein The first communication data frame includes two different eight-digit hexadecimal numbers sent continuously; The asynchronous fuzzy connection specifically includes the following steps: The host computer continuously sends two different eight-digit hexadecimal numbers to the chip; The chip determines whether the data at the first preset position of the first received eight-digit hexadecimal number is equal to the first preset value; If it is not equal, clear the frame counter and end the communication with the host computer; If it is equal, continue to determine whether the data at the second preset position of the second received eight-digit hexadecimal number is equal to the second preset value; If it is not equal, clear the frame counter and end the communication with the host computer; If it is equal, increment the frame counter by one; Determine whether the frame counter is full; If it is full, send the first confirmation data frame to the host computer; If it is not full, send the second confirmation data frame to the host computer; When the host computer receives the first confirmation data frame, an asynchronous fuzzy connection is established with the chip; When the host computer receives the second confirmation data frame, it continues to send the first communication data frame to the chip.

3. The asynchronous fuzzy communication method in the differential model according to claim 2, wherein The steps "When the host computer receives the first confirmation data frame, an asynchronous fuzzy connection is established with the chip; when the host computer receives the second confirmation data frame, the host computer continues to send the first communication data frame to the chip" specifically include the following steps: The host computer determines whether the data at the third preset position of the confirmation data frame sent by the chip is equal to the third preset value; If it is equal, it is considered that the host computer has received the first confirmation data frame and the asynchronous fuzzy connection with the chip is completed; If it is not equal, it is considered that the host computer has received the second confirmation data frame and continues to send the first communication data frame to the chip.

4. The asynchronous fuzzy communication method in the differential model according to claim 2, characterized in that, The two different eight-digit hexadecimal numbers sent continuously in the first communication data frame are the eight-digit hexadecimal number 00 and the eight-digit hexadecimal number FF respectively, and the first confirmation data frame is the eight-digit hexadecimal number 00.

5. The asynchronous fuzzy communication method in the differential model according to claim 1, characterized in that, It also includes the following steps: Asynchronous error correction: After the host computer and the chip establish a fuzzy connection, the host computer sends a calibration data frame to the chip; The chip calibrates according to the received calibration data frame. If the calibration is completed, it returns the first feedback data frame to the host computer. If the calibration is not completed, it returns the second feedback data frame to the host computer; When the host computer receives the first feedback data frame, the asynchronous error correction is completed; When the host computer receives the second feedback data frame, it resends the calibration data frame to the chip.

6. The asynchronous fuzzy communication method in the differential model according to claim 5, characterized in that The asynchronous error correction specifically includes the following steps: After the host computer and the chip establish a fuzzy connection, the host computer sends a calibration data frame to the chip; The chip calibrates according to the received calibration data frame. The chip selects hard calibration or soft calibration according to the configuration. The hard calibration is to correct the system clock factor, and the soft calibration is to correct the baud rate baseline; When hard calibration is selected, the system clock frequency will be corrected and the adjustment of the system clock factor will be started; When soft calibration is selected, the baud rate baseline will be corrected, the adjustment of the baud rate baseline will be started, and it will be converted into a baud rate correction factor; Judge whether the calibration reaches the accuracy target. If it reaches, the calibration is completed and the first feedback data frame is returned to the host computer; If it does not reach, the calibration is not completed and the second feedback data frame is returned to the host computer; When the host computer receives the first feedback data frame, the asynchronous error correction is completed, and the adjustment configuration of the hard calibration or the baud rate correction factor of the soft calibration is stored in the non-volatile memory; When the host computer receives the second feedback data frame, the calibration data frame is resent to the chip.

7. The asynchronous fuzzy communication method in the differential model according to claim 5, characterized in that It also includes the following steps: Asynchronous precise connection: After the asynchronous error correction is completed, the host computer sends a second communication data frame to the chip; The chip judges whether the received second communication data frame meets the third preset condition; If it meets, the chip returns a third confirmation data frame to the host computer; If it does not meet, the communication with the host computer ends; When the host computer receives the third confirmation data frame, an asynchronous precise connection is established with the chip.

8. The asynchronous fuzzy communication method in the differential model according to claim 7, characterized in that The asynchronous precise connection specifically includes the following steps: After the asynchronous error correction is completed, the host computer sends a second communication data frame to the chip; The chip judges whether the data of the received second communication data frame is equal to the fourth preset value; If it is not equal, the frame counter is cleared and the communication with the host computer ends; If it is equal, the frame counter is incremented by one; Judge whether the frame counter is full If the frame count is full, the chip returns a third confirmation data frame to the host computer; If the frame count is not full, the chip returns a fourth confirmation data frame to the host computer; When the host computer receives the third confirmation data frame, an asynchronous precise connection is established with the chip; When the host computer receives the fourth confirmation data frame, it continues to send a second confirmation data frame to the chip.

9. The asynchronous fuzzy communication method in the differential model according to claim 8, characterized in that, The steps "When the host computer receives the third confirmation data frame, an asynchronous precise connection is established with the chip; when the host computer receives the fourth confirmation data frame, it continues to send a second confirmation data frame to the chip" specifically include the following steps: The host computer judges whether the data of the received third confirmation data frame or the data of the fourth confirmation data frame is equal to the fifth preset value; If it is equal, when the host computer receives the third confirmation data frame, an asynchronous precise connection is established with the chip; If it is not equal, when the host computer receives the fourth confirmation data frame, it continues to send a second confirmation data frame to the chip.

10. An asynchronous fuzzy communication system in a differential model, characterized in that, It includes a host computer and a chip; When the host computer is used to establish an asynchronous fuzzy connection with the chip, it sends a first communication data frame to the chip, and when it receives the first confirmation data frame, it judges whether the first confirmation data frame meets the second preset condition. If it meets, an asynchronous fuzzy connection is established with the chip; The chip is used to judge whether the data at the preset position in the received first communication data frame meets the first preset condition, and the length of the preset position is less than the data length of the first communication data frame; If it meets, a first confirmation data frame is sent to the host computer; If not satisfied, end the communication with the host computer, and the preset position is the position in the communication data excluding the start bit and the stop bit.

Images