Hardware accelerator

Abstract

A hardware accelerator (4) includes an array (20) of direct memory access (DMA) systems (7, 8) and processing elements (PEs). Each PE (20a) includes two data inputs (40, 41) and two data outputs (42, 43) and can perform selectable logical or arithmetic operations. The array (20) includes configurable interconnects (23) for selectively connecting the outputs of the PEs to the inputs of the PEs. A first data buffer (21) includes two or more first edge circular registers (21a) for connecting the DMA systems (7, 8) to selected data inputs at the first edge of the PE array (20). A second data buffer (22) includes two or more second edge linear or circular shift registers for connecting selected data outputs at the second edge of the PE array (20) to the DMA systems.

Description

Background Technology

[0001] This invention relates to a hardware accelerator having an array of processing elements.

[0002] General-purpose processors are extremely versatile, but can be slow and energy inefficient when performing certain signal processing tasks such as calculating the Fast Fourier Transform (FFT). Digital signal processors (DSPs) can be faster but still consume a considerable amount of power; they also occupy a relatively large silicon area, making them expensive. Fixed digital logic (such as application-specific integrated circuits) can be fast, efficient, and compact, but inflexible and only provide a fixed task.

[0003] To mitigate these issues, hardware accelerators comprising arrays of relatively simple, reconfigurable hardware processing elements (PEs) are known. For example, the array could have 64 PEs logically arranged in a 4×16 rectangular array. Each PE can have multiple data inputs (e.g., two inputs) and multiple data outputs (e.g., two outputs), and can be dynamically configured to perform selected logical or arithmetic operations on its input data. Configurable interconnects allow the output of one PE to be selectively connected to the input of another PE. Data can be input to a PE along the first (e.g., top) edge of the array, traverse the PE array clockwise from one PE to the next over multiple clock cycles, and output along the second (e.g., bottom) edge of the array. Dedicated local memory can be located near these two edges for rapid input and output of data through the array.

[0004] After the PE computation and interconnects have been properly configured (e.g., by loading configuration data from a configuration file), the hardware accelerator can perform a series of complex operations on the data stored in one local memory bank, such as FFT or complex cross-correlation, and output the results to another local memory bank.

[0005] Hardware accelerators can be configured as coprocessors on a system-on-a-chip (SoC), integrated with one or more general-purpose processors. Hardware accelerators may include direct memory access (DMA) units for transferring input and output data between the hardware accelerator's local memory and system memory accessible to the general-purpose processor. DMA units can also be used to read new configuration data into the accelerator.

[0006] This hardware accelerator can provide significant performance advantages for certain repetitive processing tasks. However, the inventors have identified improvements with the potential to provide significantly better performance. Summary of the Invention

[0007] In a first aspect, the present invention provides a hardware accelerator, comprising:

[0008] Direct memory access systems are used to transfer data between hardware accelerators and system memory;

[0009] An array of processing elements, each processing element including two data inputs and two data outputs, and configured to perform selectable logical or arithmetic operations on input data received at one or more data inputs to generate output data at one or more data outputs, wherein the array includes a set of two or more first edge processing elements along a first edge of the array and a set of two or more second edge processing elements along a second edge of the array, the second edge processing elements being different from the first edge processing elements;

[0010] A configurable interconnect section is provided for selectively connecting the output terminal of a corresponding processing element to the input terminal of a corresponding processing element.

[0011] A first data buffer includes two or more first edge circular registers, each first edge circular register including multiple chained flip-flops, comprising near-end flip-flops and far-end flip-flops, wherein the far-end flip-flops of each first edge circular register are arranged to receive data from a direct memory access system, and wherein the near-end flip-flops of each first edge circular register are selectively connected to the data input of a corresponding one of the first edge processing elements; and

[0012] The second data buffer includes two or more second edge shift registers, each second edge shift register including multiple chained flip-flops, which include near-end flip-flops and far-end flip-flops, wherein the near-end flip-flops of each second edge shift register are selectively connected to the data output of a corresponding one of the second edge processing elements, and wherein the far-end flip-flops of each second edge shift register are arranged to output data to a direct memory access system.

[0013] In a second aspect, the present invention provides an integrated circuit chip including such a hardware accelerator.

[0014] The integrated circuit chip may include the system memory. It may include a bus system that connects the system memory to a direct memory access (DMA) system of a hardware accelerator. It may also include a general-purpose processor different from the hardware accelerator. It may be a system-on-a-chip device.

[0015] Therefore, it will be seen that, according to the present invention, the array-based hardware accelerator uses a data buffer of a loop register in the array along the first edge (e.g., the top edge) of the array for clockwise input of data to the processing element. Output data can be output clockwise using a set of shift registers arranged along the second edge (e.g., the bottom edge). The ability to loop at least some of the input data so that the same input data enters the array multiple times enables a series of processing tasks to be performed efficiently.

[0016] For example, in at least some implementations, the hardware accelerator can be configured to perform efficient cross-correlation operations between a template signal pattern (e.g., representing a fixed preamble in a radio communication system) and a longer incoming data stream (e.g., a received radio signal). In this example, the set of fixed coefficients representing the template signal pattern can be loaded into one or more loop registers at a time and then repeatedly looped as the array computes a series of dot product operations between the fixed coefficients and the incoming data stream.

[0017] More generally, whenever the same input data needs to be processed multiple times, the circular register can potentially provide higher efficiency than a shift register without a feedback path by reducing the need to repeatedly load the same data via DMA through a hardware accelerator.

[0018] Using a circular register also allows for a more compact implementation than using local memory (such as a register file with row and column addressing) to hold data to be loaded into the array, because a circular register does not require complex addressing logic to move data into the processing array. Instead, the output of a near-end flip-flop can be directly coupled to the input of a selected processing element. This is particularly well-suited for digital signal processing (DSP) applications where random data read and write capabilities are typically not required.

[0019] In some subpreferred embodiments, the second edge shift register may be a linear (i.e., non-cyclic) shift register, but in preferred embodiments they are also cyclic registers.

[0020] Each first edge circular register preferably includes a corresponding first feedback path, such that circulating data in each first edge circular register comprises: moving data from a far-end trigger to a near-end trigger along successive triggers in a plurality of chained triggers, and moving data from a near-end trigger to a far-end trigger along the first feedback path. In some embodiments, the first edge circular registers can be controlled (e.g., using configuration data set at runtime) to either circulate data in the registers or not to circulate data. In some embodiments, each circular register can be controlled independently (i.e., separately from other circular registers) to circulate or not to circulate. In some embodiments, the hardware accelerator can be arranged such that a configurable subset (preferably all circular registers) of one or more registers of the first and / or second data buffers can be enabled for shifting, while some or all of the remaining registers of the first and / or second data buffers (i.e., those not in the subset) are not shifted (i.e., their contents remain static when enabled registers are shifted). The configurable subset can be specified by configuration data and can even be changed dynamically during operation. Such an arrangement can support performance for operations such as cross-correlation, where a value contained in one register is shifted between consecutive phases of the operation against a value in another register of the same data buffer.

[0021] The first edge loop registers may be unidirectional, but in a preferred embodiment, they are bidirectional. The proximal trigger of each first edge loop register may be selectively connected (e.g., via a configurable switch that can be configured to open or close) to the data output of a corresponding first edge processing element, and the far-end trigger of each first edge loop register may be arranged to output data to a direct memory access system. In addition to including a first feedback path, each first edge loop register may also include a second feedback path, which allows data to be passed directly from the far-end trigger to the proximal trigger, in order to pass data directly from the far-end trigger to the proximal trigger.

[0022] Therefore, in some implementations, each first edge loop register is bidirectional and can be independently controlled to shift forward, shift backward, or not shift. This facilitates efficient data input to the processing element. For example, when a template vector stored in the first loop register is to be repeatedly applied to a signal vector stored in the second loop register in a cross-correlation operation, but the template vector occupies less than half the number of chained flip-flops in the first loop register, the template value can be shifted and looped in the forward direction toward the processing element to perform the first correlation step, and then shifted and looped in the reverse direction away from the processing element to prepare for shifting forward again in the next correlation step. However, for longer template vectors, it may be more efficient to loop the template value only in the forward direction at each successive correlation step. The ability to reconfigure implementations for different shift behaviors as required provides versatility to support different usage modes.

[0023] The second edge shift register is preferably bidirectional. The far-end flip-flop of each second edge circular register can be arranged to receive data from the direct memory access system, and the near-end flip-flop of each second edge circular register can be selectively connected to the data input of a corresponding second edge processing element.

[0024] Therefore, in some implementations, the array may be configured in a first configuration (e.g., at a first time) to process data flowing from the first edge through the array to the second edge, and in a second configuration (e.g., at a second time) to process data flowing from the second edge to the first edge.

[0025] In some implementations, the second edge shift register is also a circular register and may include a first feedback path for passing data directly from the near-end flip-flops of the circular register to the far-end flip-flops. This allows input data to circulate and be input multiple times to the second edge of the processing array without having to load data into the second edge shift register more than once. The second edge circular register may be bidirectional and may include a second feedback path for passing data directly from the far-end flip-flops of the circular register to the near-end flip-flops. In some implementations, each of the first and second edge circular registers is bidirectional and can be independently controlled to shift or not shift. These implementations provide a great deal of flexibility in how to configure and control to support a range of use cases, for example, by first configuring all circular registers to shift forward and then, after several clock cycles, reconfiguring the buffers so that a subset of the circular registers shifts backward or not at all, while the remaining registers continue to shift forward in consecutive clock cycles.

[0026] In some implementations, the proximal triggers (not just the far-end triggers) of each first edge circular register and / or each second edge circular register are arranged to receive data from the direct memory access system. This connection (as well as the connection from the DMA system to each far-end trigger of the first and / or second circular register) can be toggleable for each circular register based on configuration data (i.e., selectively enabled or disabled). This can provide greater flexibility and efficiency when loading (i.e., injecting) data into the data buffer; for example, if fewer than 32 values ​​are to be loaded into a particular circular register, they can be loaded from the proximal end to avoid having to shift the data along the array from the far end along the particular register.

[0027] The data input and data output terminals of the processing element are preferably multi-bit (e.g., for receiving and outputting 16-bit or 32-bit words). Each shift and loop register in the first and second data buffers preferably includes a chain of multi-bit registers, such as a chain of 16 or 32 parallel single-bit flip-flops for storing multi-bit values ​​at each link of the chain.

[0028] The first edge circular registers can all have the same number of registers (i.e., a common chain length), for example, each containing 32 16-bit registers in a chain. The second edge circular registers can all have a common chain length, which can be the same as the first edge circular registers, for example, both having 32 registers.

[0029] There can be at least as many first edge circular registers as there are data input terminals of the first edge processing element. There can also be at least as many second edge circular registers as there are data output terminals of the second edge processing element. This allows for fully parallel data inflow and outflow of the array.

[0030] In some implementations, each processing element has exactly two data inputs and two data outputs. In this case, the number of first edge loop registers can be twice that of the first edge processing element, and the number of second edge loop registers can be twice that of the second edge processing element.

[0031] The first edge and the second edge can be opposite edges. They can have the same number of processing elements.

[0032] The array of processing elements can have any logical shape (e.g., hexagonal), but in some implementations, it is a rectangular array (e.g., a square array). The second edge can be parallel to the first edge. The logical structure of the array may be particularly important because in some implementations, it is not possible to connect each PE output to each PE input; instead, each PE input can be connected to PE outputs in its neighborhood (and for some PEs, such as via a feedback path from the second edge to the first edge, optionally connected to one or more more distant PE outputs), but not to each PE output. This limitation may be desirable for reducing the size and complexity of configurable interconnect systems. The neighborhood of a PE can be smaller than the entire array. In some implementations, each PE in the array can receive data from all PEs in the neighborhood of a corresponding subject PE, where the neighborhoods all have a common shape (e.g., all are 3×3 squares centered on the corresponding PE). Of course, due to boundary effects, the number of PEs in a neighborhood can decrease towards one or more edges of the array (e.g., a 3×3 square window contains only 2×3=6 PEs when the object PE is at the edge of the array, and only 2×2=4 PEs when it is at a corner of the array). Neighborhoods can have any common shape and are not necessarily rectangular; they can be centered on or not on the object PE, and may or may not include the object PE. The interconnect system can also support connections to one or more distant PEs that are not part of a typical neighborhood.

[0033] In some implementations, where the array is rectangular and configured to receive input data at the input edges, the switchable connectivity neighborhood of the object PE may include any one or more of the following:

[0034] The object PE itself (i.e., allowing feedback from the output of PE to one of its own inputs);

[0035] One or both of the two PEs that are adjacent to the object PE and are at the same distance from the input edge as the object PE (e.g., the left or right side of the object PE when the input edge is the top edge);

[0036] The adjacent PE located one step away from the object PE in the direction directly opposite the input edge (i.e., a position further away along the row or column of the array) (e.g., immediately above when the input edge is the top edge);

[0037] One or both of the two PEs are displaced diagonally from the object PE in a manner that is one step away from the object PE in the direction facing the input edge and one step away from the object PE in a direction parallel to the input edge (e.g., along the upper left diagonal or along the upper right diagonal when the input edge is the top edge).

[0038] PE two steps away from the object PE in the direction directly opposite the input edge (e.g., two positions immediately above when the input edge is the top edge); and

[0039] One or both of the two PEs that are diagonally displaced from the object PE in a manner that is two steps away from the object PE in the direction facing the input edge and one step away from the object PE in a direction parallel to the input edge (e.g., the two rows above the top edge closer to the top edge and one step to the left or right).

[0040] In some implementations, at least one PE in the array is capable of receiving inputs from all nine PEs in its neighborhood. In some implementations, at least one PE in the array may receive inputs only from these nine PEs. In some implementations, each PE in the array is capable of receiving inputs from up to all nine PEs in a corresponding neighborhood of that PE, where there are PE outputs (i.e., PEs near the array edge are edge-constrained).

[0041] If the array is bidirectional, then as data moves in the opposite direction, the neighborhood can consist of the same three PEs at the front plus the six more PEs further away in the opposite direction. Therefore, the interconnect system can support connections from the object PE to a total of at least 15 PEs (including the object PE itself).

[0042] In some implementations, configurable interconnects are arranged such that each first edge PE (in addition to receiving input from the first data buffer) can also receive output from any second edge PE. This allows results to be fed directly from the second (output) edge of the array to the first (input) edge without reversing the flow direction through the array or using buffers and DMA to move results from the output edge back to the input edge. This provides additional flexibility and allows the array to support more diverse computations. When data flows in the reverse direction, i.e., from the second edge to the first edge, the configurable interconnects can also be arranged such that each second edge PE (in addition to receiving input from the second data buffer) can also receive output from any first edge PE.

[0043] In some implementations, the array is a rectangular array and configurable interconnects are arranged such that each PE along a third edge of the array perpendicular to the first and second edges is also capable (at one input, or at any of two or more different inputs) of receiving output from a corresponding PE along a fourth edge of the array parallel to the third edge. Specifically, each object PE along the third edge may be capable of receiving output from a corresponding PE located on the fourth edge and positioned one step (i.e., one row or one column) closer to the input edge than the object PE. In some implementations, this is the only corresponding fourth edge PE from which each third edge PE can receive output. Similarly, each fourth edge PE may be capable (at one input, or at any of two or more different inputs) of receiving output from a corresponding third edge PE and may not receive output from other third edge PEs, which could be PEs located on the third edge one step (i.e., one row or one column) closer to the input edge than the corresponding fourth edge PE. These connections can facilitate efficient implementation of operations such as finite impulse response (FIR) or infinite impulse response (IIR) filtering.

[0044] System memory may include RAM and / or non-volatile memory such as flash memory. A DMA system may include one or more DMA scatter-aggregate units. In some embodiments, the DMA system includes an incoming DMA unit for reading data from system memory (e.g., from RAM) and an outgoing DMA unit for writing data to system memory (e.g., RAM). The DMA system may also be arranged to read configuration data from system memory for configuring an array of processing elements. In some preferred embodiments, the DMA system is dedicated to a hardware accelerator; however, in other embodiments, it may be a shared DMA controller, which may also be configured to transfer data between system memory and one or more other peripheral devices.

[0045] In some implementations, each PE has exactly two data inputs. Each PE may have exactly two data outputs. The bit lengths of the data inputs and outputs may all be the same. Each data input may be a 16-bit input. Each data output may be a 16-bit output.

[0046] Each processing element (PE) may include (e.g., associated) a corresponding configuration memory (e.g., a register file) and is configured to determine, based on configuration data stored in the configuration memory, the logical or arithmetic operations to be performed on input data received at one or more data inputs. Each PE may be configured to perform any one or more of the following: addition, subtraction, multiplication, division, left shift, right shift, logical negation, and XOR, AND, OR, and NOT operations. The size of the configuration memory may be determined to store configuration data that precisely identifies a corresponding operation for each data output of the PE; that is, new configuration data must be loaded into the PE before it can perform different operations.

[0047] Each PE may include an immediate value register for storing immediate values ​​(i.e., constant values) used in one or more operations for one or more inputs, such as addition and / or multiplication with immediate values. Immediate values ​​can be loaded into the PE simultaneously with configuration data being loaded into configuration memory.

[0048] Each PE can be selectively configured to perform a NOP (No Operation) or a no-operation (i.e., delaying the output of unchanged input data) operation, which may have a delay equal to or greater than the delay of one or more logical and / or arithmetic operations (e.g., two clock cycles). A PE can support two or more no-operation (NOP) operations, which may have different delays; for example, the first NOP may have a two-cycle delay, and the second NOP (which may be referred to as a feedthrough operation) also outputs unchanged input data and has a one-clock-cycle delay. In other words, in some implementations, each processing element can be configured to receive a value at its data input and output that value at its data output after a delay that may be configured to have one of two different durations. This can provide greater versatility in controlling the data flow through the array.

[0049] In some implementations, each PE can perform a different operation on each of its outputs. Specifically, a PE can provide the option to output the sum of the two inputs at a first output and simultaneously output the difference (subtraction) of the same two inputs at a second output. This enables particularly efficient implementation of certain operations, such as radix-2 FFT butterfly computations. Similarly, in some implementations, a PE can provide the option to output the maximum of the two inputs at a first output and simultaneously output the minimum of the same two inputs at a second output.

[0050] In some implementations, each PE is configured to selectively perform a combined multiplication and right shift operation on data received at two data inputs. It can output the product of the two inputs, right-shifted by a predetermined number of bits, at a single data output. This can be particularly advantageous when the data output is the same size as the data input (e.g., both 16 bits long), as it allows the multiplication of two values ​​that would normally overflow the data output without losing the most significant bit of the answer. The size of the right shift can be determined by the value loaded into the immediate register of the PE.

[0051] The hardware accelerator may include configuration logic, such as a control unit implementing a state machine, for configuring processing elements to perform corresponding logical or arithmetic operations and / or for configuring configurable interconnects. The hardware accelerator may provide a register interface for receiving instructions, such as those from a general-purpose processor, for example via a bus. The hardware accelerator may be configured to obtain configuration data for the processing elements and / or configurable interconnects via a DMA system or via the register interface.

[0052] In some implementations, each input of each PE can be selectively connected to any one of a set of corresponding possible sources. Configurable interconnects may include a set of lines and a set of multiplexers, wherein each PE input is connected to the output of a corresponding multiplexer, and wherein each multiplexer can be selectively connected to one of the sets of sources. The multiplexers may be controlled by configuration data stored in the configuration memory of the corresponding PE. The set of sources may include one or more outputs of one or more other PEs in the array. They may include one or more or all of the proximal flip-flops of a first edge or second edge register. Possible sources may include one or more outputs of the same PE itself, i.e., an immediate feedback path; this may be useful when implementing iterative operations. However, in some implementations, the feedback path of a PE is instead implemented within the PE itself (rather than via a multiplexer). This may potentially allow for faster, e.g., data feedback within a single cycle.

[0053] In some implementations, each proximal flip-flop of the first edge-loop register and the second edge-loop or shift register is permanently arranged to receive data from a corresponding distinct output of the processing element, without data from the other outputs. In this way, the interconnect structure can be directly configured by selecting the source of the inputs of the relevant PEs in the array, as well as the source of the inputs of the relevant registers for any data buffers configured to receive data from the array.

[0054] In some implementations, the PEs are logically arranged in a rectangular array, and configurable interconnects are arranged such that the input of the first PE can be selectively connected to the output of the second PE, wherein the second PE is not one of the eight nearest neighbors of the first PE and is not located in either of the two positions closer to the first or second edge of the array in the same row or column as the first PE. In some implementations, the second PE can be in the row or column adjacent to the first PE and in either of the two positions closer to the first or second edge of the array, i.e., a long diagonal interconnect. In some implementations, the first PE can be a first edge PE, and the second PE can be a second edge PE, or the first PE is a second edge PE, and the second PE can be a first edge PE (i.e., providing an array feedback path).

[0055] In some implementations, the array comprises exactly 16 processing elements. These can be logically arranged in a 4x4 square array. Each of the 16 PEs can have exactly two data inputs and two data outputs. Eight circular registers can reside in the first data buffer, and eight circular registers can reside in the second data buffer. This arrangement has been found to be particularly compact, yet still supports a range of signal processing operations, including complex correlation, radix-2 FFT butterfly calculations, and impulse response filters.

[0056] Hardware accelerators can be implemented on semiconductor devices, such as silicon chips. They can be implemented using fixed, dedicated hardware logic. However, in some implementations, they can be implemented at least partially using an FPGA.

[0057] The integrated circuit chip including the hardware accelerator may also include memory storing configuration data for the hardware accelerator. When loaded into the hardware accelerator, the configuration data allows it to compute any one or more of the following: the square of the magnitude of the sum of complex products; complex dot product; complex cross-correlation; radix-2 FFT butterfly computation; radix-2 FFT computation; or any other feasible operation.

[0058] While DMA units provide a convenient means of configuring and using hardware accelerators, some implementations can load data through other means such as register interfaces. Therefore, in another aspect, the present invention provides a hardware accelerator comprising:

[0059] An interface used to transfer data between hardware accelerators and system memory;

[0060] An array of processing elements, each processing element including two data inputs and two data outputs, and configured to perform selectable logical or arithmetic operations on input data received at one or more data inputs to generate output data at one or more data outputs, wherein the array includes a set of two or more first edge processing elements along a first edge of the array and a set of two or more second edge processing elements along a second edge of the array, the second edge processing elements being different from the first edge processing elements;

[0061] A configurable interconnect section is provided for selectively connecting the output terminal of a corresponding processing element to the input terminal of a corresponding processing element.

[0062] A first data buffer includes two or more first edge circular registers, each first edge circular register including multiple chained flip-flops, comprising near-end flip-flops and far-end flip-flops, wherein the far-end flip-flops of each first edge circular register are arranged to receive data from an interface, and wherein the near-end flip-flops of each first edge circular register are selectively connected to the data input of a corresponding first edge processing element; and

[0063] The second data buffer includes two or more second edge shift registers, each second edge shift register including multiple chained flip-flops, which include near-end flip-flops and far-end flip-flops, wherein the near-end flip-flops of each second edge shift register are selectively connected to the data output of a corresponding second edge processing element, and wherein the far-end flip-flops of each second edge shift register are arranged to output data to an interface.

[0064] Features of any aspect or implementation described herein may be applied to any other aspect or implementation described herein where appropriate. When referring to different implementations or sets of implementations, it should be understood that they are not necessarily different but may overlap. Attached Figure Description

[0065] Some preferred embodiments of the invention will now be described by way of example only with reference to the accompanying drawings, wherein:

[0066] Figure 1 This is a schematic diagram of a system-on-a-chip including a hardware accelerator implementing the present invention;

[0067] Figure 2 This is a schematic diagram of a hardware accelerator;

[0068] Figure 3 It is a schematic diagram of a collection of circular registers, plus a magnified view of a typical circular register in that collection;

[0069] Figure 4 This is a schematic diagram of a typical processing element in an array;

[0070] Figure 5 This is a schematic diagram of some interconnects in a hardware accelerator;

[0071] Figure 6 This is a schematic diagram of the configuration of a hardware accelerator used to calculate the square of the magnitude of the sum of complex product products;

[0072] Figure 7 This is a schematic diagram of the configuration of the hardware accelerator used to perform complex dual-related tasks;

[0073] Figure 8 This is a schematic diagram of the state of the data buffer of a hardware accelerator at a certain point in time when performing the correlation between two vectors of different lengths;

[0074] Figure 9 This is a schematic diagram of the state of the data buffer at a later point in time;

[0075] Figure 10 This is a diagram illustrating the state of the data buffer at a later point in time; and

[0076] Figure 11 This is a schematic diagram of the configuration of a hardware accelerator used to perform radix-2 FFT butterfly computation. Detailed Implementation

[0077] Figure 1 A system-on-a-chip (SoC) device 1 is shown. It includes a microprocessor 2 (e.g., Arm). TM Cortex-M TM The system comprises a processor, a memory 3 (which may include volatile RAM and non-volatile flash memory) for storing instructions and data, and a hardware accelerator 4. These are interconnected via a bus system 5, which includes Arm... TM Advanced Peripheral Bus (APB), Arm TM The system includes an Advanced High Performance Bus (AHB-lite), a Power and Clock Gated Control (PCGC) bus, and a Programmable Peripheral Interconnect (PPI). An interrupt line (not shown) also exists from accelerator 4 to processor 2.

[0078] SoC 1 may include other components such as additional processors, DSPs, and coprocessors (e.g., for cryptographic operations); systems for managing power distribution, clock signals, and reset processing; and peripheral devices such as digital radio equipment, input / output modules, timers, etc. For simplicity, these are... Figure 1The 'm' is omitted. SoC 1 may have pins or pads for connecting to various external components such as power supplies, crystal resonators, capacitors, resistors, radio antennas, user interfaces, etc.

[0079] Hardware Accelerator 4 is a general-purpose, reconfigurable accelerator for accelerating digital signal processing applications. The design is reconfigurable, meaning its functionality can be switched at runtime to handle different algorithms.

[0080] It includes an array core 6, which comprises an array of processing elements (PEs), a first direct memory access (DMA) scatter-aggregate unit 7 (DMA_A), a second direct memory access (DMA) scatter-aggregate unit 8 (DMA_B), and a control unit 9. It also includes three interface modules: a programmable peripheral interconnect (PPI) unit 10, a power and clock gating unit 11, and an interface unit 12.

[0081] DMA units 7 and 8 can read from and write to memory 3 via AHB-lite without the involvement of processor 2. Specifically, they can read configuration data from control unit 9, as well as incoming data for processing by array core 6, and write the output of array core 6 to the outside. The first DMA unit 7 (DMA_A) is used to transfer data from data memory 3 to array core 6, while the second DMA unit 8 (DMA_B) puts the final result from array core 6 into main memory 3.

[0082] PPI unit 10 is connected to PPI and enables accelerator 4 to respond to task signals from other peripheral devices and to indicate events to other peripheral devices, such as as described in the applicant's earlier application WO 2020 / 002423.

[0083] The power and clock gating unit 11 is connected to the PCGC bus and is used to control the gating of the power and clock signals input to the accelerator 4 in order to reduce the power consumption of the accelerator 4 when it is not activated. The accelerator 4 receives three different clock signals: one for the interface unit 12, one for the control unit 9, and one for the array core 6.

[0084] Interface unit 12 is used to generate tasks, events, and event-based interrupts, and provides a register interface accessible via APB. This allows processor 2 (and potentially other components) to send computation-related task instructions and DMA-based task instructions to accelerator 4 and determine status information from accelerator 4, such as for starting or interrupting processing tasks; enabling or disabling interrupts; providing addresses in memory 3 for access by DMA7, 8; and so on.

[0085] Control unit 9 provides a state machine for controlling DMA transfers and a state machine for controlling computations performed by array core 6. It accesses computation-related information from read / write registers in interface unit 12.

[0086] Figure 2 The array core 6 is shown in more detail.

[0087] Core 6 comprises a 4×4 square array 20 of processing elements (PEs) or computing units, where each PE is the computing unit in the structure. Each PE is equipped with its own local configuration memory, which can load configuration data at system startup. New configuration streams can also be loaded at runtime, allowing the design to be dynamically reconfigured to switch its functionality to handle different algorithms.

[0088] The array core 6, including the 4×4 PE array 20, is also equipped with a first hardware data buffer 21 (data buffer A) adjacent to the top edge of the array 20 and a second hardware data buffer 22 (data buffer B) adjacent to the bottom edge of the array 20. These data buffers 21 and 22 provide the data to be processed and store intermediate and final results.

[0089] Each data buffer 21, 22 consists of eight 16-bit bidirectional circular registers (CRs), each with a length of 32 registers. Each PE has two inputs, and each of the top and bottom rows consists of four PEs, resulting in a total of eight inputs along each of the top and bottom edges. Thus, the eight CRs along each edge provide full parallelism.

[0090] Figure 3 An exemplary CR 21a from the first buffer 21 is shown in more detail. CR 21a comprises a chain of 32 16-bit registers, including a near-end register 30 (comprising 16 near-end flip-flops) closest to array 20 (and capable of receiving data from and outputting data to array 20) and a far-end register 31 (comprising 16 far-end flip-flops) furthest from array 20. It also has a first feedback path 32 for moving 16-bit register values ​​directly from near-end register 30 to far-end register 31 (when CR 21a is in a "forward" flow configuration), and a second feedback path 33 for moving 16-bit register values ​​directly from far-end register 31 to near-end register 30 (when CR 21a is in a "backward" flow configuration). When enabled, these feedback paths 32, 33 allow CR 21a to cycle data in either direction. All CRs in both buffers 21 and 22 are similar.

[0091] At any time, any custom combination of CRs can be enabled for shifting and for read and write operations by DMA units 7, 8, and PE array 20. Configuration data can specify a subset of CRs to be enabled for shifting, while the remaining CRs are not shifted. DMA units 7, 8, and PE array 20 can inject data on top of or at the bottom of the CRs. Feedback paths 32, 33 for any desired subset of the CRs can be activated at runtime as needed. Custom delays and read cycles can be defined in software for customized processing.

[0092] Each input of the PE in the top row can receive the output of the end register of any CR in the first buffer 21, and each input of the PE in the bottom row can receive the output of the end register of any CR in the second buffer 22. However, each output in the bottom row can only write to the end register of a corresponding CR in the second buffer 22, and each output in the top row can only write to the end register of a corresponding CR in the first buffer 21. (In addition, the PE outputs in the top and bottom rows can be selectively fed back to the inputs of the PEs along opposite edges, instead of or also configured to output to their adjacent buffers 21, 22, as shown below.) Figure 5 (As described in more detail.)

[0093] Data buffers 21 and 22 can be written to and read from their near or far ends using DMA units 7 and 8. The first DMA unit 7 is also responsible for transferring the configuration stream to the PE array 20. Even if the target data to be transferred is scattered in many different locations, DMA units 7 and 8 can efficiently transfer data to or from the RAM in the data memory 3.

[0094] Processor 2 sends instructions to DMA units 7 and 8 via control on the APB bus to load data from memory 3 into array core 6 and to configure data buffers 21 and 22. Configuration options include: identifying the subset of CRs enabled in each buffer to cycle through the data; setting the direction of the cycle shift for each buffer; and setting whether the DMA should access data at the top or bottom of each buffer. Selectively enabling a subset of CRs for cycling while keeping another subset stationary allows for efficient alignment of individual values ​​on the CRs in data buffers 21 and 22 without requiring circuitry that could provide individualized information to each CR about how many cycles to shift, which would be a more complex and area-intensive approach.

[0095] Processor 2 also sends computation-related information to interface unit 12, which defines the desired configuration of PE array core 6 to perform specific computations. This information includes a set of control words for PE array core 6. These are stored in registers of interface unit 12 accessible to control unit 9. Each 32-bit control word includes fields that determine the cyclic shift direction of data buffers 21 and 22, the interconnection mode between PEs, the operations to be performed by all PEs, and other cyclic precision parameters required to process subtasks.

[0096] Figure 4 An exemplary PE 20a from PE array 20 is shown in more detail. All PEs are physically similar.

[0097] Each PE 20a has two data inputs connected to a first 16-bit input register (In_A) 40 and a second 16-bit input register (In_B) 41, and two data outputs connected to a first 16-bit output register (Out_A) 42 and a second 16-bit output register (Out_B) 43, respectively. (Of course, in other embodiments, the input registers and output registers may have different lengths.) It also has a configuration register file 45 for storing configuration data of the digital logic 46 of the PE 20a. Input and output are implemented in register mode to prevent combinational loops.

[0098] The digital logic 46 in PE 20a can be configured at any time to perform one of 16 different arithmetic and logical operations for each output 42, 43. Providing two outputs 42, 43 (instead of a single output) allows the digital logic 46 to perform two different operations simultaneously on corresponding inputs or on the same pair of input operands, such as NOT from input A to output A and NEGATIVE from input B to output B; or MAX from input A and input B to output A and MIN from the same input A and input B to output B. This potential ability to perform two different operations on the same pair of inputs can be particularly helpful for efficiently implementing certain operations, such as radix-2 fast Fourier transform butterfly calculations, where sums and differences are calculated for the same pair of operands.

[0099] Digital logic 46 includes an "immediate value" register (16 bits long in this example) which can be loaded with values ​​when configuration register file 45 is loaded.

[0100] The configuration word stored in the configuration register file 45 selects the result of the operation to be multiplexed (mux-out) at one or two outputs 42, 43.

[0101] The table below shows details of each operation that the PE can perform. The PE can be configured to perform any pair of operations, provided the necessary inputs and outputs are available. The latency of the PE operations in the table is measured in clock cycles, and all arithmetic operations are of two's complement integer type.

[0102]

[0103]

[0104] The MUL-SHIFT operation right-shifts the product of inputs A and B by the specified number of bits in an immediate register. When the shift size is set appropriately, this allows the product of two 16-bit inputs to be output to a 16-bit output register in a single operation, while retaining the 16 most significant bits.

[0105] The configuration stream of array core 6 contains 16 32-bit configuration words, each corresponding to one of the 16 PEs. Each word encodes the stream identifier, PE identifier, two operation identifiers, one of the outputs of each PE, and the interconnection settings of the inputs of the PEs. The 16 different configuration streams can be loaded into hardware accelerator 4 at system startup, and then switched between them. If the algorithm requires more than 16 configuration streams, additional streams can be loaded at runtime.

[0106] Figure 5 A representative portion of the configurable interconnect structure 23 is shown. It illustrates the connection options of the first input (In_A) of an exemplary PE Dest-9 when the array core 20 is configured so that data flows down the array from top to bottom. The input can be selected via a multiplexer 23a controlled by configuration data stored in the configuration memory of the PE Dest-9.

[0107] The inputs of PE Dest-9 can receive data from PEs (Dest-10, Dest-8) to its left and right, as well as from the PE immediately above it (Dest-5) and the PEs to its left and right (Dest-6, Dest-4), and from the PE two steps above it (Dest-1) and the PEs to its left and right (Dest-2, Dest-0). PE Dest-9 also includes selectable feedback paths (not shown here) from each of its own outputs to its own inputs to support iterative operations.

[0108] Each PE in array 20 can be configured similarly, although some options are not possible for PEs located at or near the edge of the array due to the limited size of the array.

[0109] The inputs of PE (Dest-0 to Dest-7) in the top two rows can also be configured to receive data from any of the selected proximal CRs in the first data buffer 21 (CR0-CR7).

[0110] Furthermore, the inputs of each PE in the top row can be selectively connected to receive the output from any PE in the bottom row. Figure 5 An example illustrating this is shown where the top row PE Dest-3 can switchably receive a value from an output terminal Out_A of the bottom row PE Dest-14 along the array feedback path 23b at one of its inputs, In_B. In practice, this can be achieved by connecting In_B to a multiplexer input, which can be programmably configured to receive input from either data buffer 21 or the feedback path 23b from Dest-14. Although... Figure 5 Although not shown, interconnect structure 23 can be configured to connect any bottom row output to any top row input. This allows certain intermediate results to loop back through the array without having to be output to data buffers 21, 22.

[0111] In some implementations, the inputs of each PE in the leftmost column can be selectively connected to receive the outputs from the corresponding PEs in the upper row and the rightmost column. Similarly, the inputs of each PE in the rightmost column can be selectively connected to receive the outputs from the corresponding PEs in the upper row and the leftmost column. This can facilitate efficient FIR and IIR configuration.

[0112] The interconnect structure contains enough lines and multiplexers to support data flow in either direction. When the flow direction is reversed, i.e., from bottom to top, the connection options are mirrored vertically. For example, when the flow is from bottom to top, PE Dest-9 can receive data from Dest-8, Dest-9 (itself), Dest-10, Dest-12, Dest-13, and Dest-14. Because it is located in the two rows closest to the second data buffer 22, its inputs can also be configured to receive data output from any selected CR in the near-end CR of the second data buffer 22.

[0113] Figure 6 An example configuration 60 of the cell array 20 is shown, which, when the input data buffer 21 is loaded with complex coefficients as indicated, calculates the square of the magnitude of the sum of a series of products of complex pairs |∑ k (A k +iB k (X) k +iY k)| 2 The consecutive rows of the input data buffer 21 are indexed by k. The final square root operation is performed to obtain the magnitude (i.e., the absolute value) |∑ k (A k +iB k (X) k +iY k The cost is too high, so it is not performed in this example; the square of the magnitude is sufficient for many purposes (e.g., when comparing magnitudes).

[0114] In some cases, it may be useful to repeatedly multiply a long string of complex sample values ​​by a fixed set of 32 or fewer complex constants. In this case, the CRs containing the constant values ​​can be controlled at runtime to make the constants cycle repeatedly, while the first DMA unit 7 simultaneously feeds a linear stream of sample values ​​to other CRs, which are controlled to prevent their contents from cycling (i.e., set to act like simple shift registers).

[0115] Figure 7 An example configuration 70 of the cell array 20 is shown, which can be used to perform two complex correlation operations in parallel on data fed from the input data buffer 21 to the array 20. Specifically, when the complex number X is loaded from k consecutive rows of the data buffer 21... k =a1 k +ib1 k and Y k =a2 k +ib2 k coefficient a1 k b1 k a2 k b2 k At that time, the 8 PEs in the left half will output Z. n =a3 n +ib3 n coefficient a3 n and b3 n , making The eight PEs on the right side can perform another identical dot product operation independently in parallel.

[0116] Importantly, if one of the values ​​in the set (e.g., Y) kIf a fixed vector of 32 or fewer samples (e.g., representing a predefined constant preamble portion of a radio signal) is cross-correlated with the signal data stream (e.g., representing samples of the incoming radio signal), then the coefficients of this fixed vector can be looped multiple times in the CR without having to be reloaded each time. If the cross-correlation step size is less than 32 samples, it may be possible to further improve efficiency by partially looping the signal data for each cross-correlation step while introducing one or more new signal samples at each cross-correlation step.

[0117] Figure 8 , Figure 9 and Figure 10 This illustrates how reversing the flow direction can significantly improve efficiency in certain situations. In this specific example, a cross-correlation is performed between two value vectors. A bidirectional shift is performed to efficiently compute each point of the correlation operation. By using the ability to selectively change the direction of the individual circular registers (CR) 21a flowing through the hardware data buffers 21, 22, the number of clock cycles used for correlation processing is significantly reduced.

[0118] In this example, PE array 20 (not shown) is configured to perform a correlation between two vectors of unequal length, vector X (e.g., a signal vector) having a length of 32 and vector Y having a length of 5 (e.g., a template vector representing a constant preamble portion of a radio signal).

[0119] Figure 8 The diagram illustrates the data positioning within the first hardware data buffer 21 at the start of the relevant operation. Register CR7 is filled with the value of vector X, while register CR6 contains the value of vector Y. The first elements X1 and Y1 of each vector are aligned with each other at the near edge of buffer 21, ready to be input into PE array 6 in the downward flow direction.

[0120] Figure 9 This illustrates the data positioning of the X and Y vectors in the first hardware data buffer 21 after the generation of the first correlation point (the result of which will be stored in the second hardware data buffer 22). The five vector elements X1, X2, X3, X4, X5 and Y1, Y2, Y3, Y4, Y5 of vectors X and Y have been looped (i.e., using the forward feedback path 32) and now reside in the five furthest elements of registers CR7 and CR6, respectively. The remaining elements of vector X have been shifted down.

[0121] To execute the next correlation point, it is necessary to return the five elements of vector Y to the near edge of register CR6, preparing them to be input into PE array 6 along with the elements X2, X3, X4, X5, and X6 of vector X, as follows. Figure 10 As shown.

[0122] This can be achieved by performing 28 consecutive forward (i.e., down) register shifts on registers CR6 and CR7, plus one additional forward shift of the X vector in register CR7. (The number 28 is because each CR has 32 elements, and the length of vector Y is 5, and 32-5=28). However, this would take 29 clock cycles (assuming one clock cycle per shift). By utilizing the bidirectional nature of the circular register and reversing the flow direction, causing vectors X and Y to cycle backward (i.e., up) and around the backward feedback path 33 from the far edge to the near edge of buffer 21, this process can be reduced to only 5 shifts on CR6 and 4 shifts on CR7, taking only 5 clock cycles.

[0123] This forward and backward shifting of vectors X and Y can be repeated until all relevant points have been calculated.

[0124] This can result in a significant reduction in clock cycles compared to using only a one-way (i.e., forward) cyclic shift. For a correlation of a 32-point X vector and a 5-point Y vector, the complete correlation result will be 32 + 5 + 1 = 38 points long, and if only a one-way cyclic shift is used, it requires an overhead of 28 × 38 = 896 cycles (i.e., for realigning the X and Y vectors, not including the additional shift required for actually calculating the correlation), compared to only 5 × 38 = 160 cycles if a two-way cyclic shift is used. Therefore, in this case, two-way feedback can provide a speedup factor greater than 5.

[0125] This bidirectional feedback is beneficial when the length of a vector is less than half the length of the loop register. The CRs in the two data buffers 21 and 22 can be selectively and dynamically configured for feedforward or feedback shifts depending on the length of the data, and thus can be used efficiently for data of varying lengths.

[0126] Figure 11 An example configuration 80 of cell array 6 is shown, which performs a radix-2 FFT butterfly operation on a 64-point FFT.

[0127] The third PE from the left in the top row outputs a sum operation at its first output and a difference operation at its second output for the same input. The PE marked "D" simply passes through its input with a two-cycle delay, i.e., NOP.

[0128] The output of the first PE in the bottom row is W = a1 + a2; the output of the second PE is X = (a1 - a2)w1 - (b1 - b2)w2; the output of the third PE is Y = (a1 - a2)w2 + (b1 - b2)w2; and the output of the fourth PE is Z = b1 + b2. The values ​​W + iZ and X + iY are the two outputs of the FFT butterfly operation performed on a1 + ib1 and a2 + ib2.

[0129] Although the looping feature of the loop register is not necessarily utilized when performing FFT operations, the ability to perform efficient FFT butterfly operations demonstrates the flexibility of hardware accelerators to be configured to perform a variety of different processing operations.

[0130] As demonstrated, 4×4 arrays can be used to implement many important signal processing operations (all of which are useful in digital radio and other applications) while remaining compact. Specifically, a 4×4 PE array with PEs supporting joint multiplication-shift operations provides an elegant way to implement radix-2 butterfly computations in a compact array. However, implementations are not limited to 4×4 arrays, and arrays of any other size can also be implemented.

[0131] Those skilled in the art will recognize that the invention has been described by way of one or more specific embodiments, but is not limited to these embodiments; many variations and modifications are possible within the scope of the appended claims.

Claims

1. A hardware accelerator, comprising: A direct memory access system for transferring data between the hardware accelerator and the system memory; An array of processing elements, each processing element including two data inputs and two data outputs, and configured to perform selectable logical or arithmetic operations on input data received at one or more data inputs to generate output data at one or more data outputs, wherein the array includes a set of two or more first edge processing elements along a first edge of the array and a set of two or more second edge processing elements along a second edge of the array, the second edge processing elements being different from the first edge processing elements; Configurable interconnection section for selectively connecting the output terminal of a corresponding processing element to the input terminal of a corresponding processing element; A first data buffer includes two or more first edge circular registers, each first edge circular register including a plurality of chained flip-flops containing proximal and far-end flip-flops, wherein the far-end flip-flops of each first edge circular register are arranged to receive data from the direct memory access system, and wherein the proximal flip-flops of each first edge circular register are selectively connected to the data input of a corresponding first edge processing element; and The second data buffer includes two or more second edge shift registers, each second edge shift register including a plurality of chained flip-flops containing proximal and far-end flip-flops, wherein the proximal flip-flops of each second edge shift register are selectively connected to the data output of a corresponding second edge processing element in the second edge processing element, and wherein the far-end flip-flops of each second edge shift register are arranged to output data to the direct memory access system.

2. The hardware accelerator according to claim 1, wherein, Each first edge loop register is bidirectional, including a first feedback path for passing data directly from the proximal flip-flop of the loop register to the far-end flip-flop, and also including a second feedback path for passing data directly from the far-end flip-flop of the loop register to the proximal flip-flop.

3. The hardware accelerator according to claim 1 or 2, wherein, Each first edge loop register can be independently configured to either cause data to circulate in the loop register along a direct feedback path from the near-end flip-flop to the far-end flip-flop, or not cause data to circulate in the loop register.

4. The hardware accelerator of claim 1 or 2 is arranged such that a configurable subset of one or more registers of the first and second data buffers can be enabled for shifting, while the remaining registers of the first and second data buffers are not shifted.

5. The hardware accelerator according to claim 1 or 2, wherein: The first edge circular register and the second edge shift register are bidirectional; The far-end flip-flops of each second edge shift register are arranged to receive data from the direct memory access system; The proximal flip-flop of each second edge shift register can be selectively connected to the data input of a corresponding second edge processing element in the second edge processing element; The proximal flip-flop of each first edge loop register can be selectively connected to the data output of a corresponding first edge processing element in the first edge processing element; as well as The far-end flip-flops of each first edge circular register are arranged to output data to the direct memory access system.

6. The hardware accelerator according to claim 1 or 2, wherein, The array of configurable interconnects and processing elements can be configured in a first configuration to process data flowing from the first edge through the array of processing elements to the second edge, and can be configured in a second configuration to process data flowing from the second edge through the array of processing elements to the first edge.

7. The hardware accelerator according to claim 1 or 2, wherein, The second edge shift register is a circular register.

8. The hardware accelerator according to claim 7, wherein, Both the first edge loop register and the second edge loop register are bidirectional and can be independently controlled to perform shifting or not shifting.

9. The hardware accelerator according to claim 1 or 2, wherein, The proximal triggers of each first edge circular register can be selectively configured to receive data from the direct memory access system.

10. The hardware accelerator according to claim 1 or 2, wherein, Both the first edge circular register and the second edge shift register have the same number of registers.

11. The hardware accelerator of claim 1 or 2, comprising a first edge loop register as many as the data inputs of the first edge processing element and a second edge shift register as many as the data outputs of the second edge processing element.

12. The hardware accelerator according to claim 1 or 2, wherein, Each processing element has exactly two data inputs and two data outputs.

13. The hardware accelerator according to claim 1 or 2, wherein, The array of processing elements is a rectangular array, and the first edge and the second edge are opposite edges of the rectangular array.

14. The hardware accelerator according to claim 13, wherein, The array of processing elements has exactly 16 processing elements in a four-by-four square array.

15. The hardware accelerator according to claim 1 or 2, wherein, The configurable interconnect is arranged such that, for each processing element in the array of processing elements, each data input terminal of the corresponding processing element can be connected to any data output terminal of any processing element in the neighborhood of the corresponding processing element, without being connected to the data output terminal of at least one more distant processing element in the array of processing elements.

16. The hardware accelerator according to claim 1 or 2, wherein, The array of processing elements is rectangular, and wherein, for each processing element, each data input terminal of the corresponding processing element can be connected to any data output terminal of any processing element that is a processing element thereof: The corresponding processing element itself; or The distance between the array of the corresponding processing element and the first edge of the array of the processing elements is the same as that of the corresponding processing element; or One step away from the corresponding processing element in the direction of the first edge of the array facing the processing element; or The processor is shifted diagonally from the corresponding processing element in a manner that is one step away from the corresponding processing element in the direction facing the first edge and one step away from the corresponding processing element in a direction parallel to the first edge of the array of processing elements; or Two steps away from the corresponding processing element in the direction of the first edge of the array facing the processing element; or The processor is displaced diagonally from the corresponding processing element in a manner that is two steps away from the corresponding processing element in the direction facing the first edge and one step away from the corresponding processing element in a direction parallel to the first edge.

17. The hardware accelerator according to claim 1 or 2, wherein, The configurable interconnect is arranged such that each processing element on the first edge can be connected to receive output from any processing element on the second edge.

18. The hardware accelerator according to claim 1 or 2, wherein, Each processing element includes a corresponding configuration memory and is configured to determine, based on configuration data stored in the corresponding configuration memory, a logical or arithmetic operation to be performed on input data received at one or more data inputs of the processing element, wherein the size of the corresponding configuration memory of the processing element is set to store configuration data that accurately identifies a corresponding operation for each data output of the corresponding processing element.

19. The hardware accelerator according to claim 1 or 2, wherein, Each processing element can be configured to perform any one or more of the following: addition, subtraction, multiplication, division, left shift, right shift, logical inversion, XOR operation, AND operation, OR operation, and NOT operation.

20. The hardware accelerator according to claim 1 or 2, wherein, Each processing element can be configured to receive a value at its data input and output the same value at its data output after a delay, the delay being configured to have one of two or more different durations.

21. The hardware accelerator according to claim 1 or 2, wherein, Each processing element can be configured to output the sum of two values ​​received at two data inputs at a first data output of the processing element, and simultaneously output the difference of the two values ​​at a second data output of the processing element.

22. The hardware accelerator according to claim 1 or 2, wherein, Each processing element can be configured to perform a combined multiplication and right shift operation on two values ​​received at two data inputs, and output the answer at the data output of the processing element, wherein the number of bits at the data output is the same as the number of bits at each of the two data inputs.

23. An integrated circuit chip, comprising: The hardware accelerator according to claim 1; The system memory; as well as The bus system that connects the system memory to the direct memory access system of the hardware accelerator.

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