Chip testing system and chip testing method

Abstract

The present application relates to a kind of chip testing system and chip testing method, by the chip to be tested is divided into timing unit and non-timing unit, and for the same type unit in the same attribute end parallel connection is connected on the output terminal of corresponding attribute of test vector output module, in order to configure the test vector required for the full function test of the combination logic function of non-timing unit in the chip to be tested and or the timing logic function of timing unit.Testing, using the control function of controller, control test vector output module according to preset rule output test vector, and according to the output number of the single measured unit of the current test vector action that the input end of selection output circuit is connected, control selection output unit output the functional test result of the single measured unit of the current test vector action, through the test vector output by the controller control test vector output module, realize the whole functional test of each measured unit in chip, the whole process is fully automated operation, high efficiency, high reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip testing technical field, and in particular to a chip testing system and a chip testing method. BACKGROUND

[0002] With the rapid development of super large scale integrated circuits, the number of standard cells in the integrated circuit cell library is increasing, and the functions are becoming more and more complex, which makes the workload of testing all the functions of each cell larger and the verification period longer.

[0003] Therefore, in the current technology, a reasonable structure needs to be designed to test all the functions due to the increasing number of cells in the library when implementing full function testing. SUMMARY

[0004] Therefore, it is necessary to provide a chip testing system with a short testing period and capable of implementing full function testing of a chip.

[0005] In one embodiment, a chip testing system is provided, comprising:

[0006] a test vector output module, the test vector output module comprising a plurality of outputs with different attributes, the outputs with different attributes of the test vector output module being respectively used to match the input ends of each non-timed cell and the input ends of each timed cell in the chip under test, so as to configure the test vectors required for full function testing of the combinational logic function of the non-timed cell and the sequential logic function of the timed cell in the chip under test, the outputs of the test vector output module connected to different input ends of a single cell under test being different;

[0007] a selection output circuit, the input ends of the selection output circuit being connected to the output ends of each non-timed cell and the output ends of each timed cell;

[0008] a controller, the controller being connected to the control ends of the test vector output module and the control ends of the selection output circuit, and being used to control the test vector output module to output the test vectors according to a preset rule, so as to test each cell under test in the chip under test in sequence; and being used to control the selection output circuit to output the function test result of a single cell under test acted on by the current test vector;

[0009] the preset rule is a rule for ensuring that the test vector output module outputs the test vectors required for full function testing of each cell under test in the chip under test.

[0010] In one embodiment, the chip testing system further comprises:

[0011] an emulator receiving and running a design file of the chip under test; the emulator receiving the test vector provided by the test vector output module and performing test verification using the test vector to obtain a simulation result;

[0012] the controller being connected with the emulator and the output end of the selection output circuit, for obtaining the simulation result and comparing the simulation result with a functional test result of the same unit under test under the same test vector, if the verification result is consistent, determining that the functional test of the unit under test is qualified, and controlling the test vector output module to provide a next test vector to the chip under test and the emulator according to a preset rule.

[0013] In one of the embodiments, the output ends of different attributes of the test vector output module include a clock output end, a data output end and a reset output end;

[0014] the clock output end being used for connecting first clock input ends of the timing units;

[0015] the data output end being used for connecting data input ends of the timing units and data input ends of the non-timing units respectively;

[0016] the reset output end being used for connecting reset input ends of the timing units;

[0017] the clock output end, the data output end and the reset output end being used for providing the test vector to each unit under test in the chip under test through the connection relationship with each unit under test in the chip under test.

[0018] In one of the embodiments, the clock output end is used for connecting the first clock input ends of the timing units through a bus; the data output end is used for connecting the data input ends of the timing units and the data input ends of the non-timing units through a bus respectively; and the reset output end is used for connecting the reset input ends of the timing units through a bus.

[0019] In one of the embodiments, the chip test system further comprises:

[0020] an inverter, an input end of the inverter being connected with the clock output end, and an output end of the inverter being used for connecting second clock input ends of the timing units;

[0021] the clock signal provided by the clock output end being opposite to the clock signal provided by the output end of the inverter.

[0022] In one of the embodiments, the selection output circuit includes at least two data selectors.

[0023] a first input terminal of each of the data selectors is connected to an output terminal of each of the sequential units;

[0024] a second input terminal of each of the data selectors is connected to an output terminal of each of the non-sequential units;

[0025] a control terminal of each of the data selectors is connected to the controller;

[0026] the controller controls the same number of data selector output signals according to the number of output signal paths of a single unit under test acted on by a current test vector.

[0027] In one of the embodiments, the chip test system further comprises:

[0028] a clock synchronization module, a clock input terminal of the clock synchronization module is connected to the clock output terminal, a reset input terminal of the clock synchronization module is connected to the reset output terminal, and a signal input terminal of the clock synchronization module is further connected to an output terminal of each of the non-sequential units;

[0029] the controller synchronizes the actions of test vector change and selection output circuit output function test result by controlling the clock signal output by the clock output terminal of the test vector output module and the reset signal output by the reset output terminal.

[0030] In one of the embodiments, the test vector is a binary vector, and the binary vector is composed of N-bit binary numbers, where N is greater than or equal to the number of input pins of the unit with the most input pins in the chip under test.

[0031] In one of the embodiments, the preset rule is that only one binary number in any two adjacent provided binary vectors is the opposite number, and the binary numbers of the rest are the same.

[0032] A chip test method applied to the above chip test system, the test method comprising the following steps:

[0033] parallelly connecting the input terminals of the same attribute of each non-sequential unit in the chip under test to the output terminal of the corresponding attribute of the test vector output module;

[0034] parallelly connecting the input terminals of the same attribute of each sequential unit in the chip under test to the output terminal of the corresponding attribute of the test vector output module, and ensuring that the output terminals of the test vector output modules connected by different input terminals of a single unit under test are different;

[0035] connecting the input terminals of the selection output circuit to the output terminals of each of the non-sequential units and the output terminals of each of the sequential units;

[0036] a controller is connected to the control end of the test vector output module and the control end of the selection output circuit;

[0037] The test vector output module is controlled by the controller to output test vectors according to preset rules, so as to configure test vectors required for full-function test of the combinational logic function of the non-timing unit and the timing logic function of the timing unit in the chip to be tested, and sequentially test each of the units to be tested in the chip to be tested; and the selection output circuit is controlled to output the function test result of the single unit to be tested acted on by the current test vector.

[0038] The preset rules are rules for ensuring that the test vector output module outputs test vectors required for full-function test of each unit to be tested in the chip to be tested; and the unit to be tested is the timing unit or the non-timing unit in the chip to be tested.

[0039] The chip test system and the chip test method provided by the above embodiment have at least the following beneficial effects:

[0040] The chip to be tested is divided into timing units and non-timing units, and the same attribute terminals in the same type of unit are connected in parallel and then connected to the output terminals of the corresponding attributes of the test vector output module, so as to configure test vectors required for full-function test of the combinational logic function of the non-timing unit and the timing logic function of the timing unit in the chip to be tested. The specific test vector configuration is determined according to the type of the unit to be tested included in the chip to be tested. During testing, the controller is used to control the test vector output module to output the test vectors according to preset rules, so as to sequentially test each unit to be tested, and control the selection output unit to output the function test result of the single unit to be tested acted on by the current test vector. The test vectors output by the test vector output module are controlled by the controller, so that full-function test of the units in the chip is realized, and manual intervention is not required in the whole process, and the operation is fully automated, high in efficiency and high in reliability. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0042] Figure 1 It is a structural schematic diagram of a chip test system of an embodiment;

[0043] Figure 2 It is a schematic diagram of each unit to be tested in a chip to be tested connected to a test vector, and a schematic diagram of output selection of each unit to be tested;

[0044] Figure 3 Figure 1 is a schematic diagram of a portion of a circuit structure in a chip testing system in one embodiment;

[0045] Figure 4 Figure 2 is a schematic diagram of an internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0046] In order to facilitate the understanding of the present application, a more complete understanding of the present application can be had by reference to the following description in conjunction with the associated drawings. The figures included in the attached drawings are intended to illustrate the embodiments of the present application and are not limiting of the present application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0048] It should be understood that the terms “first”, “second” and so on used herein can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the other element. For example, without departing from the scope of the present application, the first resistor can be referred to as the second resistor, and similarly, the second resistor can be referred to as the first resistor. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0049] It should be understood that “connection” in the following embodiments, if the circuits, modules, units and the like connected to each other have the transmission of electrical signals or data, should be understood as “electrical connection”, “communication connection” and the like.

[0050] As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and / or “including”, or “has” and / or “having”, or variants thereof, specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0051] In one exemplary technology, a specific cell can be tested by building a test circuit using the method of circuit connection, which is time-consuming on one hand, and on the other hand, due to the change of the combination logic and the cell, time is still needed to rebuild the test circuit. The number of cells in a library is several hundred or even more than a thousand. Taking a 5-input cell to be tested as an example, 32 times of calculation and comparison are needed to test all functions. It can be imagined that the number of calculation times for testing all functions of all cells in the library is huge, and the workload of checking the calculation results is large. Sometimes, it takes more than a month to test, and the cost is high, the period is long, and the universality is poor.

[0052] In order to reduce the workload, two methods are currently used: one is to test the functions of the cells in a single library partially to reduce the number of tests and the time; the other is to use a program to simulate the results of the cells in the library to automatically compare. However, the first method may not test the functions that are wrong. The second method can test all functions, but the program design is complex, and it still needs to be redesigned for different libraries, which is not universal and universal, and the design cost is high.

[0053] In view of the above problems, as shown in Figure 1 In one embodiment, a chip test system is provided, which includes a test vector output module 10, a selection output circuit 40, and a controller 50. The controller 50 is connected to the control end of the test vector output module 10 and the control end of the selection output circuit 40, respectively.

[0054] The test vector output module 10 comprises a plurality of independent outputs, and each output of the test vector output module 10 is used to output different test vector signals. The chip under test comprises at least one non-timed unit 30 and at least one timed unit 20, the number of input terminals of each non-timed unit 30 is the same or different, the number of input terminals of each timed unit 20 is the same or different, and the number of outputs of the test vector output module 10 is greater than the number of input terminals of any non-timed unit 30 or the number of input terminals of any timed unit 20. The input terminals of each non-timed unit 30 are connected to different outputs of the test vector output module 10 to access different test vector signals output by the test vector output module 10; the input terminals of each timed unit 20 are connected to different outputs of the test vector output module 10 to access different test vector signals output by the test vector output module 10. The test vectors required for full-function testing of the combination logic function of the non-timed unit 30 and the timing logic function of the timed unit 20 in the chip under test are finally realized. The input terminals (pins) of the same attribute in each non-timed unit 30 and each timed unit 20 are connected to the same output terminal of the test vector output module 10, where the same attribute refers to the same type of signal access, for example, the input terminals for accessing clock signals in each non-timed unit 30 and each timed unit 20 are input terminals of the same attribute, and the input terminals of the same attribute are connected in parallel to the same output terminal of the test vector output module 10, thereby simplifying the test vector. Similarly, the input terminals for accessing data signals in each non-timed unit 30 and each timed unit 20 can be input terminals of the same attribute, and the input terminals of the same attribute are connected in parallel to the same output terminal of the test vector output module 10.

[0055] It should be noted that for a non-timed unit 30 or a timed unit 20, each input terminal thereof corresponds to a different output terminal of the test vector output module 10, and the purpose is to ensure that all functions of each non-timed unit 30 and each timed unit 20 can be tested, and to avoid false function testing.

[0056] In addition, the input terminals of the selection output circuit 40 are respectively connected to the output terminals of each non-timed unit 30 and the output terminals of each timed unit 20, which are used to control the test vector output module 10 to output test vectors according to a preset rule, and are used to control the selection output circuit 40 to output the function test result of a single non-timed unit 30 or a single timed unit 20 (i.e. a single unit under test) on which the current test vector acts, thereby realizing automatic testing of all functions of each non-timed unit 30 and each timed unit 20 in the chip under test. The preset rule is a rule for ensuring that the test vector output module 10 outputs test vectors required for testing all functions of each non-timed unit 30 and each timed unit 20 in the chip under test.

[0057] Specifically, the chip under test is divided into timing units 20 and non-timing units 30, and the terminals of the same attribute in the same type of unit are connected in parallel and then connected to the output terminals of the corresponding attribute of the test vector output module 10, so as to configure the test vectors required for the full function test of the combination logic function of the non-timing units 30 and the timing logic function of the timing units 20 in the chip under test. During testing, the control function of the controller 50 is used to control the test vector output module 10 to output test vectors according to the preset rules, so as to test each timing unit 20 and non-timing unit 30 in turn, and according to the number of output paths of the single timing unit 20 or single non-timing unit 30 acted on by the currently output test vector connected to the input terminal of the selection output circuit 40, the selection output unit outputs the function test result of the single timing unit 20 or single non-timing unit 30 acted on by the current test vector. By controlling the test vector output by the test vector output module 10 through the controller 50, the full function test of each timing unit 20 and non-timing unit 30 in the chip is realized, and no manual intervention is required during the whole process, which is fully automated, efficient, shortens the test time, and has high test result reliability.

[0058] With the rapid development of integrated circuits, in addition to the increasing workload of full function test of each unit under test, the workload of verifying the consistency of the functions of the units under test in the library (lib cell) and the actually manufactured units under test is also increasing, and in the traditional method, the verification period is also getting longer in the way of calculating the logic gate results for verification. Therefore, in an embodiment of the present application, the chip test system described above further comprises a simulator. For example, simulation can be realized by using a device loaded with software such as Cadence, Altium Designer and Proteus, etc. which has a simulation test function. The simulator can refer to a device capable of performing a simulation test function, for example, the simulator can be integrated in a computer device, and the simulation can be realized by running a program in the computer device, at this time, the computer device can be understood as the simulator.

[0059] In order to improve efficiency and verify the accuracy of the results, the simulator receives and runs the design file of the chip to be tested, and at the same time, the simulator also receives the test vector provided by the test vector output module 10, and uses the test vector to test and verify to obtain a simulation result. The controller 50 is connected with the output end of the simulator and the selection output circuit 40, used to obtain the simulation result, and compare the simulation result of the same test vector, the same non-timing unit 30 or timing unit 20 with the functional test result. If the verification result is consistent, it means that the functional test result of the current single unit under test (the unit under test is a non-timing unit 30 or a timing unit 20) is qualified, which can be used for subsequent IC (Integrated Circuit Chip, Integrated Circuit Chip) design, and the functional verification of the unit under test has been completed. The test vector output module 10 can provide the next test vector to the chip to be tested and the simulator according to the preset rule. Through this triggering mechanism, the automatic test and verification of all functions of each non-timing unit 30 and each timing unit 20 in the chip can be realized automatically.

[0060] Considering the commonly used several attribute ports in integrated circuits, in one embodiment, the output end of the test vector output module 10 can be designed according to attributes, including a clock output end, a data output end and a reset output end. The clock output end is used to connect the first clock input end of each timing unit 20, and provides timing signals for the functional test of the timing unit 20. The data output end is used to connect the data input end of each timing unit 20 and the data input end of each non-timing unit 30 respectively, and provides data signals required for the functional test of each unit under test. The reset output end is used to connect the reset input end of each timing unit 20, and provides reset signals for the timing unit 20, and provides test signals for testing the reset function of the timing unit 20. Based on the connection relationship between the clock output end, the data output end and the reset output end and each non-timing unit 30 or each timing unit 20 in the chip to be tested, and the content of the signals provided by each attribute output end, the test vector is provided for each non-timing unit 30 or each timing unit 20 in the chip to be tested. For example, if each output end of the test vector output module 10 outputs a binary signal, there are many combinations of binary signals output by each output end. By using such different combinations, the test of different functions of each non-timing unit 30 and each timing unit 20 can be realized.

[0061] For the convenience of connection, in one embodiment, the clock output end is used to connect the first clock input end of each of the timing units 20 through a bus; the data output end is used to connect the data input end of each of the timing units 20 and the data input end of each of the non-timing units 30 through a bus respectively; and the reset output end is used to connect the reset input end of each of the timing units 20 through a bus. By dividing the units of the chip to be tested into two categories according to whether they are timing units 20, and then connecting the same attribute ends in each category of timing units 20 in parallel to the same bit of the bus, the time required for building the circuit architecture is reduced. When the layout based on the design is simulated and tested, the verification result is also not inaccurate due to the pin deviation caused by the excessive pins in one-to-one connection during simulation.

[0062] In addition, through the bus connection mode, after the library is updated, the input end of the newly added cell in the library can be quickly connected to the corresponding bus according to the type (timing unit 20 or non-timing unit 30, such as an AND gate, a NOT gate, and an OR gate) of the newly added cell and the attribute of the input end thereof (see the above embodiment, which is determined by the signal connected thereto), that is, the change of the test vector output from the test vector output module 10 to each bus can be used to realize the full-function test of the newly added cell without the need to design a set of test circuits for the newly added cell. That is, the chip test system provided by the present application has strong versatility and can cope with the situation of adding cells in the library. The design cost is low, and due to the strong versatility, the application range is wide, and the chip test requirements of different manufacturers can be met.

[0063] Considering that some chips need two opposite timing signals when working, in one embodiment, the chip test system further includes an inverter, an input end of the inverter is connected to the clock output end, and a second clock input end of each of the timing units 20 is connected to an output end of the inverter; the clock signal provided by the clock output end is opposite to the clock signal provided by the output end of the inverter. In cooperation with the above clock output end, opposite timing signals are provided for the timing units 20, which meets the test requirements of various chips.

[0064] In one embodiment, the selection output circuit 40 comprises at least two data selectors, each of which outputs one signal. The first input of each data selector is connected to the output of each sequential unit 20, and the second input of each data selector is connected to the output of each non-sequential unit 30. The control end of each data selector is connected to the controller 50. During testing, the controller 50 controls the number of working data selectors according to the number of output signals of the single unit under test according to the current test vector, so as to ensure that the same number of data selectors output signals, and ensure that the final output signal is the signal actually output by the non-sequential unit 30 during the combinational logic function test.

[0065] In one embodiment, the chip test system further comprises a clock synchronization module, the clock input end of the clock synchronization module is connected to the clock output end, the reset input end of the clock synchronization module is connected to the reset output end, and the signal input end of the clock synchronization module is further connected to the output end of each non-sequential unit. The controller 50 controls the clock signal output by the clock output end of the test vector output module 10 and the reset signal output by the reset output end, so as to synchronize the test vector change and the output of the combinational logic function test result by the selection output circuit 40. The clock synchronization module functions as a switch, and determines when the combinational logic function test result input by the clock synchronization module is output to the selection output circuit 40. When the controller 50 controls the test vector output module 10 to switch the test vector, the clock synchronization module outputs the combinational logic function test result to the selection output module, and the controller 50 controls the selection output circuit 40 to control the same number of data selectors as the number of output signals of the combinational logic function test to work, and outputs the function test result.

[0066] In one embodiment, the controller 50 controls the test vector output module 10 to switch the test vector output by the test vector output module 10 at equal time intervals, and the controller 50 also controls the clock signal and the reset signal output by the test vector output module 10 to realize periodic collection of the function test result. That is, the function test result of the actual chip is obtained in a single clock cycle of the clock signal, and the actual test result is compared with the simulation result, so as to avoid direct calculation of the logic gate result with large workload, thereby improving the test and verification efficiency.

[0067] In one of the embodiments, the test vector provided by the embodiment is a binary vector, and the binary vector is composed of N-bit binary numbers, where N is greater than or equal to the number of input pins of the unit with the most input pins in the chip to be tested. By providing such a versatile test vector, different platforms can be tested, and the universality is strong. In addition, the number of bits of the binary number in the binary vector can be directly determined according to the number of input pins of the unit with the most input pins in the chip to be tested. Even if a multi-pin unit is added, the full-function test of the added unit can also be quickly realized by configuring the test vector.

[0068] In one of the embodiments, the preset rule is that only one binary number in the binary vector provided by any two adjacent times is the opposite number, and the binary numbers of the remaining bits are all the same. By using the preset rule, the test of all functions of each unit under test can be ensured without repeating the test of the same function of the same unit. An efficient chip unit full-function test scheme is provided.

[0069] In one of the embodiments, the controller 50 is further configured to update the number of binary bits in the test vector according to the name of the integrated circuit library, so that the test switching of different libraries can be quickly realized, and the test efficiency is improved.

[0070] The chip test system provided by the embodiment connects the input ends (input) of all the units (lib cell) in the library through a parallel mode, and the structure is as shown in Figure 2 The name (name) of the library (lib) is designed as a variable, and the units (lib cell) in the library can be divided into two groups, i.e., the non-timed units implementing the combinational logic function and the timed units implementing the timing logic function, by using the hardware TCL language according to the properties of the units (cell).

[0071] First, the input pins (input pin) of the non-timed units implementing the combinational logic function are connected (the pins are captured according to the pin properties and application commands), and the non-timed units implementing the combinational logic function are sequentially connected to a bus. One bus means that different pins of a single non-timed unit are connected to different buses. The connection mode of the timed units implementing the timing logic function is different from that of the non-timed units implementing the combinational logic function. The pins pins of all the timed units are classified according to the properties, such as the pins clock pin for inputting the clock signal, the pins data pin for inputting the data signal, and the pins reset pin for inputting the reset signal, etc. The input end pins with the same properties are connected together and connected to the same bit of the bus. All the output pins output pin of the chip under test are connected to the data selection circuit, and only the result of one unit cell is output each time, so that the automatic test of all functions of each unit is realized.

[0072] When applied to different library platforms, as long as the library name (lib name) in the above circuit design process is modified, it can be applied to the new platform, and the test results of different library platforms will not be confused.

[0073] In order to better illustrate the working process of the chip test system provided in the present application, the circuit shown in Figure 3 The controller controls the test vector output module to output data signal data[7:0], clock signal clk and reset signal rst, and the controller outputs test object selection signal sel_cell[7:0] and output selection signal out_sel. The inverter INCK outputs the received clk signal as an inverted CLK, which provides opposite timing signals for each timing unit that implements a timing logic function, meeting the functional test requirements of different timing units. At the same time, the reset signal simultaneously acts on the timing synchronization module connected to the output end of the timing logic function DFF timing unit and the non-timing unit of the combinational logic function COMB. In operation, if the function of the timing unit needs to be tested first, the test object selection signal sel_cell[7:0] output by the controller can be used to select the timing unit for testing, and the test vector output module changes the output timing signal, reset signal and data signal to realize various functional tests of the timing unit. Similarly, by controlling the test object selection signal sel_cell[7:0] output by the controller, the non-timing unit can be selected for testing, and the test vector output module changes the output timing signal, reset signal and data signal to realize various functional tests of the non-timing unit.

[0074] Through the above full-function test vector, full-function simulation is performed using a simulator. Through experiments, simulation results under the given simulation excitation are obtained, and then for a given chip under test in the experiment, the test vector including the timing unit and the non-timing unit is used to test the chip after it is taped out. The test results of each unit under test are compared with the simulation results according to the period of a single clock signal as the collection period of the functional test results and the simulation results, avoiding the direct calculation of the logic gate results which has a large workload. In the experiment, by comparing the test results under different voltages and frequencies, the IC design conditions of the given chip under test in the experiment all pass the test. The whole test process is realized by skillfully building a chip test system and comparing the machine simulation results. The inefficient steps are reused, and are not affected by the process platform, greatly improving the efficiency. And overcome the problem that part of the functional test cannot cover the possible defects.

[0075] In addition, the chip test method provided in the embodiment of the present application is applied to the above chip test system, and the test method comprises the following steps:

[0076] connecting the input terminals of the same attribute of each non-sequential unit in the chip under test in parallel to the output terminals of the corresponding attribute of the test vector output module;

[0077] connecting the input terminals of the same attribute of each sequential unit in the chip under test in parallel to the output terminals of the corresponding attribute of the test vector output module, and ensuring that the output terminals of the test vector output module connected by different input terminals of a single unit under test are different;

[0078] connecting the input terminals of the selection output circuit to the output terminals of each non-sequential unit and the output terminals of each sequential unit;

[0079] connecting a controller to the control terminals of the test vector output module and the control terminals of the selection output circuit;

[0080] After the circuit is connected according to the above operation steps, the controller controls the test vector output module to output test vectors according to a preset rule to configure the test vectors required for full function test of the combination logic function of the non-sequential unit and the sequential logic function of the sequential unit in the chip under test, so as to test each unit under test in the chip under test in turn; and the selection output circuit outputs the function test result of the single unit under test acted on by the current test vector. The preset rule is a rule for ensuring that the test vector output module outputs test vectors required for full function test of each unit under test in the chip under test, and the unit under test is the sequential unit or the non-sequential unit in the chip under test. The specific implementation of the full function test process by the controller can be referred to the description in the above chip test system embodiment, which will not be described here.

[0081] In one embodiment, the chip test method further comprises:

[0082] connecting the output terminals of the emulator and the selection output circuit to the controller; wherein the emulator can receive and run a design file corresponding to the chip under test; the emulator can also receive the test vectors provided by the test vector output module and perform test verification using the test vectors to obtain simulation results;

[0083] using the controller to obtain the simulation results, and comparing the simulation results with the function test results of the same unit under test under the same test vectors, and when the verification results are consistent, determining that the function test of the unit under test is qualified, and controlling the test vector output module to provide the next test vector to the chip under test and the emulator according to the preset rule.

[0084] In one embodiment, the output terminals of different attributes of the test vector output module include: a clock output terminal, a data output terminal, and a reset output terminal;

[0085] connecting input terminals of the same attribute of each non-timing unit in the chip under test in parallel to an output terminal of the corresponding attribute of the test vector output module; and connecting input terminals of the same attribute of each timing unit in the chip under test in parallel to an output terminal of the corresponding attribute of the test vector output module comprises:

[0086] connecting the clock output terminal to a first clock input terminal of each of the timing units;

[0087] connecting the data output terminal to a data input terminal of each of the timing units and a data input terminal of each of the non-timing units, respectively;

[0088] connecting the reset output terminal to a reset input terminal of each of the timing units;

[0089] providing test vectors for each of the units under test in the chip under test by using the connection relationship between the clock output terminal, the data output terminal, the reset output terminal and each of the units under test in the chip under test.

[0090] In addition, the chip test method provided by the embodiment of the application can further include corresponding steps of electrically connecting other modules in the chip test system to their connection objects to realize corresponding functions, which will not be described herein.

[0091] The controller can be a terminal such as a computer or a server, or a single-chip microcomputer, a microcontroller, an embedded control panel or the like.

[0092] In one embodiment, a chip test control method is also provided, comprising:

[0093] controlling the test vector output module to output the test vectors according to a preset rule;

[0094] controlling the selection output circuit to output the functional test result of the single unit under test on which the current test vector acts; the unit under test is the same as in the above embodiment;

[0095] the preset rule is a rule for ensuring that the test vector output module outputs test vectors required for full functional test of the combination logic function of the non-timing units and the timing logic function of the timing units in the chip under test;

[0096] The test vector output module includes a plurality of output terminals of different attributes, and the output terminals of different attributes of the test vector output module are respectively used to match the input terminals of each non-timing unit and the input terminals of each timing unit in the chip under test, so as to configure test vectors required for full functional test of the combination logic function of the non-timing units and the timing logic function of the timing units in the chip under test, and the output terminals of the test vector output module connected to different input terminals of a single unit under test are different;

[0097] A selection output circuit has inputs connected to outputs of the non-timed units and outputs of the timed units.

[0098] In one embodiment, the chip test control method further comprises:

[0099] The simulation result is obtained and compared with a functional test result of the same unit under the same test vector. If the verification result is consistent, it is determined that the functional test of the unit under test is qualified, and the test vector output module is controlled to provide a next test vector to the chip under test and the simulator according to a preset rule.

[0100] The simulator receives and runs a design file of the chip under test. The simulator receives the test vector provided by the test vector output module and performs test verification using the test vector to obtain a simulation result.

[0101] In one embodiment, the step of controlling the test vector output module to output the test vector according to the preset rule comprises:

[0102] The clock output end of the test vector output module is controlled to output a clock signal, the data output end is controlled to output a data signal, and the reset output end is controlled to output a reset signal.

[0103] In one embodiment, the chip test control method further comprises:

[0104] The number of output signals of the data selector is controlled according to the number of output signal lines of a single unit under test acted on by the current test vector.

[0105] In one embodiment, the chip test control method further comprises:

[0106] The clock signal output by the clock output end of the test vector output module and the reset signal output by the reset output end are controlled to be synchronized with the action of changing the test vector and outputting the functional test result by the selection output circuit.

[0107] The clock input end of the clock synchronization module is connected to the clock output end, the reset input end of the clock synchronization module is connected to the reset output end, and the signal input end of the clock synchronization module is further connected to the output end of each non-timed unit.

[0108] In one embodiment, the chip test control method further comprises:

[0109] The number of binary bits in the test vector is updated according to the number of input pins of the unit with the most input pins in the chip under test, so that the number of bits is greater than or equal to the number of input pins. For example, the number of bits can be equal to the number of input pins.

[0110] In one embodiment, the chip test control method further comprises:

[0111] configuring preset rules.

[0112] In one embodiment, the chip test control method further comprises:

[0113] According to the name of the input library, the test vector is updated. The test vector is updated for the pin conditions of the units in different libraries, so as to realize the test requirements of the units in different libraries of different manufacturers.

[0114] For implementation of the above chip test control method, refer to the description in the above chip test system and chip test method embodiments, which will not be repeated here.

[0115] In one embodiment, a chip test control device is also provided, comprising:

[0116] The test vector output control module is configured to control the test vector output module to output the test vector according to preset rules.

[0117] The selection output module is configured to control the selection output circuit to output the functional test result of the unit on which the current test vector acts.

[0118] The preset rules are rules for ensuring that the test vector output module outputs the test vector required for full functional test of each unit under test in the chip under test.

[0119] The test vector output module comprises a plurality of output terminals with different attributes, and the output terminals with different attributes of the test vector output module are respectively configured to match the input terminals of each non-timed unit and the input terminals of each timed unit in the chip under test, so as to configure the test vector required for full functional test of the combination logic function of the non-timed unit and the timing logic function of the timed unit in the chip under test. The output terminals of the test vector output module connected to different input terminals of a single unit are different.

[0120] The selection output circuit comprises an input terminal configured to be connected to the output terminal of each non-timed unit and the output terminal of each timed unit.

[0121] In one embodiment, the chip test control device further comprises:

[0122] The simulation result acquisition module is configured to acquire the simulation result, compare the simulation result with the functional test result of the same unit under the same test vector, and if the verification results are consistent, determine that the functional test of the unit under test is qualified, and control the test vector output module to provide the next test vector to the chip under test and the simulator according to preset rules.

[0123] The simulator receives and runs a design file corresponding to the chip to be tested; the simulator receives the test vector provided by the test vector output module and performs test verification using the test vector to obtain a simulation result.

[0124] In one embodiment, the test vector output control module comprises:

[0125] A multi-attribute signal output module is configured to control the test vector output module to output a clock signal from a clock output end, output a data signal from a data output end, and output a reset signal from a reset output end.

[0126] In one embodiment, the chip test control device further comprises:

[0127] A data selector driving module is configured to control the same number of data selector output signals according to the output signal paths of a single unit under test acted on by a current test vector.

[0128] In one embodiment, the chip test control device further comprises:

[0129] A synchronization control module is configured to control the clock signal output by the clock output end of the test vector output module and the reset signal output by the reset output end, so that the test vector changes and the action of outputting a functional test result by the selection output circuit are synchronized.

[0130] The clock input end of the clock synchronization module is connected with the clock output end, the reset input end of the clock synchronization module is connected with the reset output end, and the signal input end of the clock synchronization module is further configured to be connected with the output ends of the non-timed units.

[0131] In one embodiment, the chip test control device further comprises:

[0132] A test vector updating module is configured to update the number of binary bits in the test vector according to the number of input pins of a unit with the most input pins in the chip to be tested, so that the number of bits is greater than or equal to the number of input pins. For example, the number of bits can be equal to the number of input pins.

[0133] In one embodiment, the chip test control device further comprises:

[0134] A preset rule configuration module is configured to configure a preset rule.

[0135] As to the specific limitation of the chip test control device, as the chip test control method, it can be referred to the limitation of the chip test system and the chip test method, which will not be repeated here. Each module in the chip test control device can be realized by software, hardware and combination thereof. Each module can be embedded in the processor in the computer device in hardware form or independent of the processor, or stored in the memory in the computer device in software form, so that the processor can call and execute the operation corresponding to each module.

[0136] In one embodiment, a computer device, which can be a terminal, is provided, and its internal structure diagram can be shown as Figure 4 The computer device includes a processor, a memory, a communication interface, a display screen and an input device connected by a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The communication interface of the computer device is used to communicate with external terminals in wired or wireless mode. The wireless mode can be achieved by WIFI, operator network, NFC (near field communication) or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc. The user can configure the test vectors in the chip test system and update the preset rules through the input device to match the full function test requirements of each unit under test in the updated integrated circuit unit library.

[0137] Those skilled in the art can understand that Figure 4 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0138] In one embodiment, a computer device is provided, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the following steps:

[0139] controlling the test vector output module to output the test vector according to the preset rule;

[0140] controlling the selection output circuit to output the function test result of the single unit under test acted by the current test vector;

[0141] The preset rule is a rule for ensuring that the test vector output module outputs test vectors required for full function test of each unit under test in the chip under test;

[0142] The test vector output module includes a plurality of output terminals with different attributes, and the output terminals with different attributes of the test vector output module are respectively used to match the input terminals of each non-timed unit and the input terminals of each timed unit in the chip under test, so as to configure test vectors required for full function test of the combinational logic function of the non-timed unit and the sequential logic function of the timed unit in the chip under test. The output terminals of the test vector output module connected to different input terminals of a single unit under test are different. The unit under test is a non-timed unit or a timed unit.

[0143] The selection output circuit has input terminals respectively connected to the output terminals of each non-timed unit and the output terminals of each timed unit.

[0144] In one embodiment, the processor, when executing the computer program, further implements the following steps:

[0145] The simulation result is obtained, and the simulation result is compared with the function test result of the same unit under test under the same test vector. If the verification results are consistent, it is determined that the function test of the unit under test is qualified, and the test vector output module is controlled to provide the next test vector to the chip under test and the simulator according to the preset rule;

[0146] The simulator receives and runs the design file corresponding to the chip under test. The simulator receives the test vector provided by the test vector output module, and obtains a simulation result by using the test vector for test verification.

[0147] In one embodiment, the processor, when executing the computer program, further implements the following steps:

[0148] The clock output terminal of the test vector output module is controlled to output a clock signal, the data output terminal is controlled to output a data signal, and the reset output terminal is controlled to output a reset signal.

[0149] In one embodiment, the processor, when executing the computer program, further implements the following steps:

[0150] The number of output signals of the data selector is controlled according to the number of output signal paths of the single unit under test acted on by the current test vector.

[0151] In one embodiment, the processor, when executing the computer program, further implements the following steps:

[0152] Synchronize the clock signal outputted by the clock output end of the test vector output module and the reset signal outputted by the reset output end, so that the test vector changes and the action of outputting the function test result of the selection output circuit are synchronized.

[0153] The clock input end of the clock synchronization module is connected with the clock output end, the reset input end of the clock synchronization module is connected with the reset output end, and the signal input end of the clock synchronization module is further used for connecting the output ends of the non-timed units.

[0154] In one embodiment, the processor, when executing the computer program, further implements the following steps:

[0155] The number of binary bits in the test vector is updated according to the number of input pins of the unit with the most input pins in the chip to be tested, so that the number of bits is greater than or equal to the number of input pins. For example, the number of bits can be equal to the number of input pins.

[0156] In one embodiment, the processor, when executing the computer program, further implements the following steps:

[0157] Configure a preset rule.

[0158] In one embodiment, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program. The computer program is executed by a processor to implement the following steps:

[0159] Control the test vector output module to output the test vector according to the preset rule;

[0160] Control the selection output circuit to output the function test result of a single unit to be tested under the action of the current test vector;

[0161] The preset rule is a rule for ensuring that the test vector output module outputs the test vector required for full function test of the combination logic function of the non-timed unit and the timing logic function of the timed unit in the chip to be tested;

[0162] The test vector output module includes a plurality of output ends with different attributes, and the output ends with different attributes of the test vector output module are respectively used for matching and connecting the input ends of the non-timed units and the input ends of the timed units in the chip to be tested, so as to configure the test vector required for full function test of the combination logic function of the non-timed unit and the timing logic function of the timed unit in the chip to be tested. The output ends of the test vector output module connected by different input ends of a single unit are different.

[0163] The selection output circuit includes an input end connected with the output end of each non-timed unit and the output end of each timed unit.

[0164] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, storage, database or other medium used in each embodiment provided by the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0165] In the description of the present specification, the description of the terms "in one embodiment", "in some embodiments", "in an embodiment" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example.

[0166] Each technical feature of the above-mentioned embodiments can be combined arbitrarily, and in order to make the description simple, each technical feature in the above-mentioned embodiments is not described all possible combinations, however, as long as the combination of these technical features does not exist contradictory, it should be considered as the scope of the present application.

[0167] The above-mentioned embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A chip testing system, characterized by, The application relates to a test vector output module, a selection output circuit and a controller. The test vector output module comprises a plurality of different attribute outputs, and the different attribute outputs of the test vector output module are respectively used for matching the input ends of non-timing units and the input ends of timing units in a chip to be tested, so as to configure the test vectors required by full-function test of the combination logic function of the non-timing units and the timing logic function of the timing units in the chip to be tested; the outputs of the test vector output module connected to different input ends of a single unit under test are different; the unit under test is the timing unit or the non-timing unit in the chip to be tested; wherein the input ends of the same attribute of the non-timing units in the chip to be tested are connected in parallel to the outputs of the corresponding attribute of the test vector output module, and the input ends of the same attribute of the timing units in the chip to be tested are connected in parallel to the outputs of the corresponding attribute of the test vector output module. The selection output circuit is connected to the output ends of the non-timing units and the output ends of the timing units. The controller is connected to the control ends of the test vector output module and the control ends of the selection output circuit, and is used for controlling the test vector output module to output the test vectors according to a preset rule, so as to test each unit under test in the chip to be tested in sequence; and is used for controlling the selection output circuit to output the function test result of a single unit under test acted by a current test vector. The preset rule is a rule for ensuring that the test vector output module outputs the test vectors required by full-function test of each unit under test in the chip to be tested.

2. The chip testing system of claim 1, wherein, The application further comprises an emulator. The emulator receives and runs a design file of the chip to be tested; the emulator receives the test vectors provided by the test vector output module, and uses the test vectors to obtain a simulation result through test verification. The controller is connected to the outputs of the emulator and the selection output circuit, is used for obtaining the simulation result, and compares the simulation result with the function test result of the same unit under test under the same test vector; if the verification result is consistent, it is determined that the function test of the unit under test is qualified, and the test vector output module is controlled to provide the next test vector to the chip to be tested and the emulator according to the preset rule.

3. The chip testing system according to claim 1 or 2, characterized by, The different attribute outputs of the test vector output module comprise a clock output end, a data output end and a reset output end. The clock output end is used for connecting the first clock input ends of the timing units. The data output end is respectively used for connecting the data input ends of the timing units and the data input ends of the non-timing units. The reset output end is used for connecting the reset input ends of the timing units. The clock output end, the data output end and the reset output end are connected to the units under test in the chip to be tested, so as to provide the test vectors for the units under test in the chip to be tested.

4. The chip testing system of claim 3, wherein The clock output end is used to connect the first clock input end of each timing unit through a bus; the data output end is used to connect the data input end of each timing unit and the data input end of each non-timing unit through a bus; and the reset output end is used to connect the reset input end of each timing unit through a bus.

5. The chip testing system of claim 3, wherein Further comprising: an inverter, an input end of the inverter being connected to the clock output end, and an output end of the inverter being used to connect the second clock input end of each timing unit; the clock signal provided by the clock output end is opposite to the clock signal provided by the output end of the inverter.

6. The chip testing system according to claim 1 or 4 or 5, wherein The selection output circuit comprises at least two data selectors. The first input end of each data selector is used to connect the output end of each timing unit; The second input end of each data selector is used to connect the output end of each non-timing unit; The control end of each data selector is used to connect the controller; The controller controls the same number of data selector output signals according to the output signal path number of a single unit under test acted on by a current test vector.

7. The system of claim 3, wherein, Further comprising: a clock synchronization module, a clock input end of the clock synchronization module being connected to the clock output end, a reset input end of the clock synchronization module being connected to the reset output end, and a signal input end of the clock synchronization module being used to connect the output end of each non-timing unit; The controller controls the clock signal output by the clock output end of the test vector output module and the reset signal output by the reset output end, so that the test vector change and the action of outputting the functional test result of the selection output circuit are synchronized.

8. The system of claim 1 or 2 or 4 or 5 or 7, wherein, The test vector is a binary vector, and the binary vector is composed of N-bit binary numbers, wherein N is greater than or equal to the number of input pins of the unit with the most input pins in the chip to be tested.

9. The chip testing system of claim 8, wherein, The preset rule is that only one binary number in the binary numbers in any two adjacent binary vectors is the opposite number, and the binary numbers of the remaining bits are all the same.

10. A method of testing a chip, characterized by, The method is applied to the chip test system of any one of claims 1-9, and the method comprises the following steps: Parallelly connecting the input ends of the same attribute of each non-timing unit in the chip to be tested to the output end of the corresponding attribute of the test vector output module; Parallelly connecting the input ends of the same attribute of each timing unit in the chip to be tested to the output end of the corresponding attribute of the test vector output module, and ensuring that the output ends of the test vector output module connected by different input ends of a single unit under test are different; Connecting the input end of the selection output circuit to the output end of each non-timing unit and the output end of each timing unit; Connecting the controller to the control end of the test vector output module and the control end of the selection output circuit; and The test vector output module is controlled by the controller to output test vectors according to preset rules to configure test vectors required for full function test of combination logic function of non-timing unit and timing logic function of timing unit in the chip to be tested, so as to test each of the units to be tested in the chip to be tested in sequence; and the selection output circuit is controlled to output function test results of a single unit to be tested on which the current test vector acts. The preset rules are rules for ensuring that the test vector output module outputs test vectors required for full function test of each unit to be tested in the chip to be tested; and the unit to be tested is the timing unit or the non-timing unit in the chip to be tested.

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