Error Correction Capability-Based Routing Assignment

Abstract

The present application relates to routing assignments based on error correction capabilities. The systems and methods described herein relate to bidirectional data path DQ symbol mappings generated based on error correction operations. A device may include a sub-wordline driver and a bidirectional data path DQ coupled between the sub-wordline driver and an input / output I / O interface circuit system based on an assignment indicated by the DQ symbol mapping. The assignment may be generated based on an error correction operation performed on data of a memory bank. Specifically, the DQ symbol mapping may be generated to avoid some situations that may render one or more data errors uncorrectable when they occur. These systems and methods may reduce the likelihood that data errors associated with the DQ are uncorrectable.

Description

Technical Field

[0001] The present disclosure relates generally to memory device error correction, and more particularly to systems and methods for reducing the likelihood of uncorrectable memory errors occurring in a memory device. Background Art

[0002] This section is intended to introduce the reader to various aspects of the technology that may be related to various aspects of the technology described and / or claimed below. It is believed that this discussion helps to provide the reader with background information to promote a better understanding of various aspects of the present disclosure. Therefore, it should be understood that these statements are read in this light, and not as an admission of the prior art.

[0003] In general, a computing system may include devices that communicate information via electrical signals during operation. For example, a computing system may include a processor that is communicatively coupled to a memory device, such as a dynamic random access memory (DRAM) device disposed on a dual in-line memory module (DIMM). In this manner, the processor may communicate with the memory device to, for example, retrieve executable instructions, retrieve data to be processed by the processor, and / or store data output from the processor.

[0004] When data is exchanged between a memory and a processor, the data output from the memory may contain one or more errors. Errors may be caused by memory defects. Sometimes, one memory defect may cause multiple errors. As memory density increases and feature size decreases, memory defects may become more common. In addition, as the scale of relatively large-scale computing systems using a large number of high-density memories increases, the chance of memory defects may also increase. For example, a larger amount of memory operating at the same time may increase the chance of memory defects. In order to correct data errors, such as errors from memory defects, the processor may perform error correction operations. Sometimes, errors may not be correctable by the processor, such as when an error occurs that cannot be corrected by an error correction operation. Systems and methods that reduce the likelihood of uncorrectable errors occurring may be beneficial. Summary of the invention

[0005] In one aspect, the present application relates to a device comprising: a memory storage body comprising multiple planes; a storage body control circuit system comprising multiple sub-word line drivers, wherein each of the sub-word line drivers is associated with a subset of the multiple planes; and a data path circuit system comprising multiple bidirectional data paths, wherein the data path circuit system is configured to couple the storage body control circuit system to an input / output (I / O) interface circuit system based at least in part on the assignment of each of the multiple bidirectional data paths to one or more sub-word line drivers of the multiple sub-word line drivers based at least in part on error correction code (ECC) operations.

[0006] In another aspect, the present application relates to a method comprising: receiving an indication of a non-correction condition associated with an error correction code (ECC) stored in a memory bank, wherein the ECC is configured to correct one or more data errors of output data, and wherein the one or more data errors are not correctable by the ECC when the non-correction condition is met; generating a data path assignment based at least in part on the indication of the non-correction condition; generating a control signal based on the data path assignment; and transmitting the control signal to a data path circuit system, wherein the data path circuit system is configured to associate a corresponding bidirectional data path with at least two corresponding sub-word line drivers in response to the control signal.

[0007] In another aspect, the present application relates to a device comprising: a memory body control circuit system, which includes a plurality of sub-word line drivers, each of which is associated with a memory body; and a plurality of bidirectional data paths, which are configured to be coupled between the plurality of sub-word line drivers and an input / output (I / O) interface circuit system based at least in part on an indication of the assignment of each of the plurality of bidirectional data paths to one or more of the plurality of sub-word line drivers, wherein the assignment is configured to be generated based at least in part on an error correction operation performed on data of the memory body. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various aspects of the present disclosure may be better understood after reading the following detailed description and referring to the accompanying drawings, in which:

[0009] Figure 1 is a block diagram of a memory device according to an embodiment;

[0010] Figure 2 According to the embodiment Figure 1 A diagrammatic representation of a first example memory bank;

[0011] Figure 3 According to the embodiment Figure 1 A diagrammatic representation of a second example memory bank;

[0012] Figure 4 According to the embodiment Figure 1 A diagrammatic representation of a third example memory bank of;

[0013] Figure 5 According to the embodiment Figure 1 A diagrammatic representation of a fourth example memory bank of;

[0014] Figure 6 According to the embodiment Figure 1A diagrammatic representation of a fifth example memory bank;

[0015] Figure 7 For generating and using a Figure 1 A flow chart of a method for data path (DQ) routing control signals of a data path circuit system of the present invention;

[0016] Figure 8 For the embodiment corresponding to Figure 2 a circuit diagram of the symbolically mapped data routing circuitry;

[0017] Fig. 9 For the embodiment corresponding to Figure 3 a circuit diagram of the symbolically mapped data routing circuitry;

[0018] Fig.10 For the embodiment corresponding to Figure 4 a circuit diagram of the symbolically mapped data routing circuitry; and

[0019] Fig.11 For the embodiment corresponding to Figure 5 A circuit diagram of the symbol-mapped data routing circuitry. DETAILED DESCRIPTION

[0020] One or more specific embodiments will be described below. In order to provide a brief description of these embodiments, not all features of the actual implementation will be described in this specification. It should be understood that in the development process of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions are made to achieve the specific goals of the developer, such as complying with system-related and enterprise-related constraints that may vary between various implementations. In addition, it should be understood that such development efforts may be complex and time-consuming, but will be a routine of design, construction, and manufacture undertaken by a person of ordinary skill in the art who benefits from this disclosure.

[0021] When introducing elements of various embodiments of the present disclosure, the articles "a", "an", and "the" are intended to mean that there are one or more of the elements. The terms "comprising", "including", and "having" are intended to be inclusive and mean that there may be additional elements in addition to the listed elements. In addition, it should be understood that reference to "one embodiment" or "an embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that are further incorporated into the recited features.

[0022] In general, a computing system may include devices that communicate information via electrical signals when performing operations. For example, an electronic device in a computing system may include a processor communicatively coupled to a memory device. In this manner, the processor may communicate with the memory device to retrieve executable instructions, retrieve data to be processed by the processor, store data output from the processor, etc.

[0023] Memory may contain or generate one or more memory defects. Defects may be generated by degradation or performance over time, by manufacturing, etc. For example, as memory density increases and feature size decreases, memory defects may become more prevalent. For systems that use concurrently operating memory, memory defects may become increasingly a problem because concurrent operations may increase the likelihood of performance-based memory defects. For example, large-scale computing systems, distributed computing systems, remote servers, etc. may use large amounts of high-density memory and therefore have a greater likelihood of computing or service provision operations being affected by memory defects.

[0024] Error correction codes (ECC) can be used to correct data errors. Many correction algorithms organize data into symbols. Each symbol may include one or more bits and when an error occurs in one or more bits within a single symbol, the algorithm can correct the entire symbol. Due to limitations in the correction algorithm, some data errors may not be correctable by ECC when one or more non-correction situations occur. For example, a correction situation may specify that data errors occurring in multiple symbols must belong to a specific grouping of symbols to be correctable. For example, if there are 8 symbols, the correction situation may specify that a pair of symbols in which an error occurs must be (symbol A and B) or (symbol C and D) or (symbol E and F) or (symbol G and H). Due to these types of specifications, systems and methods that reduce the possibility of uncorrectable error situations occurring may be beneficial.

[0025] Dynamic random access memory (DRAM) can organize its data by data path (DQ). For example, in double date rate 4 (DDR4) DRAM, each DQ can produce 8 bits of data on each read access. For this example, each DQ can be equivalent to a symbol. DQ0 corresponds to symbol A, DQ1 corresponds to symbol B, and so on. It should be understood that there are many ways to organize the data into symbols and this assignment is an example. Some symbols can include one or more DQs. And, depending on the calibration scheme, the number of bits in each symbol definition can vary and therefore can include more or less than 8 bits.

[0026] The present disclosure relates to systems and methods for preventing or reducing the likelihood of uncorrectable data errors. A DQ symbol map may indicate an assignment of each data path symbol to one or more portions of a memory, such as an assignment that associates one or more data path symbols with one or more sub-word line drivers (SWL drivers). In order to reduce the likelihood of uncorrectable data errors, a DQ symbol map may be generated to avoid or reduce the occurrence of uncorrected conditions. Uncorrected conditions may be avoided, at least in part, by using isolation systems and methods. These isolation systems and methods may include isolation based on bank activation, isolation based on column selection, isolation based on row selection, isolation based on data placement, or a combination thereof.

[0027] The DQ symbol map may be hard-programmed into the memory device during manufacturing. At times, the communication and / or control circuitry of the memory device may reference the DQ symbol map when transferring data to and from the memory. When referencing the DQ symbol map generated based on the non-correction condition, the communication and / or control circuitry may write data to the memory in consideration of the non-correction condition and its avoidance.

[0028] In some embodiments, the memory device may include switch logic circuitry. The switch logic circuitry may couple the memory banks to the input / output circuitry and may include switch logic, multiplexing circuitry, or other suitable programmable routing to program the assignments indicated by the DQ symbol mapping. In some cases, the switch logic circuitry configures the switch logic, multiplexing circuitry, or other suitable programmable routing in response to system operation, such as in response to which memory bank is activated, to program different data paths to the memory banks.

[0029] Systems and methods for handling data based on DQ symbol mappings generated taking into account the non-correction conditions described herein can avoid or reduce the likelihood of uncorrectable data errors of corresponding memory banks occurring. When fewer uncorrectable errors occur, memory bank operations can become more reliable. Thus, memory device operations can be improved overall based on how the reliability of memory banks can be improved when using the systems and methods described herein.

[0030] Now turning to the figures, Figure 1 is a simplified block diagram illustrating certain features of memory device 10. Specifically, Figure 1 The block diagram of FIG. 1 is a functional block diagram illustrating certain functionality of the memory device 10. According to one embodiment, the memory device 10 may be a fifth generation double data rate synchronous dynamic random access memory (DDR5 SDRAM) device. Various features of the DDR5 SDRAM may permit reduced power consumption, increased bandwidth, and increased storage capacity compared to previous generations of DDR SDRAM.

[0031] The memory device 10 may include a number of memory banks 12. The memory banks 12 may be, for example, DDR5 SDRAM memory banks. The memory banks 12 may be provided on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). Each DIMM may include a number of SDRAM memory chips (e.g., x8 or x16 memory chips), as will be appreciated. Each SDRAM memory chip may include one or more memory banks 12. The memory device 10 represents a portion of a single memory chip (e.g., an SDRAM chip) having a number of memory banks 12. For DDR5, the memory banks 12 may be further arranged to form bank groups. For example, for an 8-gigabit (Gb) DDR5 SDRAM, the memory chip may include 16 memory banks 12, arranged into 8 bank groups, each bank group including 2 memory banks. For example, for 16Gb DDR5 SDRAM, the memory chip may include 32 memory banks 12, arranged into 8 memory bank groups, each memory bank group including 4 memory banks. Various other configurations, organizations, and sizes of memory banks 12 on the memory device 10 may be utilized depending on the application and design of the overall system.

[0032] The memory device 10 may include a command interface 14 and an input / output (I / O) interface 16 configured to exchange (e.g., receive and transmit) signals with an external device. The command interface 14 is configured to provide a number of signals (e.g., signal 8) from an external device (not depicted), such as a processor or controller. The processor or controller may provide various signals 8 to the memory device 10 to facilitate the transmission and reception of data to be written to or read from the memory device 10.

[0033] As will be appreciated, the command interface 14 may include several circuits, such as a clock input circuit 18 and a command address input circuit 20, such as to permit proper handling of the signal 8. The command interface 14 may receive one or more clock signals from an external device. In general, double data rate (DDR) memories utilize a differential pair of system clock signals, referred to as a true clock signal (Clk_t) and a complementary clock signal (Clk_c). The positive clock edge of DDR refers to the point where the rising true clock signal (Clk_t) crosses the falling complementary clock signal (Clk_c), while the negative clock edge indicates the transition of the falling true clock signal (Clk_t) and the rise of the complementary clock signal (Clk_c). Commands (e.g., read commands, write commands, refresh commands) typically enter on the positive edge of the clock signal, and data is transmitted or received on both the positive and negative clock edges.

[0034] The clock input circuit 18 receives the true clock signal (Clk_t) and the complementary clock signal (Clk_c) and generates an internal clock signal (CLK). The internal clock signal (CLK) is supplied to an internal clock generator 30, such as a delay locked loop (DLL) circuit. The internal clock generator 30 generates a phase-controlled internal locked clock signal (LCLK) based on the received internal clock signal (CLK). The phase-controlled internal locked clock signal (LCLK) is supplied to, for example, the I / O interface 16 and is used as a timing signal for determining the output timing of read data.

[0035] The internal clock signal (CLK) may also be provided to various other components within the memory device 10 and may be used to generate various additional internal clock signals. For example, the internal clock signal (CLK) may be provided to a command decoder 32. The command decoder 32 may receive the command signal from the command bus 34 and may decode the command signal to provide various internal commands. For example, the command decoder 32 may provide the command signal to the internal clock generator 30 via the bus 36 to coordinate the generation of a phase-controlled internal locked clock signal (LCLK). The phase-controlled internal locked clock signal (LCLK) may be used to clock data, such as through the I / O interface 16.

[0036] The command decoder 32 may decode commands such as read commands, write commands, mode register set commands, activate commands, and the like, and provide access to a particular memory bank 12 corresponding to the command via a bus path 40. As will be appreciated, the memory device 10 may include various other decoders, such as row decoders and column decoders, to facilitate access to the memory banks 12. In one embodiment, each memory bank 12 includes or is associated with a bank control block 22 that provides the necessary decoding (e.g., row decoders and column decoders) and other operations, such as timing control and data control, to facilitate execution of commands to and from the memory bank 12. The memory banks 12 and bank control blocks 22 may be collectively referred to as a memory array.

[0037] The memory device 10 performs operations such as read commands and write commands based on command / address signals received from an external device such as a processor. In one embodiment, the command / address bus may be a 14-bit bus (CA<13:0>) to accommodate command / address signals. The command / address signals are clocked to the command interface 14 using clock signals (Clk_t and Clk_c). The command interface may include a command address input circuit 20, which is configured to receive and transmit commands to provide access to the memory storage body 12 through, for example, a command decoder 32. In addition, the command interface 14 may receive a chip select signal (CS_n). The CS_n signal causes the memory device 10 to process commands on the incoming CA<13:0> bus. Access to a specific memory storage body 12 within the memory device 10 is encoded on the CA<13:0> bus by a command.

[0038] In addition, the command interface 14 may be configured to receive several other command signals. For example, a command / address on-die termination (CA_ODT) signal may be provided to facilitate proper impedance matching within the memory device 10. For example, a reset command (RESET_n) may be used during power-up to reset the command interface 14, the status register, the state machine, etc. The command interface 14 may also receive a command / address inversion (CAI) signal, which may be provided to invert the state of the command / address signal (CA<13:0>) on the command / address bus, for example, depending on the command / address routing of the specific memory device 10. A mirror (MIR) signal may also be provided to facilitate mirroring functionality. Based on the configuration of multiple memory devices in a specific application, the MIR signal may be used to multiplex signals so that they may be exchanged for implementing a specific routing of signals to the memory device 10. Various signals for facilitating testing of the memory device 10, such as a test enable (TEN) signal, may also be provided. For example, the TEN signal may be used to place the memory device 10 in a test mode for connectivity testing.

[0039] The command interface 14 may also be used to provide an alert signal (ALERT_n) to a system processor or controller for certain errors that may be detected. For example, an alert signal (ALERT_n) may be transmitted from the memory device 10 if a cyclic redundancy check (CRC) error is detected. Other alert signals may also be generated. In addition, the bus and pins used to transmit the alert signal (ALERT_n) from the memory device 10 may be used as input pins during certain operations, such as the connectivity test mode performed using the TEN signal as described above.

[0040] Utilizing the command and timing signals discussed above, data may be sent to and from the memory device 10 by transmitting and receiving data signals 44 via the I / O interface 16. More specifically, data may be sent to or retrieved from the memory bank 12 via a data path circuitry 46 comprising a plurality of bidirectional data buses. Data I / O signals, commonly referred to as DQ signals, are typically transmitted and received in one or more bidirectional data buses. For certain memory devices, such as DDR5 SDRAM memory devices, the I / O signals may be divided into upper and lower bytes. For example, for a x16 memory device, the I / O signals may be divided into upper and lower I / O signals (e.g., DQ<15:8> and DQ<7:0>), such as corresponding to the upper and lower bytes of the data signals.

[0041] To allow for higher data rates within the memory device 10, certain memory devices, such as DDR memory devices, may utilize a data strobe signal, commonly referred to as a DQS signal. The DQS signal is driven by an external processor or controller that sends data (e.g., for a write command) or by the memory device 10 (e.g., for a read command). For a read command, the DQS signal is actually an additional data output (DQ) signal with a predetermined pattern. For a write command, the DQS signal is used as a clock signal to capture the corresponding input data. Like the clock signal (Clk_t and Clk_c), a data strobe (DQS) signal may be provided as a differential pair (DQS_t and DQS_c) of data strobe signals to provide differential pair signaling during read and write. For certain memory devices, such as DDR5 SDRAM memory devices, the differential pair of DQS signals can be divided into upper data select signals and lower data select signals (e.g., UDQS_t and UDQS_c; LDQS_t and LDQS_c), which correspond to, for example, upper bytes and lower bytes of data sent to and from the memory device 10.

[0042] An impedance (ZQ) calibration signal may also be provided to the memory device 10 through the I / O interface 16. The ZQ calibration signal may be provided to a reference pin and may be used to tune the output driver and on-die termination (ODT) value by adjusting the pull-up and pull-down resistors of the memory device 10 over changes in process, voltage, and temperature (PVT) values. Because PVT characteristics may affect the ZQ resistor value, the ZQ calibration signal may be provided to the ZQ reference pin for adjusting the resistance to calibrate the input impedance to a known value. As will be appreciated, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. Such a resistor acts as a reference for adjusting the internal ODT and drive strength of the I / O pins.

[0043] In addition, a loopback signal (LOOPBACK) may be provided to the memory device 10 through the I / O interface 16. The loopback signal may be used during a test or debug phase to set the memory device 10 into a mode where the signal is looped back through the memory device 10 through the same pin. For example, the loopback signal may be used to set up the memory device 10 to test the data output of the memory device 10. The loopback may include both data and strobe, or may include a data pin to provide data and / or strobe. This is generally intended for monitoring data captured by the memory device 10 at the I / O interface 16.

[0044] Various other components such as power supply circuits (for receiving external VDD and VSS signals), mode registers (for defining various modes of programmable operation and configuration), read / write amplifiers (for amplifying signals during read / write operations), temperature sensors (for sensing the temperature of the memory device 10), etc. may also be incorporated into the memory device 10. Therefore, it should be understood that only the memory device 10 is provided. Figure 1 1 is a block diagram to highlight certain functional features of the memory device 10 to assist in the subsequent detailed description.

[0045] In some embodiments, the memory device 10 may be placed in a host device (physically integrated into or otherwise connected to the host device) or otherwise coupled to the host device. The host device may include any of a desktop computer, a laptop computer, a pager, a cellular phone, a personal organizer, a portable audio player, a control circuit, a camera, etc. The host device may also be a network node, such as a router, a server, or a client (e.g., one of the computers of the types previously described). The host device may be some other kind of electronic device, such as a copier, a scanner, a printer, a game console, a television, a set-top video distribution or recording system, a cable box, a personal digital media player, a factory automation system, an automotive computer system, a medical device, etc. The terms used to describe these various examples of the system, like many other terms used herein, may share some references and therefore should not be interpreted narrowly by means of the other items listed.

[0046] Thus, a host device may generally be a processor-based device that may include a processor, such as a microprocessor, that controls system functions and processing of requests in the host device. In addition, any host processor may include multiple processors that share system control. The host processor may be coupled directly or indirectly to additional system elements of the host device such that the host processor controls the operation of the host device by executing instructions that may be stored within the host device or external to the host device.

[0047] As discussed above, data may be written to and read from the memory device 10, for example, by a host device, whereby the memory device 10 acts as a volatile memory, such as a double data rate DRAM (e.g., DDR4 and DDR5 SDRAM). In some embodiments, the host device may also include a separate non-volatile memory, such as a read-only memory (ROM), PC-RAM, silicon-oxide-nitride-oxide-silicon (SONOS) memory, metal-oxide-nitride-oxide-silicon (MONOS) memory, polysilicon floating gate-based memory, and / or other types of flash memory of various architectures (e.g., NAND memory, NOR memory, etc.), as well as other types of memory devices (e.g., storage devices), such as a solid-state drive (SSD), a multimedia media card (MMC), a secure digital (SD) card, a flash memory (CF) card, or any other suitable device. In addition, it should be appreciated that the host device may include one or more external interfaces, such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Small Computer System Interface (SCSI), IEEE 1394 (Firewire), or any other suitable interface, and one or more input devices to permit a user to input data into the host device, such as by using buttons, switch elements, keyboards, light pens, styluses, mice, and / or voice recognition systems. The host device may also optionally include output devices such as a display coupled to the processor, and a network interface device such as a network interface card (NIC) for interfacing with a network such as the Internet. As will be appreciated, the host device may include many other components depending on the application of the host device.

[0048] With the foregoing in mind, the command decoder 32 can decode commands and control the movement of data into and out of the memory bank 12. In some cases, a DQ symbol map is generated and referenced to program the corresponding bidirectional data bus (DQ) of the data path circuit system 46. The command decoder 32 and / or the memory controller can program the configuration of the DQ symbol map to allocate different DQ symbols or different parts of the DQ symbols to one or more sub-word line (SWL) drivers, as will be discussed later. In some cases, the data path circuit system 46 also includes control logic 48 coupled between the I / O interface 16 and the DQ of the data path circuit system 46. The control logic 48 may include switch logic circuit system, control circuit system, etc. that operates in response to control signals. The control signal can be generated by the processing circuit system, command decoder, or other suitable signal generation circuit system of the control logic 48 to program one or more on-the-fly routing changes between the I / O interface 16 and the memory bank 12 to use different DQ symbol maps. The control logic 48 may include multiplexing circuitry, hard-programmed routing (eg, wires), etc. to route the DQ symbol mapping, such as Figures 2 to 6 Additionally or alternatively, the data path circuitry 46 may include multiple data paths that the control logic 48 may switch between based on the particular implementation of the memory banks 12 (e.g., DDR5 vs. DDR4). The data paths of the data path circuitry 46 may be programmed in response to control signals from the command decoder 32 corresponding to activation of one or more of the memory banks 12.

[0049] When accessing data of the memory bank 12, the circuit system of the memory bank control block 22 may misoperate. Data errors caused by misoperation can sometimes be corrected by ECC operation. However, misoperation of the memory bank control block 22 may cause data errors across multiple DQ symbols, which may make the data errors uncorrectable. For example, certain ECC operations may be able to correct data errors across the same DQ symbol, but cannot correct errors across multiple DQ symbols. Therefore, the shared circuit system of the memory bank control block 22 that writes data based on the DQ symbol configuration of the memory bank 12 to avoid the common cause of data errors that may eventually become data errors can improve the operation of the memory device by enabling more computing resources to be used to perform non-ECC operations to improve reliability, uptime and resource allocation. An example DQ symbol mapping is described herein, which represents a configuration adopted by the control logic 48 based on the rules followed by the example ECC operation to reduce the possibility of uncorrectable data errors occurring in response to memory errors.

[0050] To describe in detail, Figure 258 is a map of data lines (DQ) (e.g., DQ symbol mapping) in an embodiment of a DDR5 x4 DQ symbol mapping for a memory bank 12 illustrated in association with a sub-word line (SWL) 62 and a sub-word line driver (SWL driver) 64 of the memory bank 12 and the bank control block 22. The map 58 is used for illustrative purposes, but other embodiments may include other mappings and / or a different number of DQ symbols per bank. As illustrated, the memory bank 12A may correspond to column planes 60A1-60E (column planes 60A1, 60A2, 60A3, 60A4, 60B1, 60B2, 60B3, 60B4, 60C1, 60C2, 60C3, 60C4, 60D1, 60D2, 60D3, 60D4, 60E). Some embodiments may have a different number of column planes per memory bank 12. Column planes 60A1-60E may be associated with DQ symbols for respective column addresses and even / odd sense amplifiers. For example, column plane 60A (60A1, 60A2, 60A3, 60A4) corresponds to DQ3 (symbols M, N, O, and P), column plane 60B (60B1, 60B2, 60B3, 60B4) corresponds to DQ2 (symbols I, J, K, and L), column plane 60C (60C1, 60C2, 60C3, 60C4) corresponds to DQ1 (symbols E, F, G, and H), and column plane 60D (60D1, 60D2, 60D3, 60D4) corresponds to DQ0 (symbols A, B, C, and D). Column plane 60E corresponds to an on-die error control code (ECC). Each group of DQ symbols may correspond to two or more bytes of data, which correspond to even and odd sense amplifiers. A particular byte may be addressed using a combination of logic states of the first address signal (CA2), the second address signal (CA3), and the column select address signal C(n) (which is C10 in this example).

[0051] Data is written or read from the memory bank 12A by decoding a word line (WL) 66 that runs across the memory bank 12A in a direction perpendicular to the column plane 60. The WL 66 may be divided into sub-word lines (SWL) 62 that may correspond to SWL drivers 64. The corresponding SWL drivers 64 may control data transfer in and out of the corresponding column plane 60. For example, SWL 62A is activated by SWL driver 64A to access data stored in the column plane 60A. When the WL 66 is globally activated, the corresponding SWL drivers 64E, 64B, 64G, 64I, 64D may be activated to output data in parallel from some of the column planes 60. When the SWL driver 64 malfunctions, each of the corresponding column planes 60 outputs data with errors. For example, if SWL driver 64D malfunctions when activated via WL 66, then the data read out of column plane 60D will contain data errors in symbols A, B, C, and D, but will remain correctable because the error spans one DQ and the state of column select address signal C10 selects between symbols A and B or C and D as output, where the symbol correction rules associated with the ECC of column plane 60E can be defined as correctable.

[0052] The control logic 48 may isolate the column planes 60 of different DQ symbols by configuring the data path circuitry 46 to route the data of the different DQ symbols into the column planes 60 of different SWL drivers 64. Thus, data corresponding to the same DQ is written to the column plane 60 of the same SWL driver 64. This is an example of isolation based on data arrangement, because the isolation of the DQ symbols from each other is done based on the data arrangement followed when writing the DQ data to the column planes 60.

[0053] Even with data placement based isolation, some SWL drivers 64 may correspond to different DQ symbols, such as SWL driver 64C controlling column plane 60C1 corresponding to DQ1 (e.g., including symbols E, F, G, and H) and controlling column plane 60D4 corresponding to DQ0 (e.g., including symbols C and D). Another isolation operation - column selection based isolation may be used along with data placement based isolation to further prevent uncorrectable data errors from occurring. In practice, the column select decode signal (C10) may be used to address subsets of the column planes 60 based on different decoded addresses (e.g., C10=1 and C10=0 produce different subsets of the column planes 60). For x4 memory bank 12A, based on the C10 signal, data from column planes 60A4, 60A3, 60B4, 60B3, 60C4, 60C3, 60D4, and 60D3 may output data at different times compared to column planes 60A2, 60A1, 60B2, 60B1, 60C2, 60C1, 60D2, and 60D1. It should be noted that any suitable column select address C(n) may be used to create this isolation if different states of the signal are used between a pair of different adjacent column planes.

[0054] Control logic 48 may sometimes control memory banks 12 having row planes. For example, Figure 3 78 of DQ symbols in an embodiment of a DDR4 x4 1K activated DQ symbol mapping for a memory bank 12 illustrated in association with the SWL 62 and SWL driver 64 of the memory bank 12 and the bank control block 22. The mapping 78 is for illustrative purposes, but other embodiments may include other mappings and / or different numbers of DQ symbols per bank. As illustrated, the memory banks 12 may correspond to row planes 80A1-80E (row planes 80A1, 80A2, 80B1, 80B2, 80C1, 80C2, 80D1, 80D2, 80E) in different groups, and more or fewer row planes may be used in actual implementations. The row planes 80A1-80D2 are associated with different DQ symbols. For example, row plane 80A (80A1, 80A2) corresponds to DQ3 associated with symbols G and H, row plane 80B (80B1, 80B2) corresponds to DQ1 associated with symbols E and F, row plane 80C (80C1, 80C2) corresponds to DQ2 associated with symbols C and D, and row plane 80D (80D1, 80D2) corresponds to DQ0 associated with symbols A and B. Each pair of DQ symbols may correspond to two or more data bytes each including at least 4 bits. A global row decoder 82 may be shared across each of row planes 80A1-80D2. SWL drivers 64 may correspond to different WLs 66 (66A, 66B).

[0055] The control logic 48 may isolate the row planes 80 of different DQ symbols by configuring the data path circuitry 46 to route data of different DQ symbols into the row planes 80 of different SWL drivers 64. Thus, data corresponding to the same DQ is written to the row plane 80 of the same SWL driver 64. This may be another example of isolation based on data placement.

[0056] Even with data placement based isolation, some SWL drivers 64 may correspond to different DQ symbols, such as SWL driver 64F of WL 66A corresponding to both DQ1 symbol D and DQ2 symbol E. Without additional isolation, a single SWL driver 64 malfunctioning may fail the row plane 80 on each of its arms. For example, if both arms of SWL driver 64F malfunction, the data read out from both row planes 80B2 and 80C1 will contain data errors, and these data errors may be uncorrectable because the errors span two DQ symbols, violating the correction rules. The above applies to SWL drivers 64G, 64H.

[0057] Thus, row selection based isolation can be used together with data placement based isolation to further prevent uncorrectable data errors from occurring. The memory controller can time access the row plane 80 for adjacent DQs sharing the SWL driver 64 to structurally isolate the outputs from the DQ symbols via the address signal RA(n), such as RA16, to prevent some memory errors in one DQ symbol from crossing over to the second DQ symbol, where this crossing over breaks the example correction rule. Using two isolation operations, if the SWL driver 64E malfunctions, the data read out from the row plane 80D will contain correctable data errors because the error crosses over one DQ and includes symbols A and B. In practice, the row select decode signal (RA16) can address subsets of the row plane 80 based on different decoded addresses (e.g., RA16=1 and RA16=0 produce different subsets of the row plane 80). For x4 memory bank 12A, data from row planes 80A1, 80B1, 80C1, and 80D1 may be manipulated to output data at different times compared to row planes 80A2, 80B2, 80C2, and 80D2 via the state of RA16. Such row address segmentation (e.g., segmentation based on the state of row address symbols) may prevent uncorrectable errors from SWL driver 64F misoperation, which may otherwise cause errors to occur on symbol D and symbol E. Errors on both symbol D and symbol E may remain correctable when they occur because symbol D and symbol E are accessed at different times, thereby causing the associated errors to occur at different times based on different RA16 partitions.

[0058] With the above ideas, Figures 4 to 6Additional combinations of isolation operations applicable to different memory array structures are described.Each of the following descriptions may be used alone or in combination with other systems and methods described herein.

[0059] In some cases, the memory bank 12 includes 8 DQ symbols, and thus the control logic 48 may sometimes control a memory bank 12 having a row plane 80 corresponding to the 8 DQ symbols. For example, Figure 4 A map 100 of DQ symbols in an embodiment of a DDR4 x8 1K active DQ symbol mapping for a memory bank 12 illustrated in association with a SWL 62 and a SWL driver 64. For ease of reference, DQs may be interchangeably referenced by symbol names (e.g., symbols A through H) at a particular RA activation state (e.g., RA0=0 vs. RA0=1). Map 100 is for illustrative purposes, but other embodiments may include other mappings and / or different numbers of DQ symbols per bank.

[0060] As illustrated, memory banks 12 may correspond to row planes 80A-80I (row planes 80A, 80B, 80C, 80D, 80E, 80F, 80G, 80H, 80I), and different numbers of row planes 80 may be used in actual implementations. Row planes 80A-80I are associated with different DQs at different activation states (e.g., RA0=0 vs. RA0=1). For example, between different activation states, row plane 80A corresponds to DQ7 symbol H or DQ3 symbol D, row plane 80B corresponds to DQ5 symbol G, row plane 80C corresponds to DQ6 symbol F or DQ7 symbol H, row plane 80D corresponds to DQ4 symbol E, row plane 80E corresponds to DQ3 symbol D or DQ6 symbol F, row plane 80F corresponds to DQ1 symbol C or DQ0 symbol A, row plane 80G corresponds to DQ2 symbol B, and row plane 80H corresponds to DQ0 symbol A or DQ1 symbol C. The global row decoder 82 is shared across each of the row planes 80A- 80H.

[0061] Map 100 is an example of bank level activation isolation and data placement based isolation. SWL drivers 64 may correspond to different WLs 66 (66A, 66B) activated at different times using address signals RA0 set during activation of memory banks 12. It should be noted that although address signal RA0 is used in this example, other implementations may use different row addresses to identify which SWL driver (SWD) is activated in which column planes. When set via address signal RA0=0 in the activated state, WL 66B (e.g., SWL drivers 64B, 64D, 64F, 64H) is activated and WL 66A (e.g., SWL drivers 64A, 64C, 64E, 64G, 64I) is not activated, which enables symbols (e.g., symbols H, G, F, E, D, C, B, and A) to be read in a first parallel arrangement. When set in an active state via address signal RA0=1, WL 66B is inactivated and WL 66A is activated, which enables reading of symbols (e.g., symbols D, G, H, E, F, A, B, and C) in a second parallel arrangement different from the first parallel arrangement.

[0062] The switch logic circuitry of the control logic 48 may use bank-level based isolation and data placement based isolation via its routing configuration set by the control logic 48, memory controller, command decoder, or other suitable command generation control or input circuitry. In some cases, the switch logic circuitry may include programmable routing protected by fuses or other circuitry that permanently modifies routing. In response to different states of RA0, the switch logic circuitry reroutes write data to the memory bank 12C according to a first parallel arrangement (e.g., RA0=0) or a second parallel arrangement (e.g., RA0=1) to ensure that correction rules can be used to correct different DQ symbols of the shared SWL driver 64. In this way, if two symbols contain errors, the errors can be corrected as long as they belong to a certain pair. For example, if the data in two symbols is corrupted, the correction algorithm can correct the data when the failed data belongs to symbols (A and B) or (C and D) or (E and F) or (G and H). In other words, a SWL driver 64 driving both DQ0 symbol A and DQ1 symbol C may output uncorrectable errors, but a SWL driver 64 driving both DQ0 symbol A and DQ2 symbol B may output correctable errors if the SWL driver has a defect that causes some or all bits connected to the SWL driver to be corrupted.

[0063] As an example, Table 1 summarizes the combinations of DQ symbols with DQ0 symbol A that may or may not produce uncorrectable errors when the memory errors are caused by common cause SWL driver 64 errors. Although Table 1 is described with reference to DQ0 symbol A, it should be understood that each of the DQs has its own valid and invalid SWL driver 64 pairings based on the correction rules applied. Control circuitry, such as control logic 48, may take valid and invalid DQ pairings into account when designing or employing DQ symbol mapping.

[0064] Table 1

[0065] DQ0 Symbol A DQ1 Symbol C Invalid combination; uncorrectable error. DQ0 Symbol A DQ2 Symbol B Valid combination; correctable errors. DQ0 Symbol A DQ3 symbol D Invalid combination; uncorrectable error. DQ0 Symbol A DQ4 Symbol E Invalid combination; uncorrectable error. DQ0 Symbol A DQ5 Symbol G Invalid combination; uncorrectable error. DQ0 Symbol A DQ6 Symbol F Invalid combination; uncorrectable error. DQ0 Symbol A DQ7 Symbol H Invalid combination; uncorrectable error.

[0066] The switch logic circuitry may include interconnected multiplexer circuitry to couple to the SWL driver 64 or other switch circuitry. Control signals from the memory controller may operate the multiplexer circuitry or switch circuitry to different input / output combinations, thereby reprogramming the configuration of the switch logic circuitry in response to a command addressing RA0=1 or RA0=0. Table 2 visualizes this example reprogramming as causing a different arrangement of the DQ symbols in relative positions to the global row decoder 82. The switch logic circuitry may reroute one or more of the DQ symbols to comply with the ECC correction rules described above. It should be noted that the DQ3 symbol D and DQ1 symbol C with RA0=1 are on an edge with the symbol H and symbol A with RA0=0 and therefore may not share the SWL driver 64 with another DQ, and therefore may output correctable data errors even if the SWL driver 64A and / or SWL driver 64I malfunction, and the DQ4 symbol E and DQ5 symbol G are not rerouted in response to the RA0 state.

[0067] Table 2

[0068]

[0069] In some cases, the memory bank contains 8 DQ symbols and a double-sided global row decoder 82 instead of Figure 4 The one-sided global row decoder 82 shown in FIG. For example, Figure 5 1 is a map 120 of DQ symbols in an embodiment of a DDR4 x8 1K active DQ symbol mapping for a memory bank 12 illustrated in association with the SWL 62 and SWL driver 64 of the memory bank 12 and the bank control block 22. The map 120 is for illustrative purposes, but other embodiments may include other mappings and / or different numbers of DQ symbols per bank. Similar to Figure 4, the memory bank 12 may correspond to row planes 80A to 80I (row planes 80A, 80B, 80C, 80D, 80E, 80F, 80G, 80H, 80I), which are associated with different DQ symbols in different activation states. The placement of the global row decoder 82 is adjusted in position. Row plane 80I corresponds to DQ0 symbol A, and the global row decoder 82 may drive the word line from both sides instead of from one side. The switch logic circuit system and / or control logic 48 is used to adjust Figure 4 80B corresponds to DQ5 symbol G and DQ4 symbol E, row plane 80C corresponds to DQ6 symbol F, row plane 80D corresponds to DQ4 symbol E and DQ5 symbol G, row plane 80F corresponds to DQ3 symbol D, row plane 80G corresponds to DQ1 symbol C or DQ0 symbol A, row plane 80H corresponds to DQ2 symbol B, and row plane 80I corresponds to DQ0 symbol A or DQ1 symbol C. Table 3 shows this reprogramming. The switch logic circuit system and / or control logic 48 can reroute some of the DQ symbols according to the DQ symbol map 120 to perform isolation operations based on the memory bank level and isolation based on the data arrangement, thereby enabling the DDR4 x8 DQ memory device to comply with the rules for ECC correctability. Here, when the shared SWL driver is defective, some of the edge DQ symbols are rerouted to improve the correctability effect. DQ7 symbol H (row plane 80A) and DQ3 symbol D (row plane 80F) can maintain the original arrangement for each activation state. DQs on the edge, such as DQ7 symbol H or DQ3 symbol D, can output correctable data errors even if SWL driver 64A and / or SWL driver 64I malfunction due to the edge position not being paired with another DQ symbol.

[0070] Table 3

[0071]

[0072] The placement of the global row decoder 82 can be used to isolate the two halves of the memory bank from each other. In this way, a memory error affecting any of the DQ5-7 symbols is isolated from the DQ0-3 symbols via the global row decoder 82, and vice versa. This arrangement can also reduce the likelihood of uncorrectable memory errors.

[0073] Additionally, in some cases, a memory bank contains 4 DQ symbols instead of Figure 5 For example, Figure 61 is a map 130 of DQ symbols in an embodiment of a DDR4 x4 512 active DQ symbol mapping for a memory bank 12 with 512B page activation illustrated in association with the SWL 62 and SWL driver 64 of the memory bank 12 and the bank control block 22. The map 130 is for illustrative purposes, but other embodiments may include other mappings and / or different numbers of DQ symbols per bank. Similar to Figure 4 , the memory bank 12 may correspond to row planes 80A to 80I (row planes 80A, 80B, 80C, 80D, 80E, 80F, 80G, 80H, 80I), which are associated with different DQ symbols and even / odd sense amplifiers in different activation states.

[0074] The RA16 signal may select between one side and the other side of the memory bank 12 bisected by the global row decoder 82. The global row decoder 82 may drive the word line associated with the SWL driver 64 from both sides instead of one side.

[0075] The switch logic circuitry and / or control logic 48 may adjust Figure 5 80A to 80D shown in the figure can be arranged to accommodate a smaller number of DQ symbols. For example, between different activation states, row plane 80A corresponds to DQ3 symbol H, row plane 80B corresponds to DQ1 symbol G and DQ0 symbol E, row plane 80C corresponds to DQ2 symbol F, row plane 80D corresponds to DQ0 symbol E and DQ1 symbol G, row plane 80F corresponds to DQ3 symbol D, row plane 80G corresponds to DQ1 symbol C or DQ0 symbol A, row plane 80H corresponds to DQ2 symbol B, and row plane 80I corresponds to DQ0 symbol A or DQ1 symbol C. Table 4 can visualize this example reprogramming. The switch logic circuit system and / or control logic 48 can reroute some of the DQ symbols according to the DQ symbol mapping to perform isolation based on the memory bank level and isolation based on the data arrangement, thereby enabling the DDR4 x4 DQ memory device to comply with the ECC specification. Here, some of the edge row planes 80D and 80I are rerouted to improve overall compliance with ECC operating rules. Row planes 80A and 80F, each assigned to DQ3 symbol H, can maintain the original arrangement for each activation state. In addition, row planes 80C and 80H, each assigned to DQ2 symbol B, can maintain the original arrangement for each activation state.

[0076] Table 4

[0077]

[0078] Figure 7 To illustrate the use of Figure 1140 is a flowchart of a method of data path (DQ) symbol mapping in the data path circuitry 46 of FIG. 140. Although certain operations of the flowchart 140 are Figure 7 140, it should be understood that additional or fewer operations may be used in the same or different order of operations than those presented below. Furthermore, although described herein as being performed by control logic 48, it should be understood that other circuitry may perform some or all of the operations described herein. In practice, a processor executing instructions stored in a tangible computer-readable medium, such as instructions corresponding to a design application or other software, may perform the operations of flowchart 140.

[0079] At block 142, the control logic 48 may receive a memory command corresponding to a memory bank 12 and may access one or more connection path assignments for the memory bank 12. The memory command may instruct the control logic 48 to write data into the memory bank 12, read data from the memory bank, or refresh data stored in the memory bank, which involves activation of the memory bank 12. The connection path assignments may include information indicating the physical location of the data symbols in the memory array (e.g., the mapping between the SWL driver 64 and the data symbols) and therefore where the data stored in a particular data symbol is located. The information may indicate that the access address in the memory command, as mapped to the physical location of the data symbol within the memory bank 12. In practice, the memory bank 12 and the bank control block 22 may be connected with a specific arrangement of how the data paths physically store the symbol data in the memory bank 12. This assignment may be generated based on known correctability rules and guidelines for the system. These connection path assignments may be hard-coded when the design is first built or fuses that can be programmed for flexible mapping may be determined after the chip is built, and in some systems both approaches may be used with one or more of the memory banks 12. A processing system, such as control logic 48 or another suitable control circuit may generate the connection path assignments during operation, after user deployment, after the chip is built, etc. Symbol mapping follows the connection path assignments so that certain symbols are assigned to certain physical locations that are maintained through one or more memory accesses, where the locations may group data by sub-word line driver, column select, column plane, sense amplifier stripe, etc. In practice, circuitry, such as a processing system, may generate a mapping of the connection path assignments to help maximize data isolation and provide data groupings that have a relatively better chance of successful correction in the event of a physical defect or data error, as generally described above, to avoid generating a non-correction situation.

[0080] At box 144, the control logic 48 may generate data path assignments based on the row address information and connection path assignments provided at bank activation. The data path assignments may be used to assign received data to one or more SWL drivers 64 (and therefore data symbols) based on the physical locations of the SWL drivers 64 indicated in the connection path assignments. Bank activation may provide row addresses RA(n) and RA0 that may be used to identify which SWL drivers 64 are active, and therefore data may be assigned to one or more of the active SWL drivers 64. This may be the state of RA0 or the state of one of the other row addresses RA(n). This row address information is specific to each active bank. It may identify which SWL driver 64 to associate the data with. The data path assignments may follow a DQ symbol mapping, such as by Figures 2 to 6 As described, the data is routed to avoid the creation of a non-correction condition when the data is stored in the memory device 10 according to the DQ symbol mapping. The data path assignments may include rerouted original data path assignments that are rerouted based on the non-correction condition to avoid the creation or compliance with the non-correction condition. The control logic 48 may incrementally change the data path assignments to find an assignment that is relatively more compliant with error correction operations.

[0081] At block 146, the control logic 48 may receive bank-specific column address information when issuing a read or write command to the memory bank 12. The control logic 48 may generate one or more control signals based on the data path assignments determined at block 144 and the column address CA(n) information provided when activating the memory bank 12. The one or more control signals may be generated from the RA and CA addresses, where a subset may multiplex the data paths so that physical data locations in the memory bank 12 may be assigned to correctable symbol groups in the data paths.

[0082] At block 148, the control logic 48 may transmit the one or more control signals generated at block 146 to the data path circuitry 46 to program the data path assignment. Transmitting the one or more control signals may cause the data path circuitry 46 to reroute the bidirectional data path (DQ symbol) from the first SWL driver 64 to the second SWL driver 64. In practice, the connection path assignment may have pre-assigned the DQ symbol to the first SWL driver 64 and the control logic 48 is reallocating the DQ symbol to a relatively more compliant position of the second SWL driver 64 by transmitting the one or more control signals. For example, Figure 6 DQ1 symbol C may be rerouted from the first SWL driver 64G of the data plane when RA0=0 to the second SWL driver 64J of the internal data plane when RA0=1 to eliminate the possibility of causing a non-correction condition (e.g., memory errors on the symbol B and symbol C DQs driven through SWL driver 64H) when rerouting has not occurred.

[0083] Figures 8 to 11 1 is a circuit diagram of a data routing circuit system that may be included in the SWL driver 64 and / or upstream of the symbol. Each circuit diagram may include a data path 100 and a selectable device 152, wherein the selectable device 152 can be turned on by a received address signal (e.g., CA10, RA16, RA0) to transfer data from the corresponding one of the data path 100 to the downstream symbol (as marked), such as Figure 8 , "Symbol P" or "Symbol N" receives data from "Symbol H'", "Symbol L" or "Symbol J" receives data from "Symbol F'", etc. Thus, each transaction between the host device and the memory bank 12 involves transferring data between symbols via the selectable device 152.

[0084] Figure 8 For the corresponding Figure 2 A circuit diagram of a data routing circuit system with symbolic mapping. For example, Figure 8 1 shows how CA10 can be used to select symbols from the array. After this, when the correction code restriction can only correct multi-symbol errors occurring in symbols (A' and B') or (C' and D') or (E' and F') or (G' and H'), the illustrated data routing to various symbols can output data in such a way that physical SWL driver and column selection defects are more likely to be repairable, where ' is an apostrophe and indicates the data path version of the symbol rather than the DQ version of the symbol. CA10=0 or CA10=1 is used to select a subset of symbols or column planes 60 for output to data path 100 or loading data from data path 100. For example, the state of CA10 is used to select a subset of symbols or column planes 60 for output to data path 100 or loading data from data path 100. For example, the state of CA10 is used to select a subset of symbols or column planes 60 for output to data path 100 or loading data from data path 100. Figure 2 4 and 60A2 of the column planes 60A4 and 60A2 shown in FIG. 1 toggles the communication of the data path 100 from the memory bank 12 to the symbol H'. Other selection operations are also applicable to toggling the data path of the symbols A' to G' between different column planes 60, but are skipped for clarity of description.

[0085] Fig. 9 For the corresponding Figure 3 A circuit diagram of a symbolically mapped data routing circuit system. Similar to Figure 8 , the state of row address signal RA16 is used to select a subset of symbols or row plane 80 for access to improve the correctability of potential data errors. For example, when the correction code limit can only correct multi-symbol failures when the failure occurs in symbols (A and B) or (C and D'), RA16 is used to select the symbols to be output from the memory storage bank 12 in such a way that physical SWL driver and column selection defects are more likely to be repairable, where ' indicates the data path version of the symbol. For example, the state of RA16 is used to select the symbol subset or row plane 80 for access to improve the correctability of potential data errors. For example, when the correction code limit can only correct multi-symbol failures when the failure occurs in symbols (A and B) or (C and D'), RA16 is used to select the symbols to be output from the memory storage bank 12 in such a way that physical SWL driver and column selection defects are more likely to be repairable. Figure 3Row planes 80A1 and 80A2 are shown to toggle communication from memory bank 12 to data path 100 of symbol D' between symbol H and symbol G. Other selection operations are also applicable to toggle data paths of symbols A' to C' between different row planes 80, but are skipped for clarity of description.

[0086] Fig.10 For the corresponding Figure 4 A circuit diagram of a symbolically mapped data routing circuit system. Similar to Fig. 9 , the state of row address signal RA0 is used to select a subset of symbols or row plane 80 for access to improve the correctability of potential data errors. For example, when the correction code restriction can correct multi-symbol errors only when the errors occur in symbols (A' and B') or (C' and D') or (E' and F') or (G' and H'), RA0 is used to select the symbols to be output from the memory storage bank in such a way that physical SWL driver defects are more likely to be repairable, where ' indicates the data path version of the symbol. For example, the state of RA0 can be used to select the symbol subset or row plane 80 for access to improve the correctability of potential data errors. For example, when the correction code restriction can correct multi-symbol errors only when the errors occur in symbols (A' and B') or (C' and D') or (E' and F') or (G' and H'), RA0 is used to select the symbols to be output from the memory storage bank in such a way that physical SWL driver defects are more likely to be repairable. Figure 4 80A of the row plane 80A shown in FIG. 1 toggles the communication of the data path 100 from the memory bank 12 to the symbol H'. Other selection operations are also applicable to toggling the data paths of the symbols A', C', D' and F' between different row planes 80, but are skipped for clarity of description. The data path symbols G', E' and B' may not switch between symbols in response to the state of RA0.

[0087] Fig.11 For the corresponding Figure 5 A circuit diagram of a symbolically mapped data routing circuit system. Similar to Fig.10 , the state of row address signal RA0 is used to select a subset of symbols or row plane 80 for access to improve the correctability of potential data errors. For example, when the correction code limit can correct multi-symbol errors only when the error occurs in symbols (A' and B') or (C' and D') or (E' and F') or (G' and H'), RA0 is used to select the symbols to be output from the array in such a way that physical SWL driver defects are more likely to be repairable, where ' indicates the data path version of the symbol. For example, the state of RA0 can be used to select a symbol subset or row plane 80 for access to improve the correctability of potential data errors. For example, when the correction code limit can correct multi-symbol errors only when the error occurs in symbols (A' and B') or (C' and D') or (E' and F') or (G' and H'), RA0 is used to select the symbols to be output from the array in such a way that physical SWL driver defects are more likely to be repairable. Figure 5 80D of the row plane 80D shown in FIG. 1 toggles the communication of the data path 100 from the memory bank 12 to the symbol G'. Other selection operations are also applicable to toggling the data paths of the symbols A', C' and E' between different row planes 80, but are skipped for clarity of description. The data path symbols H', F', D' and B' may not switch between symbols in response to the state of RA0. It should be noted that similar circuit systems may be used with Figure 6The embodiments are used together to selectively route data between different portions of memory bank 12 .

[0088] Thus, with the foregoing in mind, these systems and methods can take into account ECC operation restrictions for correction when generating DQ symbol mappings to reduce the likelihood of uncorrectable data errors. The following is a non-exhaustive discussion of example ECC operation processing restrictions that can be considered by control logic 48 or other suitable control circuit systems when operating switch logic circuit systems and / or data path circuit systems 46 to route data between memory banks 12 and I / O interfaces 16.

[0089] As described above, some error correction operations may correct data errors belonging to certain symbol groupings. For example, if two symbols output data with data errors, then the data errors corresponding to those two symbols may be corrected when the two symbols are (A and B) or (C and D) or (E and F) or (G and H). For example, if symbols A and C are associated with memory defects that cause retrieval misoperation of their data, then the correction algorithm cannot correct the data. Therefore, symbols that share a SWL driver should be allocated so that when grouped together as a pair, higher correctability can be achieved. For example, a data path allocation that groups symbol A and symbol B into a pair that shares the same SWL driver 64 may be relatively more correctable than a data path allocation that groups symbol A and symbol C, symbol A and symbol D, symbol A and symbol E, etc. into a pair that shares the same SWL driver 64.

[0090] There are many ways to create correctability rules. Assigning symbol pairs based on their hypothetical correctability (e.g., assigning symbols as pairs when correctable and not assigning symbols as pairs when uncorrectable) is one example of demonstrating that knowing in advance common correctability groupings can be used to organize data. In practice, knowing in advance correctability can enable data routing assignments to be made in such a way that relatively more common array defects do not cause uncorrectable error combinations. It should be noted that although described in terms of the row plane, isolation operations and combinations can be similarly applied to memory banks using column planes, such as memory bank 12A and column plane 60, and vice versa.

[0091] In addition, there may be some embodiments in which the control logic 48 performs processing operations to generate a DQ symbol map based on an indication of one or more non-correction situations. The operations may include receiving an original DQ symbol map and performing a first compliance analysis to obtain a metric indicating the number of non-correction situations that exist within the DQ symbol map. If the number of non-correction situations that exist is less than a threshold, the control logic 48 may continue to use the map. However, if the number of non-correction situations that exist is greater than or equal to the threshold, the control logic 48 may use the indication of non-correction situations to adjust how the row planes 80 and / or column planes 60 are allocated within the DQ symbol map to avoid or reduce the likelihood of non-correction situations occurring. After adjusting the DQ symbol map, the control logic 48 may repeatedly evaluate the changes to determine whether there are fewer non-correction situations and / or whether the number of non-correction situations that exist is less than a threshold number.

[0092] Therefore, the technical effects of the present disclosure include systems and methods for reducing the possibility of uncorrectable data errors occurring without increasing the expected or actual error rate. These systems and methods describe a switch logic circuit system that can route data between a memory and an I / O interface in such a way that the DQ symbol paths are structurally isolated from each other. In practice, a pair of DQ symbol paths can produce uncorrectable data errors when an ECC operation is unable to correct the data errors. Certain circumstances may render the ECC operation unable to correct data errors, such as the number of data errors or the placement of data errors. By taking into account the circumstances when generating or adopting DQ symbol mappings through the switch logic circuit system and / or the control circuit system, pairs that can otherwise produce uncorrectable data errors can be mitigated and rerouted to avoid situations where the ECC operation is uncorrectable. Therefore, these systems and methods can prevent or reduce the possibility of certain uncorrectable error combinations occurring without increasing the expected or actual error rate.

[0093] Although various modifications and alternative forms may occur in the present disclosure, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed. In fact, the present disclosure is intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the present disclosure as defined by the appended claims.

[0094] The technology presented and claimed herein is referenced and applied to substantial objects and specific examples of a practical nature that improve the art in a demonstrable manner and are therefore not abstract, intangible, or purely theoretical. In addition, if any claim appended to the end of this specification contains one or more elements designated as "means for [performing] [the function] ..." or "steps for [performing] [the function] ...", it is intended that such elements will be interpreted in accordance with 35 U.S.C. 112(f). However, for any claim containing elements designated in any other manner, it is intended that such elements will not be interpreted in accordance with 35 U.S.C. 112(f).

Claims

1. A device comprising: a memory bank comprising a plurality of planes; bank control circuitry comprising a plurality of sub-wordline drivers, wherein each of the sub-wordline drivers is associated with a subset of the plurality of planes; as well as A data path circuit system comprising a plurality of bidirectional data paths, wherein the data path circuit system is configured to couple one or more of the plurality of bidirectional data paths to one or more of the plurality of sub-word line drivers based at least in part on one or more control signals, wherein the memory body control circuit system is configured to generate the one or more control signals to change the assignment of corresponding ones of the plurality of bidirectional data paths to one or more other ones of the plurality of sub-word line drivers based at least in part on an error correction code (ECC) operation.

2. The apparatus of claim 1, wherein a bidirectional data path map comprises the assignment, and wherein the assignment is based on a non-correction condition associated with the ECC operation. 3 . The apparatus of claim 2 , wherein the bidirectional data path mapping is a data path DQ symbol mapping.

4. The apparatus of claim 1 , wherein the plurality of bidirectional data paths comprises a first bidirectional data path that is logically adjacent to a second bidirectional data path, and wherein a first sub-word line driver of the plurality of sub-word line drivers is configured to provide data access to the first bidirectional data path at a first time and to alternately provide data access to the second bidirectional data path at a second time. 5 . The apparatus of claim 4 , wherein the first sub-word line driver is configured to provide the data access at the first time in response to a column select address signal. 6 . The apparatus of claim 4 , wherein the first sub-word line driver is configured to provide the data access at the first time and at the second time in response to different row select addresses.

7. The apparatus of claim 1, wherein the allocation is configured to change between a first allocation and a second allocation in response to a memory bank activation address.

8. A device according to claim 7, wherein the plurality of bidirectional data paths include a first bidirectional data path adjacent to a second bidirectional data path, and wherein the first allocation is configured to cause the data path circuit system to associate the first bidirectional data path and the second bidirectional data path with a first sub-word line driver among the plurality of sub-word line drivers in response to a first memory body activation address.

9. The apparatus of claim 8, wherein the second allocation is configured to cause the data path circuit system to associate the first bidirectional data path and the second bidirectional data path with a second sub-word line driver of the plurality of sub-word line drivers in response to a second memory cell activation address.

10. The apparatus of claim 1, wherein the plurality of planes comprises a plurality of row planes, wherein the allocation is configured to associate a corresponding bidirectional data path among the plurality of bidirectional data paths with a corresponding row plane among the plurality of row planes, and wherein the allocation is selected in response to a memory cell activation address.

11. The apparatus of claim 10, wherein control circuitry of the data path circuitry is configured to program the allocation via a plurality of multiplexers.

12. A method comprising: receiving an indication of a non-correction condition associated with an error correction code (ECC) stored in a memory bank, wherein the ECC is configured to correct one or more data errors of output data, and wherein the one or more data errors are not correctable by the ECC when the non-correction condition is met; generating a data path assignment based at least in part on the indication of the non-correction condition; generating a control signal based on the data path assignment; as well as The control signal is transmitted to data path circuitry, wherein the data path circuitry is configured to associate a respective bidirectional data path with at least two respective sub-word line drivers in response to the control signal.

13. The method of claim 12, wherein transmitting the control signal causes the data path circuitry to reroute a bidirectional data path from a first sub-word line driver of an edge data plane to a second sub-word line driver of an interior data plane to avoid causing the non-correction condition.

14. The method of claim 12, comprising generating the data path allocation based at least in part on the indication of the non-corrective condition and at least in part by adjusting an original data path allocation to avoid causing the non-corrective condition.

15. The method of claim 12, wherein the non-correction condition is associated with: a first pair of bidirectional data paths corresponding to a first shared sub-word line driver having an adjacent logical arrangement, a second pair of bidirectional data paths corresponding to a second shared sub-word line driver having a logical arrangement that straddles a half-byte boundary, or both.

16. An apparatus comprising: bank control circuitry comprising a plurality of sub-wordline drivers, wherein each of the plurality of sub-wordline drivers is associated with a memory bank; and A plurality of bidirectional data paths configured to be coupled between the plurality of sub-word line drivers and an input / output (I / O) interface circuit system based at least in part on an indication of an assignment of each of the plurality of bidirectional data paths to one or more of the plurality of sub-word line drivers, wherein the assignment is configured to be generated based at least in part on an error correction operation performed on data of the memory storage body.

17. The apparatus of claim 16, wherein the allocation is configured to be generated based at least in part on the error correction operation by controlling circuitry to perform operations comprising: receiving an indication of a non-correction condition associated with an error correction code (ECC) stored in the memory bank, wherein the ECC is configured to perform the error correction operation to correct one or more data errors of output data, and wherein the one or more data errors are not correctable by the ECC when the non-correction condition is met; and The allocation is generated based at least in part on the indication of the non-corrective condition.

18. The apparatus of claim 16, comprising control circuitry configured to: generate one or more control signals based on the allocation; and The control signal is transmitted to switch logic circuitry corresponding to the plurality of bidirectional data paths, wherein the switch logic circuitry is configured to associate a respective bidirectional data path with at least two respective sub-word line drivers in response to the control signal.

19. The device of claim 16, wherein the indication of the allocation comprises a first allocation when a bank activation bit has a logic high state, and wherein the indication of the allocation comprises a second allocation when the bank activation bit has a logic low state.

20. The apparatus of claim 19, wherein the memory bank comprises eight row planes, wherein the first allocation is configured to associate each of the eight row planes with each of the plurality of bidirectional data paths, and wherein when the plurality of bidirectional data paths comprises four bidirectional data paths and comprises eight bidirectional data paths, a portion of the first allocation applies to both.

21. The apparatus according to claim 16, comprising: The memory bank includes a plurality of row planes; and A data path circuit system comprising the plurality of bidirectional data paths and a multiplexing circuit system, wherein the data path circuit system transmits data between the plurality of row planes and the I / O interface circuit system at least in part by transmitting control signals based at least in part on assignment to the multiplexing circuit system.

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