Power device residual life prediction method and system based on crack length extension

Abstract

This invention provides a method and system for predicting the remaining lifetime of power devices based on solder layer crack length propagation. The remaining lifetime prediction method includes: establishing a finite element two-dimensional model / finite element three-dimensional model; dividing the chip solder layer model in the finite element two-dimensional model / finite element three-dimensional model into K cells; sequentially executing the first aging stage, the second aging stage, ..., the (S+1)th aging stage to obtain the junction-to-case thermal resistance of the power device at the completion time of the kth aging stage; the solder layer crack length increases with the number of failed cells; real-time monitoring of the power cycle count of the power device in actual tests and the junction-to-case thermal resistance of the power device corresponding to the power cycle count, determining which interval the current junction-to-case thermal resistance of the power device belongs to, and then using the corresponding formula to calculate the number of power cycles required from the current monitoring of the junction-to-case thermal resistance to the failure of the chip solder layer.

Description

Technical Field

[0001] This invention relates to an online prediction method for the remaining lifetime of power semiconductor devices, and more particularly to an online prediction method for the remaining lifetime of large-area solder layer crack propagation failure process, belonging to the technical field of welding reliability assessment of power semiconductor devices. Background Technology

[0002] Power semiconductor devices are widely used in smart grids, locomotive traction, new energy power generation, and electric vehicles. However, long-term temperature fluctuations can cause problems such as voids, crack initiation and propagation in the solder layer of power devices, ultimately leading to device degradation and failure, affecting the performance of the entire system, and even causing the entire system to fail, resulting in major safety accidents.

[0003] To address the aforementioned issues, methods for predicting the remaining lifetime of power devices have been continuously developed. Existing methods for predicting the remaining lifetime of power devices are mainly divided into two types: data-driven prediction methods and failure mechanism analysis-based prediction methods. However, existing data-driven prediction methods require a large amount of experimental aging data for optimization training to establish the mapping relationship between input and output, significantly increasing the time cost of the prediction method. Meanwhile, existing failure mechanism analysis-based prediction methods often simplify the fatigue accumulation effect of power devices during the aging failure process, failing to accurately describe the actual aging process of the solder layer, resulting in lower accuracy in predicting the remaining lifetime of power devices. Furthermore, these methods generally require multiple sets of experimental aging data to fit and obtain relevant parameters, which is time-consuming and labor-intensive. In addition, the construction of these methods is mostly related to the product type of the power device, lacking universality. Summary of the Invention

[0004] The problem this invention aims to solve is that the requirements for prediction time and prediction accuracy cannot be met simultaneously in the prediction of the remaining lifetime of existing power devices. The invention provides a method for predicting the remaining lifetime of power devices based on the expansion of solder layer crack length.

[0005] To solve the above technical problems, the technical solution adopted by the present invention is: a method for predicting the remaining lifetime of power devices based on the crack length propagation of chip solder layer, wherein a first straight line (La) is defined as a straight line extending along the height direction on the side of the power device and dividing the area of ​​the chip layer on the side of the power device equally, wherein the side of the power device is a surface composed of the height of the power device and the length / width of the power device.

[0006] The method for predicting the remaining lifetime of power devices includes:

[0007] A. Based on the material and size parameters of the power device's packaging structure, establish a finite element two-dimensional model / finite element three-dimensional model corresponding to the structure located on one side of the first straight line (La) on the side of the power device;

[0008] The two dimensions of the finite element two-dimensional model correspond to the height of the power device and the length / width of the power device, respectively.

[0009] In the finite element three-dimensional model, two dimensions correspond to the height and length / width of the power device, respectively, and the other dimension corresponds to the width / length of the power device.

[0010] The simulation environment of the finite element two-dimensional model / finite element three-dimensional model is consistent with the working environment of the power device in the actual experiment;

[0011] Along the direction corresponding to the length / width direction of the power device in the finite element two-dimensional model / finite element three-dimensional model, the chip solder layer model in the finite element two-dimensional model / finite element three-dimensional model is divided into K cells;

[0012] From the end of the chip solder layer model corresponding to the end of the actual chip solder layer, to the other end of the chip solder layer model corresponding to the center of the length / width of the actual chip solder layer, the first cell, the second cell, ..., the Kth cell are set sequentially, with 10≤K≤100;

[0013] The finite element two-dimensional model / finite element three-dimensional model is sequentially subjected to the first aging stage, the second aging stage, ..., the S+1th aging stage, wherein the length of the solder layer crack increases with the increase of the number of failed cells, and the completion time of the kth aging stage is the time when the kth cell is eliminated, k=1,2,..., S+1;

[0014] Where the value of S satisfies the following formula:

[0015]

[0016] Among them, R th(0) R is the initial junction-to-case thermal resistance of the power device. th(k) R is the junction-to-case thermal resistance of the power device at the completion time of the kth aging stage. th_u% The junction-to-shell thermal resistance corresponding to the preset percentage u% is determined when the chip solder layer fails at a junction-to-shell thermal resistance of R. th_u% The moment;

[0017] Real-time monitoring of the power cycle count of power devices and the junction-to-case thermal resistance of power devices corresponding to the power cycle count in actual tests, thereby obtaining the correspondence between the power cycle count and the junction-to-case thermal resistance;

[0018] When it is necessary to calculate the junction-to-case thermal resistance R of the current power devicex The number of power cycles L required from the moment the chip solder layer fails to the moment of failure x When, then judge If the condition is true, then determine the junction-to-case thermal resistance R of the current power device. x In the interval [R] th(1) ,R th(2) ), [R th(2) ,R th(3) ), ..., [R th(S) ,R th(S+1) If it falls within a specific interval, then monitor it; otherwise, continue monitoring.

[0019] If we determine R x In the interval [R] th(m) , R th(m+1) In the given equation, where m is an integer and 1 ≤ m ≤ S, the junction-to-case thermal resistance R of the power device can be calculated using the following formula. x The number of power cycles L required from the moment the chip solder layer fails to the moment of failure x :

[0020] ;

[0021] in:

[0022]

[0023] in, It is the correspondence with R in the above-mentioned relationship. th(1) The corresponding number of power cycles, Let be the number of power cycles performed in the i-th aging stage. The inelastic strain energy density is the loss of the first cell per power cycle in the first aging stage. Let be the inelastic strain energy density of the power cycle loss of the i-th cell during the i-th aging stage. Let be the inelastic strain energy density of the power cycle loss of the i-th cell during the j-th aging stage. Let S be the damage accumulated by the i-th cell in the j-th aging stage, where 2≤i≤S+1.

[0024] In this invention, the failure process of the chip solder layer is divided into multiple aging stages. Starting from the first aging stage, only one cell fails in the length / width direction in each aging stage. That is, executing the first power cycle from the beginning of the finite element 2D / 3D model is the first power cycle of the first aging stage. When the first cell fails, the first aging stage ends. The end of the first aging stage is also the start of the second aging stage. The more cells that fail, the longer the solder layer crack length. In the established finite element 2D / 3D model, the simulation process can be executed in advance to obtain the junction-shell thermal resistance corresponding to different numbers of cell failures (i.e., different aging stages). Furthermore, the number of failed cells corresponding to the chip solder layer failure can be obtained based on the initial value of the junction-shell thermal resistance (i.e., the value of the junction-shell thermal resistance at the start of the first aging stage) and the junction-shell thermal resistance corresponding to different numbers of cell failures. During actual testing, the power cycle count of the power device and the corresponding junction-to-shell thermal resistance of the power device are monitored. When it is necessary to determine the remaining life of the power device, the actual monitored junction-to-shell thermal resistance can be compared with the simulation results in the finite element method. This allows us to determine how many failed cells correspond to the current junction-to-shell thermal resistance of the power device, as well as the power cycle count corresponding to each aging stage. By combining the inelastic strain energy consumed by each cell in each aging stage, the remaining life of the power device can be predicted.

[0025] In the above technical solution: Finite element thermodynamic simulation is performed using the Clech algorithm or on the finite element two-dimensional model / finite element three-dimensional model to obtain... The value of .

[0026] In the above technical solution: 30≤K≤200.

[0027] In the above technical solution: 50≤K≤100.

[0028] Preferably, K=50.

[0029] In the above technical solution: the upper surface of the chip layer of the power device is square in shape.

[0030] In the above technical solution: the junction thermal resistance R th The calculation formula is:

[0031] ;

[0032] in, T is the estimated junction temperature. c P is the temperature at the bottom of the power device housing. Loss This refers to the power of the power device.

[0033] In the above technical solution: the working environment includes the power of the power device, the turn-on time and turn-off time of the power device, and the cooling conditions applied to the power device.

[0034] In the above technical solution, the power device is turned on for the same amount of time each time and turned off for the same amount of time each time.

[0035] The present invention also provides a power device remaining lifetime prediction system based on solder layer crack length propagation, including a computer device; the computer device is configured to perform the steps of the remaining lifetime prediction method described in any of the above claims.

[0036] This invention addresses the problem that traditional remaining lifetime prediction methods rarely consider the changes in parameters such as stress, strain, and strain energy as solder layer cracks propagate, as well as the unclear damage accumulation during the corresponding aging process. It proposes an online remaining lifetime prediction method that can monitor the stepwise propagation of solder layer crack length in power semiconductor modules in real time.

[0037] Based on the above technical solution, the present invention has the following beneficial effects:

[0038] 1) This invention takes into account the problem that the inelastic strain energy density of the solder layer changes during the aging process. Based on the different stress-strain response relationships at different crack lengths in the solder layer, the failure process of the solder layer is divided into multiple aging stages.

[0039] 2) This invention takes into account the dynamic failure process of the solder layer, and can simulate the change of the thermal resistance of the junction during the aging process of the solder layer in real time, and can predict the remaining life of power devices more accurately and quickly.

[0040] 3) Compared with traditional remaining life prediction methods, this invention does not require a large amount of aging test data to fit and obtain the corresponding parameters. It can establish corresponding finite element models for different packaging models and has good versatility.

[0041] 4) Compared with traditional finite element thermo-mechanical coupling simulation, this application can quickly calculate and obtain the inelastic strain energy density and damage accumulation of each cell of the solder layer at different aging stages, saving a lot of computation time. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1This is a flowchart of a power device remaining lifetime prediction method based on solder layer crack length propagation according to an embodiment of the present invention.

[0044] Figure 2 This is a schematic diagram of the internal packaging structure of a power device;

[0045] Figure 3(a) is a schematic diagram of the finite element two-dimensional model of the power device established in the embodiment of the present invention, and Figure 3(b) is a schematic diagram of the finite element three-dimensional model of the power device established in the embodiment of the present invention.

[0046] Figure 4(a) is a schematic diagram of the chip solder layer divided into 1×K units in the finite element two-dimensional model of the present invention, and Figure 4(b) is a schematic diagram of the chip solder layer divided into 1×K units in the finite element three-dimensional model of the present invention.

[0047] Figure 5 This is a schematic diagram showing the relationship between each aging stage and the number of power cycles;

[0048] Figure 6 This is a comparison chart of the remaining lifetime prediction results obtained according to the embodiments of the present invention and the remaining lifetime results obtained from actual aging tests. Detailed Implementation

[0049] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0050] The power device can be one of the following: diode module, MOSFET module, IGBT module, or thyristor module.

[0051] Define the first straight line La as a straight line extending along the height direction on the side of the power device and dividing the area of ​​the chip layer on the side of the power device equally. The side of the power device is a surface composed of the height of the power device and the length / width of the power device.

[0052] Methods for predicting the remaining lifetime of power devices based on the propagation of crack length in the chip solder layer include:

[0053] A. Step A includes steps A1 and A2.

[0054] Step A1: Establish a finite element two-dimensional model / finite element three-dimensional model in the simulation space and simulate the aging process.

[0055] Based on the material and size parameters of the power device's packaging structure, a finite element two-dimensional model / finite element three-dimensional model corresponding to the structure located on one side of the first straight line La on the side of the power device is established.

[0056] The two dimensions of the finite element two-dimensional model correspond to the height of the power device and the length / width of the power device, respectively.

[0057] In the finite element three-dimensional model, two dimensions correspond to the height and length / width of the power device, respectively, and the other dimension corresponds to the width / length of the power device.

[0058] The simulation environment of the finite element two-dimensional model / finite element three-dimensional model is consistent with the working environment of the power device in the actual experiment;

[0059] Along the direction corresponding to the length / width direction of the power device in the finite element two-dimensional model / finite element three-dimensional model, the chip solder layer model in the finite element two-dimensional model / finite element three-dimensional model is divided into K cells;

[0060] From the end of the chip solder layer model corresponding to the end of the actual chip solder layer, to the other end of the chip solder layer model corresponding to the center of the length / width of the actual chip solder layer, the first cell, the second cell, ..., the Kth cell are set sequentially, with 10≤K≤100.

[0061] A 3D model consists of height, length, and width (i.e., thickness), with the length and height dimensions being the same as in a 2D model. When the side of a power device, as mentioned above, is a surface formed by the height and length of the power device, only one mesh is needed in the width direction. In other words, the 3D model divides the solder layer into multiple solid cells, and when meshing, only one mesh is needed in the width direction.

[0062] The finite element two-dimensional model / finite element three-dimensional model is sequentially subjected to the first aging stage, the second aging stage, ..., the S+1th aging stage, wherein the length of the solder layer crack increases with the increase of the number of failed cells, and the completion time of the kth aging stage is the time when the kth cell is eliminated, k=1,2,..., S+1;

[0063] Where the value of S satisfies the following formula:

[0064]

[0065] Among them, R th(0) R is the initial junction-to-case thermal resistance of the power device. th(k) R is the junction-to-case thermal resistance of the power device at the completion time of the kth aging stage. th_u% The junction-to-shell thermal resistance corresponding to the preset percentage u% is determined when the chip solder layer fails at a junction-to-shell thermal resistance of R.th_u% The moment when the chip solder layer reaches the failure criteria is considered a power device failure.

[0066] Step A2: Real-time monitoring process of the power module during operation in a real environment.

[0067] The power cycle count of the power device and the corresponding junction-to-case thermal resistance of the power device are monitored in real time during the actual test, so as to obtain the correspondence between the power cycle count and the junction-to-case thermal resistance.

[0068] Steps A1 and A2 can be performed simultaneously, or they can be performed sequentially, or steps A2 and A1 can be performed sequentially.

[0069] B. When it is necessary to calculate the junction-to-case thermal resistance R of the current power device x The number of power cycles L required from the moment the chip solder layer fails to the moment of failure x When, then judge If the condition is true, then determine the junction-to-case thermal resistance R of the current power device. x In the interval [R] th(1) ,R th(2) ), [R th(2) ,R th(3) ), ..., [R th(S) ,R th(S+1) If it falls within a specific interval, then monitor it; otherwise, continue monitoring.

[0070] If we determine R x In the interval [R] th(m) , R th(m+1) In the given equation, where m is an integer and 1 ≤ m ≤ S, the junction-to-case thermal resistance R of the power device can be calculated using the following formula. x The number of power cycles L required from the moment the chip solder layer fails to the moment of failure x

[0071] ;

[0072] in:

[0073]

[0074] in: It is the correspondence with R in the above-mentioned relationship. th(1) The corresponding number of power cycles, Let be the number of power cycles performed in the i-th aging stage. The inelastic strain energy density is the loss of the first cell per power cycle in the first aging stage. Let be the inelastic strain energy density of the power cycle loss of the i-th cell during the i-th aging stage. Let be the inelastic strain energy density of the power cycle loss of the i-th cell during the j-th aging stage. Let S be the damage accumulated by the i-th cell in the j-th aging stage, where 2≤i≤S+1.

[0075] In the above technical solution: Finite element thermodynamic simulation is performed using the Clech algorithm or on the finite element two-dimensional model / finite element three-dimensional model to obtain... The value of .

[0076] It is calculated based on the change in junction temperature of the first cell in the first aging stage, the combined stiffness of the first cell in the first aging stage, and the applied strain.

[0077] It is calculated based on the change in junction temperature of the i-th cell in the i-th aging stage, the combined stiffness of the i-th cell in the i-th aging stage, and the applied strain.

[0078] It is calculated based on the change in junction temperature of the i-th cell in the j-th aging stage, the combined stiffness of the i-th cell in the j-th aging stage, and the applied strain.

[0079] This invention uses the Infineon IGBT half-bridge module FF150R12ME3G as an example to construct a 2D model of the model.

[0080] The flowchart of the lifetime prediction method proposed in this embodiment of the invention is as follows: Figure 1 As shown. Specifically, the prediction method of this invention is described in detail below.

[0081] Step 1: Based on the actual dimensions of the module and the material properties of each internal encapsulation layer, establish a two-dimensional model of the unaged power device. The two dimensions of the two-dimensional model correspond to the height and width / length of the power device, respectively. In finite element simulation, the two-dimensional model is a two-dimensional axisymmetric model.

[0082] Establishing the dimensions of each layer of the internal packaging of a power device (also known as a power module or module) can be achieved by removing the module's outer shell, measuring the module's dimensions using SEM scanning, and determining the material properties of each layer using EDS. The simulation accuracy of a 2D model of a power device is comparable to that of a 3D model, and it can significantly shorten the computation time of finite element simulations, improving computational efficiency. Related papers have confirmed that the differences in junction temperature and mechanical properties obtained from 2D and 3D model simulations are very small, with a matching accuracy exceeding 90%. Examples include Borong Hu et al.'s paper "Long-Term Reliability Evaluation of Power Modules With Low Amplitude Thermo-mechanical Stresses and InitialDefects" published in the journal "IEEE Journal of Emerging & Selected Topics in Power Electronics," and Hua Lu et al.'s paper "Lifetime Prediction for Power Electronics Module Substrate Mount-down Solder Interconnect" published at the conference "2007 International Symposium on High Densitypackaging and Microsystem Integration."

[0083] Traditional soldered IGBT module internal packaging such as Figure 2 As shown, this is a multi-layered structure. For ease of analysis, the bond lines can be ignored when constructing the 2D model of the FF150R12ME3G module.

[0084] like Figure 2 As shown, Tc is the location for measuring the case temperature (base plate temperature). When applying thermal grease, a small area directly below the chip can be left untreated. Holes can be drilled in the heat sink, and the case temperature can be measured by attaching a thermal resistor to the surface of the case directly below the chip.

[0085] The chip layer and the chip solder layer have the same upper surface area. The temperature at the bottom of the power device casing is... Figure 2 Temperature T in b .

[0086] As shown in Figure 3, in this embodiment, the chip solder layer is divided into 1×50 (i.e., 1 row and 50 columns) units, resulting in 50 cells of the same size.

[0087] As shown in Figure 4, in order to facilitate the subsequent explanation of the aging process, the six elements at the corners of the solder layer are sorted and a finite element simulation model is constructed based on the material parameters of the module.

[0088] Figure 4, enlarged view, shows the six cells located at the corners. Each cell is crack-free, indicating that the chip solder layer is not aged. Besides the chip solder layer, other layers can also be divided into grids.

[0089] Alternatively, the chip solder layer can be divided into different units such as 1×100 or 1×200. Considering that the more units there are, the more simulation aging stages there are, the longer it takes, and the higher the computation time cost, this application preferably divides it into 1×50 units.

[0090] This application uses a method of dividing cells and killing cells (i.e., eliminating cells) to simulate the propagation of solder layer cracks, which is equivalent to discretizing the actual aging process of solder layer crack propagation through "differentiation". Specifically, when the damage of a cell reaches 1, the cell is eliminated.

[0091] Different cell sizes will result in different inelastic strain energy densities due to the influence of other cells, but simulations and experiments have shown that the differences are not significant, and the final analysis results will not be greatly affected. Of course, larger cells simulate fewer crack propagation aging stages, leading to a relatively larger error in lifetime prediction; smaller cells simulate more crack propagation aging stages, better reflecting the actual aging process in experiments, and thus a relatively smaller error in lifetime prediction. Those skilled in the art can determine the number of cells needed based on actual requirements (e.g., accuracy requirements, prediction time costs).

[0092] The more cells are eliminated, the smaller the heat dissipation path of the module becomes, leading to heat accumulation at the chip layer and an increase in junction temperature. Since the bottom temperature of the power device housing mainly depends on the heat sink used to cool the power device (using water cooling or air cooling, in contact with or at a certain distance from the bottom of the power device), when the power module power remains constant, an increase in junction temperature leads to an increase in junction-to-case thermal resistance. The bottom temperature of the power device housing can be directly measured using thermocouples or resistance temperature detectors (RTDs). As more cells are eliminated, the heat dissipation area decreases, and junction temperature accumulates, but the case temperature (bottom temperature of the housing) does not change significantly. In this application, the power cycle time required from crack initiation to a certain increase in junction-to-case thermal resistance (e.g., an increase of 20%) is calculated; this is the remaining lifetime from crack initiation to failure.

[0093] This approach focuses on predicting the remaining lifetime after the crack propagation aging stage. As the crack propagates, the junction-to-shell thermal resistance gradually increases, and this resistance is recorded in real-time during aging tests. When the crack propagates, the junction-to-shell thermal resistance curve will inevitably show an inflection point, and the lifetime at which the crack appeared (crack initiation lifetime N0) can be extracted by consulting the curve. If the crack is small enough that the junction-to-shell thermal resistance of the power device does not change significantly, then the remaining lifetime can be predicted according to this approach.

[0094] In actual aging tests, a constant on / off strategy can be adopted, with no change in power or cooling conditions. The finite element model needs to be fitted with the same operating conditions as the test.

[0095] Even without actual testing, simulation can already obtain the temperature changes, combined stiffness, applied strain, and shell thermal resistance changes at each aging stage. Therefore, without actual testing, it is not necessary to rely on measured data; the inelastic strain energy density of each cell at each aging stage can be obtained solely from simulation data.

[0096] Step 2: Simulate crack propagation of different lengths by plotting different solder layer lengths in finite element software. Then, perform mechanical simulation analysis of different crack lengths in the solder layer to obtain the combined stiffness and applied strain of the solder layer cells for different crack propagation, and create a table, which is then written into the Clech algorithm. In this embodiment, taking the 2D model of the FF150R12ME3G module as an example, crack propagation was simulated by eliminating cells, and then the combined stiffness K and applied strain D of the solder layer corresponding to the crack length were extracted. These were then created into tables, as shown in Tables 1 and 2, and these two tables were written into the Clech algorithm in program form. The existing Clech algorithm introduced in this application can be implemented through Matlab programming, which will be understood by those skilled in the art.

[0097] Step 2: Obtain the combined stiffness and applied strain of the solder layer under different crack propagation lengths through mechanical simulation, create a table, and write it into constitutive equations such as the Clech algorithm;

[0098] In step 2, the solder layer crack propagation failure process is simulated in the finite element method by killing cells. For each mechanical simulation of solder layer crack propagation, the combined stiffness and applied strain of the corresponding cells in the critical area of ​​the solder layer need to be extracted and compiled into a table. This table is then programmed into the Clech algorithm, which can be implemented in Matlab or other software. The purpose of this table is for pre-calculation, facilitating a one-to-one correspondence between the actual shell thermal resistance data and the shell thermal resistance during the crack aging propagation stage simulated in the finite element method. It also allows for the calculation of the corresponding power cycle number that has occurred in the experiment based on the shell thermal resistance data, and the calculation of the accumulated damage.

[0099] In this scheme, the process from crack initiation to a specific crack propagation length is simulated using finite element method.

[0100] The location and direction of simulated crack initiation are determined by setting the operating conditions in the finite element thermodynamic simulation to be identical to those in the aging test. Specifically, the junction temperature fluctuations and turn-on / off times in the simulation must match those in the aging test. Then, the cumulative distribution of inelastic strain energy density in the solder layer of the power device can be obtained through thermodynamic simulation. Locations with higher inelastic strain energy in the solder layer are identified as crack initiation sites. In this scheme, finite element thermodynamic simulation revealed that the inelastic strain energy at the corners of the solder layer is higher; therefore, crack initiation occurs at the corners (the four corners of the rectangle) and propagates towards the center. Generally, it can be considered that the crack propagates diagonally from the corners towards the center.

[0101] During the research, the applicant found that the thermal resistance of the shell was not much different when all cells failed simultaneously starting from the four corners and when failure started from one corner along the length or width direction. Therefore, this application only considers the case of failure starting from one corner along the length or width direction.

[0102] In this application, cells are divided along the width / length direction of the power module, that is, the propagation of cracks on the diagonal of the surface of the cross-section (horizontal section) of the power module is projected onto the length or width direction, which facilitates modeling and calculation.

[0103] The extent of crack propagation is determined by the increment of the junction thermal resistance (JTR). JTR is widely recognized as a failure characteristic of the solder layer; generally, a 20% or 50% increase in JTR is considered solder layer failure. Therefore, in this scheme, as cells are continuously eliminated, the JTR of the module continuously increases. When the JTR increases to 20% or 50%, crack propagation ends. That is, in this application, u% can be 20% or 50%, or other values, as long as the chip solder layer fails when the JTR reaches R. th_u% At that moment.

[0104] In actual IGBT operation, only the junction temperature can be monitored, and the stiffness, strain, and strain energy density cannot be obtained. Therefore, it is necessary to establish the correspondence between stiffness, strain, and junction temperature in advance, and then find the stiffness and strain based on the junction temperature.

[0105] The critical area of ​​the solder layer is the entire kill cell range that causes the thermal resistance of the junction to increase by 20% and the solder layer to fail.

[0106] The combined stiffness mainly refers to the combined stiffness of the solder layer. Once the crack propagates, the structure of the solder layer changes, and its combined stiffness will change.

[0107] The applied strain is also a mechanical property parameter related to the structure and material properties of the solder layer. Here, it refers specifically to the applied strain of the solder layer. Combined stiffness and applied strain are used together to describe the stress reduction line. It is calculated using the shear stress and shear strain of the stress reduction line under different temperature loads, as shown in the following formula: reflecting the geometric changes of the solder and the mismatch in the coefficients of thermal expansion between the two layers near the solder.

[0108]

[0109] in, It is shear strain, which has no dimension. This is shear stress, measured in MPa. T is temperature, measured in °C. Since it is dimensionless, the units on both sides of the equation must be consistent. Therefore, in the table below, the unit of the first parameter K (or assembly stiffness) is MPa, and the unit of the second parameter Z (or imposed strain) is °C. -1 Where: K1 represents the combined stiffness of the first cell in the first aging stage, K2 represents the combined stiffness of the second cell in the second aging stage, and K... 12 Z1 represents the combined stiffness of the second cell in the first aging stage, and so on; Z2 represents the strain applied to the first cell in the first aging stage, Z3 represents the strain applied to the second cell in the second aging stage, and Z4 represents the strain applied to the second cell in the second aging stage. 12 This indicates the strain applied to the second cell in the first aging stage, and so on. For details, please refer to the paper "Reliability Prediction for IGBT Solder Joints Using Clech Algorithm" published by Hua Lu et al. at the "2016 17th International Conference on Electronic Packaging Technology".

[0110]

[0111]

[0112] Step 3: During the aging test, the module junction temperature, case temperature (i.e., the temperature at the bottom of the power device case), and power are acquired in real time online using temperature acquisition methods such as temperature-sensitive electrical parameter method and IR (thermal imager). The junction-to-case thermal resistance (thermal resistance between the chip and the power module substrate case) is also monitored in real time during the aging test. When the test reaches a certain aging level (the i-th aging stage), the junction-to-case thermal resistance R of the power module under aging is obtained at this point. th_i The test conditions were simulated in the finite element method, and the finite element thermal resistance of the shell was obtained from different aging stages, from the solder layer before aging (the initial moment of the first aging stage, i.e., the initial moment of the start of the aging stage) to the specific crack propagation length (the i-th aging stage), using effective methods such as the cell elimination technique in the finite element method. That is, R th(0) R th(1) R th(2) R th(3) ... R th(i-1) R th(i) On the thermal resistance curves of the crusts that have undergone a certain degree of aging tests, find the power cycle numbers N1, N2, N3, ..., N of these crust thermal resistance values. i-1 N i Then, the junction temperature fluctuations obtained from the finite element simulations of these aging stages, along with the combined stiffness and applied strain of the corresponding solder layer cells obtained through table lookup, are substituted into constitutive equations such as the Clech algorithm to calculate the inelastic strain energy density of each cell in the solder layer at different aging stages. Combining the number of test power cycles for different aging stages and the inelastic strain energy density of the corresponding solder layer cells, the accumulated damage value from the experiment can be calculated.

[0113] In this application, there are multiple methods for measuring junction temperature. The module can be disassembled and measured using an infrared thermal imager, or the junction temperature can be measured without disassembling the casing using a temperature-sensitive electrical parameter method (before the aging test, a linear relationship is established between the on-state voltage drop of the power device under low current and different temperatures. During the aging test, the chip junction temperature can also be indirectly obtained by measuring the on-state voltage drop of the power device under low current). These junction temperature measurement methods have been proven and applied in the literature, and those skilled in the art will understand them.

[0114] The first aging stage refers to the aging stage from the start of the aging process for power devices until the first cell fails.

[0115] The method for calculating the power cycle count consumed in an aging stage after its completion is as follows: In the finite element model simulating different aging stages of crack propagation, each cell in the solder layer undergoes a certain degree of damage. However, the degree of damage is affected by the cell's position; the closer the cell is to the crack propagation point, the greater the inelastic strain energy density and the greater the damage. The reason for obtaining the corresponding test power cycle counts for each aging stage before the i-th aging stage is to calculate the accumulated damage of the aging test module in each aging stage, so as to facilitate the subsequent calculation of the module's remaining lifespan.

[0116] As the power cycling test progresses to a certain point, the thermal resistance of the junction increases significantly. For example, when the thermal resistance increases by 10%, it is necessary to know the number of power cycles required when the solder layer reaches the failure standard of the power cycling test, i.e., when the thermal resistance of the junction increases by 20%.

[0117] The thermal resistance of the junction can be obtained through finite element thermal simulation or by establishing an RC thermal network. In this example, finite element thermal simulation was used to obtain the crack propagation length when the junction thermal resistance increases by 10%, which is the length of four cells to be eliminated. The four cells eliminated are located at the corners of the solder layer (i.e., four cells from the end of the solder layer inwards). The location of cell elimination is determined by the results of the finite element thermal simulation. Cell elimination occurs first at locations with high accumulated inelastic strain energy density. Different cell elimination locations will yield different results. At this point, the power cycle number of the aging test was recorded as N5 = 151030. Finite element thermal simulation then yielded the increase in junction thermal resistance when 3, 2, 1, and 0 cells were eliminated, as shown in Table 3. Based on these increases in junction thermal resistance, the corresponding power cycle numbers N4 = 135550, N3 = 125320, N2 = 120410, and ΔN1 = 112150 were found on the junction thermal resistance curve of the aging test where the junction thermal resistance increased by 10%, as shown in Table 4. That is, ΔN2 = N2 - ΔN1, and ΔN3 = N3 - N2. Then, the 5 cells starting from the corner of the solder layer (i.e., the boundary of the rectangular shape on the side surface of the solder layer) were eliminated. It was found that the increase in thermal resistance had reached 23.2%, meeting the failure criteria of the solder layer. Finally, the temperature fluctuation of the solder layer cells after eliminating 5 cells was recorded. Then, the temperature fluctuations are fed into the Clech algorithm, and the corresponding combined stiffness and applied strain are obtained by looking up tables (the tables obtained in step 2) (the underlined data in Tables 1 and 2 represent the combined stiffness and applied strain of the 6th cell at different aging stages). The Clech algorithm is run, and the combined stiffness and applied strain obtained by looking up the tables are substituted into the constitutive equations of the material in the Clech algorithm to obtain the inelastic strain energy density of the 6th cell at the six aging stages. The corresponding damage accumulation of the 6th cell at different aging stages is also calculated and shown in Table 4. It can be seen that:

[0118]

[0119] The thermal resistance of the junction shell is obtained by finite element thermal simulation and the establishment of an RC thermal network, which is an existing technology and can be understood by those skilled in the art.

[0120] At this point, the number of power cycles required to increase from 10% to 23.2% of the shell thermal resistance during the aging test can be predicted using the method proposed in this invention. Next, the power cycle number (N) of the aging test from a 10% increase in the thermal resistance of the solder layer to failure (a 20% increase in the thermal resistance of the solder layer) is calculated by taking the percentage. re_pro :

[0121]

[0122] In this invention, the aging stages are approximated as a linear relationship, meaning that N can be calculated by determining the proportion of each stage. re_pro .

[0123] When the actual aging test reaches a 10% increase in junction-case thermal resistance, the remaining lifetime needs to be predicted. According to the remaining lifetime prediction method proposed in this embodiment of the invention, the remaining lifetime was calculated to be 8655 cycles. To verify the effectiveness of the method, the actual aging test was continued until the junction-case thermal resistance increased by 20%, reaching the solder layer failure standard. The number of cycles from the start of use of the power device to failure was measured to be 159250 cycles (i.e., the number of power cycle cycles corresponding to a 20% increase in junction-case thermal resistance). Therefore, the actual remaining power cycle count is 159250 cycles - 151030 cycles = 8220 cycles. Thus, the prediction result N of the method in this embodiment of the invention is... re_pro The prediction error is 5.3% compared to the actual number of remaining power cycles. Figure 6 As shown, the entire prediction method takes less than one hour, demonstrating that the remaining lifetime prediction method proposed in this invention is fast, real-time, feasible, and highly accurate.

[0124]

[0125] Step 4: Next, continue to simulate crack propagation using finite element method or other methods, from the (i+1)th aging stage until the solder layer failure criteria are met. Then, obtain the temperature fluctuations of the critical cells of the solder layer at these aging stages from the (i+1)th aging stage to the point where the solder layer failure criteria are met, and input them into constitutive equations such as the Clech algorithm. In this algorithm, obtain the combined stiffness and applied strain of the solder layer cells at the corresponding crack propagation length by looking up a table. Calculate the inelastic strain energy density of the critical area cells of the solder layer at different aging stages. Finally, calculate the number of power cycles required for each aging stage from the i-th aging stage to the crack propagation length, i.e., the remaining lifetime of the module.

[0126] In step 4, the failure criterion for the solder layer is that the junction thermal resistance of the module in the aging stage increases by 20% compared to the junction thermal resistance of the unaged module. As the simulated crack propagation cells are eliminated, the heat dissipation area of ​​the solder layer decreases, and the junction temperature increases accordingly, causing the junction thermal resistance to gradually increase as the cells are eliminated in stages of aging.

[0127] Assuming each aging stage kills one cell, the total inelastic strain energy of each cell is... It is fixed. To facilitate the subsequent description of the damage accumulation of a cell at multiple different aging stages, the inelastic strain energy consumed by each cell is normalized, that is, the unit damage accumulation is defined. for The reciprocal of the power cycle. Each cell consumes a certain amount of inelastic strain energy during each power cycle. The inelastic strain energy consumed by the cell multiplied by the unit damage accumulation is the normalized inelastic strain energy consumed by the cell, which represents the corresponding damage accumulation on the cell. As the power cycle continues, once the damage accumulation on the cell reaches 1, the cell is terminated. Through accelerated aging tests, the power cycle period at which solder layer cracks and voids initiation occur in the IGBT module can be extracted. Then, the inelastic strain energy density at the corners of the solder layer extracted from the unaged module was combined with the data. (It obtains the temperature fluctuation of the solder layer cell through thermal simulation and the combined stiffness and applied strain of the solder layer cell through mechanical simulation, and then calculates it using the Clech algorithm.) The total inelastic strain energy of each cell of the solder layer can be calculated, i.e., the cumulative unit damage. As shown in equation (4.11):

[0128]

[0129] In this application, the switching on and off of the power device once is referred to as a power cycle. That is, the period from when the IGBT module starts working until the IGBT module is de-energized is referred to as one set / one power cycle test.

[0130] Each aging stage kills one cell, meaning it's considered a cell to be invalid. The eliminated cell is not further calculated and remains invalid in subsequent stages. Its thermal simulation is not involved in the calculations.

[0131] Substituting the values ​​into the Clech algorithm, the inelastic strain energy density is calculated. , is an existing technology, please refer to the literature: Reliability Prediction for IGBT Solder Joints Using Clech Algorithm; Lifetime Prediction of IGBT Modules in Suspension Choppers of Medium / Low-Speed ​​MaglevTrain Using an Energy-Based Approach; Reliability of Large Area Solder Jointswithin IGBT Modules: Numerical Modeling and Experimental Results.

[0132] When counting the number of power cycles, the count is incremented by 1 for each turn-on / off cycle (i.e., power cycle). This can be implemented through programming in a microcontroller such as a DSP or a data acquisition card, as those skilled in the art can understand.

[0133] This scheme proposes that the total inelastic strain energy of each cell is the same. Each power cycle consumes a certain amount of inelastic strain energy, i.e., the inelastic strain energy density. Therefore, subtracting the consumed inelastic strain energy from the total inelastic strain energy yields the remaining inelastic strain energy of that cell after a certain number of power cycles. Then, dividing this by the simulated inelastic strain energy density of that cell in the subsequent aging stage allows us to determine the number of power cycles required to eliminate that cell. It cannot be said that the number of power cycles for a cell is related to the inelastic strain energy consumed by that cell.

[0134] If the total inelastic strain energy of a cell is If the cell is completely damaged after N power cycles, then the cumulative damage per unit for each cell in each cycle should be: However, for the convenience of subsequently describing the damage accumulation in multiple different aging stages, As a unit damage accumulation, it facilitates the subsequent normalization of the inelastic strain energy consumed by each cell.

[0135] Inelastic strain energy density represents the degree of damage to a cell within a power cycle. A cell fails when its inelastic strain energy is depleted. The time from when a cell begins operation until it is eliminated represents the depletion of all its inelastic strain energy.

[0136] Assuming that the remaining life of the solder layer is predicted from the point of crack initiation, i.e., accelerated aging tests have been run for [number] days... The crack propagation aging stage, i.e., the first aging stage, was simulated by eliminating one cell at the corner of the solder layer, and thermal simulation was performed to extract the thermal resistance R of the junction shell. th_1 Determine if R th_1 ≥1.2 R th_0 If the judgment is not valid (no), run the transient thermal simulation or RC thermal network method corresponding to the second aging stage to obtain the temperature fluctuation, and combine it with the Clech algorithm to calculate the inelastic strain energy density of the cell in the dangerous area of ​​the solder layer. At this time, the second cell has undergone the first aging stage. Each power cycle, i.e., a certain amount of damage is accumulated. The calculation method is shown in equation (4.12):

[0137]

[0138] In the formula, The inelastic strain energy density lost by a cell that is about to fail during the crack initiation and aging stage.

[0139] Similarly, cell i went through the first aging stage. Each power cycle also consumes corresponding inelastic strain energy, calculated as shown in equation (4.12):

[0140]

[0141] In the formula, To determine the inelastic strain energy density of the i-th cell in the crack propagation aging stage during the first aging stage, finite element thermal simulation can be performed to extract the temperature fluctuation of the corresponding solder layer cell. At the same time, the corresponding combined stiffness and applied strain can be obtained by looking up the table, and the inelastic strain energy density of the cell in the dangerous area of ​​the solder layer can be calculated by combining the Clech algorithm.

[0142] Therefore, subtracting the accumulated damage of the second cell from the damage threshold of the first cell yields the remaining accumulated damage of the second cell. This remaining accumulated damage is then divided by the unit accumulated damage and the inelastic strain energy density of the second cell after crack formation, indicating impending failure. Thus, the power cycle period ΔN2 in the second aging stage (crack propagation, elimination of the second cell) can be obtained, as shown in equation (4.13):

[0143]

[0144] In the above description, the process of eliminating the first cell is the first aging stage. In the first aging stage, the second cell has not yet been eliminated and will be eliminated in the next aging stage (the second aging stage). It is the inelastic strain energy density of the second cell in the first aging stage. It is obtained from finite element thermodynamic simulation results or calculations using the Clech algorithm.

[0145] Therefore, the number of power cycles required to eliminate the second cell (i.e., from the initial moment to the moment the second cell is eliminated) is:

[0146]

[0147] Then, the process of eliminating the third cell, i.e., the third aging stage, can be simulated in a manner similar to the second aging stage, where the third cell experiences the power cycle of the first aging stage. and the power cycle of the second aging stage The inelastic strain energy density of the third cell in the third aging stage is Therefore, the number of power cycles required to eliminate the first cell and then the third cell can be calculated. :

[0148]

[0149] In summary, the number of power cycle cycles (or power loop counts) required to eliminate cell i. This depends on the damage accumulated in the cell during the previous aging stages (stage 1, stage 2, ..., stage i-1). Therefore:

[0150]

[0151] The upper surface of the power device is preferably square. A two-dimensional model can be created using the structure along the height and width directions of the power device, or it can be created using the structure along the height and length directions. Of course, the surface of the power device can also be rectangular or other shapes.

[0152] During the testing of this application, the power device can be kept in a continuously powered-on state (constantly switched on and off). However, the applicant discovered during the research that even if the power module is powered off after operating for a period of time and then restarted, after several power cycles, the data can approach or return to the original junction-to-case thermal resistance curve. That is, even if the power module is powered off, it does not affect the prediction accuracy of this application.

[0153]

[0154]

[0155] After using the method of this invention, the prediction accuracy is about 95% and the prediction time is within one hour.

[0156] This invention provides an online prediction method for remaining life that can accurately describe the progressive aging process of solder layer crack propagation. Starting from the failure mechanism of the solder layer, this prediction method decomposes the solder layer degradation process into multiple "discrete" aging stages and focuses on the damage accumulation effect during solder layer crack propagation, thus providing a more accurate and reasonable description of the solder layer fatigue aging process.

[0157] In the process of predicting remaining lifetime in this invention, firstly, a data table of combined stiffness and applied strain of solder layer cells at different aging stages is obtained through finite element method. Then, the shell thermal resistance is obtained by finite element simulation or other thermal calculation methods to simulate the aging process of solder layer crack initiation and propagation by eliminating solder layer cells. This is then matched one-to-one with the shell thermal resistance monitored in real time during the fatigue aging process that has already occurred in the test. The test power cycle number corresponding to these shell thermal resistance values ​​is found in the shell thermal resistance curve of the power cycle test. At the same time, the combined stiffness and applied strain of the solder layer are obtained by comparison and table lookup. The inelastic strain energy density of solder layer cells at different aging stages is obtained by combining the Clech algorithm or similar methods. Then, by using the found test power cycle number and the calculated inelastic strain energy density of the solder layer cells, the accumulated damage that has occurred in the aging test after a certain number of cycles is calculated. Finally, based on the known accumulated test damage, the remaining lifetime is predicted and evaluated for subsequent fatigue aging tests until failure. This establishes an online prediction method for remaining lifetime that can monitor the degree of damage to the module solder layer in real time and accurately predict solder layer failure.

[0158] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0159] The embodiments of the present invention have been described in detail above, but the content described is only a preferred embodiment of the present invention and should not be considered as limiting the scope of the present invention. All equivalent changes and modifications made within the scope of the present invention should still fall within the scope of this patent. After reading this invention, any modifications of the present invention in various equivalent forms by those skilled in the art fall within the scope defined by the appended claims. Unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

Claims

1. A method for predicting the remaining lifetime of power devices based on the crack length propagation of the chip solder layer, characterized in that: The first straight line (La) is defined as a straight line that extends along the height direction on the side of the power device and divides the area of ​​the chip layer on the side of the power device equally. The side of the power device is a surface composed of the height of the power device and the length / width of the power device. The method for predicting the remaining lifetime of power devices includes: A. Based on the material and size parameters of the power device's packaging structure, establish a finite element two-dimensional model / finite element three-dimensional model corresponding to the structure located on the side of the first straight line (La) on the side of the power device; The two dimensions of the finite element two-dimensional model correspond to the height of the power device and the length / width of the power device, respectively. In the finite element three-dimensional model, two dimensions correspond to the height and length / width of the power device, respectively, and the other dimension corresponds to the width / length of the power device. The simulation environment of the finite element two-dimensional model / finite element three-dimensional model is consistent with the working environment of the power device in the actual experiment; Along the direction corresponding to the length / width direction of the power device in the finite element two-dimensional model / finite element three-dimensional model, the chip solder layer model in the finite element two-dimensional model / finite element three-dimensional model is divided into K cells; From the end of the chip solder layer model corresponding to the end of the actual chip solder layer, to the other end of the chip solder layer model corresponding to the center of the length / width of the actual chip solder layer, the first cell, the second cell, ..., the Kth cell are set sequentially, with 10≤K≤100; The finite element two-dimensional model / finite element three-dimensional model is sequentially subjected to the first aging stage, the second aging stage, ..., the S+1th aging stage. The length of the solder layer crack increases with the increase of the number of failed cells. The completion time of the kth aging stage is the time when the kth cell is eliminated, k = 1, 2, ..., S+1. Where the value of S satisfies the following formula: R th(S) <R th_u％ ≤R th(S+1) ; Among them, R th(0) R is the initial junction-to-case thermal resistance of the power device. th(k) R is the junction-to-case thermal resistance of the power device at the completion time of the kth aging stage. th_u％ The junction-to-shell thermal resistance corresponding to the preset percentage u% is determined when the chip solder layer fails at a junction-to-shell thermal resistance of R. th_u％ The moment; Real-time monitoring of the power cycle count of power devices and the junction-to-case thermal resistance of power devices corresponding to the power cycle count in actual tests, thereby obtaining the correspondence between the power cycle count and the junction-to-case thermal resistance; When it is necessary to calculate the junction-to-case thermal resistance R of the current power device x The number of power cycles L required from the moment the chip solder layer fails to the moment of failure x When, then determine R x ≥R th(1) If the condition is true, then determine the junction-to-case thermal resistance R of the current power device. x In the interval [R] th(1) ,R th(2) ), [R th(2) ,R th(3) ), ..., [R th(S) ,R th(S+1) If it falls within a specific interval, then monitor it; otherwise, continue monitoring. If we determine R x In the interval [R] th(m) ,R th(m+1) In the given equation, where m is an integer and 1 ≤ m ≤ S, the junction-to-case thermal resistance R of the power device can be calculated using the following formula. x The number of power cycles L required from the moment the chip solder layer fails to the moment of failure x : in: Wherein, ΔN1 is the relationship between R and the given correspondence. th(1) The corresponding number of power cycles, ΔN i Let ΔW be the number of power cycles performed in the i-th aging stage, and ΔW1 be the inelastic strain energy density lost by the first cell in each power cycle of the first aging stage. i Let ΔW be the inelastic strain energy density of the i-th cell during each power cycle loss in the i-th aging stage. j,i Let D be the inelastic strain energy density of the i-th cell during each power cycle loss in the j-th aging stage. j,i Let S be the damage accumulated by the i-th cell in the j-th aging stage, where 2≤i≤S+1.

2. The method for predicting the remaining lifetime of power devices according to claim 1, characterized in that: Using the Clech algorithm or performing finite element thermodynamic simulation on the finite element 2D / 3D model, ΔW1 and ΔW can be obtained. i ΔW j,i The value of .

3. The method for predicting the remaining lifetime of power devices according to claim 1, characterized in that: 30≤K≤200。 4. The method for predicting the remaining lifetime of power devices according to claim 3, characterized in that: 50≤K≤100。 5. The method for predicting the remaining lifetime of power devices according to claim 1, characterized in that: Junction-shell thermal resistance R th The calculation formula is: Among them, T j T is the estimated junction temperature. c P is the temperature at the bottom of the power device housing. Loss This refers to the power of the power device.

6. The method for predicting the remaining lifetime of power devices according to claim 1, characterized in that: The operating environment includes the power of the power device, the turn-on and turn-off times of the power device, and the cooling conditions applied to the power device.

7. The method for predicting the remaining lifetime of power devices according to claim 6, characterized in that: The power devices are turned on for the same amount of time each time and turned off for the same amount of time each time.

8. A power device remaining lifetime prediction system based on solder layer crack length propagation, characterized in that, Includes a computer device; said computer device is configured to perform the steps of the remaining lifetime prediction method according to any one of claims 1-7.

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