Semiconductor device and method of manufacturing the same
By introducing lightly doped regions with lower doping concentrations and planar junction structures into semiconductor devices, the problem of insufficient breakdown voltage in traditional semiconductor structures is solved, achieving higher breakdown voltage and withstand voltage capability, making it suitable for high-voltage analog integrated circuits.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI DINGTAI JIANGXIN TECH CO LTD
- Filing Date
- 2023-02-02
- Publication Date
- 2026-07-24
AI Technical Summary
Traditional semiconductor structures have difficulty achieving the desired high voltage breakdown voltage, thus failing to meet user needs.
Lightly doped regions with lower doping concentrations are used to form cylindrical and planar junctions to improve breakdown voltage. This includes forming a planar junction between the substrate and the buried layer. The use of lightly doped regions with lower doping concentrations makes breakdown more likely to occur at the bottom of the well region and the buried layer. A ring structure and field oxygen structure with multiple lightly doped regions are combined to isolate the electrode lead-out region.
It effectively improves the breakdown voltage of semiconductor devices, meets user requirements, and enhances the withstand voltage and reliability of NPN transistors, making it suitable for high-voltage analog integrated circuits.
Smart Images
Figure CN115995484B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to semiconductor devices and their manufacturing methods. Background Technology
[0002] In related technologies, the semiconductor structure includes a P-type substrate and an N-type buried layer disposed within the substrate. An NPN transistor is formed in the P-well, while the N-type buried layer is used for isolation. The emitter is led out from the P-well, and the collector is led out from the N-well. The PN junction formed between the P-well and the N-well is used to improve the breakdown voltage of the semiconductor structure.
[0003] However, the breakdown voltage of traditional semiconductor structures is difficult to reach the desired high voltage value, which cannot meet the user's needs. Summary of the Invention
[0004] Therefore, it is necessary to provide a semiconductor device and its manufacturing method to address the problem that the breakdown voltage of traditional semiconductor structures is difficult to reach the expected high voltage value and cannot meet the user's needs.
[0005] According to one aspect of this application, a semiconductor device is provided, comprising:
[0006] The substrate has a first type of conductivity;
[0007] A buried layer is formed within the substrate and has a second conductivity type, the first conductivity type being the opposite of the second conductivity type;
[0008] A first well region is located on the upper surface of the buried layer and has the first conductivity type;
[0009] The second well region is located on the upper surface of the buried layer and is spaced apart from the first well region, and has the second conductivity type;
[0010] The first electrode lead-out region and the base lead-out region are both formed within the upper surface layer of the first well region and are electrically isolated from each other; the base lead-out region is located outside the first electrode lead-out region; the first electrode lead-out region has the second conductivity type, and the base lead-out region has the first conductivity type;
[0011] The second electrode lead-out region is formed within the upper surface layer of the second well region and has the second conductivity type; and
[0012] Multiple lightly doped regions, including a first lightly doped region and a second lightly doped region formed on the upper surface layer of the first well region, wherein the first lightly doped region is located between the first electrode lead-out region and the base lead-out region, and the second lightly doped region is located between the base lead-out region and the second electrode lead-out region;
[0013] The lightly doped region has the first conductivity type, and the doping concentration of the lightly doped region is less than the doping concentration of the first well region.
[0014] In one embodiment, the first conductivity type is P-type, and the second conductivity type is N-type;
[0015] The first electrode lead-out region is led out as the first electrode. When the first electrode is input with voltage, the first electrode lead-out region, the base lead-out region and the first well region together with the second electrode lead-out region constitute an NPN transistor.
[0016] In one embodiment, the second electrode lead-out region is led out as a second electrode;
[0017] When a positive voltage is input to the first electrode, the first electrode serves as the emitter of the NPN transistor, the second electrode serves as the collector of the NPN transistor, and the base lead-out region and the first well region together serve as the base region of the NPN transistor.
[0018] In one embodiment, the first lightly doped region is a ring structure and is disposed around the first electrode lead-out region; or
[0019] The first electrode lead-out region is provided in multiple ways, and the multiple first electrode lead-out regions are electrically connected to each other to serve as the first electrode; the upper surface layer of the first well region is provided with multiple base lead-out regions and multiple first lightly doped regions that correspond one-to-one with the first electrode lead-out regions; each first lightly doped region is located between the corresponding first electrode lead-out region and the corresponding base lead-out region.
[0020] In one embodiment, the second lightly doped region is a ring structure and is disposed around the first electrode lead-out region; or
[0021] The second electrode lead-out region is provided in multiple ways, and the multiple second electrode lead-out regions are electrically connected to each other to serve as second electrodes; the upper surface layer of the first well region is provided with multiple base lead-out regions and multiple second lightly doped regions that correspond one-to-one with the second electrode lead-out regions; each second lightly doped region is located between the corresponding base lead-out region and the corresponding second electrode lead-out region.
[0022] In one embodiment, the plurality of lightly doped regions further includes a third lightly doped region formed in the buried layer and located around the second electrode lead-out region, the third lightly doped region being in contact with the second well region.
[0023] In one embodiment, the semiconductor device further includes a plurality of field oxygen structures corresponding one-to-one with the lightly doped region, each of the field oxygen structures being formed on the upper surface layer of the corresponding lightly doped region.
[0024] According to another aspect of this application, a method for manufacturing a semiconductor device is provided, comprising:
[0025] A substrate is provided; the substrate has a first conductivity type;
[0026] A buried layer is formed within the substrate; the buried layer has a second conductivity type, the first conductivity type being the opposite of the second conductivity type;
[0027] A first well region is formed on the upper surface of the buried layer, and the first well region has the first conductivity type;
[0028] A second well region is formed on the upper surface layer of the buried layer, which is spaced apart from the first well region, and the second well region has the second conductivity type;
[0029] Multiple lightly doped regions are formed; the multiple lightly doped regions include a first lightly doped region and a second lightly doped region formed on the upper surface layer of the first well region;
[0030] A first electrode lead-out region and a base lead-out region are formed in the upper surface layer of the first well region, which are electrically isolated from each other; the base lead-out region is located outside the first electrode lead-out region; the first electrode lead-out region has the second conductivity type, and the base lead-out region has the first conductivity type;
[0031] A second electrode lead-out region having the second conductivity type is formed in the upper surface layer of the second well region;
[0032] Wherein, the first lightly doped region is located between the first electrode lead-out region and the base lead-out region, and the second lightly doped region is located between the base lead-out region and the second electrode lead-out region;
[0033] The lightly doped region has the first conductivity type, and the doping concentration of the lightly doped region is less than the doping concentration of the first well region.
[0034] In one embodiment, forming a plurality of lightly doped regions specifically includes:
[0035] Ions of a first conductivity type are implanted into the substrate to form multiple initial lightly doped regions;
[0036] A field oxygen layer is formed on the upper surface of the substrate, covering multiple initial lightly doped regions, and the multiple initial lightly doped regions are heated and pushed into a well using the field oxygen layer formation process, so that each initial lightly doped region is pushed into a well to form a lightly doped region.
[0037] In one embodiment, the method for manufacturing the semiconductor device further includes:
[0038] A passivation layer covering the field oxide layer is formed on the upper surface of the substrate;
[0039] The side of the passivation layer that faces away from the field oxygen layer is planarized.
[0040] A first conductive plug, a second conductive plug, and a third conductive plug are formed within the passivation layer, penetrating the passivation layer.
[0041] A first electrode, a second electrode, and a base electrode are formed on the passivation layer;
[0042] The first electrode is electrically connected to the first electrode lead-out area through the first conductive plug, the second electrode is electrically connected to the second electrode lead-out area through the second conductive plug, and the base is electrically connected to the base lead-out area through the third conductive plug.
[0043] The semiconductor device and its manufacturing method described above, since the doping concentration of the lightly doped region is lower than that of the first well region, when the first electrode is input with voltage, the first lightly doped region with a lower doping concentration is located between the first electrode lead-out region and the base lead-out region. The first lightly doped region, the second lightly doped region, and the first well region have the same conductivity type, while the first lightly doped region has the opposite conductivity type to the first electrode lead-out region, and the second lightly doped region has the opposite conductivity type to the second electrode lead-out region. The lower doping concentration of the first lightly doped region allows the cylindrical junction (PN junction) formed between the first lightly doped region and the first electrode lead-out region to have a higher breakdown voltage. Similarly, the lower doping concentration of the second lightly doped region allows the cylindrical junction (PN junction) formed between the second lightly doped region and the second electrode lead-out region to have a higher breakdown voltage. This makes breakdown more likely to occur at the bottom of the first well region and the bottom of the buried layer. Both the PN junction formed between the first well region and the buried layer and the PN junction formed between the substrate and the buried layer are planar junctions, and planar junctions have a higher breakdown voltage than cylindrical junctions. Thus, the breakdown voltage of the semiconductor device can be effectively improved to meet the user's requirements. Attached Figure Description
[0044] Figure 1 A schematic diagram of the structure of a semiconductor device according to an embodiment of this application is shown;
[0045] Figure 2 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application is shown;
[0046] Figures 3(a)-3(d) A schematic diagram illustrating the manufacturing process of a semiconductor device according to an embodiment of this application is shown;
[0047] Figure 4 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application is shown;
[0048] Figure 5 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application is shown.
[0049] In the figure: 110, substrate; 111, sacrificial layer; 112, silicon nitride layer; 120, buried layer; 130, first well region; 140, second well region; 150, first electrode lead-out region; 160, base lead-out region; 170, second electrode lead-out region; 180, lightly doped region; 181, first lightly doped region; 182, second lightly doped region; 183, third lightly doped region; 1801, initial lightly doped region; 190, field oxygen structure. Detailed Implementation
[0050] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0052] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.
[0053] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0054] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0055] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.
[0056] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.
[0057] Figure 1 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application.
[0058] Please see Figure 1 The semiconductor device provided in one embodiment of this application includes a substrate 110, a buried layer 120, a first well region 130, a second well region 140, a first electrode lead-out region 150, a base lead-out region 160, a second electrode lead-out region 170, and a plurality of lightly doped regions 180.
[0059] The substrate 110 has a first conductivity type, the buried layer 120 is formed in the substrate 110, and the buried layer 120 has a second conductivity type, the first conductivity type being the opposite of the second conductivity type.
[0060] In this embodiment, one of the first conductivity type and the second conductivity type is P-type, and the other is N-type. For example, the first conductivity type is P-type, and the second conductivity type is N-type; or, the first conductivity type is N-type, and the second conductivity type is P-type. For instance, in this embodiment, the first conductivity type is P-type, the second conductivity type is N-type, the substrate 110 has a P-type conductivity type, and the buried layer 120 has an N-type conductivity type.
[0061] The first well region 130 is disposed on the upper surface of the buried layer 120 and has a first conductivity type. The second well region 140 is disposed on the upper surface of the buried layer 120 and is spaced apart from the first well region 130. The second well region 140 has a second conductivity type. The first well region 130 and the second well region 140 have opposite conductivity types, and a PN junction can be formed between the first well region 130 and the second well region 140.
[0062] Both the first electrode lead-out region 150 and the base lead-out region 160 are formed within the upper surface layer of the first well region 130, and are electrically isolated from each other. The base lead-out region 160 is located outside the first electrode lead-out region 150, the first electrode lead-out region 150 has a second conductivity type, the base lead-out region 160 has a first conductivity type, and the second electrode lead-out region 170 is formed within the upper surface layer of the second well region 140, and also has a second conductivity type.
[0063] Thus, since the overall structure formed by the base lead-out region 160 and the first well region 130 has the opposite conductivity type to the first electrode lead-out region 150, and the overall structure formed by the base lead-out region 160 and the first well region 130 has the opposite conductivity type to the overall structure formed by the second electrode lead-out region 170 and the second well region 140, a PN junction can be formed between the overall structure formed by the base lead-out region 160 and the first well region 130 and the first electrode lead-out region 150, and a PN junction can be formed between the overall structure formed by the base lead-out region 160 and the first well region 130 and the overall structure formed by the second electrode lead-out region 170 and the second well region 140. Furthermore, the voltage bias of the PN junction formed between the first electrode lead-out region 150 and the base lead-out region 160 is opposite to that of the PN junction formed between the base lead-out region 160 and the second electrode lead-out region 170. The overall structure formed by the first electrode lead-out region 150, the base lead-out region 160 and the first well region 130, together with the second electrode lead-out region 170, constitutes a transistor. For example, if the first conductivity type is P-type and the second conductivity type is N-type, the first electrode lead-out region 150 is led out as the first electrode. When the first electrode is input with voltage, the first electrode lead-out region 150, the base lead-out region 160 and the first well region 130 together with the second electrode lead-out region 170 constitute an NPN transistor.
[0064] The plurality of lightly doped regions 180 include a first lightly doped region 181 and a second lightly doped region 182 formed on the upper surface of the first well region 130. The first lightly doped region 181 is located between the first electrode lead-out region 150 and the base lead-out region 160, and the second lightly doped region 182 is located between the base lead-out region 160 and the second electrode lead-out region 170. The second lightly doped region 182 also extends to the upper surface of the second well region 140 in order to better isolate the base lead-out region 160 and the second electrode lead-out region 170.
[0065] Since the lightly doped region 180 has a first conductivity type, and the doping concentration of the lightly doped region 180 is less than the doping concentration of the first well region 130, when the first electrode input voltage is applied, the first lightly doped region 181 with a lower doping concentration is located between the first electrode lead-out region 150 and the base lead-out region 160. The first lightly doped region 181, the second lightly doped region 182, and the first well region 130 have the same conductivity type. The first lightly doped region 181 has an opposite conductivity type to the first electrode lead-out region 150, and the second lightly doped region 182 has an opposite conductivity type to the second electrode lead-out region 170. The lower doping concentration of the first lightly doped region 181 allows the cylindrical junction (PN junction) formed between the first lightly doped region 181 and the first electrode lead-out region 150 to have a higher breakdown voltage, reducing the first electrode input voltage. The possibility of breakdown between the lightly doped region 181 and the first electrode lead-out region 150 can be reduced by using a second lightly doped region 182 with a lower doping concentration. This allows the cylindrical junction (PN junction) formed between the second lightly doped region 182 and the second electrode lead-out region 170 to have a higher breakdown voltage, thus reducing the possibility of breakdown between the second lightly doped region 182 and the second electrode lead-out region 170. This makes it easier for breakdown to occur at the bottom of the first well region 130 and the bottom of the buried layer 120. The PN junction formed between the first well region 130 and the buried layer 120, as well as the PN junction formed between the substrate 110 and the buried layer 120, are both planar junctions. Compared to cylindrical junctions, planar junctions have a higher breakdown voltage. In this way, the breakdown voltage of the semiconductor device can be effectively improved to meet the user's application requirements.
[0066] Furthermore, multiple lightly doped regions 180 can redistribute the concentration of P-type ions in the base region of the NPN transistor, thereby changing the electric field in the base region of the NPN transistor and reducing the electric field strength. This is beneficial for improving the reverse breakdown voltage of the semiconductor device and for its application in high-voltage analog integrated circuits.
[0067] In some embodiments, the doping concentration of the lightly doped region 180 is on the order of magnitude smaller than that of the first well region 130, resulting in a higher breakdown voltage for the cylindrical junction (PN junction) formed between the first lightly doped region 181 and the first electrode lead-out region 150, and a higher breakdown voltage for the cylindrical junction (PN junction) formed between the second lightly doped region 182 and the second electrode lead-out region 170. This makes breakdown more likely to occur at the bottom of the first well region 130 and the bottom of the buried layer 120, which is more conducive to improving the breakdown voltage of the semiconductor device.
[0068] In some embodiments, the second electrode lead-out region 170 is led out as the second electrode. When the first electrode is supplied with a positive voltage, the first electrode serves as the emitter of the NPN transistor, the second electrode serves as the collector of the NPN transistor, and the base lead-out region 160 and the first well region 130 together serve as the base region of the NPN transistor.
[0069] In some embodiments, the first lightly doped region 181 is a ring structure and is disposed around the first electrode lead-out region 150. The first lightly doped region 181 can be used to isolate the first electrode lead-out region 150 and the base lead-out region 160 from each other.
[0070] In other embodiments, multiple first electrode lead-out regions 150 are provided, and the multiple first electrode lead-out regions 150 are electrically connected to serve as first electrodes. The upper surface layer of the first well region 130 is provided with multiple base lead-out regions 160 and multiple first lightly doped regions 181, each corresponding to one of the first electrode lead-out regions 150. Each first lightly doped region 181 is located between the corresponding first electrode lead-out region 150 and the corresponding base lead-out region 160.
[0071] Since the multiple first electrode lead-out regions 150 are electrically connected to serve as first electrodes, and each first electrode corresponds to multiple first electrode lead-out regions 150, it is beneficial to improve the electrical conductivity of the first electrode during use, thereby improving the voltage withstand capability and reliability of the semiconductor device. Furthermore, each first lightly doped region 181 is disposed between the corresponding first electrode lead-out region 150 and the corresponding base lead-out region 160, which also helps to improve the voltage withstand capability and reliability of the semiconductor device.
[0072] In some embodiments, the second lightly doped region 182 is a ring structure and is disposed around the first electrode lead-out region 150.
[0073] The second lightly doped region 182, which has a ring structure, can effectively isolate the base lead-out region 160 and the second electrode lead-out region 170 from each other.
[0074] In other embodiments, multiple second electrode lead-out regions 170 are provided, and the multiple second electrode lead-out regions 170 are electrically connected to serve as second electrodes. The upper surface layer of the first well region 130 is provided with multiple base lead-out regions 160 and multiple second lightly doped regions 182, each corresponding to one of the second electrode lead-out regions 170, and each second lightly doped region 182 is located between the corresponding base lead-out region 160 and the corresponding second electrode lead-out region 170.
[0075] Since the multiple second electrode lead-out regions 170 are electrically connected to serve as second electrodes, and each second electrode has multiple second electrode lead-out regions 170, it is beneficial to improve the electrical conductivity of the second electrode during use, thereby improving the voltage withstand capability and reliability of the semiconductor device. Furthermore, the fact that each second lightly doped region 182 is disposed between the corresponding base lead-out region 160 and the corresponding second electrode lead-out region 170 also helps to improve the voltage withstand capability and reliability of the semiconductor device.
[0076] In some embodiments, the plurality of lightly doped regions 180 further include a third lightly doped region 183, which is formed in the buried layer 120 and located on the periphery of the second electrode lead-out region 170, and the third lightly doped region 183 is in contact with the second well region 140.
[0077] Because the third lightly doped region 183 has a low doping concentration, the cylindrical junction (PN junction) formed between the third lightly doped region 183 and the second electrode lead-out region 170 has a high breakdown voltage, which reduces the possibility of breakdown between the second well region 140 and the periphery of the buried layer 120, and is beneficial to improving the breakdown voltage of the semiconductor device.
[0078] In some embodiments, the third lightly doped region 183 has a ring structure and surrounds the second electrode lead-out region 170.
[0079] This can further reduce the possibility of breakdown between the second well region 140 and the periphery of the buried layer 120, thereby helping to improve the breakdown voltage of the semiconductor device.
[0080] In some embodiments, the semiconductor device further includes a plurality of field oxygen structures 190 corresponding one-to-one with the lightly doped region 180, each field oxygen structure 190 being formed on the upper surface layer of the corresponding lightly doped region 180.
[0081] The field oxygen structure 190 located above the first lightly doped region 181 can electrically isolate the first electrode lead-out region 150 and the base lead-out region 160 from each other. The field oxygen structure 190 located above the second lightly doped region 182 can electrically isolate the base lead-out region 160 and the second electrode lead-out region 170 from each other. In this way, the reliability of the semiconductor device can be effectively improved.
[0082] This application provides a method for manufacturing a semiconductor device, which can be used to manufacture the semiconductor device of any of the foregoing embodiments.
[0083] Figure 2 A schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of this application is shown.
[0084] Please see Figure 2 A method for manufacturing a semiconductor device according to an embodiment of this application includes the following steps:
[0085] S210, a substrate 110 is provided, the substrate 110 having a first conductivity type.
[0086] S220, referring to Figure 3(a), a buried layer 120 is formed within the substrate 110. The buried layer 120 has a second conductivity type, the first conductivity type being the opposite of the second conductivity type. A sacrificial layer 111 can be deposited on the substrate 110, and then the buried layer 120 is formed by high-temperature push-well after ion implantation. The junction depth after push-well must reach a certain depth to ensure the depletion of the semiconductor device and the conduction path of the current. The sacrificial layer 111 can be made of silicon dioxide.
[0087] S230, Referring to Figure 3(b), a first well region 130 is formed on the upper surface of the buried layer 120. The first well region 130 has a first conductivity type. The first well region 130 can be formed by high-temperature push-well after ion implantation.
[0088] S240, Referring to Figure 3(b), a second well region 140 is formed on the upper surface of the buried layer 120, spaced apart from the first well region 130. The second well region 140 has a second conductivity type. The second well region 140 can be formed by high-temperature push-in after ion implantation.
[0089] S250, please refer to Figure 3(d), a plurality of lightly doped regions 180 are formed, including a first lightly doped region 181 and a second lightly doped region 182 formed on the upper surface layer of the first well region 130.
[0090] Before step S250, which forms multiple lightly doped regions 180, the semiconductor device manufacturing method further includes removing the sacrificial layer 111.
[0091] S260, a first electrode lead-out region 150 and a base lead-out region 160 are formed in the upper surface layer of the first well region 130, which are electrically isolated from each other. The base lead-out region 160 is located around the first electrode lead-out region 150. The first electrode lead-out region 150 has a second conductivity type, and the base lead-out region 160 has a first conductivity type.
[0092] S270, a second electrode lead-out region 170 having a second conductivity type is formed in the upper surface layer of the second well region 140.
[0093] The first lightly doped region 181 is located between the first electrode lead-out region 150 and the base lead-out region 160, and the second lightly doped region 182 is located between the base lead-out region 160 and the second electrode lead-out region 170. The lightly doped region 180 has a first conductivity type, and the doping concentration of the lightly doped region 180 is less than the doping concentration of the first well region 130.
[0094] The semiconductor device manufactured using this method has a high breakdown voltage, which can meet the user's needs.
[0095] Please see Figure 4In some embodiments, step S250, which forms a plurality of lightly doped regions 180, specifically includes:
[0096] S251. Referring to Figure 3(c), ions of a first conductivity type are implanted into the substrate 110 to form multiple initial lightly doped regions 1801. Photoresist can be used as a masking film to implant ions of the first conductivity type into the substrate 110 to form multiple initial lightly doped regions 1801. Specifically, a silicon nitride layer 112 can be deposited on the substrate 110. Through photolithography, development and other processes, a pattern corresponding to the multiple lightly doped regions 180 is formed on the silicon nitride layer 112. Then, ions of the first conductivity type are implanted accordingly to form multiple initial lightly doped regions 1801.
[0097] S252. Referring to Figure 3(d), a field oxide layer is formed on the upper surface of the substrate 110, covering multiple initial lightly doped regions 1801. The multiple initial lightly doped regions 1801 are then heated and pushed into wells using a field oxide layer formation process, so that each initial lightly doped region 1801 is pushed into a lightly doped region 180. The field oxide layer includes multiple field oxide structures 190 corresponding to the initial lightly doped regions 1801. Using the field oxide oxidation process of the field oxide layer, due to the high temperature and long duration of the process, each initial lightly doped region 1801 is pushed forward to form the corresponding lightly doped region 180. The first well region 130 and the second well region 140 are also pushed forward, and the contours of the first well region 130, the second well region 140, and each lightly doped region 180 are optimized.
[0098] S253, Remove silicon nitride layer 112 (refer to Figure 3(d) and Figure 1 (To understand).
[0099] Please see Figure 5 In some embodiments, the method for manufacturing a semiconductor device further includes:
[0100] S281. A passivation layer covering the field oxide layer is formed on the upper surface of the substrate 110.
[0101] S282. Planarize the side of the passivation layer that faces away from the field oxygen layer.
[0102] S283. A first conductive plug, a second conductive plug, and a third conductive plug are formed within the passivation layer, penetrating the passivation layer.
[0103] S284. A first electrode, a second electrode, and a base are formed on the passivation layer.
[0104] In this configuration, the first electrode is electrically connected to the first electrode lead-out region 150 via a first conductive plug, the second electrode is electrically connected to the second electrode lead-out region 170 via a second conductive plug, and the base is electrically connected to the base lead-out region 160 via a third conductive plug. This allows the emitter, collector, and base of the NPN transistor to be properly connected.
[0105] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the above flowcharts may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps. It should be noted that the different embodiments described above can be combined with each other.
[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0107] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.
Claims
1. A semiconductor device, characterized in that, include: The substrate has a first type of conductivity; A buried layer is formed within the substrate and has a second conductivity type, the first conductivity type being the opposite of the second conductivity type; A first well region is located on the upper surface of the buried layer and has the first conductivity type; The second well region is located on the upper surface of the buried layer and is spaced apart from the first well region, and has the second conductivity type; The first electrode lead-out region and the base lead-out region are both formed within the upper surface layer of the first well region and are electrically isolated from each other; the base lead-out region is located outside the first electrode lead-out region; the first electrode lead-out region has the second conductivity type, and the base lead-out region has the first conductivity type; The second electrode lead-out region is formed in the upper surface layer of the second well region and has the second conductivity type; as well as Multiple lightly doped regions, including a first lightly doped region and a second lightly doped region formed on the upper surface layer of the first well region, wherein the first lightly doped region is located between the first electrode lead-out region and the base lead-out region, and the second lightly doped region is located between the base lead-out region and the second electrode lead-out region; The lightly doped region has the first conductivity type, and the doping concentration of the lightly doped region is less than the doping concentration of the first well region. The PN junction formed between the first lightly doped region and the first electrode lead-out region is a cylindrical junction, and the PN junction formed between the second lightly doped region and the second electrode lead-out region is also a cylindrical junction.
2. The semiconductor device according to claim 1, characterized in that, The first conductivity type is P-type, and the second conductivity type is N-type; The first electrode lead-out region is led out as the first electrode. When the first electrode is input with voltage, the first electrode lead-out region, the base lead-out region and the first well region together with the second electrode lead-out region constitute an NPN transistor.
3. The semiconductor device according to claim 2, characterized in that, The second electrode lead-out region is led out as the second electrode; When a positive voltage is input to the first electrode, the first electrode serves as the emitter of the NPN transistor, the second electrode serves as the collector of the NPN transistor, and the base lead-out region and the first well region together serve as the base region of the NPN transistor.
4. The semiconductor device according to any one of claims 1-3, characterized in that, The first lightly doped region is a ring structure and is disposed around the first electrode lead-out region; or The first electrode lead-out region is provided in multiple ways, and the multiple first electrode lead-out regions are electrically connected to each other to serve as the first electrode; the upper surface layer of the first well region is provided with multiple base lead-out regions and multiple first lightly doped regions that correspond one-to-one with the first electrode lead-out regions; each first lightly doped region is located between the corresponding first electrode lead-out region and the corresponding base lead-out region.
5. The semiconductor device according to any one of claims 1-3, characterized in that, The second lightly doped region has a ring structure and is disposed around the first electrode lead-out region; or The second electrode lead-out region is provided in multiple ways, and the multiple second electrode lead-out regions are electrically connected to each other to serve as second electrodes; the upper surface layer of the first well region is provided with multiple base lead-out regions and multiple second lightly doped regions that correspond one-to-one with the second electrode lead-out regions; each second lightly doped region is located between the corresponding base lead-out region and the corresponding second electrode lead-out region.
6. The semiconductor device according to any one of claims 1-3, characterized in that, The plurality of lightly doped regions also includes a third lightly doped region, which is formed in the buried layer and located on the periphery of the second electrode lead-out region, and the third lightly doped region is in contact with the second well region.
7. The semiconductor device according to any one of claims 1-3, characterized in that, The semiconductor device further includes a plurality of field oxygen structures corresponding one-to-one with the lightly doped region, each of the field oxygen structures being formed on the upper surface layer of the corresponding lightly doped region.
8. A method for manufacturing a semiconductor device, characterized in that, include: Provide substrate; The substrate has a first conductivity type; A buried layer is formed within the substrate; The buried layer has a second conductivity type, and the first conductivity type is the opposite of the second conductivity type; A first well region is formed on the upper surface of the buried layer, and the first well region has the first conductivity type; A second well region is formed on the upper surface layer of the buried layer, which is spaced apart from the first well region, and the second well region has the second conductivity type; Multiple lightly doped regions are formed; the multiple lightly doped regions include a first lightly doped region and a second lightly doped region formed on the upper surface layer of the first well region; A first electrode lead-out region and a base lead-out region are formed in the upper surface layer of the first well region, which are electrically isolated from each other; the base lead-out region is located outside the first electrode lead-out region; the first electrode lead-out region has the second conductivity type, and the base lead-out region has the first conductivity type; A second electrode lead-out region having the second conductivity type is formed in the upper surface layer of the second well region; Wherein, the first lightly doped region is located between the first electrode lead-out region and the base lead-out region, and the second lightly doped region is located between the base lead-out region and the second electrode lead-out region; The lightly doped region has the first conductivity type, and the doping concentration of the lightly doped region is less than the doping concentration of the first well region; The PN junction formed between the first lightly doped region and the first electrode lead-out region is a cylindrical junction, and the PN junction formed between the second lightly doped region and the second electrode lead-out region is also a cylindrical junction.
9. The method for manufacturing a semiconductor device according to claim 8, characterized in that, The formation of multiple lightly doped regions specifically includes: Ions of a first conductivity type are implanted into the substrate to form multiple initial lightly doped regions; A field oxygen layer is formed on the upper surface of the substrate, covering multiple initial lightly doped regions, and the multiple initial lightly doped regions are heated and pushed into a well using the field oxygen layer formation process, so that each initial lightly doped region is pushed into a well to form a lightly doped region.
10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The method for manufacturing the semiconductor device further includes: A passivation layer covering the field oxide layer is formed on the upper surface of the substrate; The side of the passivation layer that faces away from the field oxygen layer is planarized. A first conductive plug, a second conductive plug, and a third conductive plug are formed within the passivation layer, penetrating the passivation layer. A first electrode, a second electrode, and a base electrode are formed on the passivation layer; The first electrode is electrically connected to the first electrode lead-out area through the first conductive plug, the second electrode is electrically connected to the second electrode lead-out area through the second conductive plug, and the base is electrically connected to the base lead-out area through the third conductive plug.