Transient electrical stress protection circuit

Abstract

The application provides a transient electric stress protection circuit, which comprises a positive pulse protection circuit and a negative pulse protection circuit connected in parallel to a port and a ground end; the positive pulse protection circuit and the negative pulse protection circuit each comprise: a discharge device; and a reverse current blocking diode connected in series with the discharge device. Advantageous effects: while performing transient electric stress protection, the high resistance cut-off state is maintained even if the port voltage is higher than the working power voltage or lower than the ground end voltage within a certain range, thereby avoiding the interference of the leakage of the prior art protection circuit on the normal work of the port.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a transient electrical stress protection circuit. Background Technology

[0002] To improve the reliability of integrated circuits, transient electrical stress protection circuits are usually set at the ports of integrated circuits to avoid phenomena such as lightning strikes, electrostatic discharge, and surges, which can cause transient voltage / current pulses at the integrated circuit ports, resulting in damage and failure of the port circuits.

[0003] Typical structures of existing transient electrical stress protection circuits, such as Figure 1 As shown, the device includes a first current-conducting diode D1 and a second current-conducting diode D2, as well as a clamping device D3 connected to the power supply terminal VDD and the ground terminal GND. When a positive transient electrical stress pulse occurs at port IO, the first current-conducting diode D1, connected between port IO and the power supply terminal VDD, conducts in the forward bias, while the clamping device D3, connected between the power supply terminal VDD and the ground terminal GND, breaks down in the reverse bias, forming a low-resistance electrical stress discharge path from port IO to the ground terminal GND. The voltage at port IO is clamped to V. D1 +V D3 To prevent overvoltage from damaging the protected port circuit 300, where V D1 V is the forward conduction voltage of the first current-conducting diode D1. D3 This is the breakdown voltage of clamping device D3. When a negative transient electrical stress pulse occurs at port IO, the second current-conducting diode D2, connected between port IO and ground GND, is forward biased and conducts, clamping the voltage at port IO to -V. D2 V D2 This is the forward voltage of the second current-conducting diode D2.

[0004] The transient electrical stress protection circuit described above requires the normal operating voltage of the port signal to be between -V. D1 With VDD+V D1 Otherwise, a leakage path will be formed from the port IO to the power supply VDD, or from the ground GND to the port IO, thereby increasing the operating current of the pre-stage drive circuit of the port IO, or affecting the reliable communication between the circuit ports. Summary of the Invention

[0005] To address the above technical problems, this invention provides a transient electrical stress port protection circuit for a wide operating voltage range port of an integrated circuit that can be integrated on a single chip.

[0006] The technical problem solved by this invention can be achieved by the following technical solutions:

[0007] A transient electrical stress protection circuit includes a positive pulse protection circuit and a negative pulse protection circuit connected in parallel to a port and a ground terminal. The positive pulse protection circuit and the negative pulse protection circuit each include:

[0008] A discharge device;

[0009] A reverse current blocking diode is connected in series with the discharge device.

[0010] Preferably, the positive pulse protection circuit specifically includes:

[0011] A first reverse current blocking diode, wherein the anode of the first reverse current blocking diode is connected to the port;

[0012] A first discharge device, wherein the anode of the first discharge device is connected to the cathode of the first reverse current blocking diode, and the cathode of the first discharge device is connected to the ground terminal.

[0013] Preferably, the negative pulse protection circuit specifically includes:

[0014] A second discharge device, wherein the cathode of the second discharge device is connected to the port;

[0015] A second reverse current blocking diode, the cathode of which is connected to the anode of the second discharge device, and the anode of which is connected to the ground terminal.

[0016] Preferably, the reverse current blocking diode comprises:

[0017] A first shallow N-well region serves as the cathode of the reverse current blocking diode; and

[0018] A first P+ region is formed within the first shallow N-well region, and the anode of the reverse current blocking diode is drawn out from the first P+ region;

[0019] A first N+ region is formed within the first shallow N-well region and serves as the cathode lead-out terminal of the reverse current blocking diode.

[0020] Preferably, the reverse current blocking diode comprises:

[0021] A first shallow N-well region, wherein a first P+ region, a second P+ region and a first N+ region are provided in the first shallow N-well region, and the anode of the reverse current blocking diode is led out from the first P+ region;

[0022] A first body electrode region is formed above the first shallow N-well region. The first body electrode region partially covers the edges of the first P+ region and the second P+ region. The second P+ region, the first N+ region and the first body electrode region are shorted together and serve as the cathode of the reverse current blocking diode.

[0023] Preferably, the reverse current blocking diode comprises:

[0024] A first deep N-well region, wherein the first deep N-well region is provided with a first shallow P-well region and a first shallow N-well region;

[0025] A first P+ region is formed within the first shallow P-well region;

[0026] A first N+ region is formed within the first shallow N-well region;

[0027] The first shallow P-well region serves as the anode of the reverse current blocking diode, and the first deep N-well region serves as the cathode of the reverse current blocking diode.

[0028] Preferably, the reverse current blocking diode comprises:

[0029] A first N-type buried layer is formed in a portion of a first P-type substrate and diffuses upward into a first P-type epitaxial layer, wherein the first P-type epitaxial layer is disposed above the first P-type substrate;

[0030] The first deep N-well region is formed within the first P-type epitaxial layer and is disposed on both sides above the first N-type buried layer, partially covering the edge of the first N-type buried layer and the first P-type substrate.

[0031] A first shallow P-well region and a first shallow N-well region are formed within the first P-type epitaxial layer and located between the two first deep N-well regions. A first P+ region is provided within the first shallow P-well region, and a first N+ region is provided within the first shallow N-well region.

[0032] The second shallow N-well region is formed in each of the first deep N-well regions;

[0033] The N-type heavily doped regions extend vertically from the upper surface of the P-type epitaxial layer through the second shallow N-well region and the first deep N-well region to the upper surface of the first N-type buried layer.

[0034] The anode of the reverse current blocking diode is drawn from the first P+ region, and the first N+ region is shorted to the two N-type heavily doped regions and serves as the cathode of the reverse current blocking diode.

[0035] Preferably, the discharge device includes:

[0036] A second deep N-well region is formed in a second P-type substrate, and a second N+ region and a second shallow P-well region are provided in the second deep N-well region;

[0037] A third P+ region and a fourth P+ region are formed in the second P-type substrate and are located on both sides of the second deep N-well region, respectively. Both the third P+ region and the fourth P+ region are connected to the ground terminal.

[0038] A third N+ region, a fourth N+ region, and a fifth P+ region are respectively formed within the second shallow P-well region;

[0039] A second body pole region is formed above the second shallow P-well region, and the second body pole region partially covers the edges of the third N+ region and the fourth N+ region;

[0040] The second N+ region and the third N+ region are short-circuited and serve as the anode of the discharge device, while the fourth N+ region, the fourth P+ region, and the second body electrode region are short-circuited and serve as the cathode of the discharge device.

[0041] Preferably, the discharge device includes:

[0042] A second N-type buried layer is formed in a portion of a second P-type substrate and diffuses upward into a second P-type epitaxial layer, wherein the second P-type epitaxial layer is disposed above the second P-type substrate;

[0043] The second deep N-well region is formed within the second P-type epitaxial layer and is disposed on both sides above the second N-type buried layer, partially covering the edge of the second N-type buried layer and the second P-type substrate;

[0044] A third shallow N-well region is respectively disposed in each of the second deep N-well regions. A second N+ region is disposed in the third shallow N-well region. The two second N+ regions are short-circuited and serve as the anode of the discharge device.

[0045] A second shallow P-well region is formed within the second P-type epitaxial layer. A third P+ region and a third N+ region are provided within the second shallow P-well region. The third P+ region and the third N+ region are short-circuited and serve as the cathode of the reverse current blocking diode.

[0046] The advantages or beneficial effects of the technical solution of this invention are as follows:

[0047] The circuit of this invention consists of a positive pulse protection circuit and a negative pulse protection circuit connected in parallel between the port and the ground terminal. It can provide transient electrical stress protection for the integrated circuit port, and at the same time, it can maintain a high-impedance cutoff state when the port voltage is higher than the working power supply voltage or lower than the ground terminal voltage within a certain range, thus avoiding interference to the normal operation of the port caused by leakage current in the existing protection circuit. Attached Figure Description

[0048] Figure 1 This is a schematic diagram of the structure of a transient electrical stress port protection circuit in the prior art;

[0049] Figure 2 This is a schematic diagram of the transient electrical stress protection circuit in a preferred embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram of the structure of the reverse current blocking diode in a preferred embodiment of the present invention, specifically embodiment 1.

[0051] Figure 4 This is a schematic diagram of the structure of a specific embodiment 2 of the reverse current blocking diode in a preferred embodiment of the present invention;

[0052] Figure 5a This is a schematic diagram of the structure of the reverse current blocking diode in a preferred embodiment of the present invention, specifically embodiment 3.

[0053] Figure 5b In a preferred embodiment of the present invention, Figure 5a A schematic diagram of a structure containing parasitic PNP devices;

[0054] Figure 5c In a preferred embodiment of the present invention, the reverse current blocking diode of the forward pulse protection circuit adopts... Figure 5a The equivalent circuit diagram corresponding to the structure;

[0055] Figure 6 This is a schematic diagram of the structure of the reverse current blocking diode in a preferred embodiment of the present invention, specifically embodiment 4.

[0056] Figure 7a This is a schematic diagram of the structure of a discharge device in the prior art;

[0057] Figure 7b The discharge device used in the negative pulse protection circuit Figure 7a The equivalent circuit diagram corresponding to the structure;

[0058] Figure 8a This is a schematic diagram of the structure of the discharge device in a preferred embodiment of the present invention, specifically embodiment 1.

[0059] Figure 8b The discharge device used in the negative pulse protection circuit Figure 8a The equivalent circuit diagram corresponding to the structure;

[0060] Figure 9 This is a schematic diagram of the structure of the discharge device in a preferred embodiment of the present invention, specifically embodiment 2. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0063] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0064] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a transient electrical stress protection circuit is provided, belonging to the field of integrated circuit technology, such as... Figure 2 As shown, a positive pulse protection circuit 100 and a negative pulse protection circuit 200 are connected in parallel to port IO and ground GND. The anode of the positive pulse protection circuit 100 is connected between port IO and the protected port circuit 300, and the cathode of the positive pulse protection circuit 100 is connected between the protected port circuit 300 and ground GND. The anode of the negative pulse protection circuit 200 is connected between the protected port circuit 300 and ground GND, and the cathode of the negative pulse protection circuit 200 is connected between port IO and the protected port circuit 300.

[0065] The positive pulse protection circuit 100 and the negative pulse protection circuit 200 are each composed of a discharge device and a reverse current blocking diode connected in series.

[0066] To address the issue of leakage current paths in existing transient electrical stress protection circuits when the port voltage is higher than the operating power supply voltage or lower than the ground voltage, this invention addresses this problem. In the circuit structure of this embodiment, when over-stress occurs at the port, the discharge device and the reverse current blocking diode conduct, forming an electrical stress discharge path from the port to ground. When the port voltage is within the normal operating voltage range, even if it is higher than the port power supply voltage or lower than the port ground voltage, the discharge device and the reverse current blocking diode in the protection circuit are in a high-resistance cutoff state, preventing leakage current interference from disrupting the normal operation of the protected port circuit in existing transient electrical stress protection circuits.

[0067] Furthermore, the positive pulse protection circuit 100 specifically includes:

[0068] A first reverse current blocking diode D11, the anode of the first reverse current blocking diode D11 is connected to the port IO;

[0069] A first discharge device D12 is provided. The anode of the first discharge device D12 is connected to the cathode of the first reverse current blocking diode D11, and the cathode of the first discharge device D12 is connected to the ground terminal GND.

[0070] Specifically, when there is a positive pulse electrical stress at port IO, the port voltage relative to ground is higher than the sum of the forward bias conduction voltage of the first reverse current blocking diode D11 and the breakdown voltage of the first discharge device D12. In this case, the positive pulse protection circuit 100 forms a low-resistance discharge path from port IO to ground GND to protect the protected port circuit 300.

[0071] When the port voltage is within the normal operating voltage range, that is, when the port voltage relative to the ground voltage is not higher than the forward breakdown voltage of the first discharge device D12, or when the ground voltage relative to the port voltage is not higher than the reverse breakdown voltage of the first reverse current blocking diode D11, then both the first reverse current blocking diode D11 and the first discharge device D12 are in the off state, and no leakage path from port IO to ground GND will be formed.

[0072] Furthermore, the negative pulse protection circuit 200 specifically includes:

[0073] A second discharge device D21, and the cathode connection port IO of the second discharge device D21;

[0074] A second reverse current blocking diode D22, the cathode of the second reverse current blocking diode D21 is connected to the anode of the second discharge device D21, and the anode of the second reverse current blocking diode D21 is connected to the ground terminal GND.

[0075] Specifically, when there is negative pulse electrical stress at port IO, and the ground voltage relative to the port voltage is higher than the sum of the forward bias conduction voltage of the second reverse current blocking diode D22 and the breakdown voltage of the second discharge device D21, the negative pulse protection circuit 200 forms a low-resistance discharge path from the ground terminal GND to port IO.

[0076] When the port voltage relative to the ground voltage is not higher than the reverse breakdown voltage of the second reverse current blocking diode D22, or the ground voltage relative to the port voltage is not higher than the breakdown voltage of the second discharge device D21, then both the second reverse current blocking diode D22 and the second discharge device D21 are in the off state, and no leakage path from port IO to ground GND will be formed.

[0077] The following describes specific embodiments of the first reverse current blocking diode D11 and the second reverse current blocking diode D22 in the transient electrical stress protection circuit of the present invention:

[0078] In a preferred embodiment 1 of the reverse current blocking diode, such as Figure 3 As shown, the reverse current blocking diode is fabricated using a standard CMOS process-compatible method, specifically including:

[0079] A first shallow N-well region 021 (SDNW) serves as the cathode of the reverse current blocking diode; and

[0080] A first P+ region 031 is formed within a first shallow N-well region 021, and the anode of the reverse current blocking diode is drawn out from the first P+ region 031;

[0081] A first N+ region 041 is formed within a first shallow N-well region 021 and serves as the cathode lead-out terminal of the reverse current blocking diode.

[0082] Specifically, a first shallow N-well region 021 of a P-channel MOS device is formed on the first P-type substrate 011 or the epitaxial layer, serving as the cathode of the reverse current blocking diode; a first N+ region 041 of the source / drain region of the P-channel MOS device is formed, serving as the lead-out terminal of the cathode of the reverse current blocking diode; and a first P+ region 031 of the source / drain region of the P-channel MOS device is formed, serving as the anode of the reverse current blocking diode.

[0083] In a preferred embodiment 2 of the reverse current blocking diode, the drain / body junction of a P-channel MOS device in a standard CMOS process is used to realize the reverse current blocking diode. The reverse current blocking diode is formed on a first P-type substrate 011 or an epitaxial layer, such as... Figure 4 As shown, it specifically includes:

[0084] A first shallow N-well region 021 is provided, and a first P+ region 031, a second P+ region 032 and a first N+ region 041 are provided in the first shallow N-well region 021. The anode of the reverse current blocking diode is led out from the first P+ region 031.

[0085] A first body electrode region 051 is formed above a first shallow N-well region 021. The first body electrode region 051 partially covers the edges of the first P+ region 031 and the second P+ region 032. The second P+ region 032, the first N+ region 041 and the first body electrode region 051 are shorted together and serve as the cathode of the reverse current blocking diode.

[0086] Specifically, in this embodiment, the first P+ region 031 forming the drain terminal of the P-channel MOS device serves as the anode of the reverse current blocking diode; the first N+ region 041 forming the gate of the P-channel MOS, the second P+ region 032 forming the source, and the first body region 051 forming the body are shorted together to serve as the cathode of the reverse current blocking diode.

[0087] Furthermore, the above as follows Figure 3 and Figure 4In the reverse current blocking diode shown, the reverse breakdown voltage is low because the impurity concentration in the P+ region is high.

[0088] To improve the reverse breakdown voltage of the reverse current blocking diode, so that the protection circuit of this invention can also be applied to ports with higher operating voltages, a preferred embodiment 3 is provided in which the reverse current blocking diode is implemented using a simulated CMOS process-compatible method, such as... Figure 5a As shown, it specifically includes:

[0089] A first deep N-well region 061 (DNW) is provided, and the first deep N-well region 061 is provided with a first shallow P-well region 071 (SDPW) and a first shallow N-well region 021.

[0090] A first P+ region 031 is formed within a first shallow P-well region 071;

[0091] A first N+ region 032 is formed within a first shallow N-well region 021;

[0092] The first shallow P-well region 071 serves as the anode of the reverse current blocking diode, and the first deep N-well region 061 serves as the cathode of the reverse current blocking diode.

[0093] Specifically, the first shallow P-well region 071 and the first deep N-well region 061 have lower impurity concentrations compared to... Figure 3 and Figure 4 The PN structure has a high reverse breakdown voltage.

[0094] The above Figure 3 , Figure 4 and Figure 5a The structures in all of them contain parasitic PNP devices, for example, such as Figure 5b As shown, parasitic PNP devices include longitudinal PNP (PNP_SUB) devices and lateral PNP (PNP_LATERAL) devices. Figure 5c As shown, during protection, the first reverse current blocking diode D11 in the forward pulse protection circuit 100 is forward-biased and conducts, while the first discharge device D12 is broken down and conducts, forming a current discharge path from port IO to the ground terminal. However, due to the presence of the parasitic PNP device, some of the current that should flow to the ground terminal will flow to the P-type substrate (PSUB) through the parasitic PNP device. The current flowing into the substrate is mainly the hole current injected by the anode of the first reverse current blocking diode D11, i.e., the emitter of the parasitic longitudinal PNP (PNP_SUB) device. Since holes are majority carriers in the P-type substrate, they have a long lifetime and diffusion distance. When this hole current is large, it will interfere with the normal operation of the protected port circuit and may even trigger latch-up.

[0095] Based on this, in order to reduce the hole current injected into the substrate by the parasitic PNP in the reverse current diode, a preferred embodiment 4 is provided, based on an optimized structure compatible with semiconductor BCD process, such as... Figure 6 As shown, the reverse current blocking diode includes:

[0096] A first N-type buried layer 081 is formed in a portion of a first P-type substrate 011 and diffuses upward into a first P-type epitaxial layer 091 (PEPI), the first P-type epitaxial layer 091 being disposed above the first P-type substrate 011;

[0097] The first deep N-well region 061 is formed in the first P-type epitaxial layer 091 and is disposed on both sides above the first N-type buried layer 081, partially covering the edge of the first N-type buried layer 081 and the first P-type substrate 011.

[0098] A first shallow P-well region 071 and a first shallow N-well region 021 are formed within the first P-type epitaxial layer 091 and located between two first deep N-well regions 061. A first P+ region 031 is provided in the first shallow P-well region 071 and a first N+ region 041 is provided in the first shallow N-well region 021.

[0099] The second shallow N-well region 022 is formed in each of the first deep N-well regions 061;

[0100] The N-type heavily doped region 10 (DEEPN) extends vertically from the upper surface of the P-type epitaxial layer 091 through the second shallow N-well region 022 and the first deep N-well region 061 to the upper surface of the first N-type buried layer 081.

[0101] The anode of the reverse current blocking diode is drawn from the first P+ region 031, and the first N+ region 041 is shorted to the two N-type heavily doped regions 10 and serves as the cathode of the reverse current blocking diode.

[0102] Specifically, the PN junction of the reverse current blocking diode is formed by a first P-type epitaxial layer 091 doped with P-type impurities and a first shallow N-well region 021 doped with N-type impurities. A high-energy, high-concentration heavily doped N-type region 10 and a first N-type buried layer 081 isolate the first P-type epitaxial layer 091 of the PN junction from the first P-type epitaxial layer 091 outside the first deep N-well region 061 and the first P-type substrate 011. The aforementioned heavily doped N-type region 10 and the first N-type buried layer 081 constitute an N-type isolation region and are connected to the cathode of the reverse current blocking diode.

[0103] Furthermore, the base region of the parasitic lateral PNP device is an N-type heavily doped region 10, and the base of the vertical PNP device is a first N-type buried layer 081, whose impurity concentration is much higher than that of the emitter region (i.e., the first P-type epitaxial layer 091) of the parasitic PNP device, greatly reducing the emission coefficient of the emitter junction in the parasitic PNP device, thereby effectively reducing the number of holes injected into the substrate by the parasitic transistor. In addition, compared to Figure 5a The structure in the first P-type epitaxial layer 091 has a lower impurity concentration, thus having a higher reverse breakdown voltage, which can meet the protection circuit requirements of higher operating voltage ports.

[0104] The following describes specific embodiments of the first discharge device D12 and the second discharge device D21 in the transient electrical stress protection circuit of the present invention:

[0105] like Figure 7a The diagram shown is a schematic of an existing discharge device, which uses an NMOS transistor with its gate and source shorted. Figure 7b As shown, using Figure 7a The equivalent circuit diagram shown is the equivalent circuit diagram of the discharge device as the second discharge device D21 of the present invention. It includes a second N+ region 042, a third N+ region 043, and a third P+ region 033 formed in the second P-type substrate 012. The body region is the second P-type substrate 012, which is generally connected to the ground terminal. There is a parasitic diode DP between the second P-type substrate 012 and the third N+ region 043. When the voltage at the port (i.e., the cathode of the second discharge device D2) is lower than the ground level, the parasitic diode DP is forward-biased, resulting in port leakage.

[0106] In a preferred embodiment of the discharge device, the discharge device is implemented using a simulated CMOS process, such as... Figure 8a As shown, it specifically includes:

[0107] A second deep N-well region 062 is formed in a second P-type substrate 012, and a second N+ region 042 and a second shallow P-well region 072 are provided in the second deep N-well region 062.

[0108] A third P+ region 033 and a fourth P+ region 034 are formed in the second P-type substrate 012 and are located on both sides of the second deep N-well region 062, respectively. Both the third P+ region 033 and the fourth P+ region 034 are connected to the ground terminal.

[0109] A third N+ region 043, a fourth N+ region 044 and a fifth P+ region 035 are formed within the second shallow P-well region 072;

[0110] A second body pole region 052 is formed above the second shallow P-well region 072, and the second body pole region 052 partially covers the edges of the third N+ region 043 and the fourth N+ region 044.

[0111] The second N+ region 042 and the third N+ region 043 are shorted together and serve as the anode of the discharge device, while the fourth N+ region 043, the fourth P+ region 034, and the second body electrode region 052 are shorted together and serve as the cathode of the discharge device.

[0112] Specifically, a shallow P-well (SDPW) is used as the body region of the MOSFET, and a deep N-well (DNW) is used to isolate this body region from the substrate (PSUB). The deep N-well (DNW) is shorted to the drain of the MOSFET, serving as the anode of the discharge device, while the source, gate, and body of the MOSFET are shorted, serving as the cathode of the discharge device.

[0113] like Figure 8a As shown, the parasitic diode DP is connected between the anode of the second discharge device D21 and the second P-type substrate 012. Even if the port voltage is lower than the bias voltage of the second P-type substrate 012, as long as the second discharge device D21 is not turned on, there will be no leakage from the second P-type substrate 012 to the port IO.

[0114] In a preferred embodiment 2 of the discharge device, the discharge device is implemented based on BCD semiconductor process compatibility. The discharge device adopts a vertical NPN structure, specifically including:

[0115] A second N-type buried layer 082 is formed in a portion of a second P-type substrate 012 and diffuses upward into a second P-type epitaxial layer 092, which is disposed above the second P-type substrate 012.

[0116] The second deep N-well region 062 is formed within the second P-type epitaxial layer 092 and is disposed on both sides above the second N-type buried layer 082, partially covering the edge of the second N-type buried layer 082 and the second P-type substrate 012.

[0117] A third shallow N-well region 023 is respectively disposed in each second deep N-well region 062. A second N+ region 042 is disposed in the third shallow N-well region 023. The two second N+ regions 042 are short-circuited and serve as the anode of the discharge device.

[0118] A second shallow P-well region 072 (SDPW) is formed within the second P-type epitaxial layer 092. A third P+ region 033 and a third N+ region 043 are provided within the second shallow P-well region 072. The third P+ region 033 and the third N+ region 043 are shorted and serve as the cathode of the reverse current blocking diode.

[0119] Specifically, the second shallow P-well region 072 is used as the base region of the vertical NPN structure, and the third N+ region 043 in the second shallow P-well region 072 is used as the emitter region. The emitter region is short-circuited with the base region and serves as the cathode of the discharge device. The second deep N-well region 062 and the second N-type buried layer 082 are used as the collector region, which are led out and used as the anode of the discharge device.

[0120] The above technical solution has the following advantages or beneficial effects: the circuit of the present invention can provide transient electrical stress protection for the integrated circuit port, and at the same time, it can maintain a high-impedance cutoff state when the port voltage is higher than the working power supply voltage or lower than the ground voltage within a certain range, thus avoiding interference to the normal operation of the port caused by leakage current in the existing protection circuit.

[0121] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A transient electrical stress protection circuit, characterized by, The circuit includes a positive pulse protection circuit and a negative pulse protection circuit connected in parallel to the port and the ground terminal, wherein the positive pulse protection circuit and the negative pulse protection circuit each include: A discharge device; A reverse current blocking diode, wherein the reverse current blocking diode is connected in series with the discharge device; The reverse current blocking diode includes: A first N-type buried layer is formed in a portion of a first P-type substrate and diffuses upward into a first P-type epitaxial layer, wherein the first P-type epitaxial layer is disposed above the first P-type substrate; The first deep N-well region is formed within the first P-type epitaxial layer and is disposed on both sides above the first N-type buried layer, partially covering the edge of the first N-type buried layer and the first P-type substrate. A first shallow P-well region and a first shallow N-well region are formed within the first P-type epitaxial layer and located between the two first deep N-well regions. A first P+ region is provided within the first shallow P-well region, and a first N+ region is provided within the first shallow N-well region. The second shallow N-well region is formed in each of the first deep N-well regions; The N-type heavily doped regions extend vertically from the upper surface of the P-type epitaxial layer through the second shallow N-well region and the first deep N-well region to the upper surface of the first N-type buried layer. The N-type heavily doped regions and the first N-type buried layer isolate the first P-type epitaxial layer of the PN junction from the first P-type epitaxial layer and the first P-type substrate outside the first deep N-well region. The anode of the reverse current blocking diode is drawn from the first P+ region, and the first N+ region is shorted to the two N-type heavily doped regions and serves as the cathode of the reverse current blocking diode.

2. The transient electrical stress protection circuit of claim 1, wherein, The positive pulse protection circuit specifically includes: A first reverse current blocking diode, wherein the anode of the first reverse current blocking diode is connected to the port; A first discharge device, wherein the anode of the first discharge device is connected to the cathode of the first reverse current blocking diode, and the cathode of the first discharge device is connected to the ground terminal.

3. The transient electrical stress protection circuit according to claim 2, characterized in that, The negative pulse protection circuit specifically includes: A second discharge device, wherein the cathode of the second discharge device is connected to the port; A second reverse current blocking diode, the cathode of which is connected to the anode of the second discharge device, and the anode of which is connected to the ground terminal.

4. The transient electrical stress protection circuit according to claim 1, characterized in that, The reverse current blocking diode includes: A first shallow N-well region serves as the cathode of the reverse current blocking diode; and A first P+ region is formed within the first shallow N-well region, and the anode of the reverse current blocking diode is drawn out from the first P+ region; A first N+ region is formed within the first shallow N-well region and serves as the cathode lead-out terminal of the reverse current blocking diode.

5. The transient electrical stress protection circuit according to claim 1, characterized in that, The reverse current blocking diode includes: A first shallow N-well region, wherein a first P+ region, a second P+ region and a first N+ region are provided in the first shallow N-well region, and the anode of the reverse current blocking diode is led out from the first P+ region; A first body electrode region is formed above the first shallow N-well region. The first body electrode region partially covers the edges of the first P+ region and the second P+ region. The second P+ region, the first N+ region and the first body electrode region are shorted together and serve as the cathode of the reverse current blocking diode.

6. The transient electrical stress protection circuit according to claim 1, characterized in that, The reverse current blocking diode includes: A first deep N-well region, wherein the first deep N-well region is provided with a first shallow P-well region and a first shallow N-well region; A first P+ region is formed within the first shallow P-well region; A first N+ region is formed within the first shallow N-well region; The first shallow P-well region serves as the anode of the reverse current blocking diode, and the first deep N-well region serves as the cathode of the reverse current blocking diode.

7. The transient electrical stress protection circuit according to claim 1, characterized in that, The discharge device includes: A second deep N-well region is formed in a second P-type substrate, and a second N+ region and a second shallow P-well region are provided in the second deep N-well region; A third P+ region and a fourth P+ region are formed in the second P-type substrate and are located on both sides of the second deep N-well region, respectively. Both the third P+ region and the fourth P+ region are connected to the ground terminal. A third N+ region, a fourth N+ region, and a fifth P+ region are respectively formed within the second shallow P-well region; A second body pole region is formed above the second shallow P-well region, and the second body pole region partially covers the edges of the third N+ region and the fourth N+ region; The second N+ region and the third N+ region are short-circuited and serve as the anode of the discharge device, while the fourth N+ region, the fourth P+ region, and the second body electrode region are short-circuited and serve as the cathode of the discharge device.

8. The transient electrical stress protection circuit according to claim 1, characterized in that, The discharge device includes: A second N-type buried layer is formed in a portion of a second P-type substrate and diffuses upward into a second P-type epitaxial layer, wherein the second P-type epitaxial layer is disposed above the second P-type substrate; The second deep N-well region is formed within the second P-type epitaxial layer and is disposed on both sides above the second N-type buried layer, partially covering the edge of the second N-type buried layer and the second P-type substrate; A third shallow N-well region is respectively disposed in each of the second deep N-well regions. A second N+ region is disposed in the third shallow N-well region. The two second N+ regions are short-circuited and serve as the anode of the discharge device. A second shallow P-well region is formed within the second P-type epitaxial layer. A third P+ region and a third N+ region are provided within the second shallow P-well region. The third P+ region and the third N+ region are short-circuited and serve as the cathode of the reverse current blocking diode.

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