protection circuit

Abstract

This invention discloses a protection circuit, including a detection circuit and a discharge circuit. The detection circuit is coupled to a first and a second power junction pad to detect whether an electrostatic discharge (ESD) event or an overcurrent stress event has occurred on the first power junction pad. The detection circuit controls the detection voltage at the detection node based on the detection result. The first and second power junction pads belong to different power domains. The discharge circuit is coupled to the detection node and the first power junction pad. When an ESD event occurs on the first power junction pad, the discharge circuit provides a first discharge path between the first power junction pad and a ground terminal based on the detection voltage. When an overcurrent stress event occurs on the first power junction pad, the detection circuit activates a second discharge path between the first power junction pad and the ground terminal.

Description

Technical Field

[0001] This invention relates to a protection circuit, and more particularly to a protection circuit for electrostatic discharge and overcurrent stress. Background Technology

[0002] With the advancement of semiconductor manufacturing processes, integrated circuit (IC) device sizes have shrunk to the sub-micron level, improving IC performance and processing speed. However, this reduction in device size has introduced reliability issues, particularly impacting the IC's protection against electrostatic discharge (ESD). As device sizes decrease due to advanced manufacturing technologies, ESD protection also diminishes significantly, resulting in a substantial reduction in the device's ESD tolerance. Therefore, protection circuits are needed to protect devices from ESD damage. However, existing ESD protection circuits lack the capability to handle electrical overstress (EOS). Consequently, when an overstress occurs at a bonding pad of the protection circuit, excessive voltage can damage the devices within the circuit, rendering the protection circuit ineffective in protecting against ESD. Summary of the Invention

[0003] In view of this, the present invention proposes a protection circuit having a first power connection pad and a second power connection pad. The protection circuit includes a detection circuit and a discharge circuit. The detection circuit is coupled to the first power connection pad and the second power connection pad to detect whether an electrostatic discharge event or an overcurrent stress event has occurred on the first power connection pad. The protection circuit controls a detection voltage at a detection node based on a detection result. The first power connection pad and the second power connection pad belong to different power domains. The discharge circuit is coupled to the detection node and the first power connection pad. When an electrostatic discharge event occurs on the first power connection pad, the discharge circuit provides a first discharge path between the first power connection pad and a ground terminal based on the detection voltage. When an overcurrent stress event occurs on the first power connection pad, the detection circuit activates a second discharge path between the first power connection pad and the ground terminal.

[0004] The present invention also proposes a protection circuit, which includes a detection circuit and a discharge circuit. The detection circuit includes a first transistor, a resistor, and a second transistor. The first transistor has a first end coupled to a first power supply pad, a second end coupled to a first node, and a control terminal coupled to a second power supply pad. The first and second power supply pads belong to different power domains. The resistor is coupled between the first node and a ground terminal. The second transistor has a first end coupled to a detection node, a second end coupled to a ground terminal, and a control terminal coupled to the first node. The discharge circuit is coupled to the detection node and the first power supply pad, and includes a resistor, a third transistor, a fourth transistor, and a fifth transistor. The resistor is coupled between the first power supply pad and the detection node. The third transistor has a first end coupled to the first power supply pad, a second end coupled to a second node, and a control terminal coupled to the detection node. The fourth transistor has a first end coupled to the second node, a second end coupled to a ground terminal, and a control terminal coupled to the detection node. The fifth transistor has a first end coupled to a first power supply pad, a second end coupled to a ground terminal, and a control terminal coupled to a second node.

[0005] When the protection circuit of the present invention enters the operation mode, the voltage of the power supply pad is at a high level at the first moment to turn off the PMOS transistor, thereby avoiding leakage current through the PMOS transistor. Attached Figure Description

[0006] Figure 1 This is a protection circuit according to an embodiment of the present invention.

[0007] Figure 2 for Figure 1 A schematic diagram of the normal operation of the protection circuit in the operating mode.

[0008] Figure 3 for Figure 1 The diagram shows the operation of the protection circuit when it encounters an overcurrent stress event in the operating mode.

[0009] Figure 4 for Figure 1 The diagram shows the main voltages of the protection circuit during normal operation and when encountering overcurrent stress events.

[0010] Figure 5 for Figure 1 A schematic diagram of the operation of the protection circuit when it encounters an electrostatic discharge event.

[0011] Figure 6A , Figure 6B for Figure 1 The diagram shows the main voltages of the protection circuit when it encounters an electrostatic discharge event.

[0012] Figure 7 This is a protection circuit according to another embodiment of the present invention.

[0013] Figure 8 This is a protection circuit according to another embodiment of the present invention.

[0014] Figure 9 for Figure 8 A schematic diagram of the normal operation of the protection circuit in the operating mode.

[0015] Figure 10 for Figure 8 The diagram shows the operation of the protection circuit when it encounters an overcurrent stress event in the operating mode.

[0016] Figure 11 for Figure 8 A schematic diagram of the operation of the protection circuit when it encounters an electrostatic discharge event.

[0017] Explanation of icon numbers:

[0018] 1: Protection circuit

[0019] 10: Detection circuit

[0020] 11: Discharge circuit

[0021] 60-63: Curve

[0022] 90: NMOS transistor

[0023] 100: PMOS transistor

[0024] 101: NMOS transistor

[0025] 102: Resistive Devices

[0026] 110: PMOS transistor

[0027] 111, 112: NMOS transistors

[0028] 113: Resistor

[0029] 114: Capacitor

[0030] GND: Ground terminal

[0031] N10, N12: Nodes

[0032] N11: Detection Node

[0033] P10: Detection Path

[0034] P11, P12: Discharge path

[0035] PAD1, PAD2: Power connection pads

[0036] R10: Resistor

[0037] V10, V12: Voltage

[0038] V11: Detection voltage

[0039] VP1, VP2: Voltage Detailed Implementation

[0040] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, a preferred embodiment is described below in detail with reference to the accompanying drawings.

[0041] Figure 1 This is a protection circuit according to an embodiment of the present invention. See also... Figure 1 The protection circuit 1 includes a detection circuit 10 and a discharge circuit 11. The protection circuit 1 also includes two power connection pads, PAD1 and PAD2. In one operating mode, the power connection pads PAD1 and PAD2 belong to different voltage domains. The power supply voltages received by each of the power connection pads PAD1 and PAD2 will be described in detail later. The detection circuit 10 is coupled to the power connection pads PAD1 and PAD2. The discharge circuit 11 is coupled to the detection circuit 10 via a detection node N11 and is further coupled to the power connection pad PAD1.

[0042] The detection circuit 10 detects whether an electrostatic discharge (ESD) event or an electrical overstress (EOS) event has occurred on the power connection pad PAD1, and controls the detection voltage at the detection node N11 based on the detection result indicating the occurrence of an ESD event or an EOS event. When an ESD event occurs on the power connection pad PAD1, the discharge circuit 11 provides a discharge path between the power connection pad PAD1 and the ground terminal GND based on the detection voltage at the detection node N11. When an EOS event occurs on the power connection pad PAD1, the detection circuit 10 activates at least one discharge path between the power connection pad PAD and the ground terminal GND. According to an embodiment of the present invention, the protection circuit 1 provides protection against both ESD and EOS. The detailed circuit architecture and operation of the protection circuit 1 will be described below.

[0043] like Figure 1As shown, the detection circuit 10 includes transistors 100 and 101, and a resistor 102. In this embodiment, transistor 100 is implemented as a P-type metal-oxide-semiconductor (PMOS) transistor, while transistor 101 is implemented as an N-type metal-oxide-semiconductor (NMOS) transistor. The first terminal (source) of the PMOS transistor 100 is coupled to power pad PAD1, its second terminal (drain) is coupled to node N10, and its control terminal (gate) is coupled to power pad PAD2. The first terminal (drain) of the NMOS transistor 101 is coupled to detection node N11, its second terminal (source) is coupled to ground GND, and its control terminal (gate) is coupled to node N10. In this embodiment, the resistor 102 includes a resistor R10. Resistor R10 is coupled between node N10 and ground GND.

[0044] The discharge circuit 11 includes transistors 110-112, resistor 113, and capacitor 114. Resistor 113 is coupled between power pad PAD1 and detection node N11. Capacitor 114 is coupled between detection node N11 and ground GND. In this embodiment, transistor 110 is implemented as a PMOS transistor, while transistors 111-112 are implemented as NMOS transistors. The first terminal of PMOS transistor 110 is coupled to power pad PAD1, its second terminal is coupled to node N12, and its control terminal is coupled to detection node N11. The first terminal of NMOS transistor 111 is coupled to node N12, its second terminal is coupled to ground GND, and its control terminal is coupled to detection node N11. The first terminal of NMOS transistor 112 is coupled to power pad PAD1, its second terminal is coupled to ground GND, and its control terminal is coupled to node N12.

[0045] exist Figure 1 In one embodiment, the thickness of the gate oxide layer of PMOS transistor 100 is preferably greater than the thickness of the gate oxide layer of PMOS transistor 110. Therefore, the gates of PMOS transistor 100 and PMOS transistor 110 are represented by different patterns; however, this invention is not limited thereto. In other embodiments, the thickness of the gate oxide layer of PMOS transistor 100 may be equal to or less than the thickness of the gate oxide layer of PMOS transistor 110.

[0046] See Figure 2When the protection circuit 1 is operating normally in the operating mode, one operating voltage is provided to the power connection pad PAD1, and another operating voltage is provided to the power connection pad PAD2, and the ground terminal GND has a ground voltage (e.g., 0 volts (V)). In this embodiment, the operating voltage provided to the power connection pad PAD2 is greater than or equal to the operating voltage provided to the power connection pad PAD1; for example, the operating voltage provided to the power connection pad PAD1 is 18V and the operating voltage provided to the power connection pad PAD2 is 24V. Therefore, the voltage VP1 of the power connection pad PAD1 is 18V, and the voltage VP2 of the power connection pad PAD2 is 24V.

[0047] Based on voltages VP1 and VP2, PMOS transistor 100 is turned off. Figure 2 In subsequent diagrams, the off transistor will be indicated by "(OFF)". At this time, because PMOS transistor 100 is off and resistor R10 is coupled to ground GND, the voltage V10 at node N10 is low. See also... Figure 4 The voltage V10 is approximately the voltage level of ground (GND) (0V). Based on the 0V voltage V10, NMOS transistor 101 is turned off. Furthermore, in response to voltage VP1, the detection voltage V11 at detection node N11 is approximately equal to voltage VP1. For example, see [link to relevant documentation]. Figure 4 The detection voltage V11 is approximately equal to 18V (V11≈18V). Based on the detection voltage V11 of approximately 18V, PMOS transistor 110 is turned off, and NMOS transistor 111 is turned on. Figure 2 In subsequent diagrams, the conducting transistors will be marked with "(ON)". Because NMOS transistor 111 is turned on, the voltage V12 on node N12 is close to or equal to the voltage level (0V) of ground terminal GND, so that NMOS transistor 112 is turned off.

[0048] As described above, when the protection circuit 1 operates normally in the operating mode, transistors 100 and 101 of the detection circuit 10 are turned off, causing the detection voltage V11 at the detection node N11 to have a level of approximately 18V. Based on the detection voltage V11, transistors 110 and 112 of the discharge circuit 11 are both turned off. Therefore, the detection circuit 10 does not provide any circuit path between the power supply pad PAD1 and the ground terminal GND, and the discharge circuit 11 also does not provide any circuit path between the power supply pad PAD1 and the ground terminal GND.

[0049] During normal operation, if the power connection pad PAD1 experiences overcurrent stress (i.e., an overcurrent stress event occurs on the power connection pad PAD1), the voltage VP1 of the power connection pad PAD1 will rise. See also... Figure 3 and Figure 4 For example, when an overcurrent stress event occurs on power pad PAD1, the voltage VP of power pad PAD1 rises to 30V. Based on voltages VP1 and VP2, PMOS transistor 100 turns on. Because PMOS transistor 100 is on, a detection path P10 is formed between power pad PAD1 and ground GND; that is, detection circuit 10 enables detection path P10 by the conduction of PMOS transistor 100. At this time, because PMOS transistor 100 is on, the voltage V10 at node N10 rises. See also... Figure 4 When voltage VP1 rises to 30V, voltage V10 also rises. In this embodiment, depending on the size of PMOS transistor 100 and the resistance value of resistor R10, in one embodiment, the level of voltage V10 after rising is lower than the detection voltage V11; for example, voltage V10 is approximately less than or equal to 5V.

[0050] In response to the rise in voltage V10, NMOS transistor 101 turns on. Because NMOS transistor 101 is on, a discharge path P11 is formed between the power supply pad PAD1 and the ground terminal GND. That is, the detection circuit 10 enables the discharge path P11 through the conduction of NMOS transistor 101. Through a voltage divider operation implemented by resistor 113 and the on-state NMOS transistor 101, the detection voltage V11 at detection node N11 is approximately equal to a preset voltage. In this embodiment, the preset voltage must be lower than the breakdown voltage of NMOS transistor 111 (e.g., 26V). By adjusting the resistance value of resistor 113 and the size of NMOS transistor 101, the preset voltage can be made equal to 18V, i.e., the detection voltage V11 is approximately equal to 18V. See also... Figure 4 When the voltage VP1 rises to 30V, the detection voltage V11 is approximately equal to 18V (V11≈18V).

[0051] In response to a voltage VP1 of 30V and a detection voltage V11 of approximately 18V, PMOS transistor 110 turns on. Furthermore, based on the detection voltage V11 of 18V, NMOS transistor 111 also turns on. Therefore, through the voltage divider operation implemented by the on-state transistors 110 and 111, the voltage V12 at node N12 rises. See also... Figure 4When the voltage VP rises to 30V, the voltage V12 also rises. In this embodiment, depending on the dimensions of the PMOS transistor 110 and the NMOS transistor 111, the level of the voltage V12 after it rises is lower than the detection voltage V11. For example, the voltage V12 is approximately less than or equal to 5V. In response to the detection voltage V12, the NMOS transistor 112 turns on to provide a discharge path P12 between the power connection pad PAD1 and the ground terminal GND.

[0052] As described above, when an overcurrent stress event occurs on the power pad PAD1 during operation, both transistors 100 and 101 of the detection circuit 10 are turned on, forming a detection path P10 and a discharge path P11 between the power pad PAD1 and the ground terminal GND. The charge on the power pad PAD1 is conducted to the ground terminal GND through the detection path P10 and the discharge path P11. Furthermore, thanks to resistor 113 and NMOS transistor 101, the detection voltage V11 at the detection node N11 is approximately equal to a preset voltage, preventing it from becoming too high and damaging the components within the discharge circuit 11, especially capacitor 114 and NMOS transistor 111. Additionally, NMOS transistor 112 is also turned on; therefore, when an overcurrent stress event occurs on the power pad PAD1, the discharge circuit 11 also provides a discharge path P12 between the power pad PAD1 and the ground terminal GND.

[0053] See Figure 4 When the overcurrent stress event disappears, the voltage VP1 of the power supply pad PAD1 returns to 24V, and the protection circuit 1 resumes normal operation. At this time, voltages V10 and V12 drop to near or equal to the voltage level of the ground terminal GND (0V), and the detection voltage V11 responds to voltage VP1 and is approximately equal to 18V.

[0054] See Figure 5 When protection circuit 1 is not in operating mode, the operating voltage is not supplied to power pads PAD1 and PAD2; that is, power pads PAD1 and PAD2 are in a floating state or their voltages VP1 and VP2 are equal to 0V. When an electrostatic discharge event (e.g., a positive electrostatic discharge event) occurs on power pad PAD1, its voltage VP1 instantaneously increases. At this time, since power pad PAD2 is in a floating state or its voltage VP2 is equal to 0V, PMOS transistor 100 is turned on. Because PMOS transistor 100 is turned on, the voltage V10 at node N10 instantaneously increases with voltage VP1.

[0055] In response to the instantaneous increase in voltage V10, NMOS transistor 101 turns on. Due to the device characteristics of capacitor 114, the detection voltage V11 does not increase instantaneously with VP1. Furthermore, the detection voltage V11 at detection node N11 is pulled low by the turned-on NMOS transistor 101. At this time, according to the detection voltage V11, PMOS transistor 110 turns on, while NMOS transistor 111 turns off. Through the turned-on PMOS transistor 110, the voltage V12 at node N12 increases instantaneously with voltage VP1, turning on NMOS transistor 112. Due to the conduction of NMOS transistor 112, a discharge path P12 is formed between power pad PAD1 and ground GND, allowing electrostatic charges on power pad PAD1 to be conducted to ground GND through this discharge path P12, thereby protecting other devices in the circuit coupled to power pad PAD1 from damage by electrostatic charges.

[0056] As described above, when an electrostatic discharge event occurs on the power bonding pad PAD1, both transistors 100 and 101 of the detection circuit 10 are turned on, so that the detection voltage V11 can be at a low level (close to or equal to the voltage level of the ground terminal GND (0V)), thereby enabling the formation of the discharge path P12.

[0057] Furthermore, compared to an electrostatic discharge protection circuit that only has a discharge circuit 11 (but not a detection circuit 10), when an electrostatic discharge event occurs on the power supply pad PAD1, the detection voltage V11 has a lower level and the voltage V12 has a higher level due to the operation of the detection circuit 10 in this case.

[0058] See Figure 6A , Figure 6B When an electrostatic discharge (ESD) event occurs on the power contact pad PAD1, the changes in the detection voltages V11 and V12 of the ESD protection circuit with only discharge circuit 11 are represented by curves 60 and 62, respectively. In contrast, the changes in the detection voltages V11 and V12 of the protection circuit 1 in this invention are represented by curves 61 and 63, respectively. By comparing curves 60 and 61, and curves 62 and 63, it can be seen that the detection circuit V11 in this invention has a lower voltage level, allowing the PMOS transistor 110 to be fully turned on. The circuit V12 in this invention has a higher voltage level, allowing the NMOS transistor 112 to be fully turned on, thereby providing a stable discharge path P12.

[0059] according to Figure 1In the illustrated embodiment, the protection circuit 1 of this invention provides not only electrostatic discharge protection but also overcurrent stress protection. By coupling power pads PAD1 and PDA2 to different power domains, when the detection circuit 10 detects an electrostatic discharge event or an overcurrent stress on power pad PDA1, transistors 100 and 101 within the detection circuit 10 are turned on, indicating the detection result. Based on this detection result, the detection circuit 10 controls the detection node N11 to have different voltages and enables at least one discharge path.

[0060] In detail, when the detection circuit 10 detects an overcurrent stress event at the power bonding pad PDA1, it controls the detection voltage V11 at the detection node N11 to be at a level lower than the breakdown voltage of the NMOS transistor 111 (e.g., 26V) (e.g., 18V), and enables the detection path P10 through PMOS transistor 100, node N10, and resistor R11, the discharge path P11 through resistor 113, detection node N11, and NMOS transistor 101, and the discharge path P12 through NMOS transistor 112 (shown in...). Figure 3 When the detection circuit 10 detects an electrostatic discharge event at the power junction pad PDA1, it controls the detection voltage V11 at the detection node N11 to be low (close to or equal to the voltage level of the ground terminal GND (0V)) and enables the discharge path P12 through the NMOS transistor 112 (shown in...). Figure 5 ).

[0061] according to Figure 5 According to the relevant description, capacitor 114 is used to prevent the detection voltage V11 from instantaneously increasing with VP1 when an electrostatic discharge event occurs on the power bonding pad PAD1, thus keeping it at a low level. Based on the operation of the detection circuit 10 in this case, when an electrostatic discharge event occurs, the detection circuit 10 can pull the detection voltage V11 low, meaning the detection voltage V11 will not instantaneously increase with VP1. Therefore, in other embodiments, capacitor 114 can be omitted.

[0062] See Figure 7 The discharge circuit 11 does not include capacitor 114, which reduces the area of ​​the protection circuit 1. Even though the discharge circuit 11 does not include capacitor 114, the detection voltage V11 can still be at a low level when an electrostatic discharge event occurs due to the operation of the detection circuit 10. Figure 7 For the operation of the intermediate protection circuit 1, please refer to the above. Figures 1 to 6A The relevant explanation is omitted here.

[0063] In the above embodiments, the resistive device 102 is implemented as a resistor R10. In other embodiments, the resistive device 102 may be implemented as other devices capable of providing resistance.

[0064] See Figure 8 The resistor device 102 includes an NMOS transistor 90. The first end of the NMOS transistor 90 is coupled to node N10, the second end is coupled to ground GND, and the control end is coupled to power pad PAD2. Figure 8 For the connection architecture of other components in protection circuit 1, please refer to the foregoing. Figure 1 Related explanations are omitted here. See also... Figure 9 When protection circuit 1 is operating normally in operating mode, one operating voltage is supplied to power connection pad PAD1, and another operating voltage is supplied to power connection pad PAD2, with the ground terminal GND having a ground voltage (e.g., 0 volts (V)). For example, the operating voltage supplied to power connection pad PAD1 is 18V and the operating voltage supplied to power connection pad PAD2 is 24V. Therefore, the voltage VP1 of power connection pad PAD1 is 18V, and the voltage VP2 of power connection pad PAD2 is 24V.

[0065] Based on voltages VP1 and VP2, PMOS transistor 100 is turned off. Furthermore, in response to voltage VP2, NMOS transistor 90 is turned on. At this time, the voltage V10 at node N10 is pulled down to approximately 0V (0V) to ground (GND) through the turned-on NMOS transistor 90, causing NMOS transistor 101 to turn off. Additionally, in response to voltage VP1, the detection voltage V11 at node N11 is approximately equal to voltage VP1; for example, the detection voltage V11 is approximately 18V. Based on the detection voltage V11, PMOS transistor 110 is turned off, and NMOS transistor 111 is turned on. Through the turned-on NMOS transistor 111, the voltage V12 at node N12 approaches or equals the ground (GND) level (0V), causing NMOS transistor 112 to turn off.

[0066] As described above, when the protection circuit 1 operates normally in the operating mode, transistors 100 and 101 of the detection circuit 10 are turned off. Furthermore, transistors 110 and 112 of the discharge circuit 11 are also turned off. Therefore, the detection circuit 10 does not provide any circuit path between the power supply pad PAD1 and the ground terminal GND, and the discharge circuit 11 also does not provide any circuit path between the power supply pad PAD1 and the ground terminal GND.

[0067] See Figure 10During normal operation, if an overcurrent stress event occurs on the power connection pad PAD1, the voltage VP1 of the power connection pad PAD1 rises to, for example, 30V. Based on voltages VP1 and VP2, PMOS transistor 100 turns on (ON). Furthermore, in response to voltage VP2, NMOS transistor 90 turns on (ON). Since both PMOS transistor 100 and NMOS transistor 90 are on, a detection path P10 is formed between the power connection pad PAD1 and ground GND. That is, the detection circuit 10 enables the detection path P10 by the conduction of PMOS transistor 100. The detection path P10 passes through PMOS transistor 100, node N10, and NMOS transistor 90. At this time, through the voltage divider operation implemented by the on-state PMOS transistor 100 and NMOS transistor 90, the voltage V10 on node N10 rises to turn on NMOS transistor 101 (ON).

[0068] Because NMOS transistor 101 is turned on, a discharge path P11 is formed between power pad PAD1 and ground GND. That is, the detection circuit 10 enables discharge path P11 through the conduction of NMOS transistor 101. Discharge path P11 passes through resistor 113, detection node N11, and NMOS transistor 101. Through the voltage divider operation implemented by resistor 113 and the turned-on NMOS transistor 101, the detection voltage V11 is approximately equal to a preset voltage. By adjusting the resistance value of resistor 113 and the size of NMOS transistor 101, the preset voltage can be made equal to 18V, which is lower than the breakdown voltage of NMOS transistor 111 (e.g., 26V). Responding to a voltage VP1 of 30V and a detection voltage V11 of approximately 18V, PMOS transistor 110 is turned on. Furthermore, based on the 18V detection voltage V11, NMOS transistor 111 is also turned on. Therefore, through the voltage divider operation implemented by the conducting transistors 110 and 111, the voltage V12 on node N12 rises, causing NMOS transistor 112 to turn on to provide a discharge path P12 between the power junction pad PAD1 and the ground terminal GND.

[0069] As described above, when an overcurrent stress event occurs on the power pad PAD1 during operation, transistors 100, 101, and 90 of the detection circuit 10 are all turned on, forming a detection path P10 and a discharge path P11 between the power pad PAD1 and the ground terminal GND. The charge on the power pad PAD1 is conducted to the ground terminal GND through the detection path P10 and the discharge path P11. Furthermore, thanks to resistor 113 and NMOS transistor 101, the detection voltage V11 at the detection node N11 is approximately equal to a preset voltage, preventing it from becoming too high and damaging the components within the discharge circuit 11, especially capacitor 114 and NMOS transistor 111. Additionally, NMOS transistor 112 is also turned on; therefore, when an overcurrent stress event occurs on the power pad PAD1, the discharge circuit 11 also provides a discharge path P12 between the power pad PAD1 and the ground terminal GND.

[0070] See Figure 11 When protection circuit 1 is not in operating mode, the operating voltage is not supplied to power connection pads PAD1 and PAD2; that is, power connection pads PAD1 and PAD2 are in a floating state or their voltages VP1 and VP2 are equal to 0V. When an electrostatic discharge event occurs on power connection pad PAD1, the voltage VP2 of power connection pad PAD1 increases instantaneously. At this time, since power connection pad PAD2 is in a floating state or its voltage VP2 is equal to 0V, PMOS transistor 100 is turned on (ON), while NMOS transistor 90 is turned off (OFF). Through the turned-on PMOS transistor 100, the voltage V10 at node N10 increases instantaneously with the voltage VP1.

[0071] In response to the instantaneous increase in voltage V10, NMOS transistor 101 turns on. Due to the device characteristics of capacitor 114, the detection voltage V11 does not increase instantaneously with VP1. Furthermore, the detection voltage V11 at detection node N11 is pulled low by the turned-on NMOS transistor 101. At this time, according to the detection voltage V11, PMOS transistor 110 turns on, while NMOS transistor 111 turns off. Through the turned-on PMOS transistor 110, the voltage V12 at node N12 increases instantaneously with voltage VP1, turning on NMOS transistor 112. Due to the conduction of NMOS transistor 112, a discharge path P12 is formed between power pad PAD1 and ground GND, allowing electrostatic charges on power pad PAD1 to be conducted to ground GND through this discharge path P12, thereby protecting other devices in the circuit coupled to power pad PAD1 from damage by electrostatic charges.

[0072] As described above, when an electrostatic discharge event occurs on the power bonding pad PAD1, transistors 100 and 101 of the detection circuit 10 are turned on while transistor 90 is turned off, so that the detection voltage V11 can be at a low level (close to or equal to the voltage level of the ground terminal GND (0V)), thereby enabling the formation of the discharge path P12.

[0073] Based on the above, Figure 8 The protection circuit 1 provides both electrostatic discharge (ESD) protection and overcurrent stress protection. By coupling power pads PAD1 and PDA2 to different power domains, when the detection circuit 10 detects an ESD event or an overcurrent stress on power pad PDA1, transistors 100 and 101 within the detection circuit 10 are turned on, indicating the detection result. Based on this detection result, the detection circuit 10 controls the detection node N11 to have different voltages and enables at least one discharge path.

[0074] In detail, when the detection circuit 10 detects an overcurrent stress event at the power bonding pad PDA1, it controls the detection voltage V11 at the detection node N11 to be at a level lower than the breakdown voltage of the NMOS transistor 111 (e.g., 26V) (e.g., 18V), and enables the detection path P10 through PMOS transistor 100, node N10, and resistor R11, the discharge path P11 through resistor 113, detection node N11, and NMOS transistor 101, and the discharge path P12 through NMOS transistor 112 (shown in...). Figure 10 When the detection circuit 10 detects an electrostatic discharge event at the power junction pad PDA1, it controls the detection voltage V11 at the detection node N11 to be low (close to or equal to the voltage level of the ground terminal GND (0V)) and enables the discharge path P12 through the NMOS transistor 112 (shown in...). Figure 11 ).

[0075] exist Figure 8 In some embodiments, the thickness of the gate oxide layer of PMOS transistor 100 is greater than the thickness of the gate oxide layer of PMOS transistor 110; however, the present invention is not limited thereto. Figure 8 In other embodiments based on the circuit architecture, the thickness of the gate oxide layer of PMOS transistor 100 may be equal to or less than the thickness of the gate oxide layer of PMOS transistor 110.

[0076] In addition, Figure 8In some embodiments, the discharge circuit 11 may not include the capacitor 114, thus allowing the protection circuit 1 to occupy a smaller area. Even if the discharge circuit 11 does not include the capacitor 114, due to the operation of the detection circuit 10, the detection voltage V11 can be kept low by the conducting NMOS transistor 101 in the event of an electrostatic discharge, thereby enabling the formation of the discharge path P12.

[0077] In the above embodiments, when the protection circuit 1 enters the operation mode, two different operating voltages can be simultaneously supplied to power pads PAD1 and PAD2. In other embodiments, when the protection circuit 1 enters the operation mode, the two different operating voltages can be supplied to power pads PAD1 and PAD2 sequentially. For example, one operating voltage is first supplied to power pad PAD2, and then another operating voltage is supplied to power pad PAD1. In this way, when the protection circuit 1 enters the operation mode, the voltage VP2 of power pad PAD2 is high immediately to turn off the PMOS transistor 100, thereby preventing leakage current through the PMOS transistor 100.

[0078] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A protection circuit comprising a first power supply pad and a second power supply pad, characterized in that, include: A detection circuit, coupled to a first power contact pad and a second power contact pad, is used to detect whether an electrostatic discharge event occurs on the first power contact pad when the protection circuit is not in an operating mode, or whether an overcurrent stress event occurs on the first power contact pad when the protection circuit is operating normally in the operating mode. The circuit also controls a detection voltage at a detection node based on the detection result, wherein the first power contact pad and the second power contact pad belong to different power domains. A discharge circuit is coupled to the detection node and the first power contact pad. Wherein, when the electrostatic discharge event occurs on the first power bonding pad, the discharge circuit provides a first discharge path between the first power bonding pad and a ground terminal based on the detected voltage; and When the overcurrent stress event occurs on the first power bonding pad, the detection circuit enables a second discharge path, different from the first discharge path, between the first power bonding pad and the ground terminal, and the discharge circuit provides the first discharge path according to the detection voltage.

2. The protection circuit as described in claim 1, characterized in that: When the protection circuit is in normal operation in an operating mode, the first power contact pad receives a first voltage, and the second power contact pad receives a second voltage; and The second voltage is greater than or equal to the first voltage.

3. The protection circuit as described in claim 2, characterized in that, The second voltage is supplied to the second power pad earlier than the first voltage is supplied to the first power pad.

4. The protection circuit as described in claim 2, characterized in that, When the protection circuit is not in the operating mode, the first power pad does not receive the first voltage, and the second power pad floats or receives a zero-volt voltage.

5. The protection circuit as described in claim 1, characterized in that, The detection circuit includes: A first transistor has a first end coupled to the first power pad, a second end coupled to a first node, and a control end coupled to the second power pad. A resistor is coupled between the first node and the ground terminal; and A second transistor has a first terminal coupled to the detection node, a second terminal coupled to the ground terminal, and a control terminal coupled to the first node.

6. The protection circuit as described in claim 5, characterized in that: The discharge circuit includes a resistor coupled between the first power bonding pad and the detection node. as well as When the overcurrent stress event occurs on the first power bonding pad, the second discharge path passes through the resistor, the detection node, and the second transistor.

7. The protection circuit as described in claim 6, characterized in that, When the overcurrent stress event occurs on the first power bonding pad, the detection circuit further enables a detection path between the first power bonding pad and the ground terminal, and the detection path passes through the first transistor, the first node, and the resistor device.

8. The protection circuit as described in claim 5, characterized in that, The resistive device includes a resistor.

9. The protection circuit as described in claim 5, characterized in that, The resistive device includes a third transistor, and the third transistor has a first terminal coupled to the first node, a second terminal coupled to the ground terminal, and a control terminal coupled to the second power supply pad.

10. A protection circuit, characterized in that, include: A detection circuit, including: A first transistor has a first end coupled to a first power pad, a second end coupled to a first node, and a control end coupled to a second power pad, wherein the first power pad and the second power pad belong to different power domains. A resistor is coupled between the first node and a ground terminal; and A second transistor having a first terminal coupled to a detection node, a second terminal coupled to the ground terminal, and a control terminal coupled to the first node; and A discharge circuit, coupled to the detection node and the first power contact pad, and comprising: A resistor is coupled between the first power bonding pad and the detection node; A third transistor has a first end coupled to the first power junction pad, a second end coupled to a second node, and a control end coupled to the detection node; A fourth transistor having a first terminal coupled to the second node, a second terminal coupled to the ground terminal, and a control terminal coupled to the detection node; and A fifth transistor has a first end coupled to the first power supply pad, a second end coupled to the ground terminal, and a control terminal coupled to the second node.

11. The protection circuit as described in claim 10, characterized in that: When an electrostatic discharge event occurs on the first power bonding pad, the fifth transistor is turned on; as well as In one operating mode of the protection circuit, when an overcurrent stress event occurs on the first power contact pad, the first transistor and the second transistor are turned on.

12. The protection circuit as described in claim 11, characterized in that, When the overcurrent stress event occurs on the first power bonding pad, the fifth transistor is turned on.

13. The protection circuit as described in claim 11, characterized in that: When the protection circuit is in the operating mode, the first power contact pad receives a first voltage, and the second power contact pad receives a second voltage; and The second voltage is greater than or equal to the first voltage.

14. The protection circuit as described in claim 13, characterized in that, The second voltage is supplied to the second power pad earlier than the first voltage is supplied to the first power pad.

15. The protection circuit as described in claim 13, characterized in that, When the protection circuit is not in the operating mode, the first power pad does not receive the first voltage, and the second power pad floats or receives a zero-volt voltage.

16. The protection circuit as described in claim 10, characterized in that, The discharge circuit further includes: A capacitor is coupled between the detection node and the grounding terminal.

17. The protection circuit as described in claim 10, characterized in that, The thickness of the gate oxide layer of the first transistor is greater than the thickness of the gate oxide layer of the third transistor.

18. The protection circuit as described in claim 10, characterized in that, The resistive device includes a resistor.

19. The protection circuit as described in claim 10, characterized in that, The resistive device includes a sixth transistor, and the sixth transistor has a first terminal coupled to the first node, a second terminal coupled to the ground terminal, and a control terminal coupled to the second power supply pad.

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