Computing device and pcie unit

Abstract

Embodiments of the present application provide a computing device and a PCIE unit, and relate to the technical field of computing devices. The computing device comprises a housing, a hard disk backboard, a processing unit and a plurality of PCIE interfaces. The housing encloses a receiving cavity, and comprises a mounting slot. The hard disk backboard is located in the receiving cavity and is located on one side of the mounting slot along the extension direction of the mounting slot. The processing unit is located in the receiving cavity. The plurality of PCIE interfaces are arranged on the side of the hard disk backboard close to the mounting slot and are electrically connected to the processing unit. At least two PCIE interfaces are arranged side by side and located in the same mounting slot, forming a PCIE interface group. In the embodiments of the present application, at least two PCIE interfaces are arranged side by side and located in the same mounting slot, so that the elements (such as PCIE units or hard disks) located in the mounting slot can be plugged with one or more PCIE interfaces in the PCIE interface group, improving the flexibility of plugging the elements located in the mounting slot with the PCIE interfaces, thereby improving the use flexibility of the computing device.

Description

Technical Field

[0001] Embodiments of this application relate to the technical field of computing devices, and more particularly to a computing device and a PCIe unit. Background Technology

[0002] Computing devices typically include mounting slots and hard drive backplanes. The hard drive backplanes have hard drive interfaces, and each hard drive interface is located in a mounting slot. The hard drive in the mounting slot can be plugged into the hard drive interface, thereby enabling the hard drive to be electrically connected to the hard drive backplane. Summary of the Invention

[0003] The purpose of embodiments of this application is to provide a computing device and a PCIe unit for improving the flexibility of electrical connections between components located in the mounting slot and a hard disk backplane (e.g., a PCIe unit or a hard disk).

[0004] To achieve the above objectives, the following technical solution is provided:

[0005] In one aspect, embodiments of this application provide a computing device. The computing device includes a housing, a hard disk backplane, a processing unit, and multiple PCIe interfaces. The housing encloses a receiving cavity and includes a mounting slot. The hard disk backplane is located within the receiving cavity and is situated on one side of the mounting slot along its extension direction. The processing unit is located within the receiving cavity. Multiple PCIe interfaces are disposed on the side of the hard disk backplane near the mounting slot and are electrically connected to the processing unit. At least two PCIe interfaces are arranged side-by-side and located within the same mounting slot, forming a PCIe interface group.

[0006] In the embodiments of this application, at least two PCIe interfaces are arranged side by side and located in the same mounting slot to form a PCIe interface group. This allows components located in the mounting slot (such as PCIe units or hard drives) to be plugged into one or more PCIe interfaces in the PCIe interface group located on the hard drive backplane according to different bandwidth requirements. This improves the flexibility of plugging in components located in the mounting slot to PCIe interfaces located on the hard drive backplane, meets the bandwidth requirements of different components, and thus improves the flexibility of using the computing device.

[0007] In some embodiments, the computing device further includes a PCIe unit located within a mounting slot. The PCIe unit is connected to at least two PCIe interfaces in a PCIe interface group. This configuration, on the one hand, reduces the limitation imposed by the bandwidth of a single PCIe interface on the PCIe unit, allowing the PCIe interface group to meet the needs of PCIe units with different bandwidths, increasing the data transfer rate between the PCIe unit and the motherboard, thereby improving the computing device's data processing capabilities; on the other hand, it reduces the limitation imposed by the power of a single PCIe interface on the PCIe unit, allowing the PCIe interface group to meet the needs of PCIe units with different power ratings, improving the flexibility of the computing device; furthermore, by connecting the PCIe unit to at least two PCIe interfaces in the PCIe interface group located on the hard drive backplane, the connection or disconnection of the PCIe unit and PCIe interfaces can be achieved without opening the computing device's casing (i.e., the chassis), improving the ease of use of the computing device.

[0008] In some embodiments, a PCIe unit includes a first PCIe unit or a second PCIe unit. A PCIe interface group includes a first PCIe interface and a second PCIe interface. The first PCIe unit is plugged into the first PCIe interface, or the second PCIe unit is plugged into both the first and second PCIe interfaces simultaneously. The first PCIe interface also includes a detection pin. The processing unit is configured to: determine that the first PCIe unit is plugged into the PCIe interface when the detection pin receives a first level signal; determine that the second PCIe unit is plugged into the PCIe interface when the detection pin receives a second level signal; and determine that no PCIe unit is plugged into the PCIe interface when the detection pin is floating. This configuration allows the detection pin to detect whether a PCIe unit is plugged into the PCIe interface, and to determine the type of PCIe unit plugged into the PCIe interface (e.g., the first and second PCIe units) when a PCIe unit is plugged into the PCIe interface, thereby improving the reliability of the computing device.

[0009] In some embodiments, the processing unit includes a plurality of signal ports, including a plurality of first signal ports and a plurality of second signal ports arranged adjacent to each other. A first PCIe interface includes a plurality of first signal channels, each of which is electrically connected to one of the adjacent first signal ports. A second PCIe interface includes a plurality of second signal channels, each of which is electrically connected to one of the adjacent second signal ports. The plurality of first signal ports and the plurality of second signal ports are arranged adjacent to each other. This arrangement allows the plurality of signal channels (including the plurality of first signal channels and the plurality of second signal channels) of at least two PCIe interfaces in the PCIe interface group to be electrically connected to the plurality of adjacent signal ports (including the plurality of adjacent first signal ports and the plurality of adjacent second signal ports) of the processing unit, thereby enabling the PCIe unit to operate normally and improving the reliability of the computing device.

[0010] In some embodiments, the computing device further includes a management and control unit. The PCIe interface group includes multiple NCSI (Network Controller Sideband Interface) pins, which are electrically connected to the management and control unit. These multiple NCSI pins are configured on different PCIe interfaces within the PCIe interface group. This configuration allows the PCIe unit to obtain task information from the management and control unit via the NCSI pins, enabling out-of-band management of the PCIe unit and improving the ease of use of the computing device. Furthermore, it avoids conflicts between the NCSI pins and other pins on a single PCIe interface due to an insufficient number of available pins. In other words, by configuring multiple NCSI pins on different PCIe interfaces within the PCIe interface group, even if the number of NCSI pins exceeds the number of available pins on a single PCIe interface, multiple NCSI pins can still be configured on the PCIe interface group, achieving out-of-band management of the PCIe unit and improving the ease of use of the computing device.

[0011] In some embodiments, the number of NCSI pins is seven, with three located on the first PCIe interface and the other four on the second PCIe interface. This configuration allows the NCSI pins to be located on different PCIe interfaces within the PCIe interface group. Thus, even if the number of NCSI pins exceeds the number of available pins on a single PCIe interface, multiple NCSI pins can still be located across the PCIe interface group, enabling out-of-band management of the PCIe unit and improving the ease of use of the computing device.

[0012] In some embodiments, the computing device further includes at least two hard drives located in mounting slots, with at least two PCIe interfaces in the PCIe interface group corresponding to at least two hard drives. This configuration enables the PCIe interfaces to be multiplexed, allowing PCIe units or hard drives to be connected to PCIe interfaces located on the hard drive backplane, thus improving the flexibility of the computing device.

[0013] In some embodiments, the PCIe interface includes a U.2 interface. This configuration allows the PCIe interface to be a multiplexed interface, enabling hard drives or PCIe units to connect to the PCIe interface located on the hard drive backplane, improving the flexibility of computing devices. Furthermore, the PCIe interface can include a U.2 interface, allowing it to support SAS (Serial Attached SCSI) protocols, SATA (Serial Advanced Technology Attachment) protocols, and NVMe (Non-Volatile Memory Express) protocols, thus enhancing the applicability of the PCIe interface and meeting diverse usage requirements.

[0014] In some embodiments, the housing further includes a first guide plate located within the slot and positioned between two adjacent PCIe interfaces along a first direction. The extension direction of the first guide plate is the same as the extension direction of the mounting slot. This arrangement allows the first guide plate to guide and limit the insertion of components (such as PCIe units or hard drives) into the mounting slot, improving the ease of connection between the components and the PCIe interfaces located on the hard drive backplane, thereby enhancing the ease of use of the computing device.

[0015] In some embodiments, the housing further includes a second guide plate located within the mounting slot and positioned between the first guide plate and the hard disk backplane along a second direction, which intersects the first direction. This arrangement allows the second guide plate to guide and limit the insertion of components (e.g., PCIe units or hard disks) into the mounting slot, improving the ease of connection between the inserted components and the PCIe interface on the hard disk backplane, thereby enhancing the usability of the computing device.

[0016] On the other hand, embodiments of this application provide a PCIe unit for connecting to the PCIe interface of a computing device as described above. The PCIe unit includes at least two PCIe connectors, which are connected to the PCIe interface in a one-to-one correspondence.

[0017] The PCIe unit provided in the embodiments of this application is used to connect to the PCIe interface of the computing device as described above, and therefore has all the aforementioned beneficial effects, which will not be repeated here. Furthermore, by providing at least two PCIe connectors that connect one-to-one with the PCIe interfaces, the PCIe unit can connect to at least two PCIe interfaces in the PCIe interface group located on the hard drive backplane, meeting the bandwidth and power requirements of different PCIe units and improving the flexibility of the computing device.

[0018] In some embodiments, the PCIe unit further includes a circuit board and a chip. The chip is disposed on the circuit board, and at least two PCIe connectors are spaced apart at one end of the circuit board. The circuit board has clearance spaces to allow passage of a first guide plate and a second guide plate of the computing device. This arrangement prevents the first and second guide plates from obstructing the PCIe unit, allowing the PCIe unit to be inserted into the mounting slot under the guidance of the first and / or second guide plates, thus improving the ease of use of the PCIe unit. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0020] Figure 1A Structural block diagrams of computing devices provided in some embodiments of this application;

[0021] Figure 1B Structural diagrams of the housing of a computing device provided in some embodiments of this application;

[0022] Figure 1C Structural diagrams of mounting slots and hard disk backplanes provided in some embodiments of this application;

[0023] Figure 2A Structural diagrams of mounting slots and hard disk backplanes provided in other embodiments of this application;

[0024] Figure 2B This application provides structural diagrams of PCIe interface groups for some embodiments.

[0025] Figure 3A Structural diagrams of mounting slots and PCIe units provided in some embodiments of this application;

[0026] Figure 3B This application provides structural block diagrams of PCIe units and processing units in some embodiments.

[0027] Figure 3C This application provides structural diagrams of PCIe units in some embodiments.

[0028] Figure 4A Structural diagrams of mounting slots and hard disks provided in some embodiments of this application;

[0029] Figure 4B Structural block diagrams of the hard disk and processing unit provided in some embodiments of this application;

[0030] Figure 5A A structural diagram of a first PCIe interface provided in some embodiments of this application;

[0031] Figure 5B This is a structural diagram of a second PCIe interface provided in some embodiments of this application. Detailed Implementation

[0032] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0033] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0034] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0035] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0036] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0037] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0038] Figure 1A This is a structural block diagram of a computing device provided in some embodiments of this application. Figure 1B This is a structural diagram of the housing of a computing device provided in some embodiments of this application.

[0039] In some examples, such as Figure 1A As shown, embodiments of this application provide a computing device 100. It is understood that the computing device 100 can be an electronic device with processing, computing, and communication functions. For example, the computing device 100 can be a server, workstation, memory, switch, high-performance PC (Personal Computer), or repeater, etc. It is understood that embodiments of this application do not further limit the type of computing device 100.

[0040] In some examples, such as Figure 1A and Figure 1BAs shown, the computing device 100 may include a housing 110, which may enclose a receiving cavity 110a. The computing device 100 may also include a motherboard 170, which may be located within the receiving cavity 110a. For example, the motherboard 170 may include a printed circuit board (PCB).

[0041] In some examples, such as Figure 1A As shown, the computing device 100 may further include a processing unit 140, which may be located within the receiving cavity 110a and electrically connected to the motherboard 170, enabling data to be transferred between the motherboard 170 and the processing unit 140. In some examples, the processing unit 140 may be electrically connected to the motherboard 170 via a plug-in connection.

[0042] Understandably, the processing unit 140 can be used to process data. In some examples, the processing unit 140 may include a CPU (Central Processing Unit) or a TPU (Tensor Processing Unit), etc.

[0043] In some examples, the number of processing units 140 can be one or more. For example, such as... Figure 1A As shown, when there are multiple processing units 140, the multiple processing units 140 can be arranged at intervals on the motherboard 170. It can be understood that the multiple processing units 140 can be of the same type or different types.

[0044] Figure 1C This is a structural diagram of the mounting slot and hard disk backplane provided in some embodiments of this application. It should be noted that in the accompanying drawings of this application, [the following text is incomplete and likely refers to a different document or specification]. Figure 1C For example, to clearly illustrate the structure of the mounting slot 120, only one mounting slot 120 is shown, and the number of mounting slots 120 in the embodiments of this application is not further limited. See below for reference. Figure 1B and Figure 1C The mounting slot 120 and the hard drive backplane 121 are illustrated with examples.

[0045] In some examples, such as Figure 1B and Figure 1C As shown, the housing 110 may include a mounting slot 120, for example, the mounting slot 120 may be located on one side of the receiving cavity 110a along the second direction Y.

[0046] Understandably, the mounting slot 120 serves to support and protect components of the computing device 100 (such as a PCIe unit or a hard drive). For example, the housing 110 may include a plurality of mounting slots 120, which may be arranged adjacent to each other along a first direction X. The first direction X intersects a second direction Y; in some examples, the first direction X and the second direction Y may be perpendicular or approximately perpendicular.

[0047] Understandably, the first direction X and the second direction Y are "approximately perpendicular", that is, the angle between the first direction X and the second direction Y can be approximately 90°. For example, the angle between the first direction X and the second direction Y can be 88°, 89°, 90.5°, 91° or 92°, etc.

[0048] In some examples, such as Figure 1C As shown, the computing device 100 may also include a hard disk backplane 121, which may be located within the receiving cavity 110a and may be located on one side of the mounting slot 120 along the extension direction of the mounting slot 120.

[0049] In some examples, such as Figure 1B As shown, the mounting slot 120 can extend along the second direction Y, and the hard disk backplane 121 can be located on one side of the mounting slot 120 along the second direction Y and within the receiving cavity 110a. In some examples, the hard disk backplane 121 may include a PCB board.

[0050] In some examples, such as Figure 1C As shown, the mounting slot 120 may include a base plate 124, a cover plate 125, and a front panel 126. The base plate 124 may be disposed opposite to the cover plate 125, one edge of the front panel 126 may be connected to the base plate 124, and the edge of the front panel 126 away from the base plate 124 may be connected to the cover plate 125. A slot 1261 may be provided on the front panel 126, and a hard drive backplate 121 may be disposed opposite to the front panel 126.

[0051] Understandably, one edge of the panel 126 can be connected to the base plate 124, and the edge of the panel 126 away from the base plate 124 can be connected to the cover plate 125. The base plate 124 and the cover plate 125 can be positioned opposite each other, allowing the base plate 124, cover plate 125, and panel 126 to enclose the mounting slot 120. In some examples, the mounting slot 120 can be a cuboid or a cube, etc.

[0052] In some examples, such as Figure 1CAs shown, the mounting slot 120 may also include a side plate 129. For example, there may be two side plates 129, which may be arranged opposite each other. One edge of either side plate 129 may be connected to the base plate 124, and the edge of either side plate 129 away from the base plate 124 may be connected to the cover plate 125.

[0053] Understandably, since the mounting slots 120 can be arranged adjacently along the first direction X, the two mounting slots 120 arranged adjacently along the first direction X can reuse the side plate 129.

[0054] In some examples, such as Figure 1C As shown, a socket 1261 may be provided on the panel 126. Understandably, the socket 1261 can penetrate the panel 126 along the thickness direction of the panel 126, so that components (such as PCIe units or hard drives) can be inserted into the mounting slot 120 through the socket 1261.

[0055] In some examples, such as Figure 1C As shown, computing device 100 may include multiple PCIe (Peripheral Component Interconnect Express) interfaces 151. Understandably, with the rapid development of technology, network bandwidth (i.e., data transmission capacity) is becoming increasingly larger, and the speeds of various PCIe interfaces 151 are also constantly improving. For example, the PCIe protocol has evolved to the PCIe 5.0 standard, with a single-link speed reaching 32GT / s (Gigabit Transactions Per Second).

[0056] In some examples, such as Figure 1C As shown, the PCIe interface 151 can be located on the side of the hard drive backplate 121 near the mounting slot 120 and is electrically connected to the processing unit 140.

[0057] For example, the hard drive backplane 121 can be electrically connected to the motherboard 170, so that the PCIe interface 151 provided on the hard drive backplane 121 can be electrically connected to the motherboard 170, and through the motherboard 170 to the processing unit 140. In some examples, the hard drive backplane 121 can be electrically connected to the motherboard 170 via a cable.

[0058] In some examples, the PCIe interface 151 may include multiple pins, some of which may be electrically connected to the processing unit 140, thereby enabling data to be transferred between the PCIe interface 151 and the processing unit 140.

[0059] In this way, components (such as PCIe units or hard drives) can be inserted into the mounting slot 120, allowing the components in the mounting slot 120 to connect to the PCIe interface 151, thereby enabling the components in the mounting slot 120 to be electrically connected to the hard drive backplane 121. Since the hard drive backplane 121 can be electrically connected to the motherboard 170, the components in the mounting slot 120 can be electrically connected to the processing unit 140 through the hard drive backplane 121 and the motherboard 170, thereby enabling data transfer between the components in the mounting slot 120 and the processing unit 140.

[0060] In some examples, such as Figure 1A As shown, the computing device 100 may include a PCIe unit 130, which may be located in the mounting slot 120 and plugged into the PCIe interface 151.

[0061] In some examples, PCIe unit 130 may include PCIe expansion cards, such as network cards, GPU (Graphics Processing Unit) acceleration service cards, PCIe switches, CXL storage expansion cards, high-performance DPU (Data Processing Unit) cards, etc. It is understood that the embodiments of this application do not further limit the type of PCIe unit 130.

[0062] For example, there can be multiple PCIe units 130, and these multiple PCIe units 130 can be of the same or different types. Understandably, when there are multiple PCIe units 130, one PCIe unit 130 can be located within one mounting slot 120.

[0063] In some examples, PCIe unit 130 may include a PCIe connector that can be plugged into PCIe interface 151, allowing PCIe unit 130 to be electrically connected to motherboard 170. Understandably, the PCIe connector and PCIe interface 151 are hot-swappable.

[0064] In some examples, the PCIe connector can be male, and the PCIe interface 151 can be female. In other examples, the PCIe interface 151 can be female, and the PCIe interface 151 can be male.

[0065] In some examples, such as Figure 1BAs shown, the mounting slot 120 can be located on one side of the housing 110. In this way, the PCIe unit 130 can be connected to the PCIe interface 151 located on the hard drive backplate 121 without opening the housing 110 (i.e., the chassis), thus improving the ease of use of the computing device 100.

[0066] In other words, compared to placing the PCIe interface 151 on the motherboard 170, the embodiment of this application places the PCIe interface 151 on the hard drive backplane 121. This allows for the connection and disconnection of the PCIe unit 130 and the PCIe interface 151 without opening the housing 110, reducing operational difficulty and improving the convenience of hot-swapping between the PCIe unit 130 and the PCIe interface 151. This, in turn, improves the convenience of electrical connection between the PCIe unit 130 and the motherboard 170, facilitating the upgrade of the PCIe unit 130 and the expansion of the computing device 100.

[0067] In some examples, the panel 126 of the mounting slot 120 may be provided with one or more external interfaces, which may be located on the outer periphery of the socket 1261. The PCIe unit 130 located within the mounting slot 120 can be electrically connected to the external interface via a cable, thereby enabling the PCIe unit 130 to be electrically connected to other units or devices through the external interface.

[0068] For example, external interfaces may include network electrical ports, network optical ports, video display interfaces, SAS interfaces, SAS expansion ports, WIFI (Wireless Fidelity) antenna interfaces, and other low-speed interfaces such as USB interfaces, serial ports, and debug I / O (Input Output) interfaces.

[0069] In some examples, such as Figure 1A As shown, the computing device 100 may also include a hard disk 180, which can be understood to be used for storing data. For example, the hard disk 180 may include a hard disk drive (HDD), a solid state drive (SSD), and a hybrid hard drive (HHD), etc.

[0070] In some implementations, the PCIe interface 151 must conform to the PCIe CEM card standard, featuring gold fingers (connecting fingers) to support hot-swapping. However, the physical form of the hard drive interface is typically different from that of the PCIe interface 151 (for example, the hard drive interface could be a U.2 interface). This results in the PCIe interface 151 and the hard drive interface being incompatible; the PCIe interface 151 can only be connected to the PCIe unit 130, and the hard drive interface can only be connected to the hard drive 180, impacting the flexibility and convenience of using the computing device 100.

[0071] Based on this, in some examples, the PCIe interface 151 can be a multiplexed interface, allowing the hard drive 180 to be inserted into the mounting slot 120 and connected to the PCIe interface 151 located on the hard drive backplane 121, so that the hard drive 180 can be electrically connected to the motherboard 170 through the hard drive backplane 121. Since the processing unit 140 can be electrically connected to the motherboard 170, data can be transferred between the processing unit 140 and the motherboard 170.

[0072] Understandably, the PCIe interface 151 can be configured as a multiplexed interface. When the multiplexed interface is plugged into the PCIe unit 130, the multiplexed interface becomes the PCIe interface 151, serving to connect the PCIe unit 130 and the motherboard 170. When the multiplexed interface is plugged into the hard drive 180, the multiplexed interface becomes the hard drive interface, serving to connect the hard drive and the motherboard 170.

[0073] For example, hard disk 180 may include a hard disk connector that can be plugged into a hard disk interface, enabling hard disk 180 to be electrically connected to hard disk backplane 121.

[0074] Understandably, the hard drive connector and the hard drive interface are hot-swappable. In some examples, the hard drive interface can be female and the hard drive connector can be male. In other examples, the hard drive interface can be male and the hard drive connector can be female.

[0075] In some examples, the hard disk 180 and the PCIe unit 130 may be located in different mounting slots 120 and connected to different PCIe interfaces 151.

[0076] Understandably, by setting the PCIe interface 151 as a multiplexed interface, the hard drive 180 can be placed in the installation slot 120 and plugged into the PCIe interface 151. This allows for the connection or disconnection of the hard drive 180 and the PCIe interface 151 without opening the casing 110 of the computing device 100, thus improving the ease of use of the computing device 100.

[0077] Furthermore, it enables the hard disk 180 or PCIe unit 130 to be plugged into the PCIe interface 151 located on the hard disk backplane 121, thereby allowing the PCIe resources of the processing unit 140 to be flexibly allocated to the hard disk 180 (e.g., NVMe SSD) and PCIe unit 130, improving the flexibility of the computing device 100.

[0078] In some examples, computing device 100 may also include a tray, and the number of components (such as PCIe unit 130 or hard disk 180) located in the same mounting slot 120 may be multiple, with at least two components located on the same tray. The tray is used to insert at least two components into the mounting slot 120, so that the components can be plugged into the PCIe interface 151 on the hard disk backplane 121, thereby improving the ease of use of computing device 100.

[0079] Understandably, as the PCIe interface speed increased, CXL (Compute Express Link) technology based on PCIe emerged, giving rise to a new development direction for computing device architecture. More and more network devices, such as network cards and hard drives, are also developing in line with the advancements in PCIe technology.

[0080] Taking SSDs as an example, SSDs can be implemented as NVMe (Non-Volatile Memory Express) SSDs through PCIe links. Compared with traditional SAS (Serial Attached SCSI) SSDs and SATA (Serial Advanced Technology Attachment) SSDs, NVMe SSDs offer significantly improved performance.

[0081] The SSD Form Factor Work Group defines the standard form factor and signal definitions for SSD interfaces. For example, the SSD interface can be a U.2 interface, also known as the SFF-8639 interface, which supports SAS, SATA, and NVMe protocols. For example, the U.2 interface can support either 2.5-inch (2.5-inch diameter platters) or 3.5-inch (3.5-inch diameter platters) hard drives.

[0082] In some examples, PCIe interface 151 may include a U.2 interface.

[0083] Understandably, the PCIe interface 151 may include a U.2 interface, enabling the PCIe interface 151 to be a multiplexed interface. That is, the hard disk 180 or the PCIe unit 130 can be plugged into the PCIe interface 151 located on the hard disk backplane 121, thereby allowing the PCIe resources of the processing unit 140 to be flexibly allocated to the hard disk 180 (e.g., NVMe SSD) and the PCIe unit 130, improving the flexibility of the computing device 100.

[0084] In addition, the PCIe interface 151 can include a U.2 interface, enabling the PCIe interface 151 to support SAS, SATA and NVMe protocols, thereby improving the applicability of the PCIe interface 151 and meeting different usage needs.

[0085] In some implementations, such as Figure 1C As shown, a PCIe interface 151 is located within a mounting slot 120, which affects the flexibility of connecting components located within the mounting slot 120 to the PCIe interface 151.

[0086] Figure 2A This is a structural diagram of the mounting slot and hard disk backplane provided in other embodiments of this application. Figure 2B This is a structural diagram of a PCIe interface group provided in some embodiments of this application.

[0087] Based on this, in some embodiments of this application, such as Figure 2A As shown, at least two PCIe interfaces 151 are arranged side by side and located in the same mounting slot 120, forming a PCIe interface group 150.

[0088] In some examples, such as Figure 2A As shown, at least two PCIe interfaces 151 can be arranged side by side along a first direction X. For example, there may be a gap between the at least two PCIe interfaces 151 arranged side by side along the first direction X.

[0089] In some examples, such as Figure 2A As shown, the number of PCIe interfaces 151 located in the same mounting slot 120 can be two. That is, the PCIe interface group 150 located on the hard drive backplane 121 can include two PCIe interfaces 151.

[0090] In other examples, the PCIe interface group 150 located on the hard drive backplane 121 may also include 3, 4, or 5 PCIe interfaces 151. It is understood that the embodiments of this application do not further limit the number of PCIe interfaces 151 in the PCIe interface group 150.

[0091] For example, such as Figure 2A and Figure 2B As shown, at least two PCIe interfaces 151 in the PCIe interface group 150 located on the hard drive backplane 121 may extend in the same direction. In some examples, the PCIe interfaces 151 located on the hard drive backplane 121 may extend along a first direction X.

[0092] In some examples, a single PCIe interface 151 can support a maximum of x4 bandwidth, meaning a single PCIe interface 151 can include up to four signal channels (four input channels and four output channels). Understandably, components located within the mounting slot 120 (such as PCIe unit 130 or hard drive 180) can be connected to one or more PCIe interfaces 151 on the hard drive backplane 121 according to different bandwidth requirements, improving the flexibility of connection between components within the mounting slot 120 and PCIe interfaces 151 on the hard drive backplane 121, and meeting diverse usage needs.

[0093] For example, when the bandwidth requirement of a component located in mounting slot 120 is less than or equal to x4 (e.g., x1, x2, or x4 bandwidth), the component in mounting slot 120 can be connected to one PCIe interface 151 on the hard drive backplane 121. When the bandwidth requirement of a component located in mounting slot 120 is greater than x4, the component in mounting slot 120 can be connected to two or more PCIe interfaces 151 on the hard drive backplane 121.

[0094] For example, when the requirement of a component in the mounting slot 120 is x8 bandwidth, the component in the mounting slot 120 can be plugged into two PCIe interfaces 151 on the hard drive backplane 121; when the requirement of a component in the mounting slot 120 is x16 bandwidth, the component in the mounting slot 120 can be plugged into four PCIe interfaces 151 on the hard drive backplane 121, and so on.

[0095] Understandably, such as Figure 2A As shown, when a component located in the mounting slot 120 is connected to two PCIe interfaces 151 located on the hard drive backplane 121, the two PCIe interfaces 151 connected to the component in the mounting slot 120 can be spaced apart along the first direction X; as shown Figure 2BAs shown, when the component located in the mounting slot 120 is connected to the four PCIe interfaces 151 located on the hard drive backplane 121, the four PCIe interfaces 151 connected to the component in the mounting slot 120 can be arranged in an array along the first direction X and the third direction Z. The third direction Z can intersect the plane containing the first direction X and the second direction Y. In some examples, the third direction Z can be perpendicular or approximately perpendicular to the plane containing the first direction X and the second direction Y.

[0096] Understandably, the third direction Z is "approximately perpendicular" to the plane containing the first direction X and the second direction Y. That is, the angle between the third direction Z and the plane containing the first direction X and the second direction Y can be approximately 90°. For example, the angle between the third direction Z and the plane containing the first direction X and the second direction Y can be 88°, 89°, 90.5°, 91° or 92°, etc.

[0097] This configuration improves the regularity of the PCIe interface 151 on the hard drive backplane 121, facilitates the connection of the PCIe unit 130 and the hard drive 180 to the PCIe interface 151, and also improves the ease of processing the PCIe interface 151, reducing the cost of the computing device 100.

[0098] Understandably, such as Figure 2A As shown, since mounting slot 120 can accommodate at least two PCIe interfaces 151 arranged side by side, compared to mounting slot 120 accommodating only one PCIe interface 151 (see [reference]). Figure 1C As a result, the size of the mounting slot 120 will increase. In some examples, the size of the mounting slot 120 that accommodates two PCIe interfaces 151 is twice the size of the mounting slot 120 that accommodates one hard drive interface.

[0099] In the embodiments of this application, at least two PCIe interfaces 151 are arranged side by side and located in the same mounting slot 120 to form a PCIe interface group 150. This allows components located in the mounting slot 120 (such as PCIe unit 130 or hard disk 180) to be plugged into one or more PCIe interfaces 151 in the PCIe interface group 150 on the hard disk backplane 121 according to different bandwidth requirements. This improves the flexibility of plugging in components located in the mounting slot 120 to the PCIe interfaces 151 on the hard disk backplane 121, meets the bandwidth requirements of different components, and thus improves the usability flexibility of the computing device 100.

[0100] For example, when there are at least two processing units 140, at least two PCIe interfaces 151 in the PCIe interface group 150 can be electrically connected to the same processing unit 140.

[0101] Understandably, by configuring at least two PCIe interfaces 151 in the PCIe interface group 150 to be electrically connected to the same processing unit 140, components (such as PCIe units 130 or hard disks 180) plugged into at least two PCIe interfaces 151 in the PCIe interface group 150 can be electrically connected to the same processing unit 140, thereby improving the reliability of the computing device 100.

[0102] Figure 3A This is a structural diagram of the mounting slot and PCIe unit provided in some embodiments of this application. Figure 3B The following is a structural block diagram of the PCIe unit and processing unit provided in some embodiments of this application. Figure 3C This is a structural diagram of a PCIe unit provided in some embodiments of this application.

[0103] It should be noted that, in order to clearly show the PCIe unit 130 located within the mounting slot 120, Figure 3A The cover plate 125 of the mounting slot 120 is not shown.

[0104] In some examples, such as Figure 3A and Figure 3B As shown, the PCIe unit 130 is connected to at least two PCIe interfaces 151 located in the mounting slot 120 and connected to the PCIe interface group 150.

[0105] For example, such as Figure 3A As shown, the PCIe interface group 150 located on the hard drive backplane 121 may include two PCIe interfaces 151. The two PCIe interfaces 151 may be spaced apart along the first direction X. The PCIe unit 130 may be plugged into the two PCIe interfaces 151, as shown. Figure 3B As shown, the PCIe unit 130 can be electrically connected to the processing unit 140 through two PCIe interfaces 151.

[0106] Understandably, when the bandwidth requirement of PCIe unit 130 is high, for example, when PCIe unit 130 includes GPU acceleration service card, CXL storage expansion card, high bandwidth network card, high performance DPU card, or other expansion cards with high power chips or multiple chips, configuring PCIe unit 130 to be able to connect to at least two PCIe interfaces 151 in PCIe interface group 150 located on hard disk backplane 121 reduces the impact of insufficient bandwidth (e.g., x4 bandwidth) of a single PCIe interface 151 on the data transmission rate of PCIe unit 130, so that PCIe interface group 150 located on hard disk backplane 121 can meet the needs of PCIe unit 130 with different bandwidths, improve the data transmission rate between PCIe unit 130 and motherboard 170, thereby improving the data processing capability of computing device 100.

[0107] For example, taking a single PCIe interface 151 with an x4 bandwidth and a single-link data transmission rate of 32GT / s as an example, the data transmission rate of a single PCIe interface 151 is 128GT / s. If the PCIe unit 130 is connected to two PCIe interfaces 151 located on the hard drive backplane 121, the x8 bandwidth can be achieved, and the data transmission rate can reach 256GT / s. This improves the data transmission rate between the PCIe unit 130 and the processing unit 140, thereby improving the data processing capability of the computing device 100.

[0108] In some examples, a single PCIe interface 151 may include three power pins, supporting PCIe units 130 with a maximum power of 50W. The PCIe unit 130 is configured to connect to at least two PCIe interfaces 151 in a PCIe interface group 150 located on the hard drive backplane 121, such that the PCIe interface group 150 can support PCIe units 130 with a power greater than 50W.

[0109] For example, when the power of PCIe unit 130 is 75W, it can be connected to two PCIe interfaces 151 located on the hard drive back panel 121. The two PCIe interfaces 151 can support a maximum power of 100W for PCIe unit 130, thus meeting the power requirements of PCIe unit 130.

[0110] That is to say, such as Figure 3A and Figure 3B As shown, the PCIe unit 130 is configured to connect to at least two PCIe interfaces 151 in the PCIe interface group 150 located on the hard drive backplane 121. On the one hand, this reduces the limitation imposed on the PCIe unit 130 by the bandwidth of a single PCIe interface 151, allowing the PCIe interface group 150 to meet the needs of PCIe units 130 with different bandwidths, thereby increasing the data transfer rate between the PCIe unit 130 and the motherboard 170, and thus improving the data processing capability of the computing device 100. On the other hand, this reduces the power consumption of a single PCIe interface 151. The limitations imposed by the PCIe unit 130 allow the PCIe interface group 150 to meet the needs of PCIe units 130 with different power ratings, improving the flexibility of use of the computing device 100. Furthermore, by configuring the PCIe unit 130 to be connected to at least two PCIe interfaces 151 in the PCIe interface group 150 located on the hard drive backplane 121, the connection or disconnection between the PCIe unit 130 and the PCIe interface 151 can be achieved without opening the casing 110 (i.e., the chassis) of the computing device 100, thus improving the ease of use of the computing device 100.

[0111] Understandably, PCIe unit 130 can be plugged into a portion (two, three or more) of PCIe interfaces 151 in PCIe interface group 150 located on hard disk backplane 121, or PCIe unit 130 can be plugged into all of PCIe interfaces 151 in PCIe interface group 150 located on hard disk backplane 121.

[0112] In some examples, PCIe unit 130 may include at least two PCIe connectors 131, which can be plugged into PCIe interface 151 in a one-to-one correspondence.

[0113] In some examples, such as Figure 3C As shown, the number of PCIe connectors 131 can be the same as the number of PCIe interfaces 151, and the positions of the PCIe connectors 131 can correspond to the positions of the PCIe interfaces 151, so that the PCIe connectors 131 can be plugged into the PCIe interfaces 151 located on the hard drive backplane 121 one-to-one. For example, at least two PCIe connectors 131 can be spaced apart along the first direction X.

[0114] Understandably, the number of PCIe connectors 131 is at least two, and the PCIe connectors 131 can be plugged into PCIe interfaces 151 one by one, so that the PCIe unit 130 can be plugged into at least two PCIe interfaces 151 located on the hard disk backplane 121, to meet the bandwidth and power requirements of different PCIe units 130 and improve the flexibility of use of the computing device 100.

[0115] In some examples, when PCIe unit 130 needs to be connected to two PCIe interfaces 151, such as Figure 3C As shown, PCIe unit 130 may include two PCIe connectors 131, one of which is connected to a PCIe interface 151. In other examples, when PCIe unit 130 needs to be connected to four PCIe interfaces 151, PCIe unit 130 may include four PCIe connectors 131, one of which is connected to a PCIe interface 151, and so on.

[0116] In some examples, such as Figure 3A As shown, the PCIe unit 130 may include a circuit board 132 and a chip (not shown), the chip being disposed on the circuit board 132. At least two PCIe connectors 131 may be disposed at a distance from one end of the circuit board 132.

[0117] Understandably, at least two PCIe connectors 131 can be electrically connected to the circuit board 132, enabling the chip to be electrically connected to the processing unit 140 via the circuit board 132 and the PCIe connectors 131, thereby enabling data to be transmitted between the processing unit 140 and the chip.

[0118] Understandably, the circuit board 132 of a PCIe unit 130 including two PCIe connectors 131 will be larger than the circuit board 132 of a PCIe unit 130 including one PCIe connector 131. For example, the volume of the circuit board 132 of a PCIe unit 130 including two PCIe connectors 131 can be twice the volume of the circuit board 132 of a PCIe unit 130 including one PCIe connector 131.

[0119] Understandably, the increased size of the circuit board 132 of the PCIe unit 130 serves two purposes. First, it allows for a larger heatsink that exchanges heat with the circuit board 132, improving the heat dissipation effect of the heatsink on the chip and thus enhancing the heat dissipation performance of the PCIe unit 130. Second, it enables the circuit board 132 to accommodate larger chips and other components of the PCIe unit 130, allowing the PCIe unit 130 to perform different functions. This, in turn, enables the PCIe unit 130 to achieve high performance and high bandwidth, improving its overall performance.

[0120] Understandably, the size of the mounting slot 120 can be adapted to the size of the PCIe unit 130 so that the PCIe unit 130 can be inserted into the mounting slot 120.

[0121] Figure 4A The diagram shows the structure of the mounting slot and hard disk provided in some embodiments of this application. Figure 4B The diagram shows the structure of the hard disk and processing unit provided in some embodiments of this application.

[0122] It should be noted that, in order to clearly show the hard drive 180 located in the mounting slot 120, Figure 4A The cover plate 125 of the mounting slot 120 is not shown.

[0123] In some examples, such as Figure 4A and Figure 4B As shown, the computing device 100 may include at least two hard disks 180, which may be located in the mounting slot 120, and at least two PCIe interfaces 151 in the PCIe interface group 150 are connected to the at least two hard disks 180 in a one-to-one correspondence.

[0124] For example, such as Figure 4A and Figure 4BAs shown, the PCIe interface group 150 may include two PCIe interfaces 151, and the computing device 100 may include two hard drives 180. One hard drive 180 can be plugged into one PCIe interface 151 located on the hard drive backplane 121. Understandably, the two hard drives 180 can be spaced apart along a first direction X within the mounting slot 120.

[0125] In some examples, the size of the mounting slot 120 can support the insertion of one PCIe unit 130, or the size of the mounting slot 120 can also support the insertion of two hard drives 180, improving the compatibility of the mounting slot 120. This allows users to insert one PCIe unit 130 or two hard drives 180 into the mounting slot 120 according to their usage needs, thereby improving the applicability of the computing device 100 and meeting different usage requirements.

[0126] Understandably, the hard drive 180 can be either a 2.5-inch or 3.5-inch hard drive. For example, a 2.5-inch hard drive is approximately 70mm long, 100mm wide, and 7mm or 9mm thick. A 3.5-inch hard drive is approximately 147mm long, 102mm wide, and 26mm thick.

[0127] In order to allow two hard drives 180 to be inserted into the installation slot 120, in some examples, such as Figure 4A As shown, the mounting slot 120 can be approximately 200 mm in length along the first direction X, supporting the insertion of two 2.5-inch hard drives; alternatively, the mounting slot 120 can be approximately 204 mm in length along the first direction X, supporting the insertion of two 3.5-inch hard drives. Understandably, the dimensions of the base plate 124 and the cover plate 125 along the first direction X are larger than the dimensions of the mounting slot 120 along the first direction X.

[0128] In some examples, such as Figure 4A As shown, the mounting slot 120 can be approximately 70mm in the second direction Y to support 2.5-inch hard drive insertion; or, the mounting slot 120 can be approximately 147mm in the second direction Y to support 3.5-inch hard drive insertion. Understandably, the dimensions of the base plate 124 and the cover plate 125 in the second direction Y can be larger than the dimensions of the mounting slot 120 in the second direction Y.

[0129] In some examples, such as Figure 4A As shown, the dimensions of the mounting slot 120 along the third direction Z can be approximately 7mm, 9mm, or 26mm. For example, when the dimensions of the mounting slot 120 along the third direction Z are approximately 7mm or 9mm, it can support the insertion of a 2.5-inch hard drive; when the dimensions of the mounting slot 120 along the third direction Z are approximately 26mm, it can support the insertion of a 3.5-inch hard drive.

[0130] In some examples, such as Figure 3A and Figure 4A As shown, the housing 110 may further include a first guide plate 127, which is located within the mounting slot 120 and positioned between two adjacent PCIe interfaces 151 along a first direction X. The extending direction of the first guide plate 127 is the same as the extending direction of the mounting slot 120.

[0131] In some examples, the first guide plate 127 may extend along the second direction Y. Understandably, since the first guide plate 127 is located within the mounting slot 120, the extension direction of the first guide plate 127 is the same as the extension direction of the mounting slot 120, and the first guide plate 127 is located along the first direction X between two adjacent PCIe interfaces 151, so that the first guide plate 127 can guide and limit the components (such as PCIe unit 130 or hard disk 180) inserted into the mounting slot 120.

[0132] In some examples, the first guide plate 127 may be connected to the cover plate 125 of the support portion 122. The first guide plate 127 and the side edge away from the base plate 124 have a gap to avoid the PCIe unit 130, so as to prevent the first guide plate 127 from blocking the PCIe unit 130 and allow the PCIe unit 130 to be inserted into the mounting slot 120.

[0133] In some examples, the length of the first guide plate 127 along the second direction Y may be the same as or approximately the same as the length of the cover plate 125 and the bottom plate 124 along the second direction Y.

[0134] For example, when the PCIe unit 130 is inserted into the mounting slot 120, a portion of the PCIe unit 130 along the first direction X can be located within the gap between the edge of the first guide plate 127 away from the cover plate 125 and the base plate 124. This allows the first guide plate 127 to limit and guide the PCIe unit 130, reducing the risk of the PCIe connector 131 of the PCIe unit 130 shifting relative to the PCIe interface 151 on the hard drive backplane 121, and improving the ease of connection between the PCIe unit 130 and the PCIe interface 151 on the hard drive backplane 121.

[0135] In some examples, the PCIe unit 130 may include a heatsink for heat exchange with the circuit board 132. The heatsink may be comb-shaped, and a first guide plate 127 may be located in the gaps between the teeth of the heatsink, so that the first guide plate 127 can guide and limit the PCIe unit 130.

[0136] In some examples, the circuit board 132 of the PCIe unit 130 may have clearance space for the first guide plate 127 of the computing device 100.

[0137] In some examples, the circuit board 132 of the PCIe unit 130 may have a notch so that the circuit board 132 can avoid the first guide plate 127, thus preventing the first guide plate 127 from obstructing the PCIe unit 130. In other examples, the electronic components disposed on the circuit board 132 may be arranged to form clearance spaces so that the circuit board 132 can avoid the first guide plate 127, thus preventing the first guide plate 127 from obstructing the PCIe unit 130.

[0138] For example, when hard disk 180 is inserted into mounting slot 120, hard disk 180 can be located on one side of the first guide plate 127 along the first direction X. When two hard disks 180 are inserted into mounting slot 120, the two hard disks 180 can be located on opposite sides of the first guide plate 127 along the first direction X.

[0139] Understandably, the thickness of the hard drive 180 along the third direction Z can be greater than the width of the gap between the first guide plate 127 and the edge of the side away from the base plate 124 and the base plate 124. This allows the first guide plate 127 to guide and limit the hard drive 180, enabling the hard drive 180 to be located on one side of the first guide plate 127 along the first direction X. This reduces the risk of the hard drive 180 shifting relative to the PCIe interface 151 on the hard drive backplate 121 and improves the ease of connection between the hard drive 180 and the PCIe interface 151 on the hard drive backplate 121.

[0140] That is, by setting the first guide plate 127, the components (such as PCIe unit 130 or hard disk 180) inserted into the installation slot 120 can be guided and limited, improving the convenience of connecting the components inserted into the installation slot 120 to the PCIe interface 151 located on the hard disk backplane 121, thereby improving the ease of use of the computing device 100.

[0141] In some examples, the first guide plate 127 may be fixedly connected to the cover plate 125 to improve the reliability of the connection between the first guide plate 127 and the cover plate 125.

[0142] In some examples, such as Figure 3A and Figure 4A As shown, the housing 110 may also include a second guide plate 128, which is located in the mounting slot 120 and is located between the first guide plate 127 and the hard disk backplane 121 along the second direction Y, where the second direction Y intersects with the first direction X.

[0143] Understandably, since the second guide plate 128 is located within the mounting slot 120 and is positioned between the first guide plate 127 and the hard disk backplane 121 along the second direction Y, the second guide plate 128 can guide and limit the components (such as PCIe unit 130 or hard disk 180) inserted into the mounting slot 120.

[0144] In some examples, the extension direction of the second guide plate 128 may be the same as the extension direction of the mounting slot 120, and the second guide plate 128 may be located between two adjacent PCIe interfaces 151 along the first direction X.

[0145] In some examples, the circuit board 132 of the PCIe unit 130 may have clearance space for the second guide plate 128 of the computing device 100.

[0146] For example, such as Figure 4A As shown, the circuit board 132 of the PCIe unit 130 may include a clearance notch to avoid the second guide plate 128 from obstructing the PCIe unit 130. This allows the second guide plate 128 to guide and limit the PCIe unit 130, reducing the risk of the PCIe connector 131 of the PCIe unit 130 shifting relative to the PCIe interface 151 on the hard drive backplane 121, and improving the ease of connection between the PCIe unit 130 and the PCIe interface 151 on the hard drive backplane 121.

[0147] In some examples, when hard disk 180 is inserted into mounting slot 120, hard disk 180 may be located on one side of the second guide plate 128 along the first direction X. When two hard disks 180 are inserted into mounting slot 120, the two hard disks 180 may be located on opposite sides of the second guide plate 128 along the first direction X.

[0148] Understandably, by setting the second guide plate 128, the components (such as PCIe unit 130 or hard disk 180) inserted into the mounting slot 120 can be guided and limited, improving the convenience of connecting the components inserted into the mounting slot 120 to the PCIe interface 151 located on the hard disk backplane 121, thereby improving the ease of use of the computing device 100.

[0149] In some examples, the second guide plate 128 may be connected to the cover plate 125, the base plate 124, and the first guide plate 127 to reduce the risk of the second guide plate 128 shifting or wobbling within the mounting slot 120. For example, the first guide plate 127 and the second guide plate 128 may be an integrally formed structure.

[0150] In some examples, the dimensions of the first guide plate 127 and the second guide plate 128 can be adjusted according to different usage requirements to improve the ease of use of the computing device 100.

[0151] In some examples, PCIe unit 130 may include a first PCIe unit or a second PCIe unit.

[0152] For example, the bandwidth of the first PCIe unit can be different from that of the second PCIe unit. For instance, the first PCIe unit can have x4 bandwidth, and the second PCIe unit can have x8 bandwidth.

[0153] As can be seen from the above, the number of PCIe interfaces 151 that can be plugged into the PCIe unit 130 may be different when the bandwidth of the PCIe unit 130 is different. For example, the first PCIe unit can be plugged into one PCIe interface 151 located on the hard drive backplane 121, and the second PCIe unit can be plugged into two PCIe interfaces 151 located on the hard drive backplane 121.

[0154] In some examples, such as Figure 3A As shown, the PCIe interface 151 may include a first PCIe interface 151a and a second PCIe interface 151b. Taking a first PCIe unit with x4 bandwidth and a second PCIe unit with x8 bandwidth as an example, the first PCIe unit can be plugged into the first PCIe interface 151a, or the second PCIe unit can be plugged into both the first PCIe interface 151a and the second PCIe interface 151b simultaneously. That is, both the first PCIe unit and the second PCIe unit can be plugged into the first PCIe interface 151a.

[0155] It should be noted that the first PCIe interface 151a and the second PCIe interface 151b simply refer to two different PCIe interfaces 151, and do not further limit the structure of the PCIe interface 151.

[0156] Figure 5A This is a structural diagram of a first PCIe interface provided for some embodiments of this application. Figure 5B This is a structural diagram of a second PCIe interface provided in some embodiments of this application.

[0157] In some examples, such as Figure 5A As shown, the first PCIe interface 151a may also include a detection pin 152.

[0158] Understandably, since both the first PCIe unit and the second PCIe unit can be plugged into the first PCIe interface 151a, the detection pin 152 is set on the first PCIe interface 151a so that the detection pin 152 can be plugged into the first PCIe unit and the second PCIe unit.

[0159] For example, detection pin 152 can be electrically connected to processing unit 140, so that processing unit 140 can detect whether a PCIe unit 130 is plugged into detection pin 152 and the type of PCIe unit 130 plugged into detection pin 152.

[0160] In some examples, processing unit 140 is configured to: determine that a first PCIe unit is plugged into PCIe interface 151 when a first level signal is received on detection pin 152; determine that a second PCIe unit is plugged into PCIe interface 151 when a second level signal is received on detection pin 152; and determine that no PCIe unit 130 is plugged into PCIe interface 151 when detection pin 152 is floating.

[0161] Understandably, the first level signal can be either a high-level signal or a low-level signal, and the second level signal can also be either a high-level signal or a low-level signal. For example, when the first level signal is low, the second level signal can be high. When the second level signal is high, the first level signal can be low.

[0162] In some examples, the first PCIe unit can provide a first-level signal to detection pin 152, and the second PCIe unit can provide a second-level signal to detection pin 152. Therefore, when the first PCIe unit is plugged into the first PCIe interface 151a, detection pin 152 can receive the first-level signal, enabling the processing unit 140 to identify the plugging of the first PCIe unit into the PCIe interface 151 through detection pin 152. When the second PCIe unit is plugged into the first PCIe interface 151a and the second PCIe interface 151b, detection pin 152 can receive the second-level signal, enabling the processing unit 140 to identify the plugging of the second PCIe unit into the PCIe interface 151 through detection pin 152.

[0163] Understandably, when no level signal is received at detection pin 152, processing unit 140 can determine that no PCIe unit 130 (including the first PCIe unit and the second PCIe unit) is connected to PCIe interface 151. As can be seen from the above, hard disk 180 can also be connected to PCIe interface 151. Therefore, when no PCIe unit 130 is connected to PCIe interface 151, it can be that hard disk 180 is connected to PCIe interface 151, or it can be that neither hard disk 180 nor PCIe unit 130 is connected to PCIe interface 151.

[0164] Understandably, the processing unit 140 can not only identify whether the PCIe unit 130 is plugged into the PCIe interface 151 and the type of the PCIe unit 130 plugged into the PCIe interface 151 through the detection pin 152, but also identify the model and manufacturer of the PCIe unit 130 through the protocol of the PCIe unit 130 when the PCIe unit 130 is plugged into the PCIe interface 151; and identify the model and manufacturer of the hard drive 180 through the protocol of the hard drive 180 when the hard drive 180 is plugged into the PCIe interface 151.

[0165] For example, the processing unit 140 can send an presence detection signal to the PCIe interface 151. When a component (such as PCIe unit 130 or hard disk 180) located in the mounting slot 120 is plugged into the PCIe interface 151, the component plugged into the PCIe interface 151 can receive the presence detection signal sent by the processing unit 140 and send a feedback signal to the processing unit 140 based on the received presence detection signal.

[0166] After receiving the feedback signal, the processing unit 140 can read the protocol of the component plugged into the PCIe interface 151, and determine the model and manufacturer of the component plugged into the PCIe interface 151 according to the read protocol, thereby running different programs so that data can be transmitted between the processing unit 140 and the component plugged into the PCIe interface 151 (such as PCIe unit 130 or hard disk 180), thereby enabling the computing device 100 to operate normally.

[0167] Understandably, by setting a detection pin 152 on the first PCIe interface 151a, the detection pin 152 can detect whether the PCIe unit 130 is plugged into the PCIe interface 151, and when the PCIe unit 130 is plugged into the PCIe interface 151, it can determine the type of the PCIe unit 130 plugged into the PCIe interface 151 (e.g., the first PCIe unit and the second PCIe unit), thereby improving the reliability of the computing device 100.

[0168] In some examples, taking the PCIe interface 151 including a U.2 interface as an example, each U.2 interface can include the signal channels (4 input channels and 4 output channels) required by the four PCIe units 130. Two pins can form one input channel or one output channel, that is, 16 pins are needed to form four signal channels. In addition, other signal pins need to be set on the U.2 interface, such as SAS signal pins, SATA signal pins, etc., and power pins also need to be set. For example, in addition to the above pins, each U.2 interface can have 4 spare pins, that is, each PCIe interface 151 includes 4 Reserved (RSVD) pins.

[0169] Understandably, since the PCIe interface group 150 can include two PCIe interfaces 151, and each PCIe interface 151 can have 4 spare pins, that is, the PCIe interface group 150 can include 8 spare pins.

[0170] In some examples, such as Figure 5A and Figure 5B As shown, pins E16, S15, P1, and P3 of the PCIe interface 151 (including the first PCIe interface 151a and the second PCIe interface 151b) can be unused pins. In other examples, pins E16, E17, P1, and P3 can be unused pins.

[0171] Understandably, such as Figure 5A As shown, since pin E16 on the first PCIe interface 151a can be a spare pin, pin E16 on the first PCIe interface 151a can be set as detection pin 152. This prevents detection pin 152 from conflicting with other signal pins or power pins on the first PCIe interface 151a, reducing the mutual interference between the level signal (e.g., the first level signal and the second level signal) received by detection pin 152 and other signals. This allows processing unit 140 to determine whether PCIe unit 130 is plugged into PCIe interface 151 through detection pin 152, and to determine the type of PCIe unit 130 plugged into PCIe interface 151, thereby improving the reliability of computing device 100.

[0172] In other examples, other unused pins (such as pins S15, P1, and P3) can also be set as detection pin 152. Understandably, the number of detection pins 152 can be one or more to meet different usage requirements.

[0173] In some examples, the processing unit 140 may include multiple signal ports, which may include multiple first signal ports arranged adjacent to each other and multiple second signal ports arranged adjacent to each other. It is understood that the number of first signal ports and the number of second signal ports may be the same or different.

[0174] In some examples, taking the processing unit 140 as a CPU, multiple first signal channels and multiple second signal channels can be X8 PCIe Ports.

[0175] Understandably, the PCIe interface 151 may include multiple pins. In some examples, two of the multiple pins may form an input channel, and the other two pins may form an output channel. An input channel and an output channel may form a signal channel, so that the PCIe interface 151 may include multiple signal channels.

[0176] In some examples, the first PCIe interface 151a may include multiple first signal channels, which can be electrically connected one-to-one with multiple adjacent first signal ports of the processing unit 140. The second PCIe interface 151b may include multiple second signal channels, which can be electrically connected one-to-one with multiple adjacent second signal ports of the processing unit 140. The multiple first signal ports and the multiple second signal ports can be arranged adjacent to each other.

[0177] In some examples, taking the first PCIe interface 151a as a U.2 interface, the first PCIe interface 151a may include four signal channels (four input channels and four output channels). Taking the second PCIe interface 151b as a U.2 interface, the second PCIe interface 151b may include four signal channels (four input channels and four output channels).

[0178] In other examples, the first PCIe interface 151a may include other numbers of signal channels, and the second PCIe interface 151b may also include other numbers of signal channels. It is understood that the number of signal channels in the first PCIe interface 151a may be the same as or different from the number of signal channels in the second PCIe interface 151b. The embodiments of this application do not further limit the number of signal channels in the first PCIe interface 151a and the second PCIe interface 151b.

[0179] In some examples, the number of first signal channels of the first PCIe interface 151a can be the same as the number of first signal ports of the processing unit 140, so that multiple first signal channels can be electrically connected to multiple adjacent first signal ports in a one-to-one correspondence. The number of second signal channels of the second PCIe interface 151b can be the same as the number of second signal ports of the processing unit 140, so that multiple second signal channels can be electrically connected to multiple adjacent second signal ports in a one-to-one correspondence.

[0180] Understandably, since multiple first signal ports and multiple second signal ports can be arranged adjacently, multiple signal channels (including multiple first signal channels and multiple second signal channels) of at least two PCIe interfaces 151 in the PCIe interface group 150 can be electrically connected to multiple signal ports (including multiple first signal ports and multiple second signal ports) arranged adjacently in the processing unit 140, thereby enabling the PCIe unit 130 to operate normally and improving the reliability of the computing device 100.

[0181] For example, the processing unit 140 may include eight adjacent signal ports, defined as signal port 1 to signal port 8. The first PCIe interface 151a may include four signal channels, and the second PCIe interface 151b may also include four signal channels.

[0182] For example, the four signal channels of the first PCIe interface 151a can be electrically connected to signal ports 1 to 4 of the processing unit 140 in a one-to-one correspondence (that is, signal ports 1 to 4 are the first signal ports), and the four signal channels of the second PCIe interface 151b can be electrically connected to signal ports 5 to 8 of the processing unit 140 in a one-to-one correspondence (that is, signal ports 5 to 8 are the second input / output terminals).

[0183] In some examples, computing device 100 may also include a management control unit (not shown in the figure). For example, the management control unit may include a BMC (Baseboard Management Controller), which may be electrically connected to the motherboard 170.

[0184] It should be noted that different companies use different names for the BMC in their computing devices 100. For example, some companies call it BMC, some call it iLO, and others call it iDRAC. Regardless of whether it is called BMC, iLO, or iDRAC, it can be understood as the BMC in this embodiment of the invention.

[0185] In some examples, such as Figure 5A and Figure 5B As shown, the PCIe interface group 150 may include multiple NCSI (Network Controller Sideband Interface) pins 153, which can be electrically connected to the management control unit.

[0186] Understandably, since the NCSI pin 153 can be electrically connected to the management control unit, signals can be transmitted between the management control unit and the PCIe unit 130 through the NCSI pin 153. This allows the PCIe unit 130 (e.g., the second PCIe unit) to obtain task information from the management control unit through the NCSI pin 153, enabling out-of-band management of the PCIe unit 130 and improving the ease of use of the computing device 100.

[0187] As described above, each PCIe interface 151 may include four unused pins. In some examples, multiple NCSI pins 153 are provided on different PCIe interfaces 151 within the PCIe interface group 150. For example, multiple NCSI pins 153 may be provided on unused pins of different PCIe interfaces 151 within the PCIe interface group 150.

[0188] Understandably, when the PCIe interface group 150 includes a first PCIe interface 151a and a second PCIe interface 151b, some (one, two, or more) of the multiple NCSI pins 153 can be set on the first PCIe interface 151a, and the other part (one, two, or more) can be set on the second PCIe interface 151b. In this way, even if the number of NCSI pins 153 is greater than the number of unused pins on the PCIe interface 151, multiple NCSI pins 153 can still be set on the PCIe interface group 150, thereby enabling out-of-band management of the PCIe unit 130 and improving the ease of use of the computing device 100.

[0189] Understandably, configuring multiple NCSI pins 153 on different PCIe interfaces 151 within the PCIe interface group 150 avoids conflicts between NCSI pins 153 and other pins on a single PCIe interface 151 due to insufficient available pins. In other words, this configuration ensures that even if the number of NCSI pins 153 exceeds the number of available pins on a single PCIe interface 151, multiple NCSI pins 153 can still be configured on the PCIe interface group 150, enabling out-of-band management of the PCIe unit 130 and improving the ease of use of the computing device 100.

[0190] In some embodiments, the number of NCSI pins 153 is 7, of which 3 are located on the first PCIe interface 151a and the other 4 are located on the second PCIe interface 151b.

[0191] Understandably, setting three NCSI pins 153 on the first PCIe interface 151a and four NCSI pins 153 on the second PCIe interface 151b allows the NCSI pins 153 to be set on different PCIe interfaces 151 within the PCIe interface group 150. In this way, even if the number of NCSI pins 153 is greater than the number of free pins on a single PCIe interface 151, multiple NCSI pins 153 can still be set on the PCIe interface group 150, realizing out-of-band management of the PCIe unit 130 and improving the ease of use of the computing device 100.

[0192] For example, the signal definitions of the unused pins of the first PCIe interface 151a and the second PCIe interface 151b are shown in Table 1.

[0193] Table 1

[0194]

[0195] As shown in Table 1, in the first PCIe interface 151a, pins P1, P3, and S15 (or E17) are set as NCSI pin 153, and pin E16 is set as detection pin 152. In the second PCIe interface 151b, pins P1, P3, E16, and S15 (or E17) are all set as NCSI pin 153.

[0196] That is, in some examples, as shown in Table 1, the PCIe interface group 150 may include seven NCSI pins 153 and one detection pin 152.

[0197] In other examples, the PCIe interface group 150 may also include more than seven NCSI pins 153; for example, the number of NCSI pins 153 in the PCIe interface group 150 may be eight, nine, or ten, etc. Understandably, since the PCIe interface group 150 may include three, four, or more PCIe interfaces 151, the number of spare pins in the PCIe interface group 150 can be increased, allowing multiple (e.g., more than seven) NCSI pins 153 to be provided on the PCIe interface group 150.

[0198] Understandably, to meet different usage requirements, NCSI pin 153 and detection pin 152 can also be defined in ways other than those shown in Table 1. For example, pin P1 can be set as detection pin 152, and pin E16 can be set as NCSI pin 153. Alternatively, pin P1 can be set as NCSI RX D0, and pin P3 can be set as NCSI CRS DV. The embodiments of this application do not further limit the definition of NCSI pin 153 and detection pin 152.

[0199] In summary, the embodiments of this application have at least the following beneficial effects:

[0200] In the embodiments of this application, at least two PCIe interfaces 151 are arranged side by side and located in the same mounting slot 120 to form a PCIe interface group 150. This allows components located in the mounting slot 120 (such as PCIe unit 130 and hard disk 180) to be plugged into one or more PCIe interfaces 151 in the PCIe interface group 150 on the hard disk backplane 121 according to different bandwidth requirements. This improves the flexibility of plugging in components located in the mounting slot 120 to the PCIe interfaces 151 on the hard disk backplane 121, meets the bandwidth requirements of different components, and thus improves the usability flexibility of the computing device 100.

[0201] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A computing device, characterized in that, include: A housing that encloses a receiving cavity; the housing includes a mounting slot. A hard drive backplate is located within the receiving cavity, and the hard drive backplate is located on one side of the mounting slot along the extension direction of the mounting slot; The processing unit is located within the receiving cavity; Multiple PCIe interfaces are located on the side of the hard drive backplate near the mounting slot and are electrically connected to the processing unit; at least two of the PCIe interfaces are arranged side by side and located in the same mounting slot, forming a PCIe interface group. The PCIe unit is located within the mounting slot; The PCIe unit is plugged into at least two of the PCIe interfaces in the PCIe interface group; The PCIe unit includes a first PCIe unit or a second PCIe unit; The PCIe interface group includes a first PCIe interface and a second PCIe interface; The first PCIe unit is plugged into the first PCIe interface; or, the second PCIe unit is plugged into both the first PCIe interface and the second PCIe interface simultaneously; the first PCIe interface further includes a detection pin; the processing unit is configured to: determine that the first PCIe unit is plugged into the PCIe interface when the detection pin receives a first level signal; When the detection pin receives a second level signal, it is determined that the second PCIe unit is plugged into the PCIe interface; when the detection pin is floating, it is determined that no PCIe unit is plugged into the PCIe interface.

2. The computing device according to claim 1, characterized in that, The processing unit includes multiple signal ports, among which multiple first signal ports and multiple second signal ports are arranged adjacently. The first PCIe interface includes multiple first signal channels, and the multiple first signal channels are electrically connected to multiple adjacent first signal ports in a one-to-one correspondence; the second PCIe interface includes multiple second signal channels, and the multiple second signal channels are electrically connected to multiple adjacent second signal ports in a one-to-one correspondence. The first signal ports and the second signal ports are arranged adjacent to each other.

3. The computing device according to claim 1 or 2, characterized in that, It also includes a management control unit; the PCIe interface group includes multiple NCSI pins, which are electrically connected to the management control unit; the multiple NCSI pins are disposed on different PCIe interfaces in the PCIe interface group.

4. The computing device according to claim 1 or 2, characterized in that, The computing device further includes at least two hard drives, which are located in the mounting slots, and at least two PCIe interfaces in the PCIe interface group are connected to at least two hard drives in a one-to-one correspondence.

5. The computing device according to claim 1 or 2, characterized in that, The housing also includes a first guide plate, which is located within the mounting slot and positioned between two adjacent PCIe interfaces along a first direction; the extension direction of the first guide plate is the same as the extension direction of the mounting slot.

6. The computing device according to claim 5, characterized in that, The housing also includes a second guide plate located within the mounting slot, and the second guide plate is positioned between the first guide plate and the hard disk backplate along a second direction, the second direction intersecting the first direction.

7. A PCIe unit, characterized in that, For connecting to the PCIe interface of the computing device as described in any one of claims 1 to 5; the PCIe unit includes at least two PCIe connectors, each of which is connected to the PCIe interface in a one-to-one correspondence.

8. The PCIe unit according to claim 7, characterized in that, Also includes: Circuit board; A chip is disposed on the circuit board, and at least two PCIe connectors are spaced apart at one end of the circuit board. The circuit board has clearance space for avoiding the first guide plate and the second guide plate of the computing device.

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