A control method and system based on multi-core DSP parallel operation

Abstract

The application discloses a control method and system based on multi-core DSP parallel operation, which comprises the following steps: interrupt step: after the core completes operation, the corresponding flag bit of the receiving core in the interrupt register is set, the inter-core interrupt ID number is written into the interrupt register after being assigned, the inter-core interrupt is generated and sent to the receiving core; the receiving core receiving the inter-core interrupt clears the corresponding flag bit in the interrupt register in real time, and uses if to judge after the corresponding inter-core interrupt ID number is acquired; queue management step: after the core completes operation, the queue element is stored in the queue; after the waiting interrupt step is completed, the receiving core takes out the queue element from the corresponding queue, so that the corresponding data in the memory is taken out and processed; memory management step: the buffer data address required by the core operation is applied, or the specified buffer data address is released; operation management step: the core operation completion condition is judged, and the running state of the corresponding operation is set. The application can improve the operation efficiency of parallel operation and reduce the development cost.

Description

Technical Field

[0001] This invention relates to the field of data processing, and in particular to a control method and system based on multi-core DSP parallel computing. Background Technology

[0002] Multi-core DSP operations can be categorized into two types based on core usage: serial and parallel operations. Compared to serial operations, parallel operations are more complex, requiring detailed design of memory usage and operating mechanisms for each core. Data interaction and communication between cores are particularly crucial.

[0003] Currently, the inter-core communication method of multi-core DSPs is to call the relevant libraries of the chip manufacturer for inter-core communication. The design is relatively complex and encapsulated. It has a high degree of integration, but it has problems such as poor usage flexibility, large memory consumption, and unclear operation mechanism. At the same time, there is no detailed explanation for its use in different scenarios, resulting in low development efficiency. Summary of the Invention

[0004] The technical problem to be solved by this invention is: to address the technical problems existing in the prior art, this invention provides a control method and system based on multi-core DSP parallel computing, so as to achieve simple, fast and efficient development, improve the computing efficiency of parallel computing, and reduce development costs.

[0005] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows:

[0006] A control method based on multi-core DSP parallel computing includes the following steps:

[0007] The interrupt procedure includes: after any core of the multi-core DSP completes the operation, the flag corresponding to the receiving core in the interrupt register is set, and the inter-core interrupt ID number is assigned and written to the interrupt register to generate an inter-core interrupt and send it to the receiving core; after receiving the inter-core interrupt, the receiving core clears the corresponding flag in the interrupt register in real time, obtains the corresponding inter-core interrupt ID number in the interrupt register in real time and uses if to judge.

[0008] The queue management steps include: after any core of the multi-core DSP completes the operation, the queue element corresponding to the operation result is stored in the queue; after the interrupt step is completed, the receiving core retrieves the queue element from the corresponding queue, retrieves the corresponding data from memory according to the queue element, and processes it;

[0009] The memory management steps include: requesting cache data addresses in memory for any core of the multi-core DSP to perform operations, or releasing specified cache data addresses in memory;

[0010] The operation management steps include: determining the completion status of any core operation of the multi-core DSP and setting the running status of the corresponding operation.

[0011] Furthermore, the queue management steps also include: adding a specified queue element to the tail of the queue, or selecting a queue element from the head of a specified queue and removing or retaining the selected queue element.

[0012] Furthermore, the queue element includes data type, data starting address, and length.

[0013] Furthermore, the step of sending the parallel computation results through the receiving core specifically includes:

[0014] Before cores 2 and 3 begin operation, a memory management step is performed to allocate corresponding cache data addresses in the free space of memory for cores 2 and 3 respectively.

[0015] After the operations of cores 2 and 3 are completed, the results are stored in the corresponding cache data addresses of cores 2 and 3, respectively. Then, the queue management step is executed to store the queue elements corresponding to the operation results of cores 2 and 3 into the queue.

[0016] Execute the interrupt procedure, write the inter-core interrupt ID number corresponding to core 2 and core 3 into the interrupt register, set the flag corresponding to core 0 of the second core in the interrupt register, generate an inter-core interrupt and send it to core 0;

[0017] After receiving an inter-core interrupt, core 0 retrieves the queue element from the corresponding queue, retrieves the corresponding data from memory based on the queue element, and processes and sends the data.

[0018] Perform memory management steps to release the cached data addresses corresponding to cores 2 and 3.

[0019] Furthermore, it also includes the step of sending external data to the receiving core for parallel computation, specifically including:

[0020] The external data acquired by core 1 is stored in the cached data address requested in the pre-execution memory management steps;

[0021] Execute the operation management steps to determine the operation status of core 2 and core 3 of the second core. If core 2 or core 3 is in an idle state, execute the memory management steps to request the next cache data address in the free space of memory. If core 2 and core 3 are both in a busy state, execute the operation management steps to continue to determine the operation status of core 2 and core 3 of the second core until core 2 or core 3 is in an idle state.

[0022] Execute the queue management steps to store the queue elements corresponding to the external data obtained by core 1 into the queue;

[0023] Execute the operation management step, set the idle core 2 or core 3 to the busy state, execute the interrupt step, write the inter-core interrupt ID number corresponding to core 1 into the interrupt register, set the flag corresponding to core 2 or core 3 in the interrupt register, generate an inter-core interrupt and send it to core 2 or core 3;

[0024] After receiving an inter-core interrupt, core 2 or core 3 retrieves a queue element from the corresponding queue, retrieves the corresponding data from memory based on the queue element, and performs the operation.

[0025] Execute memory management steps to release the cached data address, and execute operation management steps to set core 2 or core 3, which has completed the operation, to an idle state.

[0026] This invention also proposes a control system based on multi-core DSP parallel computing, comprising:

[0027] The interrupt module is used to set the flag corresponding to the receiving core in the interrupt register after any core of the multi-core DSP has completed its operation, and to write the value of the inter-core interrupt ID number into the interrupt register, thereby generating an inter-core interrupt and sending it to the receiving core.

[0028] The queue management module is used to store the queue element corresponding to the calculation result into the queue after any core of the multi-core DSP has completed the calculation.

[0029] The memory management module is used to request cache data addresses required for the operation of any core of a multi-core DSP in memory, or to release specified cache data addresses in memory, or to add specified queue elements to the tail of the queue, or to select the queue element at the head of the queue from a specified queue and remove or retain the selected queue element.

[0030] The computation management module is used to determine the completion status of any core computation of a multi-core DSP and set the running status of the corresponding computation.

[0031] Furthermore, data access between the queue management module, memory management module, and operation management module is mutually exclusive.

[0032] Compared with the prior art, the advantages of the present invention are as follows:

[0033] This invention configures an interrupt module for executing interrupt steps, a queue management module for executing queue management steps, a memory management module for executing memory management steps, and an operation management module for executing operation management steps for controlling parallel operations of multi-core DSPs. These modules can be used in combination according to actual needs, improving the flexibility of parallel operations between multi-core DSPs, clarifying the interaction mechanism between multi-core DSPs, and making it suitable for various application scenarios, thereby improving the efficiency of multi-core DSP development. Attached Figure Description

[0034] Figure 1 This is a module relationship diagram of the present invention.

[0035] Figure 2 This is a flowchart of Embodiment 1 of the present invention.

[0036] Figure 3 This is a flowchart of Embodiment 2 of the present invention. Detailed Implementation

[0037] The present invention will be further described below with reference to the accompanying drawings and specific preferred embodiments, but this does not limit the scope of protection of the present invention.

[0038] To enhance the flexibility, simplify the development process, and improve efficiency of multi-core DSP development, we designed the following modules for controlling parallel operations in multi-core DSPs: an inter-core interrupt module for inter-core notification, a queue management module for inter-core data exchange, a memory management module for storing cached data addresses for core operations, and a core operation status management module. Depending on the specific needs, only one, three, or all four modules can be used, greatly expanding the applicability and flexibility. Each module is described in detail below:

[0039] 1. Interrupt module

[0040] The interrupt module is used to execute interrupt procedures. These procedures specifically include: after any core of the multi-core DSP completes its operation, setting the flag corresponding to the receiving core in the interrupt register, assigning the inter-core interrupt ID number, and writing it back to the interrupt register, thus generating an inter-core interrupt and sending it to the receiving core, thereby completing the inter-core notification function. The receiving core needs to enable inter-core interrupt reception. After receiving an inter-core interrupt, it immediately clears the corresponding flag in the interrupt register and immediately retrieves the corresponding inter-core interrupt ID number from the interrupt register, enabling the reception of inter-core interrupts from different cores performing different operations. The main functional divisions of the interrupt module are as follows:

[0041] a. Inter-core interrupt initialization;

[0042] b. Inter-core interrupt transmission, including the receiving core's core number and the inter-core interrupt ID number;

[0043] c. Inter-core interrupt reception, including inter-core interrupt command number.

[0044] To enable parallel processing of inter-core interrupts, including simultaneous sending and receiving by multiple cores, and to prevent interrupt loss, inter-core interrupt sending is implemented using the following code:

[0045]

[0046] As can be seen from the code above, in order to achieve simultaneous inter-core interrupt transmission, the following two conditions must be met.

[0047] The value of a.cmd must be a power of 2. This is because the DSP's interrupt register is a single 32-bit register, meaning each bit corresponds to one interrupt. Therefore, a power of 2 is necessary to send multiple interrupts simultaneously, thus enabling parallel interrupt processing. Otherwise, the interrupt register would need to be reassigned.

[0048] b. The interrupt send function must use a logical OR to set the interrupt register.

[0049] Since multiple interrupts may occur simultaneously, interrupt reception can be implemented using the following code:

[0050]

[0051] As can be seen from the code above, in order to achieve simultaneous interrupt reception between cores, the following two conditions must be met.

[0052] a. IPC_CORE2_CORE0_TCP and IPC_CORE3_CORE0_TCP are used as examples to represent interrupt definition variables. Their values ​​must be powers of 2 to enable simultaneous reception of multiple interrupts.

[0053] b. The interrupt receiving function must use an if statement to check the inter-core interrupt ID number, which can enable parallel and timely processing when two interrupts arrive at the same time, and prevent the loss of inter-core interrupts.

[0054] 2. Queue Management Module

[0055] The queue management module executes queue management steps, which specifically include: after any core of the multi-core DSP completes its calculation, storing the queue element corresponding to the calculation result into the queue, thus preparing for data transmission; after the receiving core completes its corresponding interrupt step, it also retrieves the queue element from the corresponding queue and, based on the queue element, retrieves the corresponding data from memory for further processing. The queue element includes data type, data start address, and length. During this process, the calculation result data remains in memory and is not transferred; it is simply processed differently by different cores. The amount of data exchanged between cores is minimal, improving system real-time performance and reducing memory usage. The main functional divisions of the queue management module are as follows:

[0056] a. Creation of the queue management module, including the size and number of queue elements;

[0057] b. Add the specified queue element to the tail of the queue;

[0058] c. Select the queue element at the head of the specified queue and remove or retain the selected queue element.

[0059] 3. Memory Management Module

[0060] The memory management module executes memory management steps, which specifically include: allocating cache data addresses in memory for any core of the multi-core DSP; managing the acquisition and release of cache data on the same or different cores; enabling fast processing of computational data without data transfer; and defining cache start addresses at different memory addresses to improve flexibility. Since the memory allocation by the memory management module is of a fixed length, a relatively simple memory pool approach can be used to improve real-time performance. The main functionalities of the memory management module are as follows:

[0061] a. Initialization of the memory management module, including cache start address, number of management units, and size of management units;

[0062] b. Locate and retrieve the address of the currently free cache in memory;

[0063] c. Release the specified cached data address in memory;

[0064] 4. Operation Management Module

[0065] The computation management module executes computation management steps, which specifically include: determining the completion status of any core operation in the multi-core DSP and setting the running status of any core operation, thereby realizing the reallocation of computation. The main functional divisions of the computation management module are as follows:

[0066] a. Initialize the operation status management module.

[0067] b. Obtain the completion status of a certain operation.

[0068] c. Set the running status of a certain operation, including idle or busy.

[0069] Since the queue management module, memory management module, and operation management module involve read and write operations of shared data between multiple cores, there is a problem of simultaneous read and write. The mutual exclusion of data access between the queue management module, memory management module, and operation management module of this invention can be achieved by disabling interrupts, mathematical algorithms (such as Peterson's algorithm and Bakery's algorithm), system locks, atomic locks, etc. Data access mutual exclusion processing is performed inside the module, realizing mutual exclusion access to shared data between cores, and providing a foundation for the stable operation of the module.

[0070] Example 1

[0071] This embodiment proposes a control method based on multi-core DSP parallel computing, based on the aforementioned modules, to be applied to scenarios with multiple data sources and a single data destination, such as... Figure 1As shown, in the TMS320C6678 multi-core DSP, cores 2 and 3 perform operations simultaneously, generating results intermittently. These results need to be sent to the host computer via Ethernet through core 0. Therefore, the process includes the step of sending the parallel operation results of the first core through the second core:

[0072] A1) Before the first core's cores 2 and 3 perform their operations, the memory management module is called to execute memory management steps, which allocate corresponding cache data addresses in the free space of memory for cores 2 and 3 respectively to store the operation results;

[0073] A2) After the operations on cores 2 and 3 are completed, the results are stored in the corresponding cached data addresses of cores 2 and 3, respectively. The queue management module is then called to perform the queue management steps, storing the queue elements corresponding to the operation results of cores 2 and 3 into the queue. The queue element includes the data type of the operation result, the starting address of the data, and the length. An example of the queue element structure is as follows:

[0074]

[0075] A3) Call the interrupt module to execute the interrupt steps, write the inter-core interrupt ID number corresponding to core 2 and core 3 into the interrupt register, set the flag corresponding to core 0 of the second core in the interrupt register, generate an inter-core interrupt and send it to core 0;

[0076] A4) After receiving an inter-core interrupt, core 0 retrieves the queue element from the corresponding queue. Specifically, it retrieves the queue element from the head of the corresponding queue (deletes the queue head), retrieves the corresponding data from memory according to the data address in the queue element, processes the data, and sends the processed data to the host computer via Ethernet.

[0077] A5) Call the memory management module to perform memory management steps, release the cache data addresses corresponding to core 2 and core 3, thereby completing the data sending function.

[0078] Example 2

[0079] This embodiment proposes a control method based on multi-core DSP parallel computing, based on the aforementioned modules, to be applied to scenarios with one data source and multiple data destinations, such as... Figure 2 As shown, in the TMS320C6678 multi-core DSP, core 1 receives data of varying lengths from an external interface at irregular intervals and needs to send it to cores 2 and 3 for processing. Therefore, the process includes the step of the first core sending data to the second core for parallel processing:

[0080] B1) The external data acquired by the first core (core 1) is stored in the cache data address requested by the memory management module in advance to perform the memory management steps;

[0081] B2) Call the computation management module to execute computation management steps, determine the computation status of core 2 and core 3 of the second core. Specifically, if core 2 is busy, then determine whether core 3 is busy. If core 2 or core 3 is idle, call the memory management module to execute memory management steps, and request the next cache data address in the free space of memory. If both core 2 and core 3 are busy, call the computation management module to execute computation management steps, and continue to determine the computation status of core 2 and core 3 of the second core until core 2 or core 3 is idle.

[0082] B3) Call the queue management module to execute the queue management steps, store the queue element corresponding to the external data obtained by core 1 into the queue, and the queue element includes the data address and length of this data;

[0083] B4) Call the operation management module to execute the operation management steps, set the idle core 2 or core 3 to the busy state, call the interrupt module to write the inter-core interrupt ID number corresponding to core 1 into the interrupt register, and set the flag corresponding to core 2 or core 3 in the interrupt register to generate an inter-core interrupt and send it to core 2 or core 3, thereby realizing the task allocation of core 2 or core 3.

[0084] B5) After receiving an inter-core interrupt, core 2 or core 3 retrieves the queue element from the corresponding queue, retrieves the corresponding data from memory according to the data address of the queue element, and performs the operation.

[0085] B6) After the operation of core 2 or core 3 is completed, the memory management module is called to perform memory management steps, release the cached data address, and the operation management module is called to perform operation management steps, setting the completed core 2 or core 3 to an idle state.

[0086] This completes the computation of the acquired external data. For each subsequent parallel computation of the acquired external data, steps B1 to B6 will be executed.

[0087] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention should fall within the protection scope of the present invention.

Claims

1. A control method based on multi-core DSP parallel computing, characterized in that, Includes the following steps: The interrupt procedure includes: after any core of the multi-core DSP completes the operation, the flag corresponding to the receiving core in the interrupt register is set, and the inter-core interrupt ID number is assigned and written to the interrupt register to generate an inter-core interrupt and send it to the receiving core; after receiving the inter-core interrupt, the receiving core clears the corresponding flag in the interrupt register in real time, obtains the corresponding inter-core interrupt ID number in the interrupt register in real time and uses if to judge. The queue management steps include: after any core of the multi-core DSP completes the operation, the queue element corresponding to the operation result is stored in the queue; after the interrupt step is completed, the receiving core retrieves the queue element from the corresponding queue, retrieves the corresponding data from memory according to the queue element, and processes it; The memory management steps include: requesting cache data addresses in memory for any core of the multi-core DSP to perform operations, or releasing specified cache data addresses in memory; The operation management steps include: determining the completion status of any core operation of the multi-core DSP and setting the running status of the corresponding operation.

2. The control method based on multi-core DSP parallel operation according to claim 1, characterized in that, The queue management steps further include: adding a specified queue element to the tail of the queue, or selecting a queue element from the head of a specified queue and removing or retaining the selected queue element.

3. The control method based on multi-core DSP parallel operation according to claim 1, characterized in that, The queue element includes data type, data starting address, and length.

4. The control method based on multi-core DSP parallel operation according to claim 1, characterized in that, This includes the step of sending the results of parallel computation through the receiving core, specifically including: Before cores 2 and 3 begin operation, a memory management step is performed to allocate corresponding cache data addresses in the free space of memory for cores 2 and 3 respectively. After the operations of cores 2 and 3 are completed, the results are stored in the corresponding cache data addresses of cores 2 and 3, respectively. Then, the queue management step is executed to store the queue elements corresponding to the operation results of cores 2 and 3 into the queue. Execute the interrupt procedure, write the inter-core interrupt ID number corresponding to core 2 and core 3 into the interrupt register, set the flag corresponding to core 0 of the second core in the interrupt register, generate an inter-core interrupt and send it to core 0; After receiving an inter-core interrupt, core 0 retrieves the queue element from the corresponding queue, retrieves the corresponding data from memory based on the queue element, and processes and sends the data. Perform memory management steps to release the cached data addresses corresponding to cores 2 and 3.

5. The control method based on multi-core DSP parallel operation according to claim 1, characterized in that, It also includes the step of sending external data to the receiving core for parallel computation, specifically including: The external data acquired by core 1 is stored in the cached data address requested in the pre-execution memory management steps; Execute the operation management steps to determine the operation status of core 2 and core 3 of the second core. If core 2 or core 3 is in an idle state, execute the memory management steps to request the next cache data address in the free space of memory. If core 2 and core 3 are both in a busy state, execute the operation management steps to continue to determine the operation status of core 2 and core 3 of the second core until core 2 or core 3 is in an idle state. Execute the queue management steps to store the queue elements corresponding to the external data obtained by core 1 into the queue; Execute the operation management step, set the idle core 2 or core 3 to the busy state, execute the interrupt step, write the inter-core interrupt ID number corresponding to core 1 into the interrupt register, set the flag corresponding to core 2 or core 3 in the interrupt register, generate an inter-core interrupt and send it to core 2 or core 3; After receiving an inter-core interrupt, core 2 or core 3 retrieves a queue element from the corresponding queue, retrieves the corresponding data from memory based on the queue element, and performs the operation. Execute memory management steps to release the cached data address, and execute operation management steps to set core 2 or core 3, which has completed the operation, to an idle state.

6. A control system based on multi-core DSP parallel computing, characterized in that, include: The interrupt module is used to set the flag corresponding to the receiving core in the interrupt register after any core of the multi-core DSP has completed its operation, and to write the value of the inter-core interrupt ID number into the interrupt register, thereby generating an inter-core interrupt and sending it to the receiving core. The queue management module is used to store the queue element corresponding to the calculation result into the queue after any core of the multi-core DSP has completed the calculation. The memory management module is used to request cache data addresses required for the operation of any core of a multi-core DSP in memory, or to release specified cache data addresses in memory, or to add specified queue elements to the tail of the queue, or to select the queue element at the head of the queue from a specified queue and remove or retain the selected queue element. The computation management module is used to determine the completion status of any core computation of a multi-core DSP and set the running status of the corresponding computation.

7. The control system based on multi-core DSP parallel computing according to claim 6, characterized in that, Data access is mutually exclusive among the queue management module, memory management module, and operation management module.

Images