Driving circuit of display panel, display device, electronic device and driving chip

Abstract

The present disclosure relates to a driving circuit of a display panel, a display device, an electronic device and a driving chip. The driving circuit comprises a gray scale voltage generating circuit, a driving voltage generating circuit, an output buffer circuit and a polarity control circuit. The polarity control circuit is configured to determine a target compensation mode according to a circuit connection mode of each sub-pixel unit in the pixel unit array circuit, and convert the polarity of an offset voltage of a target amplifier according to the target compensation mode. Different circuit connection modes correspond to at least one target compensation mode. The driving circuit provided by the present disclosure can improve the display quality of the display panel.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of display panels, and particularly relates to a driving circuit of a display panel, a display device, an electronic device and a driving chip. BACKGROUND

[0002] With the development of the field of display panels, the requirements for the display effect of display panels are also gradually increasing. In the existing display panel driving chip, at least one amplifier is usually included, which can be used to generate a gray scale voltage in a gray scale voltage generation circuit, or to output a voltage signal to each sub-pixel unit in an output buffer circuit. In other words, the performance of the amplifier in the driving chip can affect the voltage signal received by each sub-pixel unit. Among them, the pixel unit array circuit includes a plurality of pixel units, each pixel unit corresponds to a pixel point of an image displayed by the display panel, and each pixel unit includes R (red), G (green) and B (blue) three colors. The above-mentioned sub-pixel unit is responsible for displaying one color in the pixel unit.

[0003] Since the amplifier itself has an offset voltage, it is easy to cause the voltage signal received by the sub-pixel unit to deviate from the expected voltage signal, and thus the display effect of the display panel cannot reach the expected effect, reducing the quality of the display panel display picture.

[0004] Therefore, the present disclosure provides a driving circuit of a display panel, which can solve the problem of display quality degradation caused by the offset voltage of the amplifier. SUMMARY

[0005] The present disclosure provides a driving circuit of a display panel, which includes a gray scale voltage generation circuit, a driving voltage generation circuit, an output buffer circuit, and a polarity control circuit; the gray scale voltage generation circuit is used to generate and output a gray scale voltage to the driving voltage generation circuit; the driving voltage generation circuit is used to generate and output a plurality of driving voltages to the output buffer circuit according to a data signal of an input image and the gray scale voltage; the output buffer circuit is used to output the plurality of driving voltages to a plurality of sub-pixel units in the pixel unit array circuit through a plurality of source lines, and drive the plurality of sub-pixel units to emit light; the polarity control circuit is used to determine a target compensation mode according to the circuit connection mode of each sub-pixel unit in the pixel unit array circuit; and convert the polarity of the offset voltage of a target amplifier according to the target compensation mode; wherein a plurality of different circuit connection modes correspond to at least one target compensation mode.

[0006] In a possible implementation, the target amplifier is an amplifier used to generate the gray scale voltage in the gray scale voltage generation circuit, and / or an amplifier used to output the driving voltage in the output buffer circuit.

[0007] In a possible implementation, when the circuit connection mode of each sub-pixel unit in the pixel unit array circuit is that the sub-pixel units in the same column are electrically connected through the same source line, the sub-pixel units in the same row are electrically connected through the same gate line, or when the circuit connection mode of each sub-pixel unit in the pixel unit array circuit is that the sub-pixel units in adjacent two columns are electrically connected through the same source line, and in any row of sub-pixel units, the sub-pixel units in the odd-numbered columns and the sub-pixel units in the even-numbered columns are electrically connected through different gate lines, the polarity control circuit determines that the target compensation mode is the first compensation mode; wherein the first compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the sub-pixel units in adjacent two rows in the pixel unit array circuit opposite.

[0008] In a possible implementation, when the circuit connection mode of each sub-pixel unit in the pixel unit array circuit is that in the sub-pixel units in the same column, the sub-pixel units in the odd-numbered columns are electrically connected through the same source line, the sub-pixel units in the even-numbered columns are electrically connected through the same source line, and the sub-pixel units in the same row are electrically connected through the same gate line, the polarity control circuit determines that the target compensation mode is the second target compensation mode; wherein the second compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the sub-pixel units in each group opposite, and make the polarities of the offset voltages of the target amplifiers corresponding to the sub-pixel units in the first row in each odd-numbered group opposite to the polarities of the offset voltages of the target amplifiers corresponding to the sub-pixel units in the first row in each even-numbered group, in the case that the sub-pixel units in adjacent two rows are taken as a group, and there is no repeated sub-pixel unit in any two groups.

[0009] In a possible implementation, when the circuit connection mode of each sub-pixel unit in the pixel unit array circuit is that the sub-pixel units in adjacent two columns are electrically connected through the same source line, and in any row of sub-pixel units, the sub-pixel units in the odd-numbered columns and the sub-pixel units in the even-numbered columns are electrically connected through different gate lines, the polarity control circuit determines that the target compensation mode is the third target compensation mode; wherein the third compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the sub-pixel units in each group same, and make the polarities of the offset voltages of the target amplifiers corresponding to the sub-pixel units in each odd-numbered group opposite to the polarities of the offset voltages of the target amplifiers corresponding to the sub-pixel units in each even-numbered group, in the case that the sub-pixel units in adjacent two rows are taken as a group, and there is no repeated sub-pixel unit in any two groups.

[0010] In a possible implementation, the polarity control circuit is further configured to determine the circuit connection mode of each sub-pixel unit in the pixel unit array circuit according to the driving voltage output by the output buffer circuit to each source line when the input image is a preset image.

[0011] In a possible implementation, the driving voltage generation circuit comprises a driving control unit, which is electrically connected to the polarity control circuit, and is configured to generate and output a row synchronization signal, a field synchronization signal, a data driving signal and a scanning driving signal according to the input image; and a data driving unit, which is electrically connected to the driving control unit and the gray scale voltage generation circuit, and is configured to receive the gray scale voltage output by the gray scale voltage generation circuit and the row synchronization signal, the field synchronization signal, the data driving signal and the scanning driving signal output by the driving control unit, to generate at least one driving voltage according to the row synchronization signal, the field synchronization signal, the data driving signal, the scanning driving signal and the gray scale voltage, and to output the at least one driving voltage to the corresponding at least one sub-pixel unit according to the row synchronization signal, the field synchronization signal and the scanning driving signal.

[0012] In a possible implementation, the driving control unit is electrically connected to the polarity control circuit, and is configured to output the generated data driving signal to the polarity control circuit when the input image is a preset image; and the polarity control circuit is further configured to determine the circuit connection mode of each sub-pixel unit in the pixel unit array circuit according to the data driving signal.

[0013] In a possible implementation, when the display panel displays the preset image, only the sub-pixel unit corresponding to red in the pixel unit array circuit is lit, and / or only the sub-pixel unit corresponding to blue in the pixel unit array circuit is lit, and / or only the sub-pixel unit corresponding to green in the pixel unit array circuit is lit, and / or only the sub-pixel unit corresponding to the odd or even row in the pixel unit array circuit is lit, and / or the gray scale value corresponding to each sub-pixel unit in the pixel unit array circuit is different from the gray scale value corresponding to any adjacent sub-pixel unit.

[0014] According to another aspect of the present disclosure, the present disclosure further provides a display device, which comprises a plurality of display units and at least one driving circuit of a display panel as described above.

[0015] In a possible implementation, the display unit comprises a display panel, and the display panel comprises at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.

[0016] According to another aspect of the present disclosure, the present disclosure also provides an electronic device comprising the display device as described above.

[0017] According to another aspect of the present disclosure, the present disclosure also provides a driving chip comprising the driving circuit of the display panel as described above.

[0018] The driving circuit of the display panel provided by the present disclosure can select a corresponding compensation mode according to the circuit connection mode of each sub-pixel unit in the pixel unit array circuit, convert the polarity of the offset voltage of the target amplifier, and make the display panel display a picture that can achieve the expected effect as seen by the human eye. In addition, the present disclosure can prevent the occurrence of dark lines or bright lines in the picture as seen by the human eye, thereby improving the display quality of the display panel.

[0019] Other features and aspects of the present disclosure will become apparent from the following detailed description of the exemplary embodiments with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the present disclosure and serve to explain the principles of the present disclosure.

[0021] Figure 1 A schematic diagram of the polarity of the offset voltage of an amplifier provided by an embodiment of the present disclosure.

[0022] Figure 2 A schematic diagram of the polarity of the offset voltage of an amplifier provided by an embodiment of the present disclosure.

[0023] Figure 3 A schematic diagram of the circuit structure of a driving circuit provided by an embodiment of the present disclosure.

[0024] Figure 4 A circuit connection mode of a sub-pixel unit provided by the present disclosure.

[0025] Figure 5 Another circuit connection mode of a sub-pixel unit provided by the present disclosure.

[0026] Figure 6Another circuit connection mode of a sub-pixel unit provided by the present disclosure.

[0027] Figure 7 A schematic diagram of source line output data corresponding to the circuit connection mode of the plurality of sub-pixel circuits provided by the present disclosure.

[0028] Figure 8 A structural schematic diagram of an electronic device provided by the present disclosure. DETAILED DESCRIPTION

[0029] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numbers in the drawings indicate functionally similar or identical elements. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0030] In the description of the present disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0031] In addition, the terms "first", "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0032] In the present disclosure, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood broadly, for example, can be fixedly connected, or can be detachably connected, or integrated; can be mechanically connected, or electrically connected; can be directly connected, or indirectly connected through an intermediate medium; can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0033] The term "and / or", used in the present document, only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can represent three cases of A alone, A and B together, and B alone. In addition, the term "at least one" in the present document means any one of the plurality or any combination of at least two of the plurality, for example, at least one of A, B and C includes any one or more elements selected from the set consisting of A, B and C.

[0034] In the prior art, the driving chip of the display panel generally includes a gray scale voltage generation circuit, a driving voltage generation circuit and an output buffer circuit. The gray scale voltage generation circuit is used to generate and output a gray scale voltage to the driving voltage generation circuit, and the driving voltage generation circuit generates a plurality of driving voltages according to a data signal of an input image (i.e. an image to be displayed by the display panel) and the gray scale voltage output by the gray scale voltage generation circuit, and outputs the plurality of driving voltages to corresponding sub-pixel units in the pixel unit array circuit through the output buffer circuit.

[0035] The gray scale voltage generation circuit described above can generate a gray scale voltage through two amplifiers and a plurality of resistors, and the output buffer circuit can output a plurality of driving voltages to corresponding sub-pixel units through a plurality of amplifiers. Referring to Figure 1 and Figure 2 , since the amplifiers have offset voltages (i.e. Figure 1 and Figure 2 V ABS ), the gray scale voltage generated by the gray scale voltage generation circuit and the driving voltage output by the output buffer circuit will have a certain deviation from the expected gray scale voltage and the expected driving voltage, thereby making the display effect of the display panel unable to achieve the expected effect. For example, if the voltage input to the first input end 100 of the amplifier is V in (here, the input voltage of the output buffer circuit is taken as an example), in the case that the offset voltage of the second input end 200 of the amplifier is 1v, the voltage output by the amplifier is V in -1v, that is, the output voltage of the output buffer circuit has a loss of 1v compared with the input voltage, so that the corresponding sub-pixel unit cannot emit light according to the expected brightness, thereby causing the display effect of the display panel to be unable to achieve the expectation.

[0036] Referring to Figures 1-2 , in the related art, the polarity of the offset voltage of the amplifier can be converted to make the average value of the voltages output by the amplifier twice equal to the expected voltage, thereby making the picture finally seen by the human eye consistent with the expected picture. However, in the existing display panel, the circuit connection mode of each sub-pixel unit of the pixel unit array circuit is not single (see Figures 4-6In different circuit connection modes, if the polarity of the offset voltage of the amplifier in the gray scale voltage generation circuit and / or the amplifier in the output buffer circuit is converted by the existing conversion mode, obvious dark lines or bright lines that can be seen by the human eye exist in the picture displayed by the display panel, that is, a certain part of the display picture is obviously dark or a certain part of the display picture is obviously bright, thereby reducing the display effect of the display panel.

[0037] Therefore, referring to FIG. 1, Figure 3 The display panel driving circuit 1 provided by the display panel driving circuit 1 can select a corresponding compensation mode according to the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2, convert the polarity of the offset voltage of a target amplifier, and make the picture displayed by the display panel that can be seen by the human eye achieve the expected effect. Meanwhile, the display panel driving circuit 1 can also prevent the occurrence of the case that the display picture that can be seen by the human eye has dark lines or bright lines, thereby improving the display quality of the display panel.

[0038] Referring to FIG. 1, Figure 3 The display panel driving circuit 1 provided by the display panel driving circuit 1 can select a corresponding compensation mode according to the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2, convert the polarity of the offset voltage of a target amplifier, and make the picture displayed by the display panel that can be seen by the human eye achieve the expected effect. Meanwhile, the display panel driving circuit 1 can also prevent the occurrence of the case that the display picture that can be seen by the human eye has dark lines or bright lines, thereby improving the display quality of the display panel.

[0039] For example, the gray scale voltage generation circuit 12 is configured to generate and output a gray scale voltage to the driving voltage generation circuit 11. The driving voltage generation circuit 11 is configured to generate and output a plurality of driving voltages to the output buffer circuit 13 according to a data signal of an input image and the gray scale voltage. The output buffer circuit 13 is configured to output the plurality of driving voltages to a plurality of sub-pixel units 21 in the pixel unit array circuit 2 through a plurality of source lines, and drive the plurality of sub-pixel units 21 to emit light.

[0040] For example, the process of generating the gray scale voltage by the gray scale voltage generation circuit 12 and the process of generating the driving voltage by the driving voltage generation circuit 11 can be known in the art, and will not be described herein.

[0041] For example, the polarity control circuit 14 is configured to determine a target compensation mode according to the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2. The polarity of the offset voltage of a target amplifier is converted according to the target compensation mode.

[0042] For example, a plurality of different circuit connection manners can correspond to at least one target compensation manner, i.e., the circuit connection manner A can correspond to the target compensation manner A, the circuit connection manner B can correspond to the target compensation manner A and the compensation manner B (the compensation manner selected in actual application can be determined according to actual conditions), and the circuit connection manner C can correspond to the target compensation manner B. The disclosure does not limit the correspondence between the circuit connection manner and the compensation manner, which can ensure that the final display of the display panel viewed by the human eye meets the expected effect, and there is no bright line or dark line as mentioned above.

[0043] In a possible implementation, the target amplifier can be an amplifier for generating a gray-scale voltage in the gray-scale voltage generation circuit 12 and / or an amplifier for outputting a driving voltage in the output buffer circuit 13.

[0044] For example, in the case where the gray-scale voltage generation circuit 12 generates a gray-scale voltage through at least one amplifier and a plurality of resistors, the amplifier for generating a gray-scale voltage in the gray-scale voltage generation circuit 12 can be the target amplifier. In the case where the output buffer circuit 13 outputs the above-mentioned plurality of driving voltages through at least one amplifier electrically connected to the source line, the amplifier for outputting a driving voltage in the output buffer circuit 13 (for example, the amplifier with the output end electrically connected to the source line) can be the target amplifier. If the driving circuit 1 of the display panel simultaneously has an amplifier for generating a gray-scale voltage and an amplifier for outputting a driving voltage, the amplifier for generating a gray-scale voltage and / or the amplifier for outputting a driving voltage can be selected as the target amplifier. The selection range of the target amplifier in the disclosure is not limited to only between the amplifier for generating a gray-scale voltage and the amplifier for outputting a driving voltage, and other amplifiers in the display panel that affect the driving voltage can be selected as the target amplifier according to actual conditions.

[0045] In a possible implementation, referring to Figures 4-5 For example, in the case where the circuit connection manner of each sub-pixel unit 21 in the pixel unit array circuit 2 is that the sub-pixel units 21 in the same column are electrically connected through the same source line, and the sub-pixel units 21 in the same row are electrically connected through the same gate line (i.e., the circuit connection manner shown in FIG. 2), or in the case where the circuit connection manner of each sub-pixel unit 21 in the pixel unit array circuit 2 is that the sub-pixel units 21 in the adjacent two columns are electrically connected through the same source line, and in any row of sub-pixel units 21, the sub-pixel units 21 in the odd-numbered column and the sub-pixel units 21 in the even-numbered column are electrically connected through different gate lines (i.e., the circuit connection manner shown in FIG. 3), the target compensation manner can be the compensation manner A. Figure 4 For example, in the case where the circuit connection manner of each sub-pixel unit 21 in the pixel unit array circuit 2 is that the sub-pixel units 21 in the same column are electrically connected through the same source line, and the sub-pixel units 21 in the same row are electrically connected through the same gate line (i.e., the circuit connection manner shown in FIG. 2), or in the case where the circuit connection manner of each sub-pixel unit 21 in the pixel unit array circuit 2 is that the sub-pixel units 21 in the adjacent two columns are electrically connected through the same source line, and in any row of sub-pixel units 21, the sub-pixel units 21 in the odd-numbered column and the sub-pixel units 21 in the even-numbered column are electrically connected through different gate lines (i.e., the circuit connection manner shown in FIG. 3), the target compensation manner can be the compensation manner A. Figure 5As shown in the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2, when the sub-pixel units 21 in the pixel row A are to be driven, the polarity control circuit 14 determines the target compensation mode as the first compensation mode. The first compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the two adjacent rows of sub-pixel units 21 in the pixel unit array circuit 2 opposite.

[0046] As shown in the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2, when the sub-pixel units 21 in the pixel row A are to be driven, the polarity control circuit 14 determines the target compensation mode as the first compensation mode. The first compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the two adjacent rows of sub-pixel units 21 in the pixel unit array circuit 2 opposite. Figure 4 As shown in the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2, when the sub-pixel units 21 in the pixel row A are to be driven, the polarity control circuit 14 determines the target compensation mode as the first compensation mode. The first compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the two adjacent rows of sub-pixel units 21 in the pixel unit array circuit 2 opposite. Figure 4 As shown in the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2, when the sub-pixel units 21 in the pixel row A are to be driven, the polarity control circuit 14 determines the target compensation mode as the first compensation mode. The first compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the two adjacent rows of sub-pixel units 21 in the pixel unit array circuit 2 opposite. As shown in the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2, when the sub-pixel units 21 in the pixel row A are to be driven, the polarity control circuit 14 determines the target compensation mode as the first compensation mode. The first compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the two adjacent rows of sub-pixel units 21 in the pixel unit array circuit 2 opposite.

[0047] As shown in the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2, when the sub-pixel units 21 in the pixel row A are to be driven, the polarity control circuit 14 determines the target compensation mode as the first compensation mode. The first compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the two adjacent rows of sub-pixel units 21 in the pixel unit array circuit 2 opposite. Figure 3 As shown in the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2, when the sub-pixel units 21 in the pixel row A are to be driven, the polarity control circuit 14 determines the target compensation mode as the first compensation mode. The first compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the two adjacent rows of sub-pixel units 21 in the pixel unit array circuit 2 opposite. Figure 4 As shown in the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2, when the sub-pixel units 21 in the pixel row A are to be driven, the polarity control circuit 14 determines the target compensation mode as the first compensation mode. The first compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the two adjacent rows of sub-pixel units 21 in the pixel unit array circuit 2 opposite. Figure 4 As shown in the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2, when the sub-pixel units 21 in the pixel row A are to be driven, the polarity control circuit 14 determines the target compensation mode as the first compensation mode. The first compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the two adjacent rows of sub-pixel units 21 in the pixel unit array circuit 2 opposite. Figure 1 As shown in the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2, when the sub-pixel units 21 in the pixel row A are to be driven, the polarity control circuit 14 determines the target compensation mode as the first compensation mode. The first compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the two adjacent rows of sub-pixel units 21 in the pixel unit array circuit 2 opposite. ABS As shown in the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2, when the sub-pixel units 21 in the pixel row A are to be driven, the polarity control circuit 14 determines the target compensation mode as the first compensation mode. The first compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to the two adjacent rows of sub-pixel units 21 in the pixel unit array circuit 2 opposite. Figure 1The polarity of the offset voltage of the target amplifier shown is referred to as the P state. At this time, the gate line L1 is turned on, and the driving voltage is output to the source lines S1 to S4, driving the sub-pixel units A1 to A4 in the pixel row A to emit light. When the sub-pixel units 21 in the pixel row B are to be driven, the polarity control circuit 14 switches the polarity of the offset voltage of the target amplifier, i.e., makes the polarity of the offset voltage of the target amplifier as shown Figure 2 i.e., the negative of the offset voltage of the target amplifier is connected to the second input terminal 200 of the target amplifier, making the voltage of the second input terminal 200 of the target amplifier equal to -V ABS , the following Figure 2 The polarity of the offset voltage of the target amplifier shown is referred to as the N state. At this time, the gate line L2 is turned on, and the driving voltage is output to the source lines S1 to S4, driving the sub-pixel units B1 to B4 in the pixel row B to emit light. When the sub-pixel units 21 in the pixel row C are to be driven, the polarity control circuit 14 makes the offset voltage of the target amplifier be in the P state, at which time the gate line L3 is turned on, and the driving voltage is output to the source lines S1 to S4, driving the sub-pixel units C1 to C4 in the pixel row C to emit light. When the sub-pixel units in the pixel row D are to be driven, the polarity control circuit 14 makes the polarity of the offset voltage of the target amplifier be in the N state, at which time the gate line L4 is turned on, and the driving voltage is output to the source lines S1 to S4, driving the sub-pixel units D1 to D4 in the pixel row D to emit light. In other words, the polarity control circuit 14 switches the polarity of the offset voltage of the target amplifier once for each row of sub-pixel units 21 driven by the driving circuit 1.

[0048] For example, referring to Figure 3 and Figure 5 shown, Figure 5 the circuit connection of each sub-pixel unit 21 in the pixel row A is as follows: the sub-pixel units 21 in the pixel column 1 and the pixel column 2 are electrically connected through the source line S1, and the sub-pixel units 21 in the pixel column 3 and the pixel column 4 are electrically connected through the source line S2. The sub-pixel unit A1 and the sub-pixel unit A3 in the pixel row A are electrically connected through the gate line L1, and the sub-pixel unit A2 and the sub-pixel unit A4 in the pixel row A are electrically connected through the gate line L2. The sub-pixel unit B1 and the sub-pixel unit B3 in the pixel row B are electrically connected through the gate line L3, and the sub-pixel unit B2 and the sub-pixel unit B4 in the pixel row B are electrically connected through the gate line L4. The sub-pixel unit C1 and the sub-pixel unit C3 in the pixel row C are electrically connected through the gate line L5, and the sub-pixel unit C2 and the sub-pixel unit C4 in the pixel row C are electrically connected through the gate line L6. The sub-pixel unit D1 and the sub-pixel unit D3 in the pixel row D are electrically connected through the gate line L7, and the sub-pixel unit D2 and the sub-pixel unit D4 in the pixel row D are electrically connected through the gate line L8.

[0049] For example, see [link to relevant documentation]. Figure 5 As shown, when gate line L1 is on and source lines S1 and S2 output driving voltages, sub-pixel unit A1 receives the driving voltage output by source line S1, and sub-pixel unit A3 receives the driving voltage output by source line S2. At this time, sub-pixel units A1 and A3 are driven. When gate line L2 is on and source lines S1 and S2 output driving voltages, sub-pixel unit A2 receives the driving voltage output by source line S1, and sub-pixel unit A4 receives the driving voltage output by source line S2. At this time, sub-pixel units A2 and A4 are driven. When gate line L3 is on and source lines S1 and S2 output driving voltages, sub-pixel unit B1 receives the driving voltage output by source line S1, and sub-pixel unit B3 receives the driving voltage output by source line S2. At this time, sub-pixel units B1 and B3 are driven. When gate line L4 is in the on state and source lines S1 and S2 output driving voltages, sub-pixel unit B2 receives the driving voltage output by source line S1, and sub-pixel unit B4 receives the driving voltage output by source line S2. At this time, sub-pixel unit B2 and sub-pixel unit B4 are driven, and so on.

[0050] For example, the circuit connection method of each sub-pixel unit 21 in the pixel unit array circuit 2 is as follows: Figure 5 In the case shown, when sub-pixel unit 21 in pixel row A is to be driven, the polarity control circuit 14 makes the polarity of the offset voltage of the target amplifier in the P state. At this time, the gate line L1 is turned on first, and the driving voltage is output to the source line S1 to the source line S2 to drive the sub-pixel unit A1 and sub-pixel unit A3 in pixel row A to emit light. Then the gate line L2 is turned on, and the driving voltage is output to the source line S1 to the source line S2 to drive the sub-pixel unit A2 and sub-pixel unit A4 in pixel row A to emit light. When a sub-pixel unit in pixel row B is to be driven, the polarity control circuit 14 reverses the polarity of the offset voltage of the target amplifier, making the polarity of the offset voltage of the target amplifier in the N state. At this time, the gate line L3 is first turned on, and a driving voltage is output to the source lines S1 to S2, driving sub-pixel units B1 and B3 in pixel row B to emit light. Then, the gate line L4 is turned on, and a driving voltage is output to the source lines S1 to S2, driving sub-pixel units B2 and B4 in pixel row A to emit light. Similarly, the circuit connection of each sub-pixel unit 21 in the pixel unit array circuit 2 is as follows: Figure 5 In the case shown, for each row of sub-pixel units 21 driven by the driving circuit 1, the polarity control circuit 14 will switch the polarity of the target amplifier offset voltage once.

[0051] It is worth mentioning that when the sub-pixel units 21 in the pixel row A are to be driven, the polarity control circuit 14 can make the polarity of the offset voltage of the target amplifier as shown in (i.e. the polarity of the offset voltage is in the N state). When the sub-pixel units 21 in the pixel row B are to be driven, the polarity control circuit 14 makes the polarity of the offset voltage of the target amplifier as shown in (i.e. the polarity of the offset voltage is in the P state). When the sub-pixel units 21 in the pixel row C are to be driven, the polarity control circuit 14 makes the offset voltage of the target amplifier in the N state. When the sub-pixel units 21 in the pixel row D are to be driven, the polarity control circuit 14 makes the polarity of the offset voltage of the target amplifier in the P state. The present disclosure does not limit the initial state of the polarity change of the offset voltage of the target amplifier (i.e. it can be first converted from the P state to the N state, or it can be first converted from the N state to the P state), which can ensure that the polarities of the offset voltages corresponding to the two adjacent rows of sub-pixel units 21 are different. Figure 2 Figure 1 In a possible implementation, referring to FIG. 2 and FIG. 3, the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2 is that in the same column of sub-pixel units 21, the sub-pixel units 21 in the odd-numbered column are electrically connected through the same source line, the sub-pixel units 21 in the even-numbered column are electrically connected through the same source line, and the sub-pixel units 21 in the same row are electrically connected through the same gate line. In this case, the polarity control circuit 14 determines the target compensation mode as the second target compensation mode. The second compensation mode is that in the case that the sub-pixel units 21 in adjacent two rows are taken as a group, and there is no repeated sub-pixel unit 21 in any two groups, the polarities of the offset voltages of the target amplifiers corresponding to the two rows of sub-pixel units 21 in each group are opposite, and the polarity of the offset voltage of the target amplifier corresponding to the sub-pixel unit 21 in the first row in each odd-numbered group is opposite to the polarity of the offset voltage of the target amplifier corresponding to the sub-pixel unit 21 in the first row in each even-numbered group.

[0052] In a possible implementation, referring to Figure 3 and Figure 6 In a possible implementation, referring to and

[0053] In a possible implementation, referring to Figure 6 and Figure 6The circuit connection of each sub-pixel unit 21 in the pixel column is as follows: In pixel column 1, sub-pixel units A1 and C1 are electrically connected through source line S1, and sub-pixel units B1 and D1 are electrically connected through source line S2. In pixel column 2, sub-pixel units A2 and C2 are electrically connected through source line S2, and sub-pixel units B2 and D2 are electrically connected through source line S3. In pixel column 3, sub-pixel units A3 and C3 are electrically connected through source line S3, and sub-pixel units B3 and D3 are electrically connected through source line S4. In pixel column 4, sub-pixel units A4 and C4 are electrically connected through source line S4, and sub-pixel units B4 and D4 are electrically connected through source line S5. Sub-pixel units 21 (i.e., sub-pixel units A1 to A4) located in pixel row A are electrically connected through gate line L1, sub-pixel units 21 (i.e., sub-pixel units B1 to B4) located in pixel row B are electrically connected through gate line L2, sub-pixel units 21 (i.e., sub-pixel units C1 to C4) located in pixel row C are electrically connected through gate line L3, and sub-pixel units 21 (i.e., sub-pixel units D1 to D4) located in pixel row D are electrically connected through gate line L4.

[0054] For example, see [link to relevant documentation]. Figure 6 As shown, when gate line L1 is on and source lines S1 to S5 output driving voltages, sub-pixel unit 21 in pixel row A is driven. Sub-pixel unit A1 receives the driving voltage output from source line S1, sub-pixel unit A2 receives the driving voltage output from source line S2, sub-pixel unit A3 receives the driving voltage output from source line S3, and sub-pixel unit A4 receives the driving voltage output from source line S4. When gate line L2 is on and source lines S1 to S5 output driving voltages, sub-pixel unit 21 in pixel row B is driven. Sub-pixel unit B1 receives the driving voltage output from source line S2, sub-pixel unit B2 receives the driving voltage output from source line S3, sub-pixel unit B3 receives the driving voltage output from source line S4, sub-pixel unit B4 receives the driving voltage output from source line S5, and so on.

[0055] For example, the circuit connection method of each sub-pixel unit 21 in the pixel unit array circuit 2 is as follows: Figure 6In the illustrated case, sub-pixel units 21 in pixel row A and sub-pixel units 21 in pixel row B are grouped together (hereinafter referred to as the first pixel group), and sub-pixel units 21 in pixel row C and sub-pixel units 21 in pixel row D are grouped together (hereinafter referred to as the second pixel group). When sub-pixel units 21 in pixel row A are to be driven, the polarity control circuit 14 can set the polarity of the offset voltage of the target amplifier to the P state. When sub-pixel units 21 in pixel row B are to be driven, the polarity control circuit 14 reverses the polarity of the offset voltage of the target amplifier, that is, sets the polarity of the offset voltage of the target amplifier to the N state. When sub-pixel units 21 in pixel row C are to be driven, the polarity control circuit 14 keeps the polarity of the offset voltage of the target amplifier in the N state. When sub-pixel units 21 in pixel row D are to be driven, the polarity control circuit 14 reverses the polarity of the offset voltage of the target amplifier, that is, sets the polarity of the offset voltage of the target amplifier to the P state. In other words, the polarity control circuit 14 sets the polarity switching process of the target amplifier's offset voltage to switch from P state to N state, maintain N state, and then switch from N state to P state, that is, to cycle through the polarity of the target amplifier's offset voltage in the form of PNNP.

[0056] It is worth noting that the polarity control circuit 14 can set the polarity switching process of the target amplifier's offset voltage to switch from N state to P state, maintain P state, and then switch from P state to N state, that is, to cycle through the polarity of the target amplifier's offset voltage in the form of NPPN.

[0057] In one possible implementation, see [reference] Figure 3 as well as Figure 5 As shown, the circuit connection method of each sub-pixel unit 21 in the pixel unit array circuit 2 is as follows: Figure 5 In the case shown, the polarity control circuit 14 determines the target compensation method as the third target compensation method. The third compensation method involves grouping the sub-pixel units 21 in two adjacent rows into a single group, ensuring that no two groups contain duplicate sub-pixel units 21. Furthermore, the polarity of the offset voltage of the target amplifier corresponding to the sub-pixel units 21 in each group is the same, and the polarity of the offset voltage of the target amplifier corresponding to the sub-pixel units 21 in each odd-numbered group is opposite to the polarity of the offset voltage of the target amplifier corresponding to the sub-pixel units 21 in each even-numbered group.

[0058] For example, the circuit connection method of each sub-pixel unit 21 in the pixel unit array circuit 2 is as follows: Figure 5In the case shown, the sub-pixel units 21 in the pixel row A and the sub-pixel units 21 in the pixel row B are taken as a group (hereinafter referred to as a first pixel group), and the sub-pixel units 21 in the pixel row C and the sub-pixel units 21 in the pixel row D are taken as a group (hereinafter referred to as a second pixel group). When the sub-pixel units 21 in the pixel row A are to be driven, the polarity control circuit 14 can make the polarity of the offset voltage of the target amplifier be in the P state. When the sub-pixel units 21 in the pixel row B are to be driven, the polarity control circuit 14 does not convert the polarity of the offset voltage of the target amplifier, that is, the polarity of the offset voltage of the target amplifier is still in the P state. When the sub-pixel units 21 in the pixel row C are to be driven, the polarity control circuit 14 converts the polarity of the offset voltage of the target amplifier, that is, the polarity of the offset voltage of the target amplifier is in the N state. When the sub-pixel units 21 in the pixel row D are to be driven, the polarity control circuit 14 does not convert the polarity of the offset voltage of the target amplifier, that is, the polarity of the offset voltage of the target amplifier is still in the N state. In other words, the polarity control circuit 14 sets the conversion process of the polarity of the offset voltage of the target amplifier to start from the P state, keep the P state, and then convert from the P state to the N state, keep the N state, that is, in the form of PPNN, the polarity of the offset voltage of the target amplifier is converted in a cycle.

[0059] It is worth noting that the polarity control circuit 14 can set the conversion process of the polarity of the offset voltage of the target amplifier to start from the N state, keep the N state, and then convert from the N state to the P state, keep the P state, that is, in the form of NNPP, the polarity of the offset voltage of the target amplifier is converted in a cycle.

[0060] In addition, it is also worth noting that the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2 in the above is as shown in Figure 5 In the case shown, the first compensation mode and the third compensation mode can be corresponded, and in actual application, whether the first compensation mode or the second compensation mode is selected to convert the polarity of the offset voltage of the target amplifier can be determined according to actual conditions. At the same time, the compensation mode provided by the present disclosure is not limited to the first compensation mode, the second compensation mode and the third compensation mode, and the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2 is also not limited to the circuit connection mode shown in Figures 4-6 .

[0061] In a possible implementation, referring to Figure 7 , the polarity control circuit 14 is further configured to, in a case that the input image is a preset image, determine the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2 according to the driving voltage output by the output buffer circuit 13 to each source line.

[0062] For example, referring to Figures 3-7As shown, when the display panel displays the preset image, only the sub-pixel units 21 corresponding to red in the pixel unit array circuit 2 are lit (corresponding to the first preset image in Figure 7 ), and / or, only the sub-pixel units 21 corresponding to blue in the pixel unit array circuit 2 are lit, and / or, only the sub-pixel units 21 corresponding to green in the pixel unit array circuit 2 are lit, and / or, only the sub-pixel units 21 corresponding to the odd rows or even rows in the pixel unit array circuit 2 are lit (corresponding to the second preset image in Figure 7 ), and / or, the gray scale value corresponding to each sub-pixel unit 21 in the pixel unit array circuit 2 is different from the gray scale value corresponding to any one of the adjacent sub-pixel units 21 (corresponding to the third preset image in Figure 7 ).

[0063] For example, the sub-pixel units 21 in the pixel column 1 are the sub-pixel units corresponding to red, the sub-pixel units 21 in the pixel column 2 are the sub-pixel units corresponding to green, the sub-pixel units 21 in the pixel column 3 are the sub-pixel units corresponding to blue, and the sub-pixel units 21 in the pixel column 4 are the sub-pixel units corresponding to red. Although the present disclosure is described only in the 4*4 pixel unit array circuit 2, it should not be considered that the present disclosure is limited in the 4*4 pixel unit array circuit 2, and the number of sub-pixel units included in the pixel array circuit 2 can be determined according to actual conditions.

[0064] For example, continuing to refer to Figures 3-7 , in Figure 7 , the data "FF" corresponds to the highest gray scale, the data "00" corresponds to the lowest gray scale, and when the display panel displays the preset image, the gray scale value corresponding to each sub-pixel unit 21 in the pixel unit array circuit 2 is different from the gray scale value corresponding to any one of the adjacent sub-pixel units 21 (that is, taking the display panel displaying the third preset image in Figure 7 as an example), if the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2 of the display panel is as shown in Figure 4 , then the driving voltages output by the source lines S1 and S3 at the same time are the same, the driving voltages output by the source lines S2 and S4 at the same time are the same, and the driving voltages output by the source lines S1 and S3 at the same time are completely different. Referring to Figure 4 and Figure 7As shown in the data corresponding to the third preset image in the first set of data, the driving voltages output by source lines S1 and S3 to pixel row A are the driving voltages corresponding to the highest gray level value (i.e., the driving voltage corresponds to the data "FF"), the driving voltages output to pixel row B are the driving voltages corresponding to the lowest gray level value (i.e., the driving voltage corresponds to the data "00"), the driving voltages output to pixel row C are the driving voltages corresponding to the highest gray level value (i.e., the corresponding data "FF"), and the driving voltages output to pixel row D are the driving voltages corresponding to the lowest gray level value (i.e., the driving voltage corresponds to the data "00"). The driving voltages output by source lines S2 and S4 to pixel row A are the driving voltages corresponding to the lowest gray level value (i.e., the driving voltage corresponds to data "00"). The driving voltages output to pixel row B are the driving voltages corresponding to the highest gray level value (i.e., the driving voltage corresponds to data "FF"). The driving voltages output to pixel row C are the driving voltages corresponding to the lowest gray level value (i.e., the driving voltage corresponds to data "00"). The driving voltages output to pixel row D are the driving voltages corresponding to the lowest high gray level value (i.e., the driving voltage corresponds to data "FF").

[0065] For example, see [link to relevant documentation]. Figures 4-7 As shown, also in Figure 7 In the image, "FF" corresponds to the highest grayscale, and "00" corresponds to the lowest grayscale. When displaying a preset image on the display panel, the grayscale value of each sub-pixel unit in the pixel unit array circuit is different from the grayscale value of any adjacent sub-pixel unit. (This is illustrated by the example of displaying the image on the display panel.) Figure 7 Taking the third preset image as an example, if the circuit connection method of each sub-pixel unit 21 in the pixel unit array circuit 2 of the display panel is as follows: Figure 6 As shown, the driving voltages output to each pixel row by source lines S1 and S3 at the same time are consistent, and the sub-pixel units 21 in each pixel row that receive the driving voltage through source lines S1 and S3 all receive the same grayscale value. Similarly, the driving voltages output to each pixel row by source lines S2 and S4 at the same time are consistent, and the sub-pixel units 21 in each pixel row that receive the driving voltage through source lines S2 and S4 all receive the same grayscale value. (See reference...) Figure 7 As shown in the data corresponding to the third preset image in the second set of data, the driving voltages output by source lines S1 and S3 to pixel rows A, B, C, and D are all driving voltages corresponding to the highest grayscale value (i.e., the driving voltage corresponds to the data "FF"), while the driving voltages output by source lines S2 and S4 to pixel rows A, B, C, and D are all driving voltages corresponding to the lowest grayscale value (i.e., the driving voltage corresponds to the data "00").

[0066] For example, see [link to relevant documentation]. Figures 4-7 As shown, also in Figure 7 In the image, the data "FF" corresponds to the highest grayscale, and the data "00" corresponds to the lowest grayscale. Furthermore, when displaying a preset image on the display panel, the grayscale value of each sub-pixel unit 21 in the pixel unit array circuit 2 is different from the grayscale value of any adjacent sub-pixel unit 21. (This is illustrated by the example of displaying the image on the display panel.) Figure 7 Taking the third preset image as an example, if the circuit connection method of each sub-pixel unit 21 in the pixel unit array circuit 2 of the display panel is as follows: Figure 5 As shown, the driving voltage output from the source line at the same time corresponds to the same grayscale value. (See also...) Figure 7 As shown in the data corresponding to the third preset image in the third set of data, the driving voltages of the sub-pixel units 21 (i.e., sub-pixel units A1 and A3 in pixel row A) output from source lines S1 and S2 to gate line L1 are both driving voltages corresponding to the highest grayscale value (i.e., the driving voltage corresponds to the data "FF"). The driving voltages of the sub-pixel units 21 (i.e., sub-pixel units A2 and A4 in pixel row A) output from source lines S1 and S2 to gate line L2 are both driving voltages corresponding to the lowest grayscale value (i.e., the driving voltage corresponds to the data "FF"). For data “00”), the driving voltages of the sub-pixel units 21 (i.e., sub-pixel units B1 and B3 in pixel row B) corresponding to the gate line L3 output by source lines S1 and S2 are the driving voltages corresponding to the lowest gray level value (i.e., the driving voltages correspond to data “00”), and the driving voltages corresponding to the sub-pixel units 21 (i.e., sub-pixel units B2 and B4 in pixel row B) corresponding to the gate line L4 output by source lines S1 and S2 are the driving voltages corresponding to the highest gray level value (i.e., the driving voltages correspond to data “FF”), and so on.

[0067] For example, the grayscale value corresponding to each sub-pixel unit 21 in the pixel unit array circuit 2 can be made different from the grayscale value corresponding to any adjacent sub-pixel unit 21, thus determining the circuit connection method of each sub-pixel unit 21 in the pixel unit array circuit 2. Alternatively, only the red sub-pixel units 21 in the pixel unit array circuit 2 can be lit first to determine whether the circuit connection method of each sub-pixel unit 21 in the pixel unit array circuit 2 is as described. Figure 4 As shown, only the sub-pixel units 21 corresponding to the odd or even rows in the pixel unit array circuit 2 are lit up, and the circuit connection method of each sub-pixel unit 21 in the pixel unit array circuit 2 is determined as follows. Figure 4 As shown, or as Figure 5 As shown.

[0068] In a possible implementation, the driving voltage generation circuit comprises a driving control unit and a data driving unit.

[0069] For example, the driving control unit is electrically connected with the polarity control circuit, and the data driving unit is electrically connected with the driving control unit and the gray scale voltage generation circuit. The driving control circuit is configured to generate and output a row synchronization signal, a field synchronization signal, a data driving signal and a scanning driving signal according to an input image. The data driving unit is configured to receive the gray scale voltage output by the gray scale voltage generation circuit, and the row synchronization signal, the field synchronization signal, the data driving signal and the scanning driving signal output by the driving control unit. At least one driving voltage is generated according to the row synchronization signal, the field synchronization signal, the data driving signal, the scanning driving signal and the gray scale voltage. The at least one driving voltage is output to the corresponding at least one sub-pixel unit 21 according to the row synchronization signal, the field synchronization signal and the scanning driving signal.

[0070] For example, the process in which the driving control circuit generates the row synchronization signal, the field synchronization signal, the data driving signal and the scanning driving signal, the process in which the data driving unit generates the at least one driving voltage, and the process in which the at least one driving voltage is output to the corresponding at least one sub-pixel unit 21 according to the row synchronization signal, the field synchronization signal and the scanning driving signal can be known in the art, and the present disclosure does not limit them. The driving control unit can be a timing controller.

[0071] In a possible implementation, the driving control unit is electrically connected with the polarity control circuit 14. The driving control unit is configured to output the generated data driving signal to the polarity control circuit 14 when the input image is a preset image. The polarity control circuit 14 is further configured to determine the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2 according to the data driving signal.

[0072] For example, the polarity control circuit 14 can determine the gray scale value corresponding to the driving voltage output by the source line at each moment through the driving control unit, and then determine the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2. The determination of the circuit connection mode of the sub-pixel unit can be known in the art, and the present disclosure does not limit it. Figure 7 As shown in the figure, the polarity control circuit 14 can also determine the gray scale value corresponding to the driving voltage output by the source line at each moment through the driving control unit, and then determine the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2. The determination of the circuit connection mode of the sub-pixel unit can be known in the art, and the present disclosure does not limit it.

[0073] For example, the circuit connection mode of each sub-pixel unit 21 in the pixel unit array circuit 2 can also be determined by other ways, such as directly observing the wiring in the pixel unit array circuit, and the present disclosure does not limit it.

[0074] The driving circuit provided by the present disclosure can determine the circuit connection mode of each sub-pixel unit in the pixel unit array circuit according to the data output by the source line or the data driving signal generated by the driving control unit when the display panel displays a preset image, and can further simplify the process of determining the circuit connection mode of each sub-pixel unit in the pixel unit array circuit, thereby improving the determination efficiency of the target compensation mode corresponding to the circuit connection mode.

[0075] According to another aspect of the present disclosure, a display device is also provided, which includes a plurality of display units and at least one driving circuit of the display panel as described above.

[0076] In a possible implementation, the display unit includes a display panel, and the display panel includes at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.

[0077] According to another aspect of the present disclosure, a driving chip is also provided, which includes the driving circuit of the display panel as described above.

[0078] According to another aspect of the present disclosure, an electronic device is also provided, which includes the display device as described above.

[0079] Exemplarily, the electronic device in the present embodiment includes but is not limited to a desktop computer, a television, a mobile device with a large-size screen such as a mobile phone, a tablet computer, and other common electronic devices that need to be connected in cascade with multiple chips to realize driving.

[0080] Exemplarily, the electronic device can also be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device, or a vehicle-mounted device, etc. Exemplarily, some terminals are exemplified as: a display, a smart phone or a portable device, a mobile phone, a tablet computer, a notebook computer, a palm computer, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in smart grid, a wireless terminal in transportation safety, a wireless terminal in smart city, a wireless terminal in smart home, a wireless terminal in Internet of Vehicles, etc. For example, the server can be a local server or a cloud server.

[0081] Figure 8 A block diagram of an electronic device 1900 according to an embodiment of the disclosure is shown. For example, the electronic device 1900 can be provided as a server or a terminal device. Referring to Figure 8 , the electronic device 1900 includes a processing component 1922, which further includes one or more processors, and a memory resource represented by a memory 1932, for storing instructions executable by the processing component 1922, such as an application program. The application program stored in the memory 1932 can include one or more than one module each corresponding to a set of instructions. In addition, the processing component 1922 is configured to execute the instructions to perform the above-mentioned method.

[0082] The electronic device 1900 can also include a power supply component 1926 configured to perform power management of the electronic device 1900, a wired or wireless network interface 1950 configured to connect the electronic device 1900 to a network, and an input / output (I / O) interface 1958. The electronic device 1900 can operate based on an operating system stored in the memory 1932, such as Windows ServerTM, Mac OS XTM, UnixTM, LinuxTM, FreeBSDTM or the like.

[0083] In an example embodiment, a non-transitory computer-readable storage medium, such as the memory 1932 including computer program instructions, is also provided, which can be executed by the processing component 1922 of the electronic device 1900 to complete the above method.

[0084] The above descriptions are only some exemplary embodiments of the present application, and are not intended to limit the protection scope of the present application, which is defined by the appended claims.

[0085] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other implementations.

[0086] It should be noted that, in the present document, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element preceded by "comprises... a" does not, without more constraints, foreclose the existence of additional identical elements in the process, method, article, or apparatus that comprises the stated elements.

[0087] The flow diagrams and block diagrams in the drawings are presented to illustrate the architecture, functionality, and operations of possible implementations of systems, methods and computer program products according to the present disclosure. In this regard, each block in the flow diagrams and block diagrams can represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical functions. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flow diagrams, and combinations thereof, can be implemented by dedicated hardware-based systems that perform the specified functions or acts, or combinations of hardware and software.

[0088] Having described above several embodiments of the disclosure, any modifications and variations that fall within the scope of the described embodiments are also intended to be within the scope of the disclosure. As will be apparent to those skilled in the art, some modifications and variations to the embodiments described above can be practiced while staying within the scope and spirit of the described embodiments. The foregoing description of the described embodiments has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the described embodiments to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended that the disclosed embodiments be limited only by the claims.

Claims

1. A drive circuit of a display panel, characterized by, The driving circuit comprises a gray-scale voltage generating circuit, a driving voltage generating circuit, an output buffer circuit, and a polarity control circuit; The gray-scale voltage generating circuit is configured to generate and output a gray-scale voltage to the driving voltage generating circuit; The driving voltage generating circuit is configured to generate and output a plurality of driving voltages to the output buffer circuit according to a data signal of an input image and the gray-scale voltage; The output buffer circuit is configured to output the plurality of driving voltages to a plurality of sub-pixel units in a pixel unit array circuit through a plurality of source lines, and drive the plurality of sub-pixel units to emit light; The polarity control circuit is configured to determine a target compensation mode according to a circuit connection mode of each sub-pixel unit in the pixel unit array circuit, and convert a polarity of an offset voltage of a target amplifier according to the target compensation mode; wherein a plurality of different circuit connection modes correspond to at least one target compensation mode; The polarity control circuit is further configured to determine the circuit connection mode of each sub-pixel unit in the pixel unit array circuit according to the driving voltage output by the output buffer circuit to each source line in a case where the input image is a preset image; The polarity control circuit is configured to determine a target compensation mode according to a circuit connection mode of each sub-pixel unit in a pixel unit array circuit, comprising: In a case where the circuit connection mode of each sub-pixel unit in the pixel unit array circuit is that sub-pixel units located in the same column in the pixel unit array circuit are electrically connected through the same source line, sub-pixel units located in the same row are electrically connected through the same gate line, or in a case where the circuit connection mode of each sub-pixel unit in the pixel unit array circuit is that sub-pixel units located in adjacent two columns are electrically connected through the same source line, and in any row of sub-pixel units, sub-pixel units located in odd-numbered columns and sub-pixel units located in even-numbered columns are electrically connected through different gate lines, the polarity control circuit determines that the target compensation mode is a first compensation mode; wherein the first compensation mode is to make the polarities of the offset voltages of the target amplifiers corresponding to adjacent two rows of sub-pixel units in the pixel unit array circuit opposite; or, In a case where the circuit connection mode of each sub-pixel unit in the pixel unit array circuit is that in the same column of sub-pixel units, sub-pixel units located in odd-numbered columns are electrically connected through the same source line, sub-pixel units located in even-numbered columns are electrically connected through the same source line, and sub-pixel units located in the same row are electrically connected through the same gate line, the polarity control circuit determines that the target compensation mode is a second compensation mode. The second compensation mode is that, in the case that the sub-pixel units in adjacent two rows are taken as a group and there is no repeated sub-pixel unit in any two groups, the polarities of the offset voltages of the target amplifiers corresponding to the two rows of sub-pixel units in each group are opposite, and the polarity of the offset voltage of the target amplifier corresponding to the sub-pixel unit in the first row in each odd group is opposite to the polarity of the offset voltage of the target amplifier corresponding to the sub-pixel unit in the first row in each even group. The circuit connection mode of each sub-pixel unit in the pixel unit array circuit is that the sub-pixel units in adjacent two columns are electrically connected through the same source line, and in any one row of sub-pixel units, the sub-pixel units in the odd columns and the sub-pixel units in the even columns are electrically connected through different gate lines. The third compensation mode is that, in the case that the sub-pixel units in adjacent two rows are taken as a group and there is no repeated sub-pixel unit in any two groups, the polarities of the offset voltages of the target amplifiers corresponding to the two rows of sub-pixel units in each group are the same, and the polarity of the offset voltage of the target amplifier corresponding to the sub-pixel unit in each odd group is opposite to the polarity of the offset voltage of the target amplifier corresponding to the sub-pixel unit in each even group.

2. The drive circuit according to claim 1, characterized in that, The target amplifier is an amplifier used for generating the gray-scale voltage in the gray-scale voltage generation circuit and / or an amplifier used for outputting the driving voltage in the output buffer circuit.

3. The drive circuit according to claim 1, characterized by The driving voltage generation circuit comprises: a driving control unit electrically connected with the polarity control circuit, configured to generate and output a row synchronization signal, a field synchronization signal, a data driving signal and a scanning driving signal according to the input image; a data driving unit electrically connected with the driving control unit and the gray-scale voltage generation circuit, configured to receive the gray-scale voltage output by the gray-scale voltage generation circuit and the row synchronization signal, the field synchronization signal, the data driving signal and the scanning driving signal output by the driving control unit, generate at least one driving voltage according to the row synchronization signal, the field synchronization signal, the data driving signal, the scanning driving signal and the gray-scale voltage, and output the at least one driving voltage to the corresponding at least one sub-pixel unit according to the row synchronization signal, the field synchronization signal and the scanning driving signal.

4. The drive circuit according to claim 3, characterized in that, The driving control unit is electrically connected with the polarity control circuit, and is configured to output the generated data driving signal to the polarity control circuit in the case that the input image is a preset image. The polarity control circuit is further configured to determine the circuit connection mode of each sub-pixel unit in the pixel unit array circuit according to the data driving signal.

5. The drive circuit according to claim 1 or 4, characterized in that, When the display panel displays the preset image, only the sub-pixel units corresponding to red in the pixel unit array circuit are lit, and / or only the sub-pixel units corresponding to blue in the pixel unit array circuit are lit, and / or only the sub-pixel units corresponding to green in the pixel unit array circuit are lit, and / or only the sub-pixel units corresponding to the odd or even rows in the pixel unit array circuit are lit, and / or the gray scale value corresponding to each sub-pixel unit in the pixel unit array circuit is different from the gray scale value corresponding to any adjacent sub-pixel unit.

6. A display device, characterized by comprising: The display device comprises a plurality of display units and at least one driving circuit of the display panel according to claims 1-5.

7. The display device of claim 6, wherein, The display unit comprises a display panel, and the display panel comprises at least one of a liquid crystal display panel, a micro light-emitting diode display panel, a light-emitting diode display panel, a mini light-emitting diode display panel, a quantum dot light-emitting diode display panel, an organic light-emitting diode display panel, a cathode ray tube display panel, a digital light processing display panel, a field emission display panel, a plasma display panel, an electrophoretic display panel, an electrowetting display panel, and a small-pitch display panel.

8. An electronic device, comprising: The electronic device comprises the display device according to claim 6 or 7.

9. A driver chip, characterized by comprising: The driving chip comprises the driving circuit of the display panel according to any one of claims 1-5.

Images