Semiconductor test cell fabrication method and bit line contact structure resistance test method

Abstract

The present disclosure provides a semiconductor test unit manufacturing method and a bit line contact structure resistance testing method. The semiconductor test unit manufacturing method comprises: manufacturing a plurality of active region groups in a scribe lane region, each active region group comprising a plurality of first active regions arranged along a first direction; performing one etching on the active region groups to form a plurality of test active regions, each test active region comprising two second active regions connected side by side along the first direction; manufacturing a plurality of bit line contact structures on the plurality of test active regions, each bit line contact structure connecting one second active region; forming a plurality of bit lines extending in a third direction on the plurality of bit line contact structures; and manufacturing a first test point and a second test point on adjacent two bit lines connecting the same test active region respectively, the first test point being close to a first end of one bit line, and the second test point being close to a second end of the other bit line. The embodiments of the present disclosure can accurately test the resistance of the bit line contact structure in the semiconductor circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular, to a semiconductor test unit manufacturing method, a semiconductor test circuit comprising the semiconductor test unit, and a bit line contact structure resistance testing method applied to the semiconductor test circuit. BACKGROUND

[0002] In the development process of DRAM (Dynamic Random Access Memory), the main method to increase the device integration is to reduce the feature size of the memory cell array device. Currently, the size of the bit line (BL) and the bit line contact structure (BLC) has been shrunk to the extent of 10 nm, which is the smallest feature size structure in the entire DRAM structure. The resistance of the BL bit line and the BLC bit line contact structure will affect the speed of data writing or reading from the DRAM cell, which is an important parameter to measure the performance of the DRAM bit line. Therefore, an on-line automatic detection mechanism must be established to determine the health of the resistance of the bit line contact structure (hereinafter referred to as the bit line contact structure resistance).

[0003] Therefore, how to accurately measure the bit line contact structure resistance of each memory cell has become a problem in the field.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The purpose of the present disclosure is to provide a semiconductor test unit manufacturing method, a semiconductor test circuit, and a bit line contact structure resistance testing method, which at least partially overcome the problem of inaccurate testing of the bit line contact structure resistance of the memory cell due to the limitations and defects of the related art.

[0006] According to a first aspect of this disclosure, a method for manufacturing a semiconductor test cell is provided, comprising: fabricating a plurality of active region groups in a dicing region, each active region group including a plurality of first active regions arranged and connected along a first direction, the plurality of active region groups being arranged along a second direction perpendicular to the first direction; etching the active region groups once to form a plurality of test active regions, each test active region including two second active regions arranged side-by-side along the first direction, the second active regions being formed by etching an edge of the first active regions extending in the second direction; fabricating a plurality of bit line contact structures on the plurality of test active regions, each bit line contact structure connecting one second active region; forming a plurality of bit lines extending parallel to a third direction on the plurality of bit line contact structures, the third direction having a first angle with the first direction, each bit line having a first end and a second end; fabricating a first test point and a second test point on two adjacent bit lines connecting the same test active region, the first test point being close to the first end of one bit line, and the second test point being close to the second end of the other bit line.

[0007] In an exemplary embodiment of this disclosure, the step of fabricating multiple bit line contact structures on the plurality of test active regions includes: sequentially fabricating a first mask layer and a second mask layer on the test active regions to form a plurality of target regions, each target region corresponding to the center of a second active region; and fabricating bit line contact structures corresponding to the second active regions in the target regions.

[0008] In one exemplary embodiment of this disclosure, the first mask layer includes a plurality of first rectangular regions arranged in an array, and the second mask layer includes a plurality of second rectangular regions arranged in an array, wherein the first rectangular regions and the second rectangular regions are staggered.

[0009] In an exemplary embodiment of this disclosure, the first rectangular regions are arranged in a row along a third direction with a first gap, and multiple rows of the first rectangular regions are arranged in a fourth direction with a second gap to form the first mask layer; the second rectangular regions are arranged in a row along the third direction with a third gap, and multiple rows of the second rectangular regions are arranged in a fourth direction with a fourth gap to form the second mask layer; the target region is the intersection of the first gap and the fourth gap, or the target region is the intersection of the second gap and the third gap.

[0010] In one exemplary embodiment of this disclosure, two adjacent test active regions in the second direction have a first displacement in the first direction.

[0011] In one exemplary embodiment of this disclosure, the first included angle is less than 90°.

[0012] In one exemplary embodiment of this disclosure, the method further includes: forming a first contact pad connecting the first test point at the first end of the bit line, and forming a second contact pad connecting the second test point at the second end of the bit line.

[0013] In one exemplary embodiment of this disclosure, the first contact pad connects to the first test point of a plurality of semiconductor test units arranged in a fourth direction, and the second contact pad connects to the second test point of the plurality of semiconductor test units.

[0014] In one exemplary embodiment of this disclosure, the height of the first test point and the height of the second test point are equal, and the height of the first test point is higher than the height of the bit line. The step of forming a first contact pad connecting the first test point at the first end of the bit line and forming a second contact pad connecting the second test point at the second end of the bit line includes: forming a third mask layer above the bit line, the third mask layer including a first region and a second region, the first region exposing the first test point and the second test point; depositing metal in the first region of the third mask layer to form the first contact pad and the second contact pad.

[0015] According to a second aspect of this disclosure, a semiconductor test circuit is provided, disposed in a dicing region, comprising one or more semiconductor test units, each semiconductor test unit comprising: one or more test active regions disposed in parallel, each test active region comprising two second active regions connected in parallel along a first direction, one second active region being provided with a first bit line contact structure, and the other second active region being provided with a second bit line contact structure; a first bit line extending along a third direction and connecting the first bit line contact structure in the one or more test active regions, the third direction having a first angle with the first direction; a second bit line extending along the third direction and connecting the second bit line contact structure in the one or more test active regions, the first bit line having a first end and a second end, and the second bit line having a first end and a second end; a first test point near the first end of the first bit line; and a second test point near the second end of the second bit line.

[0016] In one exemplary embodiment of this disclosure, the first included angle is less than 90°.

[0017] In one exemplary embodiment of this disclosure, in one of the test active regions, the first bit line contact structure is located in the middle of one of the second active regions, and the second bit line contact structure is located in the middle of another of the second active regions.

[0018] In one exemplary embodiment of this disclosure, the plurality of semiconductor test units are arranged along a fourth direction, the fourth direction being perpendicular to the first bit line. The semiconductor test circuit further includes: a first contact pad connecting the first test point of the one or more semiconductor test units; and a second contact pad connecting the second test point of the one or more semiconductor test units.

[0019] According to a third aspect of this disclosure, a method for testing the resistance of a bit line contact structure is provided, applied to a semiconductor test circuit as described in any of the preceding claims, comprising: determining a first number of semiconductor test units connected between a first contact pad and a second contact pad; determining a second number of test active regions connected by a first bit line and a second bit line between a first test point and a second test point in each of the semiconductor test units, and the resistance of each second active region in the test active regions; obtaining a measured resistance between the first contact pad and the second contact pad; and determining the bit line contact structure resistance using the following formula: Among them, R BLC The resistance of the bit line contact structure is n, where n is the first quantity, m is the second quantity, and R is the resistance of the bit line contact structure. t The measured resistance, R AA It is the resistance of the second active region.

[0020] This embodiment of the present disclosure performs only one etching on the active region array of the cut channel region, so that the two adjacent active regions connected by the two adjacent bit lines are directly connected. When testing the resistance of the memory cell connected by the two adjacent bit lines, it can avoid the resistance test result caused by the gap between the independent active regions being too large, and can improve the accuracy of measuring the resistance of the bit line contact structure of the memory cell.

[0021] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0022] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0023] Figure 1 This is a flowchart of a semiconductor test cell manufacturing method in an exemplary embodiment of this disclosure.

[0024] Figure 2 This is a schematic diagram of an active region group in one embodiment of this disclosure.

[0025] Figure 3This is a schematic diagram of testing an active region in one embodiment of this disclosure.

[0026] Figure 4 This is a schematic diagram of the mid-line contact structure in one embodiment of the present disclosure.

[0027] Figure 5 This is a schematic diagram of determining the target region for fabricating the bit line contact structure in one embodiment of this disclosure.

[0028] Figure 6 This is a schematic diagram of fabricating a bit line contact structure in a target region in one embodiment of the present disclosure.

[0029] Figure 7 This is a schematic diagram of the connection between the bit line contact structure and the bit line in one embodiment of this disclosure.

[0030] Figure 8 This is a schematic diagram showing the connection relationship between multiple bit lines BL and the active region AA as viewed from the first and second directions.

[0031] Figure 9A This is a schematic diagram of test points shown in one embodiment of the present disclosure, with reference to a third direction and a fourth direction.

[0032] Figure 9B This is a schematic diagram of test points shown in one embodiment of the present disclosure, with a first direction and a second direction as references.

[0033] Figure 10 This is a schematic diagram of a semiconductor test circuit in one embodiment of the present disclosure.

[0034] Figure 11 This is a schematic diagram of a semiconductor test circuit including a semiconductor test unit in an embodiment of this disclosure.

[0035] Figure 12 This is a schematic diagram of a semiconductor test circuit including multiple semiconductor test units in an embodiment of this disclosure.

[0036] Figure 13 This is a flowchart of the bit line contact structure resistance testing method provided in the embodiments of this disclosure. Detailed Implementation

[0037] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more of the specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0038] Furthermore, the accompanying drawings are merely illustrative of this disclosure, and the same reference numerals in the drawings denote the same or similar parts, thus repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0039] The exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0040] Figure 1 This is a flowchart of a semiconductor test cell manufacturing method in an exemplary embodiment of this disclosure.

[0041] refer to Figure 1 The semiconductor test cell manufacturing method 100 may include:

[0042] Step S1: Create multiple active area groups in the cutting channel area. Each active area group includes multiple first active areas connected along a first direction. The multiple active area groups are arranged along a second direction, which is perpendicular to the first direction.

[0043] Step S2: Etch the active region group once to form multiple test active regions. Each test active region includes two second active regions connected in parallel along the first direction. The second active regions are formed by etching an edge of the first active region extending in the second direction.

[0044] Step S3: Fabricate multiple bit line contact structures on multiple test active regions, with each bit line contact structure connected to a second active region;

[0045] Step S4: Multiple bit lines extending parallel to a third direction are formed on multiple bit line contact structures. The third direction has a first angle with the first direction. Each bit line has a first end and a second end.

[0046] Step S5: Create a first test point and a second test point on two adjacent bit lines that connect the same active test region. The first test point is close to the first end of one bit line, and the second test point is close to the second end of the other bit line.

[0047] In related technologies, the common method for testing the bit line contact structure resistance is to measure the resistance between two adjacent bit lines, and then determine the bit line contact structure resistance of each memory cell based on the number of memory cells connected in parallel between the two bit lines. However, since each memory cell is connected to only one bit line, and adjacent bit lines are connected to transistors of different memory cells, the resistance between the transistors can significantly affect the accuracy of the bit line contact structure resistance measurement. This disclosure embodiment uses... Figure 1 The method shown manufactures as follows Figure 2 The semiconductor test unit shown in Figure 9 can avoid the influence of the resistance between transistors on the measurement of the bit line contact structure resistance.

[0048] Figure 2 Figure 9 is based on Figure 1 The diagram shows a method for manufacturing a semiconductor test cell.

[0049] Figure 2 This is a schematic diagram of an active region group in one embodiment of this disclosure.

[0050] refer to Figure 2 In step S1, multiple active area groups 1 are created in the cutting channel area. Each active area group 1 includes multiple first active areas AA arranged along a first direction. The multiple active area groups 1 are arranged along a second direction, which is perpendicular to the first direction.

[0051] Figure 3 This is a schematic diagram of testing an active region in one embodiment of this disclosure.

[0052] refer to Figure 3 In step S2, the active region group 1 is etched once to form a plurality of test active regions 2, each test active region 2 including two second active regions 21 arranged side by side along a first direction.

[0053] In one embodiment of this disclosure, two adjacent test active regions 2 in the second direction have a first displacement D in the first direction. A plurality of adjacent second active regions 21 in the second direction are all connected to a single bit line. The first displacement D increases the spacing between adjacent bit lines and the distance between bit line contact structures between adjacent second active regions 21 in the second direction, preventing memory failures due to excessively close bit line contact structures after increased integration density.

[0054] Figure 4 This is a schematic diagram of the mid-line contact structure in one embodiment of the present disclosure.

[0055] refer to Figure 4 In step S3, multiple bit line contact structures 22 are fabricated on multiple test active regions 2, each bit line contact structure 22 connecting to a second active region 21. The projection of the bit line contact structure 22 (BLC) corresponds to the position of the transistor drain in the second active region 21. Figure 4 In the illustrated embodiment, one second active region 21 corresponds to two transistors, and the middle part of the second active region 21 is a drain region shared by the two transistors. The bit line contact structure 22 is located in the middle of the second active region 21. In other embodiments, when the transistor arrangement is... Figure 4 As shown, the bit line contact structure 22 can also be located at other positions in the second active region 21.

[0056] In one embodiment, step S3 may include: sequentially fabricating a first mask layer and a second mask layer on the test active region 2 to form a plurality of target regions, each target region corresponding to the middle of a second active region 21, and then fabricating a bit line contact structure 22 corresponding to the second active region in the target region.

[0057] Figure 5 and Figure 6 This is a schematic diagram illustrating the process of fabricating a bit line contact structure in one embodiment of this disclosure.

[0058] Figure 5 This is a schematic diagram of determining the target region for fabricating the bit line contact structure in one embodiment of this disclosure.

[0059] refer to Figure 5 To better illustrate the connection between the bit line and the active region, Figure 5 The second active region 21 is rotated by a first angle (equal to the first angle α between the third direction and the first direction) and displayed.

[0060] exist Figure 5 In the illustrated embodiment, the first mask layer includes a plurality of first rectangular regions 51 arranged in an array, and the second mask layer includes a plurality of second rectangular regions 52 arranged in an array, with the first rectangular regions 51 and the second rectangular regions 52 being staggered.

[0061] In one embodiment, the first rectangular regions 51 are arranged in a row along a third direction with a first gap d1, and multiple rows of the first rectangular regions 51 are arranged along a fourth direction with a second gap d2 to form a first mask layer; the second rectangular regions 52 are arranged in a row along a third direction with a third gap d3, and multiple rows of the second rectangular regions are arranged along a fourth direction with a fourth gap d4 to form a second mask layer; the target region 53 is the intersection of the first gap d1 and the fourth gap d4, or the target region is the intersection of the second gap d2 and the third gap d3.

[0062] In one embodiment of this disclosure, the third direction has a first angle α with the first direction, and the fourth direction is perpendicular to the third direction. The first angle may be, for example, less than 90°.

[0063] The first and second mask layers are used to position the target area 53, thereby providing positioning assistance for the subsequent fabrication of the bitline contact structure 22 within the target area 53. Although Figure 5 The target area 53 formed by positioning through the first mask layer and the second mask layer is rectangular. However, in other embodiments of this disclosure, other mask shapes may be used to position target areas 53 of different shapes. For example, the target area 53 may be positioned as a circle or a parallelogram, or other methods may be used to determine the target area 53 for fabricating the bit line contact structure 22. This disclosure does not impose any special limitations on this.

[0064] Figure 6 This is a schematic diagram of fabricating a bit line contact structure in a target region in one embodiment of the present disclosure.

[0065] After forming the target region 53, a bit line contact structure 22 can be fabricated within the target region 53 to form a structure such as Figure 6 The bit line contact structure 22 is shown.

[0066] Figure 7 This is a schematic diagram of the connection between the bit line contact structure and the bit line in one embodiment of this disclosure.

[0067] refer to Figure 7 In step S4, multiple bit lines BL are formed on the multiple bit line contact structures 22, extending parallel to the third direction. Each bit line BL has a first end and a second end, and each bit line BL is connected to the multiple bit line contact structures 22 arranged in the third direction.

[0068] Figure 8 This is a schematic diagram showing the connection relationship between multiple bit lines BL and the second active region 21 as viewed from the first and second directions.

[0069] Next, test points (Periphery contacts) can be set on two adjacent bit lines to measure the bit line contact structure resistance of multiple second active regions 21 between two adjacent bit lines.

[0070] Figure 9A This is a schematic diagram of test points shown in one embodiment of the present disclosure, with reference to a third direction and a fourth direction.

[0071] Figure 9B This is a schematic diagram of test points shown in one embodiment of the present disclosure, with a first direction and a second direction as references.

[0072] Also refer to Figure 9A and Figure 9B In step S5, a first test point 93 and a second test point 94 are respectively fabricated on two adjacent bit lines (bit line 91 and bit line 92) that connect the same test active region 2. The first test point 93 is close to the first end of bit line 91, and the second test point 94 is close to the second end of bit line 92. The specific positions of the first end and the second end can be defined by those skilled in the art.

[0073] Through steps S1 to S5, the semiconductor test circuit provided in the embodiments of this disclosure can be formed.

[0074] Figure 10 This is a schematic diagram of a semiconductor test circuit in one embodiment of the present disclosure.

[0075] refer to Figure 10 The semiconductor test circuit 1000 is disposed in the dicing area of ​​the wafer, and includes:

[0076] One or more semiconductor test units 101, each semiconductor test unit 101 includes one or more test active regions 2 arranged in parallel, each test active region 2 includes two second active regions 21 connected in parallel along a first direction, one second active region 21 is provided with a first bit line contact structure 221, and the other second active region 21 is provided with a second bit line contact structure 222.

[0077] The first line 91 extends along a third direction and connects to the first line contact structure 221 in one or more test active regions 2. The third direction has a first angle α with the first direction. The first line 91 has a first end and a second end.

[0078] The second bit line 92 extends along a third direction and connects to the second bit line contact structure 222 in one or more test active regions 2. The second bit line 92 has a first end and a second end.

[0079] The first test point 93 is located near the first end of the first line 91.

[0080] The second test point 94 is located near the second end of the second bit line 92.

[0081] In one embodiment of this disclosure, the first included angle is less than 90°.

[0082] Figure 10 The second active region 21 shown is Figure 3 The second active regions 21 shown are the same area. In one embodiment of this disclosure, the second active regions 21 are all rectangular. In a test active region 2, the first bit line contact structure 221 is located in the middle of one second active region 21, and the second bit line contact structure 222 is located in the middle of another second active region 21.

[0083] The first bit line 91, the second bit line 92, the first test point 93, and the second test point 94 together constitute a semiconductor test unit 101. N test active regions 2 are connected in parallel between the two bit lines of the semiconductor test unit 101. Figure 10 In the illustrated embodiment, the semiconductor test circuit 1000 includes two semiconductor test units 101. Each semiconductor test unit 101 has three active test regions 2 connected in parallel between its first test point 93 and second test point 94. Each active test region 2 includes two second active regions 21, which are connected to the first bit line 91 and the second bit line 92 via a first bit line contact structure 221 and a second bit line contact structure 222, respectively.

[0084] When testing a semiconductor test unit 101, the parallel resistance of the N test active regions can be measured by testing the resistance between the first test point 93 and the second test point 94. Then, based on the number of test active regions and the resistance of the second active region in each test active region, the resistance of the bit line contact structure in each test active region can be calculated.

[0085] In one embodiment, a first contact pad connecting to a first test point 93 may be formed at the first end of the first bit line 91 and the second bit line 92, and a second contact pad connecting to a second test point 94 may be formed at the second end of the first bit line 91 and the second bit line 92, thereby forming a semiconductor test circuit provided in this embodiment of the present disclosure.

[0086] In one embodiment of this disclosure, the height of the first test point 93 and the height of the second test point 94 are equal, and the height of the first test point 93 is higher than the height of the first line 91, such as... Figure 11As shown, during the process of forming a first contact pad 111 connecting the first test point 93 at the first end of the first bit line 91 and a second contact pad 112 connecting the second test point 94 at the second end of the second bit line 92, a third mask layer (not shown) can be formed first above the first bit line 91 and the second bit line 92. The third mask layer includes a first region and a second region. The first region exposes the first test point and the second test point, and the second region covers other parts of the circuit. Then, metal is deposited in the first region of the third mask layer to form the first contact pad and the second contact pad. The type of metal deposited can be, for example, tungsten, and this disclosure does not impose any particular limitation on it. After the metal is deposited, CMP (Chemical Mechanical Polishing) is performed on the first contact pad and the second contact pad, and then the aforementioned second region covering other areas of the circuit in the third mask layer is removed, completing the fabrication of the first contact pad and the second contact pad. An exemplary shape of the first contact pad and the second contact pad is, for example, Figure 11 and Figure 12 As shown.

[0087] Figure 11 This is a schematic diagram of a semiconductor test circuit including a semiconductor test unit in an embodiment of this disclosure.

[0088] Figure 12 This is a schematic diagram of a semiconductor test circuit including multiple semiconductor test units in an embodiment of this disclosure.

[0089] refer to Figure 11 and Figure 12 In one embodiment of this disclosure, a plurality of semiconductor test units 101 are arranged along a fourth direction, which is perpendicular to the first line 91. A first contact pad 111 is connected to a first test point 93 of one or more semiconductor test units 101, and a second contact pad 112 is connected to a second test point 94 of one or more semiconductor test units 101.

[0090] exist Figure 11 In the embodiment shown, the first contact pad 111 is connected to the first test point 93 of a semiconductor test unit 101, and the second contact pad 112 is connected to the second test point 94 of the semiconductor test unit 101.

[0091] exist Figure 12 In the embodiment shown, the first contact pad 111 connects to the first test point 93 of the plurality of semiconductor test units 101, and the second contact pad 112 connects to the second test point 94 of the plurality of semiconductor test units 101.

[0092] Figure 11 and Figure 12The shapes of the first contact pad 111 and the second contact pad 112 shown are merely examples. In other embodiments of this disclosure, the first contact pad 111 and the second contact pad 112 may be other shapes.

[0093] The resistance of each bit line contact structure can be obtained by testing the resistance between the first contact pad 111 and the second contact pad 112.

[0094] Figure 13 This is a flowchart of the bit line contact structure resistance testing method provided in the embodiments of this disclosure.

[0095] Figure 13 The method shown can be used for testing. Figure 11 or Figure 12 The circuit shown contains a bit-line contact structure resistor.

[0096] refer to Figure 13 ,right Figure 11 or Figure 12 The semiconductor test circuit shown in the figure is used to determine the bit line contact structure resistance corresponding to each second active region. Test method 1300 may include:

[0097] Step S131: Determine the first number n of semiconductor test units 101 connected between the first contact pad and the second contact pad;

[0098] Step S132: Determine the second number m of the active test regions 2 connected by the first bit line 91 and the second bit line 92 between the first test point 93 and the second test point 94 in each semiconductor test unit 101, and the resistance R of each second active region 21 in the active test region 2. AA ;

[0099] Step S133: Obtain the measured resistance R between the first contact pad 111 and the second contact pad 112. t ;

[0100] Step S134: Determine the resistance R of the bit line contact structure using formula (1). BLC :

[0101]

[0102] Among them, R BLC This refers to the line contact structure resistance, where n is the first quantity, m is the second quantity, and R is the resistance. t It is the measured resistance, R AA It is the resistor of the second active region 21.

[0103] Specifically, step S134 can be described as determining the bit line contact structure resistance of each second active region 21 based on half of the difference between the product of the first quantity, the second quantity, and the measured resistance and the resistance of the second active region 21.

[0104] For example, in Figure 11 In the illustrated embodiment, three active test regions are connected in parallel between the first contact pad 111 and the second contact pad 112. A test probe flows out through the first contact pad 111, the first test point 93, and the first bit line 91, then simultaneously enters the first bit line contact structure 221 of the three active test regions 2. In each active test region 2, the current sequentially enters two second active regions 21 from the first bit line contact structure 221, then enters the second bit line 92 via the second bit line contact structure 222, and finally reaches the second contact pad 112 through the second test point 94 and flows into another test probe. Here, a 2R is formed in each active test region 2. BLC +R AA The equivalent resistance (the total length of the second active region 21 between the first line contact structure 221 and the second line contact structure 222 through which the test current flows in the test active region is the length of one second active region 21), and m of these equivalent resistances are connected in parallel to form the measured resistance R between the first contact pad 111 and the second contact pad 112. t .exist Figure 11 In the embodiment shown, a semiconductor test unit 101 is connected between the first contact pad 111 and the second contact pad 112, n=1, thereby the resistance of the midline contact structure in each second active region 21 can be obtained according to formula (1).

[0105] exist Figure 12 In the illustrated embodiment, multiple semiconductor test units 101 are connected in parallel between the first contact pad 111 and the second contact pad 112. Therefore, the measured resistance R between the first contact pad 111 and the second contact pad 112 is... t For the parallel resistance of multiple semiconductor test units 101, it is only necessary to substitute the number n of the parallel semiconductor test units 101 into formula (1). Figure 12 (where n=4), that is, based on the measured resistance R between the first contact pad 111 and the second contact pad 112. t The resistance of the midline contact structure in each second active region 21 is obtained.

[0106] Since the two second active regions 21 being measured in this embodiment are directly connected, the resistance R of the second active region 21 is used. AA The calculations are not affected by the gaps between active regions, resulting in more accurate measurement and calculation results. This effectively overcomes the problem of inaccurate resistance measurement in related technologies.

[0107] This disclosure also provides a memory circuit and a chip including the semiconductor test circuit described in the above embodiments. It is understood that the semiconductor test circuit, memory circuit, and chip provided by this disclosure can more accurately measure the resistance of the bit line contact structure. In the context of technological advancements leading to smaller component sizes and increased component density, this enables more accurate monitoring of potential faults during the manufacturing process, effectively improving the yield rate of chip products and providing strong technical support for the development of integrated circuit technology.

[0108] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0109] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and concept of this disclosure are indicated by the claims.

Claims

1. A method of manufacturing a semiconductor test unit, characterized by, The method comprises: forming a plurality of active region groups in a scribe lane region, each of the active region groups comprising a plurality of first active regions connected in a first direction, the plurality of active region groups being arranged in a second direction perpendicular to the first direction; performing one etching on the active region groups to form a plurality of test active regions, each of the test active regions comprising two second active regions connected side by side in the first direction, the second active regions being formed by etching one edge of the first active regions extending in the second direction; forming a plurality of bit line contact structures on the plurality of test active regions, each of the bit line contact structures connecting one of the second active regions; forming a plurality of bit lines extending in a third direction on the plurality of bit line contact structures, the third direction having a first included angle with the first direction, each of the bit lines having a first end and a second end; forming a first test point and a second test point on two adjacent bit lines connecting the same test active region respectively, the first test point being close to the first end of one of the bit lines, and the second test point being close to the second end of the other bit line.

2. The method of claim 1, wherein the semiconductor test unit is a semiconductor test unit for testing a semiconductor device. The forming a plurality of bit line contact structures on the plurality of test active regions comprises: sequentially forming a first mask layer and a second mask layer on the test active regions to form a plurality of target regions, each of the target regions corresponding to a middle part of one of the second active regions; forming a bit line contact structure corresponding to the second active region in the target region.

3. The method of claim 2, wherein the semiconductor test cell is formed by a process comprising: The first mask layer comprises a plurality of first rectangular regions arranged in an array, and the second mask layer comprises a plurality of second rectangular regions arranged in an array, the first rectangular regions and the second rectangular regions being staggered.

4. The method of claim 3, wherein the semiconductor test unit is a semiconductor test unit for testing a semiconductor device. The first rectangular regions are arranged in a row with a first gap in a third direction, and a plurality of rows of the first rectangular regions are arranged in a second direction with a second gap to form the first mask layer; the second rectangular regions are arranged in a row with a third gap in the third direction, and a plurality of rows of the second rectangular regions are arranged in the second direction with a fourth gap to form the second mask layer, the target region being an intersection of the first gap and the fourth gap, or the target region being an intersection of the second gap and the third gap.

5. The method of claim 1, wherein the semiconductor test cell is manufactured by a method comprising: Two adjacent test active regions in the second direction have a first displacement in the first direction. ​ 6. The method of claim 1, wherein the semiconductor test cell is manufactured by: The first included angle is less than 90°.

7. The method of claim 1, wherein the semiconductor test cell is a semiconductor test cell for testing a semiconductor device. The method further comprises: forming a first contact pad connecting the first test point at the first end of the bit line, and forming a second contact pad connecting the second test point at the second end of the bit line.

8. The method of claim 7, wherein the semiconductor test cell is manufactured by: The first contact pad connects the first test points of a plurality of semiconductor test units arranged in a fourth direction, and the second contact pad connects the second test points of the plurality of semiconductor test units.

9. The method of manufacturing a semiconductor test unit according to claim 7 or 8, wherein, The height of the first test point is equal to the height of the second test point, and the height of the first test point is higher than the height of the bit line, and the forming a first contact pad connecting the first test point at the first end of the bit line and a second contact pad connecting the second test point at the second end of the bit line comprises: forming a third mask layer above the bit lines, the third mask layer comprising a first region and a second region, the first region exposing the first test point and the second test point; depositing a metal in the first region of the third mask layer to form the first contact pad and the second contact pad.

10. A semiconductor test circuit, characterized by, The semiconductor test circuit comprises: one or more test active regions arranged in parallel, each of the test active regions comprising two second active regions connected side by side along a first direction, one of the second active regions being provided with a first bit line contact structure and the other of the second active regions being provided with a second bit line contact structure; a first bit line extending along a third direction and connecting the first bit line contact structures in the one or more test active regions, the third direction having a first included angle with the first direction; a second bit line extending along the third direction and connecting the second bit line contact structures in the one or more test active regions, the first bit line having a first end and a second end, and the second bit line having a first end and a second end; a first test point close to the first end of the first bit line; a second test point close to the second end of the second bit line.

11. The semiconductor test circuit of claim 10, wherein, The first included angle is less than 90°.

12. The semiconductor test circuit of claim 10, wherein, In one of the test active regions, the first bit line contact structure is located in a middle of one of the second active regions, and the second bit line contact structure is located in a middle of the other of the second active regions.

13. The semiconductor test circuit of claim 10, wherein, The plurality of semiconductor test units are arranged along a fourth direction perpendicular to the first bit line, and the semiconductor test circuit further comprises: a first contact pad connecting the first test points of the one or more semiconductor test units; a second contact pad connecting the second test points of the one or more semiconductor test units.

14. A bit line contact structure resistance test method, comprising: The semiconductor test circuit is applied to any one of claims 10-13, comprising: determining a first number of semiconductor test units connected between the first contact pad and the second contact pad; determining a second number of test active regions in each of the semiconductor test units, and a resistance of each of the second active regions in the test active regions, wherein the first number of semiconductor test units, the second number of test active regions, and the resistance of each of the second active regions are determined by: obtaining a measured resistance between the first contact pad and the second contact pad; determining a bit line contact structure resistance by the following formula: wherein R BLC is the resistance of the bit line contact structure, n is the first number, m is the second number, R t is the measured resistance, R AA is the resistance of the second active region.

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