Electrostatic discharge protection device

Abstract

This invention discloses an electrostatic discharge protection device, comprising an N-type semiconductor substrate, a P-type semiconductor layer, a first N-type well region, a P-type well region, a second N-type well region, a first heavily doped P-type well region, a first heavily doped N-type well region, and a second heavily doped P-type well region. The semiconductor layer is disposed on the substrate, and the well regions are disposed within the semiconductor layer. The second N-type well region directly contacts the substrate, and the first heavily doped P-type well region is disposed within the first N-type well region. The first heavily doped N-type well region and the second heavily doped P-type well region are disposed within the P-type well region, and the second heavily doped P-type well region is coupled to the second N-type well region via an external wire. The second heavily doped P-type well region can be replaced by a second heavily doped N-type well region.

Description

Technical Field

[0001] This invention relates to a protective device, and more particularly to an electrostatic discharge protection device. Background Technology

[0002] Electrostatic discharge (ESD) damage has become a major reliability issue for CMOS integrated circuit (IC) products manufactured using nanoscale complementary metal-oxide-semiconductor (CMOS) processes. ESD protection devices are typically designed to release ESD energy, thus preventing ESD damage to integrated circuit chips.

[0003] The working principle of electrostatic discharge protection device is as follows: Figure 1 As shown, on the integrated circuit chip, electrostatic discharge (ESD) protection device 1 is connected in parallel with the circuit 2 to be protected. When an ESD event occurs, ESD protection device 1 is triggered instantaneously. Simultaneously, ESD protection device 1 also provides a low-resistance path for the instantaneous ESD current to discharge, allowing the energy of the instantaneous ESD current to be released through ESD protection device 1. In US Patent No. 10896903B2, Figure 1 A semiconductor device is shown, comprising a lightly doped P-type anode region and an N-type cathode region. When an electrostatic discharge current flows from the cathode to the anode, both the lightly doped P-type anode region and the N-type cathode region exhibit high breakdown voltages. Therefore, the semiconductor device cannot be used in low-voltage applications. When an electrostatic discharge current flows from the anode to the cathode, the semiconductor device exhibits high clamping voltages due to the low doping concentrations of the lightly doped P-type anode region and the N-type cathode region. In US Patent No. 10923466B2, when a high voltage and a low voltage are coupled at a first pin and a second pin, respectively, an electrostatic discharge current flows through a parasitic NPN bipolar junction transistor. Due to the high hold-up voltage of this NPN bipolar junction transistor, the conducting bipolar junction transistor exhibits a high clamping voltage.

[0004] Therefore, the present invention addresses the aforementioned problems by proposing an electrostatic discharge protection device to solve the issues arising from the prior art. Summary of the Invention

[0005] The purpose of this invention is to provide an electrostatic discharge protection device having a low trigger-on voltage and a low clamping voltage, and for use in low-voltage applications.

[0006] In one embodiment of the present invention, an electrostatic discharge protection device is provided, comprising an N-type semiconductor substrate, a P-type semiconductor layer, a first N-type well region, a P-type well region, a second N-type well region, a first heavily doped P-type well region, a first heavily doped N-type well region, and a second heavily doped P-type well region. The P-type semiconductor layer is disposed on the N-type semiconductor substrate, and the first N-type well region, the P-type well region, and the second N-type well region are disposed within the P-type semiconductor layer, wherein the second N-type well region directly contacts the N-type semiconductor substrate. The first heavily doped P-type well region is disposed within the first N-type well region, and the first heavily doped N-type well region and the second heavily doped P-type well region are disposed within the P-type well region, wherein the second heavily doped P-type well region is coupled to the second N-type well region via an external wire.

[0007] In one embodiment of the present invention, the second N-type well region is an N-type heavily doped well region.

[0008] In one embodiment of the present invention, the electrostatic discharge protection device further includes an N-type heavily doped region disposed in the second N-type well region.

[0009] In one embodiment of the present invention, the electrostatic discharge protection device further includes a second N-type heavily doped region, which is disposed in the first N-type well region.

[0010] In one embodiment of the present invention, the first N-type heavily doped region, the first P-type heavily doped region and the second N-type heavily doped region are coupled to a first pin, and the N-type semiconductor substrate is coupled to a second pin.

[0011] In one embodiment of the present invention, a first P-type heavily doped region, a first N-type well region, a P-type semiconductor layer, and an N-type semiconductor substrate form a parasitic silicon controlled rectifier. The first N-type heavily doped region, the P-type well region, the P-type semiconductor layer, and the N-type semiconductor substrate form a parasitic bipolar junction transistor. When a positive electrostatic discharge voltage and a ground voltage are received at the first and second terminals respectively, the electrostatic discharge current flows from the first terminal through the parasitic silicon controlled rectifier and the parasitic bipolar junction transistor to the second terminal.

[0012] In one embodiment of the present invention, a parasitic diode is formed by a P-type well region, a first N-type heavily doped region, and a second P-type heavily doped region. When the first pin and the second pin receive a negative electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the second pin through the N-type semiconductor substrate, the second N-type well region, the external wire, and the parasitic diode to the first pin.

[0013] In one embodiment of the present invention, the first N-type heavily doped region, the first P-type heavily doped region and the second N-type heavily doped region are coupled to a first pin, and an external wire is coupled to a second pin.

[0014] In one embodiment of the present invention, a first P-type heavily doped region, a first N-type well region, a P-type semiconductor layer, an N-type semiconductor substrate, and a second N-type well region form a parasitic silicon controlled rectifier (SCR), and the first N-type heavily doped region, P-type well region, P-type semiconductor layer, N-type semiconductor substrate, and second N-type well region form a parasitic bipolar junction transistor (BJT). When the first pin and the second pin receive a positive electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the first pin through the parasitic SCR and the BJT to the second pin.

[0015] In one embodiment of the present invention, the P-type well region, the first N-type heavily doped region and the second P-type heavily doped region form a parasitic diode, and the electrostatic discharge current flows from the second pin through the external wire and the parasitic diode to the first pin.

[0016] In one embodiment of the present invention, the electrostatic discharge protection device further includes a third P-type heavily doped region disposed in the P-type well region, and the third P-type heavily doped region directly contacts the bottom of the first N-type heavily doped region.

[0017] In one embodiment of the present invention, an electrostatic discharge protection device is provided, comprising an N-type semiconductor substrate, a P-type semiconductor layer, a first N-type well region, a P-type well region, a second N-type well region, a first heavily doped P-type well region, a first heavily doped N-type well region, and a second heavily doped N-type well region. The P-type semiconductor layer is disposed on the N-type semiconductor substrate, and the first N-type well region, the P-type well region, and the second N-type well region are disposed within the P-type semiconductor layer, wherein the second N-type well region directly contacts the N-type semiconductor substrate. The first heavily doped P-type well region is disposed within the first N-type well region, and the first heavily doped N-type well region and the second heavily doped N-type well region are disposed within the P-type well region, wherein the second heavily doped N-type well region is coupled to the second N-type well region via an external wire.

[0018] In one embodiment of the present invention, the second N-type well region is an N-type heavily doped well region.

[0019] In one embodiment of the present invention, the electrostatic discharge protection device further includes an N-type heavily doped region disposed in the second N-type well region.

[0020] In one embodiment of the present invention, the electrostatic discharge protection device further includes a third N-type heavily doped region, which is disposed in the first N-type well region.

[0021] In one embodiment of the present invention, the first N-type heavily doped region, the first P-type heavily doped region and the third N-type heavily doped region are coupled to a first pin, and the N-type semiconductor substrate is coupled to a second pin.

[0022] In one embodiment of the present invention, a first P-type heavily doped region, a first N-type well region, a P-type semiconductor layer, and an N-type semiconductor substrate form a parasitic silicon controlled rectifier (SCR), and the first N-type heavily doped region, a P-type well region, a P-type semiconductor layer, and an N-type semiconductor substrate form a parasitic vertical bipolar junction transistor (PBT). When a positive electrostatic discharge voltage and a ground voltage are received at the first and second pins, respectively, the electrostatic discharge current flows from the first pin through the parasitic SCR and the PBT to the second pin.

[0023] In one embodiment of the present invention, a P-type well region, a first N-type heavily doped region, and a second N-type heavily doped region form a parasitic lateral bipolar junction transistor. When the first pin and the second pin receive a negative electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the second pin through the N-type semiconductor substrate, the second N-type well region, the external wire, and the parasitic lateral bipolar junction transistor to the first pin.

[0024] In one embodiment of the present invention, the first N-type heavily doped region, the first P-type heavily doped region and the third N-type heavily doped region are coupled to a first pin, and the external wire is coupled to a second pin.

[0025] In one embodiment of the present invention, a first P-type heavily doped region, a first N-type well region, a P-type semiconductor layer, an N-type semiconductor substrate, and a second N-type well region form a parasitic silicon controlled rectifier (SCR), and the first N-type heavily doped region, P-type well region, P-type semiconductor layer, N-type semiconductor substrate, and second N-type well region form a parasitic vertical bipolar junction transistor (PBT). When the first pin and the second pin respectively receive a positive electrostatic discharge voltage and a ground voltage, the electrostatic discharge current flows from the first pin through the parasitic SCR and the PBT to the second pin.

[0026] In one embodiment of the present invention, a P-type well region, a first heavily doped N-type region, and a second heavily doped N-type region form a parasitic lateral bipolar junction transistor. When the first pin and the second pin receive a negative electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the second pin through an external wire and the parasitic lateral bipolar junction transistor to the first pin.

[0027] In one embodiment of the present invention, the electrostatic discharge protection device further includes a second P-type heavily doped region disposed in the P-type well region, and the second P-type heavily doped region directly contacts the bottom of the first N-type heavily doped region.

[0028] In one embodiment of the present invention, the electrostatic discharge protection device further includes a third P-type heavily doped region disposed in the P-type well region, and the third P-type heavily doped region directly contacts the bottom of the second N-type heavily doped region.

[0029] Based on the above, electrostatic discharge (ESD) protection devices utilize a parasitic bipolar junction transistor (BJT) to facilitate the conduction of a parasitic silicon controlled rectifier (SCR), thereby reducing the trigger voltage and clamping voltage. The ESD protection device also incorporates a lateral diode or BJT to further reduce the clamping voltage. Therefore, ESD protection devices are used in low-voltage applications. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of an electrostatic discharge protection device for connecting an integrated circuit chip to a circuit to be protected, based on existing technology.

[0031] Figure 2 This is a structural cross-sectional view of the first embodiment of the electrostatic discharge protection device of the present invention.

[0032] Figure 3 This is a structural cross-sectional view of a second embodiment of the electrostatic discharge protection device of the present invention.

[0033] Figure 4 This is a structural cross-sectional view of the third embodiment of the electrostatic discharge protection device of the present invention.

[0034] Figure 5 This is a structural cross-sectional view of the fourth embodiment of the electrostatic discharge protection device of the present invention.

[0035] Figure 6 This is a structural cross-sectional view of the fifth embodiment of the electrostatic discharge protection device of the present invention.

[0036] Figure 7 This is a structural cross-sectional view of the sixth embodiment of the electrostatic discharge protection device of the present invention.

[0037] Figure 8 This is a structural cross-sectional view of the seventh embodiment of the electrostatic discharge protection device of the present invention.

[0038] Figure 9 This is a structural cross-sectional view of the eighth embodiment of the electrostatic discharge protection device of the present invention.

[0039] Figure reference numerals: 1-Electrostatic discharge protection device; 2-Circuit to be protected; 3-Electrostatic discharge protection device; 30-N-type semiconductor substrate; 31-P-type semiconductor layer; 32-First N-type well region; 33-P-type well region; 34-Second N-type well region; 340-Heavily doped N-type region; 35-First heavily doped P-type region; 36-First heavily doped N-type region; 37-Second heavily doped P-type region; 38-Second heavily doped N-type region; 39-Third heavily doped P-type region; 4-External conductor; 5-First pin; 6- Second pin; 7-Electrostatic discharge protection device; 70-N-type semiconductor substrate; 71-P-type semiconductor layer; 72-First N-type well region; 73-P-type well region; 74-Second N-type well region; 740-Heavily doped N-type region; 75-First heavily doped P-type region; 76-First heavily doped N-type region; 77-Second heavily doped N-type region; 78-Third heavily doped N-type region; 79-Second heavily doped P-type region; 79'-Third heavily doped P-type region; 4'-External conductor; 5'-First pin; 6'-Second pin. Detailed Implementation

[0040] Embodiments of the present invention will be further explained below with reference to the accompanying drawings. Wherever possible, the same reference numerals represent the same or similar components in the drawings and description. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It is understood that elements not specifically shown in the drawings or described in the description are forms known to those skilled in the art. Those skilled in the art can make various changes and modifications based on the content of this invention.

[0041] Unless otherwise specified, certain conditional clauses or words, such as "can," "could," "might," or "may," are generally intended to express features, elements, or steps that are present in the embodiments of this invention, but may also be interpreted as features, elements, or steps that may not be required. In other embodiments, these features, elements, or steps may be unnecessary.

[0042] In the following description of "one embodiment" or "an embodiment," the term refers to a specific element, structure, or feature associated with at least one embodiment. Therefore, the multiple descriptions of "one embodiment" or "an embodiment" appearing in various places below do not refer to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in a suitable manner.

[0043] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The word "comprising" in the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to". Furthermore, "coupled" here includes any direct and indirect connection means. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission or optical transmission, or indirectly electrically or signal connected to the second element through other elements or connection means.

[0044] This invention is described in particular by way of the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this invention. Therefore, the scope of protection of this invention is determined by the claims. Throughout the specification and claims, unless explicitly specified, the terms “a” and “described” include statements containing “a or at least one” of the stated elements or components. Furthermore, as used herein, the singular article also includes statements of a plurality of elements or components unless clearly excluded from the specific context. Moreover, when applied in this description and all the following claims, unless explicitly specified, “in which” can mean both “in which” and “therein”. The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meaning in the context of this invention and its specific application. Certain terms used to describe the invention will be discussed below or elsewhere in this specification to provide additional guidance to practitioners in describing the invention. Examples throughout this specification, including examples of any terms discussed herein, are for illustrative purposes only and do not limit the scope or meaning of the invention or any of the illustrative terms. Similarly, the invention is not limited to the various embodiments set forth in this specification.

[0045] The following description provides an electrostatic discharge (ESD) protection device that utilizes a parasitic bipolar junction transistor (BJT) to facilitate the conduction of a parasitic silicon controlled rectifier (SCR), thereby reducing a trigger-on voltage and a clamping voltage. The ESD protection device also incorporates a lateral diode or BJT to reduce the clamping voltage. Therefore, the ESD protection device is used in low-voltage applications.

[0046] Figure 2This is a structural cross-sectional view of the first embodiment of the electrostatic discharge protection device of the present invention. Please refer to [link / reference]. Figure 2 The following describes a first embodiment of the electrostatic discharge protection device 3 of the present invention. The first embodiment is a unidirectional electrostatic discharge protection device. The electrostatic discharge protection device 3 includes an N-type semiconductor substrate 30, a P-type semiconductor layer 31, a first N-type well region 32, a P-type well region 33, a second N-type well region 34, a first heavily doped P-type region 35, a first heavily doped N-type region 36, and a second heavily doped P-type region 37. The P-type semiconductor layer 31 is disposed on the N-type semiconductor substrate 30. The first N-type well region 32, the P-type well region 33, and the second N-type well region 34 are disposed within the P-type semiconductor layer 31. The second N-type well region 34 directly contacts the N-type semiconductor substrate 30, i.e., the second N-type well region 34 and the N-type semiconductor substrate 30 are structurally unstructured. The electrostatic discharge protection device 3 may further include a heavily doped N-type region 340 disposed within the second N-type well region 34 to form an ohmic contact. Alternatively, the second N-type well region 34 may be a heavily doped N-type well region to form an ohmic contact. A first heavily doped P-type region 35 is disposed in the first N-type well region 32. A first heavily doped N-type region 36 and a second heavily doped P-type region 37 are disposed in a P-type well region 33. The second heavily doped P-type region 37 is coupled to either the heavily doped N-type region 340 or the second N-type well region 34 via an external conductor 4. In some embodiments, the P-type well region 33 may be disposed between the first N-type well region 32 and the second N-type well region 34. To form an ohmic contact in the first N-type well region 32, the electrostatic discharge protection device 3 may further include a second heavily doped N-type region 38 disposed in the first N-type well region 32. The first heavily doped N-type region 36, the first heavily doped P-type region 35, and the second heavily doped N-type region 38 are coupled to a first pin 5, and the N-type semiconductor substrate 30 is coupled to a second pin 6.

[0047] A first P-type heavily doped region 35, a first N-type well region 32, a P-type semiconductor layer 31, and an N-type semiconductor substrate 30 form a parasitic silicon controlled rectifier (SCR). A first N-type heavily doped region 36, a P-type well region 33, a P-type semiconductor layer 31, and an N-type semiconductor substrate 30 form a parasitic bipolar junction transistor (BJT). The parasitic SCR and the BJT must share the same P-type semiconductor layer 31. When a positive electrostatic discharge (ESD) voltage and a ground voltage are received at the first pin 5 and the second pin 6, respectively, the ESD current flows from the first pin 5 through the parasitic SCR and the BJT to the second pin 6. Because the potential of the P-type semiconductor layer 31 rises due to the collapse of the junction between the first N-type heavily doped region 36 and the P-type well region 33, a forward bias is applied to the P-type semiconductor layer 31 and the N-type semiconductor substrate 30. The parasitic bipolar junction transistor (BJT) helps turn on the parasitic silicon controlled rectifier (SCR), thereby reducing the trigger and clamping voltages. It's important to note that because the trigger voltage of the BJT is lower than that of the SCR, the trigger voltage of the electrostatic discharge (ESD) protection device 3 depends on the trigger voltage of the BJT. Therefore, the ESD protection device 3 is suitable for low-voltage applications.

[0048] The P-type well region 33, the first heavily doped N-type region 36, and the second heavily doped P-type region 37 form a lateral parasitic diode. When the first pin 5 and the second pin 6 receive a negative electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the second pin 6 through the N-type semiconductor substrate 30, the second N-type well region 34, the heavily doped N-type region 340, the external conductor 4, and the parasitic diode to the first pin 5. The path of the parasitic diode has a low clamping voltage.

[0049] Figure 3 This is a structural cross-sectional view of a second embodiment of the electrostatic discharge protection device of the present invention. Please refer to [link / reference]. Figure 3The following describes a second embodiment of the electrostatic discharge protection device 3 of the present invention. The difference between the second and first embodiments is that the second embodiment further includes a third P-type heavily doped region 39, which is disposed in the P-type well region 33, and the third P-type heavily doped region 39 directly contacts the bottom of the first N-type heavily doped region 36. That is, there is no structure between the bottom of the third P-type heavily doped region 39 and the first N-type heavily doped region 36. The remaining features of the second embodiment have been described in the first embodiment and will not be repeated here. The collapse of the junction between the third P-type heavily doped region 39 and the first N-type heavily doped region 36 causes an increase in the potential of the P-type semiconductor layer 31, thus the third P-type heavily doped region 39 can further reduce the trigger voltage of the parasitic bipolar junction transistor. Therefore, a forward bias is applied to the P-type semiconductor layer 31 and the N-type semiconductor substrate 30. The parasitic bipolar junction transistor helps to turn on the parasitic silicon controlled rectifier, thereby reducing the trigger voltage and clamping voltage. It should be noted that because the trigger voltage of the parasitic bipolar junction transistor is lower than that of the parasitic silicon controlled rectifier, the trigger voltage of the electrostatic discharge protection device 3 depends on the trigger voltage of the parasitic bipolar junction transistor.

[0050] Figure 4 This is a structural cross-sectional view of a third embodiment of the electrostatic discharge protection device of the present invention. Please refer to [link / reference]. Figure 4The following describes a third embodiment of the electrostatic discharge protection device 7 of the present invention. The third embodiment is a bidirectional electrostatic discharge protection device. The electrostatic discharge protection device 7 includes an N-type semiconductor substrate 70, a P-type semiconductor layer 71, a first N-type well region 72, a P-type well region 73, a second N-type well region 74, a first heavily doped P-type region 75, a first heavily doped N-type region 76, and a second heavily doped N-type region 77. The P-type semiconductor layer 71 is disposed on the N-type semiconductor substrate 70, and the first N-type well region 72, P-type well region 73, and second N-type well region 74 are disposed within the P-type semiconductor layer 71. The second N-type well region 74 directly contacts the N-type semiconductor substrate 70, i.e., the second N-type well region 74 and the N-type semiconductor substrate 70 are structurally unstructured. The electrostatic discharge protection device 7 may further include an heavily doped N-type region 740, which is disposed within the second N-type well region 74 to form an ohmic contact. Alternatively, the second N-type well region 74 may be a heavily doped N-type well region to form an ohmic contact. A first heavily doped P-type region 75 is disposed in the first N-type well region 72. A first heavily doped N-type region 76 and a second heavily doped N-type region 77 are disposed in a P-type well region 73. The second heavily doped N-type region 77 is coupled to the second N-type well region 74 via an external conductor 4'. In some embodiments, the P-type well region 73 may be disposed between the first N-type well region 72 and the second N-type well region 74. To form an ohmic contact in the first N-type well region 72, the electrostatic discharge protection device 7 may further include a third heavily doped N-type region 78 disposed in the first N-type well region 72. The first heavily doped N-type region 76, the first heavily doped P-type region 75, and the third heavily doped N-type region 78 are coupled to a first pin 5', and the N-type semiconductor substrate 70 is coupled to a second pin 6'.

[0051] A first heavily doped P-type region 75, a first N-type well region 72, a P-type semiconductor layer 71, and an N-type semiconductor substrate 70 form a parasitic silicon controlled rectifier (SCR). A first heavily doped N-type region 76, a P-type well region 73, a P-type semiconductor layer 71, and an N-type semiconductor substrate 70 form a parasitic vertical bipolar junction transistor (PBT). The parasitic SCR and the PBT must share the same P-type semiconductor layer 71. When a positive electrostatic discharge (ESD) voltage and a ground voltage are received at the first pin 5' and the second pin 6', respectively, the ESD current flows from the first pin 5' through the parasitic SCR and the PBT to the second pin 6'. A breakdown event at the junction between the first heavily doped N-type region 76 and the P-type well region 73 causes an increase in the potential of the P-type semiconductor layer 71, thus a forward bias is applied to the P-type semiconductor layer 71 and the N-type semiconductor substrate 70. The parasitic vertical bipolar junction transistor (VBI) helps turn on the parasitic silicon controlled rectifier (SCR), thereby reducing the trigger and clamping voltages. It's important to note that because the trigger voltage of the VBI is lower than that of the SCR, the trigger voltage of the electrostatic discharge (ESD) protection device 7 depends on the trigger voltage of the VBI. Therefore, the ESD protection device 7 is suitable for low-voltage applications.

[0052] The P-type well region 73, the first heavily doped N-type region 76, and the second heavily doped N-type region 77 form a parasitic lateral bipolar junction transistor. When the first pin 5' and the second pin 6' receive a negative electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the second pin 6' through the N-type semiconductor substrate 70, the second N-type well region 74, the heavily doped N-type region 740, the external wire 4', and the parasitic lateral bipolar junction transistor to the first pin 5'. The path of the parasitic lateral bipolar junction transistor has a low clamping voltage.

[0053] Figure 5 This is a structural cross-sectional view of the fourth embodiment of the electrostatic discharge protection device of the present invention. Please refer to [link / reference]. Figure 5The following describes a fourth embodiment of the electrostatic discharge protection device 7 of the present invention. The difference between the fourth and third embodiments is that the fourth embodiment further includes a second P-type heavily doped region 79, which is disposed in the P-type well region 73. The second P-type heavily doped region 79 directly contacts the bottom of the first N-type heavily doped region 76, that is, there is no structure between the bottom of the second P-type heavily doped region 79 and the bottom of the first N-type heavily doped region 76. The remaining technical features of the fourth embodiment have been described in the third embodiment and will not be repeated here. The collapse event of the junction between the first N-type heavily doped region 76 and the second P-type heavily doped region 79 causes an increase in the potential of the P-type semiconductor layer 71, thus the second P-type heavily doped region 79 can reduce the trigger voltage of the parasitic vertical bipolar junction transistor. Therefore, a forward bias is applied to the P-type semiconductor layer 71 and the N-type semiconductor substrate 70. The parasitic vertical bipolar junction transistor can help turn on the parasitic silicon controlled rectifier, thereby reducing the trigger voltage and clamping voltage. It should be noted that because the trigger voltage of the parasitic vertical bipolar junction transistor is lower than that of the parasitic silicon controlled rectifier, the trigger voltage of the electrostatic discharge protection device 7 depends on the trigger voltage of the parasitic vertical bipolar junction transistor. Therefore, the electrostatic discharge protection device 7 is suitable for low-voltage applications.

[0054] Furthermore, the electrostatic discharge protection device 7 may also include a third P-type heavily doped region 79', which is disposed in the P-type well region 73. The third P-type heavily doped region 79' directly contacts the bottom of the second N-type heavily doped region 77, that is, there is no structure between the bottom of the third P-type heavily doped region 79' and the bottom of the second N-type heavily doped region 77. The third P-type heavily doped region 79' can further reduce the trigger voltage and clamping voltage of the parasitic lateral bipolar junction transistor.

[0055] Figure 6 This is a structural cross-sectional view of the fifth embodiment of the electrostatic discharge protection device of the present invention. Please refer to [link / reference]. Figure 6 The fifth embodiment of the electrostatic discharge protection device 3 of the present invention is described below. The difference between the fifth embodiment and the first embodiment lies in the position of the second pin 6. The other features have been described above and will not be repeated here.

[0056] The first heavily doped P-type region 35, the first N-type well region 32, the P-type semiconductor layer 31, the N-type semiconductor substrate 30, the second N-type well region 34, and the heavily doped N-type region 340 form a parasitic silicon controlled rectifier (SCR). The first heavily doped N-type region 36, the P-type well region 33, the P-type semiconductor layer 31, the N-type semiconductor substrate 30, the second N-type well region 34, and the heavily doped N-type region 340 form a parasitic bipolar junction transistor (BJT). When the first pin 5 and the second pin 6 receive a positive electrostatic discharge (ESD) voltage and a ground voltage, respectively, the ESD current flows from the first pin 5 through the parasitic SCR and the BJT to the second pin 6. Because the collapse of the junction between the first heavily doped N-type region 36 and the P-type well region 33 causes a potential increase in the P-type semiconductor layer 31, a forward bias is applied to the P-type semiconductor layer 31 and the N-type semiconductor substrate 30. The parasitic bipolar junction transistor (BJT) helps turn on the parasitic silicon controlled rectifier (SCR), thereby reducing the trigger and clamping voltages. It's important to note that because the trigger voltage of the BJT is lower than that of the SCR, the trigger voltage of the electrostatic discharge (ESD) protection device 3 depends on the trigger voltage of the BJT. Therefore, the ESD protection device 3 is suitable for low-voltage applications.

[0057] The P-type well region 33, the first N-type heavily doped region 36, and the second P-type heavily doped region 37 form a lateral parasitic diode. When the first pin 5 and the second pin 6 receive a negative electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the second pin 6 through the external wire 4 and the parasitic diode to the first pin 5. The path of the parasitic diode has a low clamping voltage.

[0058] Figure 7 This is a structural cross-sectional view of the sixth embodiment of the electrostatic discharge protection device of the present invention. Please refer to [link / reference]. Figure 7The following describes a sixth embodiment of the electrostatic discharge protection device 3 of the present invention. The difference between the sixth and fifth embodiments is that the sixth embodiment further includes a third P-type heavily doped region 39, which is disposed in the P-type well region 33, and the third P-type heavily doped region 39 directly contacts the bottom of the first N-type heavily doped region 36. That is, there is no structure between the bottom of the third P-type heavily doped region 39 and the first N-type heavily doped region 36. The remaining features of the sixth embodiment have been described in the fifth embodiment and will not be repeated here. The collapse of the junction between the third P-type heavily doped region 39 and the first N-type heavily doped region 36 causes an increase in the potential of the P-type semiconductor layer 31, thus the third P-type heavily doped region 39 can further reduce the trigger voltage of the parasitic bipolar junction transistor. Therefore, a forward bias is applied to the P-type semiconductor layer 31 and the N-type semiconductor substrate 30. The parasitic bipolar junction transistor helps to turn on the parasitic silicon controlled rectifier, thereby reducing the trigger voltage and clamping voltage. It should be noted that because the trigger voltage of the parasitic bipolar junction transistor is lower than that of the parasitic silicon controlled rectifier, the trigger voltage of the electrostatic discharge protection device 3 depends on the trigger voltage of the parasitic bipolar junction transistor.

[0059] Figure 8 This is a structural cross-sectional view of the seventh embodiment of the electrostatic discharge protection device of the present invention. Please refer to [link / reference]. Figure 8 The seventh embodiment of the electrostatic discharge protection device 7 of the present invention is described below. The difference between the seventh embodiment and the third embodiment lies in the position of the second pin 6'. In the seventh embodiment, the second pin 6' is coupled to the external conductor 4'.

[0060] A parasitic silicon controlled rectifier (SCR) is formed by a first P-type heavily doped region 75, a first N-type well region 72, a P-type semiconductor layer 71, an N-type semiconductor substrate 70, a second N-type well region 74, and an N-type heavily doped region 740. A parasitic vertical bipolar junction transistor (VBI) is formed by a first N-type heavily doped region 76, a P-type well region 73, a P-type semiconductor layer 71, an N-type semiconductor substrate 70, a second N-type well region 74, and an N-type heavily doped region 740. The parasitic SCR and the VBI must share the same P-type semiconductor layer 71. When a positive electrostatic discharge (ESD) voltage and a ground voltage are received at the first pin 5' and the second pin 6' respectively, the ESD current flows from the first pin 5' through the parasitic SCR and the VBI to the second pin 6'. The collapse event at the junction between the first heavily doped N-type region 76 and the P-type well region 73 causes an increase in the potential of the P-type semiconductor layer 71, thus applying a forward bias voltage to the P-type semiconductor layer 71 and the N-type semiconductor substrate 70. The parasitic vertical bipolar junction transistor (VBI) helps to turn on the parasitic silicon controlled rectifier (SCR), thereby reducing the trigger voltage and clamping voltage. It should be noted that because the trigger voltage of the VBI is lower than the trigger voltage of the SCR, the trigger voltage of the electrostatic discharge protection device 7 depends on the trigger voltage of the VBI. Therefore, the electrostatic discharge protection device 7 is suitable for low-voltage applications.

[0061] The P-type well region 73, the first heavily doped N-type region 76, and the second heavily doped N-type region 77 form a parasitic lateral bipolar junction transistor. When the first pin 5' and the second pin 6' receive a negative electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the second pin 6' through the external wire 4' and the parasitic lateral bipolar junction transistor to the first pin 5'. The path of the parasitic lateral bipolar junction transistor has a low clamping voltage.

[0062] Figure 9 This is a structural cross-sectional view of the eighth embodiment of the electrostatic discharge protection device of the present invention. Please refer to [link / reference]. Figure 9The following describes an eighth embodiment of the electrostatic discharge protection device 7 of the present invention. The difference between the eighth and seventh embodiments is that the eighth embodiment of the electrostatic discharge protection device 7 further includes a second P-type heavily doped region 79, which is disposed in the P-type well region 73. The second P-type heavily doped region 79 directly contacts the bottom of the first N-type heavily doped region 76, that is, there is no structure between the bottom of the second P-type heavily doped region 79 and the bottom of the first N-type heavily doped region 76. The remaining technical features of the eighth embodiment have been described in the seventh embodiment and will not be repeated here. The collapse event of the junction between the first N-type heavily doped region 76 and the second P-type heavily doped region 79 causes an increase in the potential of the P-type semiconductor layer 71, thus the second P-type heavily doped region 79 can reduce the trigger voltage of the parasitic vertical bipolar junction transistor. Therefore, a forward bias is applied to the P-type semiconductor layer 71 and the N-type semiconductor substrate 70. The parasitic vertical bipolar junction transistor can help turn on the parasitic silicon controlled rectifier, thereby reducing the trigger voltage and clamping voltage. It should be noted that because the trigger voltage of the parasitic vertical bipolar junction transistor is lower than that of the parasitic silicon controlled rectifier, the trigger voltage of the electrostatic discharge protection device 7 depends on the trigger voltage of the parasitic vertical bipolar junction transistor. Therefore, the electrostatic discharge protection device 7 is suitable for low-voltage applications.

[0063] Furthermore, the electrostatic discharge protection device 7 may also include a third P-type heavily doped region 79', which is disposed in the P-type well region 73. The third P-type heavily doped region 79' directly contacts the bottom of the second N-type heavily doped region 77, that is, there is no structure between the bottom of the third P-type heavily doped region 79' and the bottom of the second N-type heavily doped region 77. The third P-type heavily doped region 79' can further reduce the trigger voltage and clamping voltage of the parasitic lateral bipolar junction transistor.

[0064] According to the above embodiments, the electrostatic discharge protection device has a low trigger voltage and a low clamping voltage, and can be used in low-voltage applications.

[0065] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent variations and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included within the protection scope of the present invention.

Claims

1. An electrostatic discharge protection device, characterized in that, include: An N-type semiconductor substrate; A P-type semiconductor layer is disposed on the N-type semiconductor substrate; A first N-type well region, a P-type well region, and a second N-type well region are disposed in the P-type semiconductor layer, wherein the second N-type well region directly contacts the N-type semiconductor substrate; A first P-type heavily doped region is located within the first N-type well region; as well as A first N-type heavily doped region and a second P-type heavily doped region are disposed in the P-type well region, wherein the second P-type heavily doped region is coupled to the second N-type well region via an external wire.

2. The electrostatic discharge protection device as described in claim 1, characterized in that, The second N-type well region is an N-type heavily doped well region.

3. The electrostatic discharge protection device as described in claim 1, characterized in that, It also includes an N-type heavily doped region, which is located in the second N-type well region.

4. The electrostatic discharge protection device as described in claim 1, characterized in that, It also includes a second N-type heavily doped region, which is located in the first N-type well region.

5. The electrostatic discharge protection device as described in claim 4, characterized in that, The first N-type heavily doped region, the first P-type heavily doped region, and the second N-type heavily doped region are coupled to a first pin, and the N-type semiconductor substrate is coupled to a second pin.

6. The electrostatic discharge protection device as described in claim 5, characterized in that, The first P-type heavily doped region, the first N-type well region, the P-type semiconductor layer, and the N-type semiconductor substrate form a parasitic silicon controlled rectifier. The first N-type heavily doped region, the P-type well region, the P-type semiconductor layer, and the N-type semiconductor substrate form a parasitic bipolar junction transistor. When the first pin and the second pin receive a positive electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the first pin through the parasitic silicon controlled rectifier and the parasitic bipolar junction transistor to the second pin.

7. The electrostatic discharge protection device as described in claim 5, characterized in that, The P-type well region, the first N-type heavily doped region, and the second P-type heavily doped region form a parasitic diode. When the first pin and the second pin receive a negative electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the second pin through the N-type semiconductor substrate, the second N-type well region, the external wire, and the parasitic diode to the first pin.

8. The electrostatic discharge protection device as described in claim 4, characterized in that, The first N-type heavily doped region, the first P-type heavily doped region, and the second N-type heavily doped region are coupled to a first pin, and the external conductor is coupled to a second pin.

9. The electrostatic discharge protection device as described in claim 8, characterized in that, The first P-type heavily doped region, the first N-type well region, the P-type semiconductor layer, the N-type semiconductor substrate, and the second N-type well region form a parasitic silicon controlled rectifier. The first N-type heavily doped region, the P-type well region, the P-type semiconductor layer, the N-type semiconductor substrate, and the second N-type well region form a parasitic bipolar junction transistor. When the first pin and the second pin receive a positive electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the first pin through the parasitic silicon controlled rectifier and the parasitic bipolar junction transistor to the second pin.

10. The electrostatic discharge protection device as described in claim 8, characterized in that, The P-type well region, the first N-type heavily doped region, and the second P-type heavily doped region form a parasitic diode. The electrostatic discharge current flows from the second pin through the external wire and the parasitic diode to the first pin.

11. The electrostatic discharge protection device as described in claim 1, characterized in that, It also includes a third P-type heavily doped region, which is located in the P-type well region, and the third P-type heavily doped region directly contacts the bottom of the first N-type heavily doped region.

12. An electrostatic discharge protection device, characterized in that, include: An N-type semiconductor substrate; A P-type semiconductor layer is disposed on the N-type semiconductor substrate; A first N-type well region, a P-type well region, and a second N-type well region are disposed in the P-type semiconductor layer, wherein the second N-type well region directly contacts the N-type semiconductor substrate; A first P-type heavily doped region is located within the first N-type well region; as well as A first N-type heavily doped region and a second N-type heavily doped region are disposed in the P-type well region, wherein the second N-type heavily doped region is coupled to the second N-type well region via an external wire.

13. The electrostatic discharge protection device as described in claim 12, characterized in that, The second N-type well region is an N-type heavily doped well region.

14. The electrostatic discharge protection device as described in claim 12, characterized in that, It also includes an N-type heavily doped region, which is located in the second N-type well region.

15. The electrostatic discharge protection device as described in claim 12, characterized in that, It also includes a third N-type heavily doped region, which is located in the first N-type well region.

16. The electrostatic discharge protection device as described in claim 15, characterized in that, The first N-type heavily doped region, the first P-type heavily doped region, and the third N-type heavily doped region are coupled to a first pin, and the N-type semiconductor substrate is coupled to a second pin.

17. The electrostatic discharge protection device as described in claim 16, characterized in that, The first P-type heavily doped region, the first N-type well region, the P-type semiconductor layer, and the N-type semiconductor substrate form a parasitic silicon controlled rectifier. The first N-type heavily doped region, the P-type well region, the P-type semiconductor layer, and the N-type semiconductor substrate form a parasitic vertical bipolar junction transistor. When the first pin and the second pin receive a positive electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the first pin through the parasitic silicon controlled rectifier and the parasitic vertical bipolar junction transistor to the second pin.

18. The electrostatic discharge protection device as described in claim 16, characterized in that, The P-type well region, the first N-type heavily doped region, and the second N-type heavily doped region form a parasitic lateral bipolar junction transistor. When the first pin and the second pin receive a negative electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the second pin through the N-type semiconductor substrate, the second N-type well region, the external wire, and the parasitic lateral bipolar junction transistor to the first pin.

19. The electrostatic discharge protection device as described in claim 15, characterized in that, The first N-type heavily doped region, the first P-type heavily doped region, and the third N-type heavily doped region are coupled to a first pin, and the external conductor is coupled to a second pin.

20. The electrostatic discharge protection device as described in claim 19, characterized in that, The first P-type heavily doped region, the first N-type well region, the P-type semiconductor layer, the N-type semiconductor substrate, and the second N-type well region form a parasitic silicon controlled rectifier. The first N-type heavily doped region, the P-type well region, the P-type semiconductor layer, the N-type semiconductor substrate, and the second N-type well region form a parasitic vertical bipolar junction transistor. When the first pin and the second pin receive an electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the first pin through the parasitic silicon controlled rectifier and the parasitic vertical bipolar junction transistor to the second pin.

21. The electrostatic discharge protection device as described in claim 19, characterized in that, The P-type well region, the first N-type heavily doped region, and the second N-type heavily doped region form a parasitic lateral bipolar junction transistor. When the first pin and the second pin receive a negative electrostatic discharge voltage and a ground voltage, respectively, the electrostatic discharge current flows from the second pin through the external wire and the parasitic lateral bipolar junction transistor to the first pin.

22. The electrostatic discharge protection device as described in claim 12, characterized in that, It also includes a second P-type heavily doped region, which is located in the P-type well region, and the second P-type heavily doped region directly contacts the bottom of the first N-type heavily doped region.

23. The electrostatic discharge protection device as described in claim 22, characterized in that, It also includes a third P-type heavily doped region, which is located in the P-type well region, and the third P-type heavily doped region directly contacts the bottom of the second N-type heavily doped region.

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