Semiconductor device and method of manufacturing the same

Abstract

The application relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a buried layer arranged in the substrate, a first well region arranged on the upper surface layer of the buried layer, a second well region arranged on the upper surface layer of the buried layer and partially in contact with the substrate, the second well region being located at the periphery of the first well region, a plurality of emitter lead-out regions and base lead-out regions arranged on the upper surface layer of the first well region and spaced apart from each other, a gate structure arranged on the upper surface of the substrate and comprising a gate, the orthographic projection of the gate on the first well region being staggered with the emitter lead-out regions, and a collector lead-out region formed in the upper surface layer of the second well region. The plurality of emitter lead-out regions are connected in parallel to lead out the emitter, and the gate and the collector lead-out region are connected in parallel to lead out the collector. The input voltage of the collector can be changed to control the gain current of the semiconductor device and the effective doping concentration of the emitter lead-out region.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] In the related art, a semiconductor structure includes a P-type substrate and an N-type buried layer arranged in the substrate, and an NPN transistor is formed in the P-well, and the N-type buried layer is used for isolation, the emitter is drawn from the P-well, the collector is drawn from the N-well, and the PN junction between the P-well and the N-well is used to improve the breakdown voltage of the semiconductor structure.

[0003] However, the emitter region of the conventional semiconductor structure is usually a heavily doped region, which affects the current gain of the semiconductor structure. SUMMARY

[0004] Therefore, it is necessary to provide a semiconductor device and a manufacturing method thereof to solve the problem of low gain current of the conventional semiconductor structure.

[0005] According to an aspect of the present application, a semiconductor device is provided, comprising:

[0006] a substrate having a first conductivity type;

[0007] a buried layer arranged in the substrate and having a second conductivity type, the first conductivity type being opposite to the second conductivity type;

[0008] a first well region arranged on an upper surface layer of the buried layer and having the first conductivity type;

[0009] a second well region arranged on the upper surface layer of the buried layer and partially in contact with the substrate, the second well region being located at the periphery of the first well region and having the second conductivity type;

[0010] a plurality of emitter drawing regions and base drawing regions arranged on an upper surface layer of the first well region and spaced apart from each other; the base drawing regions have the first conductivity type, and the emitter drawing regions have the second conductivity type;

[0011] a gate structure arranged on an upper surface of the substrate and comprising a gate, a normal projection of the gate on the first well region being staggered with the emitter drawing regions;

[0012] a collector drawing region formed in an upper surface layer of the second well region and having the second conductivity type;

[0013] wherein the plurality of emitter drawing regions are connected in parallel to draw an emitter;

[0014] the gate and the collector drawing region are connected in parallel to draw a collector.

[0015] In one of the embodiments, the collector is configured to be capable of adjustable input of a positive voltage.

[0016] In one of the embodiments, a plurality of the collector extraction regions are provided in an upper surface layer of the second well region, and the plurality of the collector extraction regions are connected in parallel with the gate to extract the collector.

[0017] In one of the embodiments, the gate structure includes a plurality of the gates, and each of the gates is located above a region between two adjacent ones of the emitter extraction regions.

[0018] In one of the embodiments, the gate structure further includes a gate dielectric layer provided on an upper surface of the substrate.

[0019] The plurality of the gates are provided on the gate dielectric layer.

[0020] The gate dielectric layer has a thickness of a predetermined value.

[0021] In one of the embodiments, the plurality of the emitter extraction regions are arranged to form a plurality of groups of the emitter extraction regions spaced apart along a first direction, and each of the groups of the emitter extraction regions includes a plurality of the emitter extraction regions spaced apart along a second direction.

[0022] The gate and the plurality of the groups of the emitter extraction regions are staggered along the first direction.

[0023] The first direction and the second direction intersect each other.

[0024] In one of the embodiments, the base extraction region is located at a periphery of the emitter extraction region.

[0025] In one of the embodiments, the method further includes forming a plurality of field oxide structures in an upper surface layer of the substrate, and the plurality of the field oxide structures include first field oxide structures for electrically isolating the emitter extraction region and the base extraction region from each other, and second field oxide structures for electrically isolating the base extraction region and the collector extraction region from each other.

[0026] In one of the embodiments, the first conductivity type is P-type, and the second conductivity type is N-type.

[0027] When the collector input voltage is input, the emitter extraction region, the base extraction region, and the first well region together with the collector extraction region form an NPN transistor.

[0028] According to another aspect of the present application, there is provided a method of manufacturing a semiconductor device, including:

[0029] providing a substrate; the substrate has a first conductivity type;

[0030] forming a buried layer in the substrate; the buried layer has a second conductivity type, the first conductivity type being opposite to the second conductivity type;

[0031] forming a first well region on an upper surface layer of the buried layer, the first well region having the first conductivity type;

[0032] forming a second well region on an upper surface layer of the buried layer, the second well region being located peripherally to the first well region, a part of the second well region being in contact with the substrate and having the second conductivity type;

[0033] forming a gate structure on an upper surface of the substrate;

[0034] forming a plurality of emitter lead-out regions and base lead-out regions in the upper surface layer of the first well region, the emitter lead-out regions and the base lead-out regions being arranged alternately; wherein the gate structure comprises a gate, a normal projection of the gate on the first well region being staggered with the emitter lead-out regions; the base lead-out regions have the first conductivity type, and the emitter lead-out regions have the second conductivity type;

[0035] forming a collector lead-out region having the second conductivity type in an upper surface layer of the second well region;

[0036] wherein a plurality of the emitter lead-out regions are connected in parallel to lead out an emitter;

[0037] the gate and the collector lead-out region are connected in parallel to lead out a collector.

[0038] The semiconductor device and the manufacturing method thereof provided above can make the collector input a positive voltage, and when the input voltage of the collector is 0V-0.4V, the voltage difference formed between the gate and the first well region is small, and no inversion layer is formed at the area of the first well region below the gate. Since the multiple emitter lead-out areas are connected in parallel, the electrical conductivity of the emitter during use can be improved, the overall area of all the emitter areas can be ensured, the current gain of the semiconductor device can be improved, and the current gain of the semiconductor device is not affected by the too high doping concentration of the emitter lead-out area. When the input voltage of the collector is 0.4V-0.7V, the voltage difference formed between the gate and the first well region can form an electric field that repels holes and attracts electrons, so that the holes at the area of the first well region below the gate are repelled, and the minority carriers (electrons) in the P-type first well region are attracted to the area of the first well region below the gate, and the electrons can form an inversion layer at the area of the first well region below the gate. Since the positive projection of the gate on the first well region is staggered with the emitter lead-out areas, it can be understood that the formed inversion layer is located between the adjacent two emitter lead-out areas, and electrically connects the adjacent two emitter lead-out areas, which is equivalent to that a low-doped inversion layer with the same conductivity type as the emitter lead-out area is formed between the adjacent two emitter lead-out areas. In this way, the effective doping concentration of the emitter lead-out area can be effectively increased, the effective area of the emitter lead-out area is increased, and the gain current of the semiconductor device is also improved. In this way, the gain current of the semiconductor device and the effective doping concentration of the emitter lead-out area can be controlled by changing the input voltage of the collector. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 A structure schematic diagram of a semiconductor device according to an embodiment of the present application is shown;

[0040] Figure 2 A layout schematic diagram of a gate and an emitter lead-out area according to an embodiment of the present application is shown;

[0041] Figure 3 A flow schematic diagram of a manufacturing method of a semiconductor device according to an embodiment of the present application is shown;

[0042] Figures 4(a)-4(g) A manufacturing process schematic diagram of a semiconductor device according to an embodiment of the present application is shown;

[0043] Figure 5 A flow schematic diagram of a manufacturing method of a semiconductor device according to an embodiment of the present application is shown.

[0044] In the figure: 110, substrate; 111, sacrificial layer; 112, oxide layer; 113, silicon nitride layer; 120, buried layer; 130, first well region; 140, second well region; 150, emitter lead-out region; 160, base lead-out region; 170, collector lead-out region; 180, gate structure; 181, gate; 182, gate dielectric layer; 191, first field oxide structure; 192, second field oxide structure; 193, third field oxide structure; 200, passivation layer; 310, first conductive plug; 320, second conductive plug; 330, third conductive plug. DETAILED DESCRIPTION

[0045] For the purposes of this disclosure the singular form "a", "an", and "the" include plural references unless the context clearly dictates otherwise. The term "includes" means "comprises" or is "consist of". The term "coupled" means directly or indirectly connected, linked, or associated.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for describing particular embodiments only and is not intended to be limiting of the application. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety for the teachings relevant to the sentence and / or paragraph in which the reference is presented.

[0047] It should be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms since the terms are relative. The above-described arrangement is merely one implementation and other arrangements can be devised without departing from the spirit and scope of the present application. Thus, the above-described arrangement is merely one implementation and other arrangements can be devised without departing from the spirit and scope of the present application.

[0048] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is inverted, then a dependent element or feature described as "below" or "beneath" another element or feature is still oriented "above" the other element or feature or element(s). Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] Embodiments of the application are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the application. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change between implanted and non-implanted regions. Similarly, an implanted region formed by implantation can result in some implant in a region between the implanted region and a surface over which implantation occurs. Thus, the regions illustrated in the figures are schematic and are not intended to illustrate actual dimensions but are intended to be exemplary of the regions used in the devices described herein.

[0051] As used herein, semiconductor field terms are used by those skilled in the art, for example, for P-type and N-type impurities, to distinguish doping concentrations, simply P+ type represents a heavily doped P-type, P-type represents a medium doped P-type, P- type represents a lightly doped P-type, N+ type represents a heavily doped N-type, N-type represents a medium doped N-type, N- type represents a lightly doped N-type.

[0052] Figure 1 A structure schematic diagram of a semiconductor device according to an embodiment of the present application.

[0053] Referring to Figure 1 The semiconductor device according to an embodiment of the present application comprises a substrate 110, a buried layer 120, a first well region 130, a second well region 140, an emitter lead-out region 150, a base lead-out region 160, a collector lead-out region 170 and a gate structure 180.

[0054] The substrate 110 has a first conductivity type, and the buried layer 120 is arranged in the substrate 110 and has a second conductivity type, the first conductivity type being opposite to the second conductivity type.

[0055] For example, the first conductivity type is P type, and the second conductivity type is N type; or, the first conductivity type is N type, and the second conductivity type is P type. In the embodiment, for example, the first conductivity type is P type, and the second conductivity type is N type, i.e., the substrate 110 has P type conductivity, and the buried layer 120 has N type conductivity.

[0056] The first well region 130 is arranged in an upper surface layer of the buried layer 120 and has the first conductivity type, and the second well region 140 is arranged in the upper surface layer of the buried layer 120 and has a part of the region in contact with the substrate 110, the second well region 140 being located at the periphery of the first well region 130 and having the second conductivity type.

[0057] The plurality of emitter lead-out regions 150 and base lead-out regions 160 are arranged in the upper surface layer of the first well region 130 and are spaced apart from each other, the base lead-out regions 160 having the first conductivity type, and the emitter lead-out regions 150 having the second conductivity type. The gate structure 180 is arranged on the upper surface of the substrate 110 and comprises a gate 181, a normal projection of the gate 181 on the first well region 130 being staggered with the emitter lead-out regions 150, and the collector lead-out region 170 is formed in the upper surface layer of the second well region 140 and has the second conductivity type.

[0058] Therefore, the emitter lead-out regions 150, the base lead-out regions 160 and the first well region 130 form a whole, and the collector lead-out region 170 and the second well region 140 form another whole, and the whole formed by the emitter lead-out regions 150, the base lead-out regions 160 and the first well region 130 and the whole formed by the collector lead-out region 170 and the second well region 140 together constitute a triode.

[0059] The plurality of emitter extraction regions 150 are connected in parallel to extract the emitter, and the gate 181 and the collector extraction region 170 are connected in parallel to extract the collector. The collector can be input with a positive voltage, and when the input voltage of the collector is 0V-0.4V, the voltage difference between the gate 181 and the first well region 130 is small, and no inversion layer is formed at the area of the first well region 130 under the gate 181. Since the plurality of emitter extraction regions 150 are connected in parallel, the electrical conduction capability of the emitter during use is improved, the overall area of all the emitter regions is ensured, and the current gain of the semiconductor device is also improved, avoiding the influence of the current gain of the semiconductor device due to the too high doping concentration of the emitter extraction region 150. When the input voltage of the collector is 0.4V-0.7V, a voltage difference is formed between the gate 181 and the first well region 130, an electric field that repels holes and attracts electrons is formed, the holes at the area of the first well region 130 under the gate 181 are repelled, and the minority carriers (electrons) in the P-type first well region 130 are attracted to the area of the first well region 130 under the gate 181, and these electrons form an inversion layer at the area of the first well region 130 under the gate 181. Since the normal projection of the gate 181 on the first well region 130 is staggered with the emitter extraction region 150, it can be understood that the formed inversion layer is located between the two adjacent emitter extraction regions 150, and the two adjacent emitter extraction regions 150 are electrically connected, which is equivalent to that a low-doped inversion layer with the same conductivity type as the emitter extraction region 150 is formed between the two adjacent emitter extraction regions 150. In this way, the effective doping concentration of the emitter extraction region 150 can be effectively increased, and the effective area of the emitter extraction region 150 is also increased, which is also beneficial to improve the gain current of the semiconductor device. In this way, the gain current of the semiconductor device and the effective doping concentration of the emitter extraction region 150 can be controlled by changing the input voltage of the collector.

[0060] When the input voltage of the collector is greater than 0.7V, a strong inversion layer can be formed at the area of the first well region 130 under the gate 181, which is more beneficial to improve the gain current of the semiconductor device.

[0061] In some embodiments, the doping concentration of the emitter extraction region 150 is 4×10 19 cm -3 ~8×10 19 cm -3Compared with the traditional heavily doped region, the emitter lead-out region 150 has a lower doping concentration, and since the multiple emitter lead-out regions 150 are connected in parallel to lead out the emitter, the current conducting capability of the emitter during use is improved, the overall area of all the emitter regions is ensured, the current gain of the semiconductor device is improved, and the current gain of the semiconductor device is not affected by the excessively high doping concentration of the emitter lead-out region 150.

[0062] In some embodiments, the collector is configured to be able to adjustably input a positive voltage. The input voltage of the collector can be adjusted to the required voltage value as needed, so as to control the gain current of the semiconductor device and the effective doping concentration of the emitter lead-out region 150.

[0063] In some embodiments, the upper surface layer of the second well region 140 is provided with multiple collector lead-out regions 170, and the multiple collector lead-out regions 170 are connected in parallel with the gate 181 to lead out the collector. The multiple collector lead-out regions 170 are connected in parallel to serve as the collector, which is beneficial to improve the current conducting capability of the collector during use, thereby improving the voltage resistance capability and reliability of the semiconductor device.

[0064] In some embodiments, the gate structure 180 includes multiple gates 181, and each gate 181 is located above the region between two adjacent emitter lead-out regions 150. In this way, when the input voltage of the collector is greater than 0.4V, a low-doped region with the same conductivity type as the emitter lead-out region 150 is formed between each adjacent two emitter lead-out regions 150, which can electrically connect each adjacent two emitter lead-out regions 150 through the corresponding low-doped region, and is beneficial to improve the effective doping concentration of the emitter lead-out region 150, thereby increasing the effective area of the emitter lead-out region 150 and improving the gain current of the semiconductor device.

[0065] In some embodiments, referring to Figure 1 The gate structure 180 further includes a gate dielectric layer 182 provided on the upper surface of the substrate 110, the multiple gates 181 are provided on the gate dielectric layer 182, and the thickness of the gate dielectric layer 182 is a preset value. The thickness of the gate dielectric layer 182 can be set according to the required voltage resistance value of the transistor, for example, the thickness of the gate dielectric layer 182 can be 40-50 angstroms when the required voltage resistance value of the transistor is 3V.

[0066] In some embodiments, referring to Figure 2 The multiple emitter lead-out regions 150 are arranged to form multiple groups of emitter lead-out regions arranged at intervals along a first direction F1, each group of emitter lead-out regions includes multiple emitter lead-out regions 150 arranged at intervals along a second direction F2, the gate 181 is staggered with the multiple groups of emitter lead-out regions along the first direction F1, and the first direction F1 and the second direction F2 intersect with each other.

[0067] It can be understood that the plurality of emitter extraction regions 150 are arranged in an array, and the first direction F1 can be perpendicular to the second direction F2.

[0068] The plurality of gates 181 are connected in parallel, so that the gate resistance is more uniform, which is beneficial to improve the current sharing characteristics of the gate 181, and can reduce the gate resistance to realize the fast switching of the "series connection" between the two adjacent emitter extraction regions 150 below the gate 181. Since the gate 181 is staggered with the plurality of groups of emitter extraction region groups along the first direction F1, when the input voltage of the collector is greater than 0.4V, the adjacent two emitter extraction regions 150 in the same gate 181 corresponding to the adjacent two groups of the plurality of groups of emitter extraction region groups form a low-doped layer with the same conductivity type as the emitter extraction region 150, which can electrically connect each adjacent two emitter extraction regions 150 through the corresponding inversion layer, and is more beneficial to increase the effective doping concentration of the emitter extraction region 150, thereby increasing the effective area of the emitter extraction region 150, and is also beneficial to increase the gain current of the semiconductor device.

[0069] In some embodiments, the base extraction region 160 is located at the periphery of the emitter extraction region 150, which is beneficial to improve the voltage resistance of the semiconductor device.

[0070] In some embodiments, the semiconductor device further includes a plurality of field oxide structures formed in the upper layer of the substrate 110, the plurality of field oxide structures including a first field oxide structure 191 for electrically isolating the emitter extraction region 150 and the base extraction region 160 from each other, and a second field oxide structure 192 for electrically isolating the base extraction region 160 and the collector extraction region 170 from each other.

[0071] The first field oxide structure 191 also extends to the upper layer of the first well region 130, and the first field oxide structure 191 can be a ring structure to better electrically isolate the emitter extraction region 150 and the base extraction region 160.

[0072] A part of the second field oxide structure 192 extends to the upper layer of the first well region 130, and another part of the second field oxide structure 192 extends to the upper layer of the second well region 140, and the second field oxide structure 192 can be a ring structure to better electrically isolate the base extraction region 160 and the collector extraction region 170.

[0073] Of course, the application is not limited to this, and the collector lead-out region 170 can be provided with multiple, the upper surface layer of the first well region 130 is provided with multiple base lead-out regions 160 corresponding to the collector lead-out region 170 one by one, and the upper surface layer of the first well region 130 is provided with multiple second field oxide structures 192 extending to the upper surface layer of the second well region 140 and corresponding to the collector lead-out region 170 one by one. Each second field oxide structure 192 is arranged between the corresponding base lead-out region 160 and the corresponding collector lead-out region 170 to electrically isolate the corresponding base lead-out region 160 and the corresponding collector lead-out region 170.

[0074] The multiple field oxide structures further include a third field oxide structure 193 arranged on the upper surface layer of the second well region 140 and located at the periphery of the collector lead-out region 170. The third field oxide structure 193 is located at the periphery of the collector lead-out region 170 to isolate the semiconductor device from other devices, further improving the isolation performance of the semiconductor device.

[0075] The third field oxide structure 193 can be a ring structure to better electrically isolate the semiconductor device from other devices.

[0076] In other embodiments, the first field oxide structure 191, the second field oxide structure 192, and the third field oxide structure 193 can be shallow trench field oxide structures.

[0077] In some embodiments, the first conductivity type is P-type, and the second conductivity type is N-type. When the collector input voltage, the emitter lead-out region 150, the base lead-out region 160, and the first well region 130 form an NPN transistor together with the collector lead-out region 170.

[0078] The application further provides a manufacturing method of a semiconductor device, which can be used to manufacture the semiconductor device of any one of the preceding embodiments.

[0079] Figure 3 A flowchart of a manufacturing method of a semiconductor device according to an embodiment of the application is shown.

[0080] Referring to Figure 3 The manufacturing method of the semiconductor device according to an embodiment of the application includes the following steps:

[0081] S210, providing a substrate 110, the substrate 110 has a first conductivity type.

[0082] S220, referring to Fig. 4(a), a buried layer 120 is formed in the substrate 110, the buried layer 120 has a second conductivity type, the first conductivity type is opposite to the second conductivity type. A sacrificial layer 111 can be deposited on the substrate 110, and then the buried layer 120 is formed by ion implantation and high-temperature push-out, and the depth of the push-out must reach a certain depth to ensure the depletion of the semiconductor device and the conduction path of the current. The material of the sacrificial layer 111 can be silicon dioxide.

[0083] S230, referring to Fig. 4(b), a first well region 130 is formed on the upper surface of the buried layer 120, the first well region 130 has a first conductivity type. The first well region 130 can be formed by ion implantation and high-temperature push-out.

[0084] S240, referring to Fig. 4(b), a second well region 140 is formed on the upper surface of the buried layer 120 and surrounds the first well region 130, part of the second well region 140 is in contact with the substrate 110, and the second well region 140 has a second conductivity type. The second well region 140 can be formed by ion implantation and high-temperature push-out.

[0085] S250, referring to Fig. 4(e), a gate structure 180 is formed on the upper surface of the substrate 110.

[0086] S260, referring to Fig. 4(f), a plurality of emitter lead-out regions 150 and base lead-out regions 160 are formed in the upper surface of the first well region 130, the base lead-out regions 160 are arranged around the emitter lead-out regions 150, the gate structure 180 includes a gate 181, and the normal projection of the gate 181 on the first well region 130 is staggered with the emitter lead-out regions 150. The base lead-out regions 160 have a first conductivity type, and the emitter lead-out regions 150 have a second conductivity type.

[0087] S270, referring to Fig. 4(f), a collector lead-out region 170 having a second conductivity type is formed in the upper surface of the second well region 140.

[0088] The plurality of emitter lead-out regions 150 are connected in parallel to lead out the emitter, and the gate 181 and the collector lead-out region 170 are connected in parallel to lead out the collector. The input voltage of the collector can be changed to control the gain current of the semiconductor device and the effective doping concentration of the emitter lead-out region 150.

[0089] In some embodiments, before the step S250 of forming the gate structure 180 on the upper surface layer of the substrate 110, the method for manufacturing the semiconductor device further comprises: forming a plurality of field oxide structures on the upper surface layer of the substrate 110, specifically, as shown in FIG. 4(c) and FIG. 4(d), the sacrificial layer 111 is removed, the upper surface of the substrate 110 is cleaned, and an oxide layer 112 is formed on the upper surface of the substrate 110, then a layer of silicon nitride layer 113 is deposited on the oxide layer 112, a pattern corresponding to the plurality of field oxide structures is formed on the silicon nitride layer 113 by photoetching, developing and other processes, and high-temperature thermal oxidation is performed on the substrate 110 at positions corresponding to the pattern of the field oxide structures, so as to form the plurality of field oxide structures.

[0090] The plurality of field oxide structures can be formed by a field oxide oxidation process. Due to the high-temperature and long-time advancement of the field oxide structures, on the one hand, the field oxide structures themselves are advanced, and a part of the plurality of field oxide structures, such as the first field oxide structure 191, extends to the upper surface layer of the first well region 130; another part of the plurality of field oxide structures, such as a part of the second field oxide structure 192, extends to the upper surface layer of the first well region 130, and another part of the second field oxide structure 192 extends to the upper surface layer of the second well region 140. Still another part of the plurality of field oxide structures, such as the third field oxide structure 193, extends to the upper surface layer of the second well region 140. On the other hand, the first well region 130 and the second well region 140 are also advanced, and the junction profiles of the first well region 130 and the second well region 140 are optimized, and the junction depths of the first well region 130 and the second well region 140 after the advancement can reach a certain depth, so as to ensure the depletion and current conduction path of the semiconductor device.

[0091] The step S250 of forming the gate structure 180 on the upper surface layer of the substrate 110 specifically comprises:

[0092] S251, as shown in FIG. 4(d), the oxide layer 112 and the silicon nitride layer 113 are removed, and a gate dielectric layer 182 located between adjacent two field oxide structures is formed on the upper surface of the substrate 110.

[0093] S252, as shown in FIG. 4(e), a gate electrode 181 is formed on the gate dielectric layer 182 in a region above the first well region 130.

[0094] In some embodiments, the step S260 of forming the plurality of spaced-apart emitter lead-out regions 150 and base lead-out regions 160 in the upper surface layer of the first well region 130 specifically comprises:

[0095] Referring to FIG. 4(f), second-conductivity-type ions are implanted into the first well region 130 with photoresist as a masking film to form the plurality of emitter lead-out regions 150, and first-conductivity-type ions are implanted into the first well region 130 with photoresist as a masking film to form the base lead-out regions 160.

[0096] In some embodiments, the step S270 of forming the collector lead-out region 170 having the second conductivity type in the upper surface layer of the second well region 140 specifically comprises:

[0097] Referring to Fig. 4(f), the second conductivity type ions are implanted into the second well region 140 with the photoresist as a mask to form the collector lead-out region 170.

[0098] In some embodiments, referring to Fig. 4(g), and in combination with the description of Figure 5 The method for manufacturing the semiconductor device further comprises:

[0099] S281, forming a passivation layer 200 covering the gate structure 180 and the plurality of field oxide structures on the upper surface of the substrate 110.

[0100] S282, performing a planarization process on the side of the passivation layer 200 away from the gate structure 180.

[0101] S283, forming the first conductive plug 310, the second conductive plug 320 and the third conductive plug 330 penetrating through the passivation layer 200 in the passivation layer 200.

[0102] S284, forming the emitter, the collector and the base on the passivation layer 200.

[0103] The emitter is electrically connected to the emitter lead-out region 150 through the first conductive plug 310, the collector is electrically connected to the collector lead-out region 170 through the second conductive plug 320, and the base is electrically connected to the base lead-out region 160 through the third conductive plug 330. The emitter, the collector and the base of the NPN transistor can be normally led out.

[0104] It should be understood that, although the steps in the flowcharts in the above embodiments are displayed in sequence according to the arrows, these steps are not necessarily executed in the order according to the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other sequences. Moreover, at least a part of the steps in the above flowcharts can comprise a plurality of sub-steps or a plurality of stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least a part of other steps or sub-steps or stages of other steps. It should be noted that the different embodiments described above can be combined with each other.

[0105] Any combination of the technical features in the above-described embodiments can be made, and for the sake of brevity, not all possible combinations are described, however, as long as the combination of the technical features does not exist in contradiction, it shall be considered within the scope of the present disclosure.

[0106] The above-described embodiments only express several implementation manners of the present application, and the description is relatively specific and detailed, but it shall not be understood as a limitation on the patent scope of the present application. It shall be pointed out that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, and these shall be within the protection scope of the present application. Therefore, the protection scope of the present application patent shall be subject to the appended claims.

Claims

1. A semiconductor device, characterized by, The application comprises: a substrate having a first conductivity type; a buried layer disposed in the substrate and having a second conductivity type, the first conductivity type being opposite to the second conductivity type; a first well region disposed on an upper surface of the buried layer and having the first conductivity type; a second well region disposed on the upper surface of the buried layer and partially in contact with the substrate, the second well region being located at the periphery of the first well region and having the second conductivity type; a plurality of emitter and base lead-out regions disposed on the upper surface of the first well region and spaced apart from each other; the base lead-out regions have the first conductivity type, and the emitter lead-out regions have the second conductivity type; a gate structure disposed on the upper surface of the substrate and comprising a plurality of gates, the projection of each gate on the first well region is staggered with the emitter lead-out regions; a collector lead-out region formed on the upper surface of the second well region and having the second conductivity type; wherein the plurality of emitter lead-out regions are connected in parallel to lead out the emitter; the gate and the collector lead-out region are connected in parallel to lead out the collector.

2. The semiconductor device according to claim 1, wherein The collector is configured to be able to adjustably input a positive voltage.

3. The semiconductor device of claim 1, wherein A plurality of collector lead-out regions are disposed on the upper surface of the second well region, and the plurality of collector lead-out regions are connected in parallel with the gate to lead out the collector.

4. The semiconductor device according to any one of claims 1 to 3, wherein The gate structure comprises a plurality of gates, each gate is located above the region between two adjacent emitter lead-out regions.

5. The semiconductor device of claim 4, wherein, The gate structure further comprises a gate dielectric layer disposed on the upper surface of the substrate; the plurality of gates are disposed on the gate dielectric layer; the thickness of the gate dielectric layer is a predetermined value.

6. The semiconductor device according to claim 5, wherein The plurality of emitter lead-out regions are arranged to form a plurality of groups of emitter lead-out regions spaced apart along a first direction, each group of emitter lead-out regions comprises a plurality of emitter lead-out regions spaced apart along a second direction; the gate and the plurality of groups of emitter lead-out regions are staggered along the first direction; the first direction and the second direction intersect each other.

7. The semiconductor device according to any one of claims 1 to 3, wherein The base lead-out regions are located at the periphery of the emitter lead-out regions.

8. The semiconductor device of claim 7, wherein, Further comprising a plurality of field oxide structures formed on the upper surface of the substrate, the plurality of field oxide structures comprise first field oxide structures for electrically isolating the emitter lead-out regions and the base lead-out regions from each other, and second field oxide structures for electrically isolating the base lead-out regions and the collector lead-out region from each other.

9. The semiconductor device according to any one of claims 1 to 3, wherein The first conductivity type is P-type, and the second conductivity type is N-type; When the collector input voltage is input, the emitter lead-out regions, the base lead-out regions and the first well region form an NPN transistor together with the collector lead-out region.

10. A method of manufacturing a semiconductor device, characterized by The application comprises: providing a substrate; the substrate has a first conductivity type; forming a buried layer in the substrate; the buried layer has a second conductivity type, the first conductivity type being opposite to the second conductivity type; forming a first well region on the upper surface of the buried layer, the first well region having the first conductivity type; forming a second well region located outside the first well region on an upper surface layer of the buried layer, a part of the second well region being in contact with the substrate and having the second conductivity type; forming a gate structure on an upper surface of the substrate; forming a plurality of emitter lead-out regions and base lead-out regions in the upper surface layer of the first well region, the emitter lead-out regions and the base lead-out regions being arranged alternately; the gate structure comprises a gate, a normal projection of the gate on the first well region being staggered with the emitter lead-out regions; the base lead-out regions have the first conductivity type, and the emitter lead-out regions have the second conductivity type; forming a collector lead-out region having the second conductivity type in an upper surface layer of the second well region; wherein a plurality of the emitter lead-out regions are connected in parallel to lead out an emitter; the gate and the collector lead-out region are connected in parallel to lead out a collector.

Images